Display panel, display device and driving method thereof, image rendering method

Abstract

The display panel, the display device, the driving method of the display device, and the image rendering method are provided. The display panel comprises a first substrate, a plurality of scan lines located on one side of the first substrate, the plurality of scan lines extending along a first direction and arranged along a second direction, the first direction and the second direction intersecting, a plurality of data lines located on the same side of the first substrate as the scan lines, the plurality of data lines extending along the second direction and arranged along the first direction, a plurality of sub-pixels located in regions divided by the plurality of scan lines and the plurality of data lines, the plurality of sub-pixels forming a plurality of pixel islands, the plurality of pixel islands being divided into a plurality of control areas, each control area comprising at least one pixel island, and each control area being independently driven to emit light.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a display device, a driving method thereof, and an image rendering method thereof. Background Technology

[0002] With the continuous development of display technology, three-dimensional (3D) display technology is attracting increasing attention. 3D display technology can make displayed images more realistic and immersive. Its principle lies in utilizing the left and right eyes to receive images with a certain parallax. When these two parallax images are received by the left and right eyes respectively, the brain superimposes and fuses the image information to construct a 3D visual display effect. To achieve compatibility between multi-viewpoint 3D display and light field display, traditional subpixels are made into pixel island structures. Each pixel island contains multiple subpixels. When the display information of multiple subpixels is different and a single eye enters multiple viewpoints, ordinary light field display can be achieved. When the display information of multiple subpixels is different and a single eye enters a single viewpoint, multi-viewpoint light field 3D display can be achieved.

[0003] However, as the resolution of display panels increases, display products are experiencing problems such as low aperture ratio and high power consumption. Summary of the Invention

[0004] This disclosure provides a display panel, which includes:

[0005] First substrate;

[0006] Multiple scan lines are located on one side of the first substrate, extending along a first direction and arranged along a second direction; the first and second directions intersect.

[0007] Multiple data lines are located on the same side of the first substrate as the scan lines, and the multiple data lines extend along the second direction and are arranged along the first direction;

[0008] Multiple sub-pixels are located in areas divided by multiple scan lines and multiple data lines; multiple sub-pixels constitute multiple pixel islands; multiple pixel islands are divided into multiple control areas, each control area includes at least one pixel island, and each control area is independently driven to emit light.

[0009] In some embodiments, the display panel further includes:

[0010] Multiple scan signal input lines, each corresponding to a scan line, extend along a first direction and are arranged along a second direction;

[0011] Multiple control signal lines are arranged along the first direction;

[0012] Multiple fixed potential lines;

[0013] Multiple control circuits are located between adjacent sub-pixels; a pixel island is connected to at least n control circuits, where n is the number of sub-pixel rows included in the pixel island; one control circuit corresponds to one row of sub-pixels in the pixel island.

[0014] The control circuit is configured to transmit the signal provided by the scan signal input line or the signal provided by the fixed potential line to the scan line under the control of the control signal line;

[0015] At least a portion of the multiple control signal lines includes: multiple portions extending along a second direction and multiple portions extending along a first direction; the portions extending along the second direction and the portions extending along the first direction are alternately connected.

[0016] In some embodiments, the control circuit includes: a first transistor and a second transistor;

[0017] The control electrode of the first transistor is electrically connected to a control signal line, the first electrode of the first transistor is electrically connected to the scan signal input line, and the second electrode of the first transistor is electrically connected to the scan line.

[0018] The control electrode of the second transistor is electrically connected to a control signal line, the first electrode of the second transistor is electrically connected to a fixed potential line, and the second electrode of the second transistor is electrically connected to a scan line.

[0019] In some embodiments, the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to the same control signal line;

[0020] The first transistor is an N-type transistor and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0021] In some embodiments, the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines.

[0022] In some embodiments, the display panel further includes: a gate driving circuit;

[0023] The gate drive circuit includes multiple cascaded shift registers, one of which is electrically connected to each scan signal input line in a row control area.

[0024] In some embodiments, each scan line includes a plurality of sub-scan lines arranged along a first direction and disconnected from each other; the number of sub-scan lines in each scan line is the same as the number of control areas arranged in the first direction, and each sub-scan line corresponds to a row of sub-pixels of a control area.

[0025] In some embodiments, the display panel is divided into a display area and a peripheral area surrounding the display area, with pixel islands located in the display area and scan lines and data lines extending from the display area to the peripheral area;

[0026] The display panel also includes:

[0027] Multiple first data selection control lines, multiple first data input lines, and multiple first data selection circuits are located in the surrounding area;

[0028] Each first data selection circuit includes at least two multiplexers; in each first data selection circuit, the input terminals of different multiplexers are electrically connected to different first data input lines, the control terminals of different multiplexers are electrically connected to different first data selection control lines, and the i-th output terminal of different multiplexers is electrically connected to the same data line, where i is a positive integer; in two adjacent first data selection circuits, the two multiplexers electrically connected to different first data selection control lines are electrically connected to the same first data input line; the first data selection circuit is configured to: under the control of multiple first data selection control lines, provide the signal of the corresponding first data input line to each electrically connected data line respectively.

[0029] In some embodiments, each sub-pixel row in the pixel island includes h sub-pixels, each sub-pixel row is divided into a sub-pixel groups, and each sub-pixel group includes f sub-pixels, where a = h / f, and a, h, and f are all positive integers greater than 1.

[0030] Each sub-pixel group is connected to multiple data lines that are electrically connected to a first data selection circuit, and different sub-pixel groups are connected to multiple data lines that are electrically connected to different first data selection circuits.

[0031] Each multiplexer includes f outputs, one input, and f control inputs.

[0032] In some embodiments, each first data selection circuit includes j multiplexers;

[0033] The number of first data selection control lines is j*f, the number of first data selection circuits is m, and the number of first data input lines is n; m and n satisfy: n=m+j-1;

[0034] In each of the j consecutive first data selection circuits, the j multiplexers, which are electrically connected to different first data selection control lines, are electrically connected to one first data input line, where j is a positive integer less than m.

[0035] In some embodiments, a multiplexer includes f switching transistors; control stages of different switching transistors are electrically connected to different first data selection control lines; first terminals of different switching transistors are electrically connected to the same first data input line; and second terminals of different switching transistors are electrically connected to different data lines.

[0036] In each first data selection circuit, the second terminal of the i-th switching transistor in different multiplexers is electrically connected to the same data line.

[0037] In some embodiments, a multiplexer includes f switching circuits;

[0038] Each switching circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor;

[0039] The control stage of the fifth transistor is electrically connected to the first data selection control line. The first terminal of the fifth transistor and the first terminal of the sixth transistor are both electrically connected to the first data input line. The second terminal of the fifth transistor is electrically connected to the control stage of the sixth transistor, the control stage of the seventh transistor, and the first terminal of the first capacitor. The second terminals of the sixth transistor and the seventh transistor are electrically connected to the data line. The second terminal of the first capacitor is grounded.

[0040] The display panel also includes:

[0041] A dummy signal line is electrically connected to the first electrode of the seventh transistor.

[0042] In some embodiments, the colors of all sub-pixels arranged in a row in the first direction are the same;

[0043] The display panel also includes a light-shielding layer, which consists of only a plurality of light-shielding portions extending along a first direction and arranged along a second direction.

[0044] This disclosure provides a display device comprising:

[0045] The display panel provided in the embodiments of this disclosure;

[0046] A cylindrical lens structure is located on the light-emitting side of the display panel; the cylindrical lens structure includes multiple cylindrical lenses arranged in an array.

[0047] The controller, connected to the display panel, is configured to provide independent drive signals to each control zone.

[0048] In some embodiments, each sub-pixel row in a pixel island includes: h sub-pixels; each pixel island corresponds to N cylindrical lenses; where h and N are both positive integers, h>N, and h / N is a non-integer.

[0049] In some embodiments, each sub-pixel row in the pixel island includes a light-shielding area, and the ratio of the area of ​​the sub-pixel to the area of ​​the light-shielding area is X, where X = N-1.

[0050] In some embodiments, the controller includes:

[0051] The data parsing circuit is configured to parse the image to be displayed and obtain image parsing data.

[0052] The data configuration circuit is configured to generate a data drive signal corresponding to the control area of ​​the display panel based on the current display mode and image parsing data.

[0053] The timing control circuit is configured to generate a gate drive signal for the gate drive circuit based on the current display mode and the viewing area and non-viewing area of ​​the display panel.

[0054] In some embodiments, it also includes:

[0055] An eye-tracking system is used to determine in real time where the user's eyes are focused on the display device.

[0056] In some embodiments, the eye-tracking system includes:

[0057] An image acquisition circuit includes: multiple first cameras and at least one second camera; the resolution of the first cameras is greater than the resolution of the second camera; the first cameras are configured to acquire images of the user's pupils, and the second camera is configured to acquire images of the user's face;

[0058] The camera calibration circuit is configured to calibrate the first camera and the second camera to obtain the internal parameter matrix and external parameter matrix of the first camera and the second camera;

[0059] The camera time-division and zone control circuit is configured to control the shooting sequence of multiple first cameras, so as to realize that multiple first cameras can acquire images in a cyclical and alternating manner;

[0060] The face detection circuit is configured to: search for face bounding boxes in the image captured by the second camera, detect face feature points, obtain the eye region within the face bounding box, and then obtain the spatial coordinate transformation matrix of the eye region through the mapping relationship between the face feature points and the standard face model;

[0061] The image coordinate system transformation circuit is configured to: transform the face image coordinate system into the pupil image coordinate system, or transform the pupil coordinate system into the face image coordinate system;

[0062] The pupil detection circuit is configured to: calculate the pupil coordinates in the image captured by the first camera; based on the eye region coordinates obtained by the face detection circuit, transform them to the pupil image coordinate system through the coordinate transformation circuit to obtain the eye region on the pupil image; perform pupil detection within the eye region to obtain the pupil coordinates in the pupil image coordinate system.

[0063] The spatial coordinate calculation circuit is configured to: transform the pupil coordinates to the face image coordinate system, and then calculate the pupil coordinates in three-dimensional space through the spatial coordinate transformation matrix obtained by the face detection circuit;

[0064] The spatial gaze tracking circuit is configured to: determine the eyeball center coordinates based on the pupil coordinates and a preset human eye model; calculate the direction vectors of the pupil coordinates and the eyeball center coordinates as line vectors; obtain the gaze intersection point between the human eye and the display panel based on the distance from the human eye to the display panel and the equation of the plane on which the display panel is located; and obtain the coordinates of the human eye's gaze point on the display panel based on the gaze focus.

[0065] In some embodiments, the display device further includes: an image rendering system electrically connected to the controller, comprising:

[0066] The coordinate extraction circuit is configured to: determine the three-dimensional spatial coordinates of the human eye relative to the display panel based on the position of the human eye's line of sight on the display panel in the display device, which is determined by the human eye tracking system;

[0067] The lens bonding detection circuit is configured to: obtain the bonding error of the cylindrical lens, adjust the bonding parameters of the cylindrical lens according to the bonding error, and obtain the viewpoint crosstalk curve.

[0068] The image rendering circuit is configured to: generate a multi-view initial image based on the image to be displayed; and to optimize the multi-view initial image based on the human eye position, fit detection parameters, and crosstalk curve to obtain an optimized multi-view image as the image to be displayed.

[0069] This disclosure provides a driving method for a display device, wherein the method includes:

[0070] Real-time determination of the user's gaze area and non-gaze area on the display device;

[0071] The control area corresponding to the gaze region is independently driven to display the image at a first resolution, and the control area corresponding to the non-gaze region is driven to display the image at a second resolution; wherein, the first resolution is higher than the second resolution.

[0072] In some embodiments, determining the user's gaze area and non-gaze area on the display device specifically includes:

[0073] The system uses eye-tracking technology to determine the area where the user's eyes are focused on the display device.

[0074] The area in the display device other than the gaze area is defined as the non-gaze area.

[0075] In some embodiments, obtaining the area of ​​the user's gaze on the display device through an eye-tracking system specifically includes:

[0076] The system controls the first camera in the eye-tracking system to alternately acquire images of the user's pupils, and controls the second camera in the eye-tracking system to acquire images of the user's face.

[0077] Search for face bounding boxes in the images captured by the second camera, detect face feature points, obtain the eye region within the face bounding box, and then obtain the spatial coordinate transformation matrix of the eye region through the mapping relationship between face feature points and the standard face model.

[0078] Transform the face image coordinate system into the pupil image coordinate system, or convert the pupil coordinate system into the face image coordinate system;

[0079] Calculate the pupil coordinates in the image captured by the first camera; transform the coordinates of the human eye region to the pupil image coordinate system to obtain the human eye region on the pupil image; perform pupil detection within the human eye region on the pupil image to obtain the pupil coordinates in the pupil image coordinate system.

[0080] The pupil coordinates are transformed to the face image coordinate system, and then the spatial coordinate transformation matrix is ​​used to calculate the pupil coordinates in three-dimensional space.

[0081] The coordinates of the eyeball center are determined based on the pupil coordinates and a preset human eye model.

[0082] Calculate the direction vectors of the pupil coordinates and the eyeball center coordinates, and use them as line vectors;

[0083] The intersection of the line of sight between the human eye and the display panel is obtained based on the distance from the human eye to the display panel and the equation of the plane on which the display panel is located;

[0084] Based on the focal point of the gaze, the coordinates of the human eye's gaze point on the display panel are obtained, and the area where the human eye's gaze point coordinates are located on the display panel is determined as the gaze area.

[0085] In some embodiments, independently driving the control area corresponding to the gaze region to display an image at a first resolution, and driving the control area corresponding to the non-gaze region to display an image at a second resolution, specifically includes:

[0086] Based on the display mode, the gaze area, and the non-gaze area, determine the display information of each sub-pixel in the pixel island of the control area corresponding to the gaze area, and determine the display information of each sub-pixel in the pixel island of the control area corresponding to the non-gaze area.

[0087] According to the displayed information, a first data selection control signal is provided to the first data selection control line, and the data signal provided by the first data write line is provided to the data line corresponding to the first data selection circuit through the first data selection circuit.

[0088] In some embodiments, independently driving the gaze region to display an image at a first resolution and driving the non-gaze region to display an image at a second resolution further includes:

[0089] The controller of the display device provides a gate driving signal to the gate driving circuit of the display panel to control the corresponding multi-row pixel islands in the viewing area to open row by row, and control the F rows of pixel islands in the corresponding multi-row pixel islands in the non-viewing area to open synchronously, where F is a positive integer and F is equal to the ratio of the first resolution to the second resolution.

[0090] In some embodiments, the gate driving circuit of the display panel includes multiple gate driving groups, each gate driving group includes B gate driving subgroups, and each gate driving subgroup includes C shift registers; wherein B and C are integers greater than 1.

[0091] The controller of the display device provides gate drive signals to the gate drive circuit of the display panel, specifically including:

[0092] The controller provides clock control signals to the gate drive groups so that in each gate drive group, the multiple shift registers in the gate drive subgroup are sequentially input with enable signals in the order of the first to the Bth gate drive subgroups.

[0093] In some embodiments, it also includes:

[0094] The gaze area is driven to display an image at a first refresh rate, and the non-gaze area is driven to display an image at a second refresh rate, wherein the first refresh rate is higher than the second refresh rate.

[0095] In some embodiments, driving the gaze area to display an image at a first refresh rate and driving the non-gaze area to display an image at a second refresh rate specifically includes:

[0096] Drive each sub-pixel within the gaze area to refresh Z times;

[0097] Drive each sub-pixel within the non-focused area to refresh Y times;

[0098] Where Z and Y are positive integers, and Z is greater than Y.

[0099] In some embodiments, driving each sub-pixel within the gaze area to refresh specifically includes:

[0100] Each scan signal input line corresponding to the driving gaze area sequentially transmits an effective level signal;

[0101] Control each control signal line to transmit control signals, and transmit the signal provided by the scan signal input line to the scan line corresponding to the gaze area to the scan line corresponding to the non-gaze area.

[0102] Drive the refresh of each sub-pixel within the non-focused region, including:

[0103] Each scan signal input line within the drive display panel sequentially transmits a valid level signal;

[0104] When the scan detects each sub-pixel row corresponding to the gaze area, the control signal lines transmit control signals, transmitting the signal provided by the fixed potential line to the scan line corresponding to the gaze area, and transmitting the signal provided by the scan signal input line to the scan line corresponding to the non-gaze area.

[0105] This disclosure provides a three-dimensional image rendering method for a display device, the method comprising:

[0106] Determine the position of the human eye's line of sight on the display panel in the display device, and determine the three-dimensional spatial coordinates of the human eye relative to the display panel;

[0107] Generate a multi-viewpoint initial image based on the image to be displayed;

[0108] The cylindrical lens array bonding test is performed on the display device to obtain the bonding error of the cylindrical lens and the viewpoint crosstalk curve.

[0109] The initial multi-view image is optimized based on the human eye position, fit detection parameters, and crosstalk curve to obtain the optimized multi-view image;

[0110] The optimized multi-view images are transmitted to the controller. Attached Figure Description

[0111] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0112] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0113] Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present disclosure;

[0114] Figure 3 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0115] Figure 4 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0116] Figure 5 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0117] Figure 6 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0118] Figure 7 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0119] Figure 8 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0120] Figure 9 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0121] Figure 10 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0122] Figure 11 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0123] Figure 12 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0124] Figure 13 A schematic diagram of the switching circuit of another display panel provided in an embodiment of this disclosure;

[0125] Figure 14 A timing diagram of a display panel provided in an embodiment of this disclosure;

[0126] Figure 15 A timing diagram of a data line for a display panel provided in an embodiment of this disclosure;

[0127] Figure 16 This is a schematic diagram showing the correspondence between sub-pixels in a pixel island of a display panel and a viewpoint, provided by an embodiment of this disclosure.

[0128] Figure 17 This is a schematic diagram showing the correspondence between sub-pixels in a pixel island and a viewpoint in another embodiment of the present disclosure.

[0129] Figure 18 A schematic diagram showing the correspondence between sub-pixels in a pixel island and a viewpoint in another embodiment of the present disclosure;

[0130] Figure 19 A schematic diagram showing the correspondence between sub-pixels in a pixel island and a viewpoint in another embodiment of the present disclosure;

[0131] Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0132] Figure 21 This is a schematic diagram of the viewpoint spatial distribution of a display device provided in an embodiment of the present disclosure;

[0133] Figure 22 This is a schematic diagram of the viewpoint spatial distribution of a display device provided in an embodiment of the present disclosure;

[0134] Figure 23 A schematic diagram of the interpupillary visual area of ​​a display device provided in an embodiment of this disclosure;

[0135] Figure 24 A schematic diagram of the interpupillary visual area of ​​another display device provided in an embodiment of this disclosure;

[0136] Figure 25 This is a schematic diagram of the structure of a controller provided in an embodiment of the present disclosure;

[0137] Figure 26 A schematic diagram of another controller provided in an embodiment of this disclosure;

[0138] Figure 27 A schematic diagram illustrating resolution partitioning control provided in an embodiment of this disclosure;

[0139] Figure 28 This is a schematic diagram of another display device provided in an embodiment of the present disclosure;

[0140] Figure 29 A schematic flowchart illustrating a driving method for a display device provided in an embodiment of this disclosure;

[0141] Figure 30 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0142] Figure 31 A timing diagram of a gate driving circuit provided for an embodiment of this disclosure;

[0143] Figure 32 A timing diagram of another gate drive circuit provided in an embodiment of this disclosure;

[0144] Figure 33 This is a schematic flowchart of an image rendering method for a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0145] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0146] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0147] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this application. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0148] This disclosure provides a display panel, such as... Figure 1 As shown, the display panel includes:

[0149] First substrate 1;

[0150] Multiple scan lines 2 are located on one side of the first substrate 1. The multiple scan lines 2 extend along the first direction X and are arranged along the second direction Y; the first direction X and the second direction Y intersect.

[0151] Multiple data lines 3 are located on the same side of the first substrate 1 as the scan lines 2. The multiple data lines 3 extend along the second direction Y and are arranged along the first direction X.

[0152] Multiple sub-pixels 4 are located in the areas divided by multiple scan lines 2 and multiple data lines 3 respectively; multiple sub-pixels 4 constitute multiple pixel islands 5; multiple pixel islands 5 are divided into multiple control areas 14, each control area 14 includes at least one pixel island 5, and each control area 14 is independently driven to emit light.

[0153] The display panel provided in this embodiment divides multiple pixel islands into multiple control areas, each of which is independently driven to emit light. This allows for zoned control of the display panel's resolution and refresh rate based on the displayed image. When the display panel's resolution is zoned, it can be divided into high-definition and low-definition areas, with the high-definition area having a higher resolution than the low-definition area. For example, this can improve the resolution of the area the human eye is focused on, thereby enhancing the display effect. Similarly, when the display panel's refresh rate is zoned, it can be divided into high-refresh-rate and low-refresh-rate areas, thus saving power consumption in the display product.

[0154] It should be noted that, Figure 1 Only a portion of the subpixels in the display panel are shown. Figure 1 The first direction X and the second direction Y are perpendicular.

[0155] In some embodiments, such as Figure 1 As shown, in the second direction Y, each pixel island 5 includes multiple sub-pixel rows 6.

[0156] Figure 1 In the middle, each pixel island 5 includes 3 sub-pixel rows 6, namely the first sub-pixel row 48, the second sub-pixel row 49 and the third sub-pixel row 50;

[0157] The first subpixel row 48 includes a plurality of first color subpixels arranged along the first direction X;

[0158] The second subpixel row 49 includes a plurality of second color subpixels arranged along the first direction X;

[0159] The third subpixel row 50 includes a plurality of third-color subpixels arranged along the first direction X.

[0160] In some embodiments, such as Figure 1 As shown, the first color sub-pixel is the red sub-pixel R, the second color sub-pixel is the green sub-pixel G, and the third color sub-pixel is the blue sub-pixel B.

[0161] In some embodiments, such as Figure 1 As shown, the colors of all sub-pixels 4 arranged in the first direction X are the same.

[0162] Alternatively, in some embodiments, such as Figure 2As shown, the colors of the sub-pixels 4 arranged in the first direction X are not completely identical. For example, the first sub-pixel row 48, the second sub-pixel row 49, and the third sub-pixel row 50 are arranged as a repeating unit in a column along the second direction Y, with the odd-numbered columns staggered relative to the even-numbered columns. Pixel island 5 includes a first pixel island 55 and a second pixel island 56. The first pixel island 55 includes the first sub-pixel row 48 and the second sub-pixel row 49, and the second pixel island 56 includes the third sub-pixel row 50. When driving the display panel for display, sub-pixel rendering technology allows the first pixel island 55 to borrow from the adjacent column of the second pixel island 56 to form a pixel for display. This improves the resolution of the display panel.

[0163] In specific implementation, the display panel provided in the embodiments of this disclosure can be a rigid display panel or a flexible display panel, that is, the display panel can be bent and folded.

[0164] In some embodiments, the display panel provided in this disclosure is a liquid crystal display panel. Its type may be a twisted nematic (TN), vertical alignment (VA), in-plane switching (IPS), or advanced super-dimensional switching (ADS) liquid crystal display panel, etc.

[0165] In some embodiments, the liquid crystal display panel includes: an array substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the counter substrate.

[0166] In practice, scan lines and data lines can be set on the array substrate.

[0167] In specific implementation, such as Figures 3-6 As shown, the opposing substrate includes a black matrix 7 and a color filter 8.

[0168] In some embodiments, such as Figure 3 As shown, the black matrix 7 is positioned in the region between adjacent pixel islands in the second direction.

[0169] In some embodiments, such as Figure 4 As shown, the black matrix 7 is set in the region between adjacent pixel islands and the region between adjacent sub-pixel columns in the second direction.

[0170] In some embodiments, it can also be as follows Figure 5 As shown, black matrix 7 is set in the area between adjacent sub-pixel rows and the area between adjacent sub-pixel columns.

[0171] In some embodiments, when all sub-pixels arranged in a row along the first direction X have the same color, it can also be as follows: Figure 6 As shown, black matrix 7 is only set in the area between adjacent sub-pixel rows.

[0172] Since all sub-pixels in a row arranged in the first direction X have the same color, even if a black matrix is ​​not set between sub-pixel columns, sub-pixels between adjacent sub-pixel rows will not interfere with each other. Setting a black matrix only between adjacent sub-pixel rows can improve the aperture ratio of the display panel.

[0173] In some embodiments, the display panel provided in this disclosure is an electroluminescent display panel. The electroluminescent display panel may be, for example, an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, etc. In a specific implementation, each sub-pixel includes, for example, a pixel driving circuit and an electroluminescent device electrically connected to the pixel driving circuit. The pixel driving circuit includes, for example, transistors, capacitors, etc.

[0174] In some embodiments, such as Figure 7 , Figure 8 , Figure 10 As shown, the display panel also includes:

[0175] Multiple scan signal input lines 7 correspond one-to-one with scan lines 2, extending along the first direction X and arranged along the second direction Y;

[0176] Multiple control signal lines 8 are arranged along the first direction X;

[0177] Multiple fixed potential lines 9;

[0178] Multiple control circuits 10 are located between adjacent sub-pixels 4; a pixel island 5 is connected to at least n control circuits 10; a control circuit 10 corresponds to a sub-pixel row 6 in the pixel island 5;

[0179] The control circuit 10 is configured to transmit the signal provided by the scan signal input line 7 or the signal provided by the fixed potential line 9 to the scan line 2 under the control of the control signal line 8.

[0180] The display panel provided in this embodiment includes a control circuit and control signal lines, fixed potential lines, and scan signal input lines electrically connected to the control circuit. This allows the control circuit to transmit signals provided by the scan signal input lines or the fixed potential lines to the scan lines. In other words, during image display, for areas requiring refresh, the control circuit can input normal scan signals to the corresponding scan lines; for areas not requiring refresh, the control circuit can input fixed potential signals transmitted by the fixed potential lines to the corresponding scan lines. This enables partitioned driving of pixel islands, thereby saving power consumption in the display product. Furthermore, the pixel island array arrangement, with each pixel island electrically connected to the control circuit, allows for partitioned control of each pixel island in the display panel in a second direction.

[0181] When the display panel is a liquid crystal display panel, in some embodiments, such as Figure 7 , Figure 8 , Figure 10 As shown, sub-pixel 4 includes a driving transistor Td and a pixel electrode (not shown) electrically connected to the driving transistor. The control electrode of the driving transistor Td is electrically connected to the scan line 2, the first electrode of the driving transistor Td is electrically connected to the data line 3, and the second electrode of the driving transistor Td is electrically connected to the pixel electrode.

[0182] In some embodiments, the liquid crystal display panel further includes a common electrode layer, which may be disposed in the array substrate or in the opposing substrate.

[0183] In some embodiments, a low-level signal is input to the fixed potential line.

[0184] In some embodiments, such as Figure 7 , Figure 8 , Figure 10 As shown, each scan line 2 includes a plurality of sub-scan lines 11 arranged and disconnected from each other in the first direction X; in each scan line 2, the number of sub-scan lines 11 is the same as the number of rows of control areas 14 arranged in the first direction X, and each sub-scan line 11 corresponds to a row of sub-pixels 4 of a control area 14.

[0185] That is, the scan lines are disconnected between control areas, so that each control area can be independently controlled by the control circuit.

[0186] In some embodiments, such as Figure 7 , Figure 8 , Figure 10 As shown, one pixel island 5 corresponds to n control circuits.

[0187] In some embodiments, such as Figure 7 , Figure 8 , Figure 10As shown, in each control area 14, a row of pixel islands 5 arranged in the first direction X are connected to n control circuits 10.

[0188] Of course, in practice, each pixel island can also be connected to n control circuits.

[0189] In some embodiments, such as Figure 7 , Figure 8 , Figure 10 As shown, each pixel island 5 includes 3 sub-pixel rows 6. That is, n=3, and each pixel island 5 is connected to 3 control circuits 10.

[0190] In some embodiments, such as Figure 7 , Figure 8 , Figure 9 , Figure 10 As shown, the control circuit 10 includes: a first transistor T1 and a second transistor T2;

[0191] The control electrode of the first transistor T1 is electrically connected to a control signal line 8, the first electrode of the first transistor T1 is electrically connected to the scan signal input line 7, and the second electrode of the first transistor T1 is electrically connected to the scan line 2.

[0192] The control electrode of the second transistor T2 is electrically connected to a control signal line 8, the first electrode of the second transistor T2 is electrically connected to a fixed potential line 9, and the second electrode of the second transistor T2 is electrically connected to a scan line 2.

[0193] In practical implementation, for multiple control circuits corresponding to a control area, under the control of the control signal input on the control signal line, when the first transistor is turned on and the second transistor is turned off, the signal input on the scan signal input line is transmitted to the scan line through the first transistor to refresh the pixel islands of that control area. When the second transistor is turned on and the first transistor is turned off, under the control of the control signal input on the control signal line, the low-level signal input on the fixed potential line is transmitted to the scan line through the second transistor, meaning that the pixel islands of that control area do not need to be refreshed.

[0194] In some embodiments, the second terminal of the first transistor T1 and the second terminal of the second transistor T1 in a control circuit are electrically connected to the same sub-scan line.

[0195] In some embodiments, such as Figure 7 As shown, the control electrode of the first transistor T1 and the control electrode of the second transistor T1 are electrically connected to the same control signal line 8.

[0196] The first transistor is an N-type transistor and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0197] In some embodiments, such as Figure 8 , Figure 9 , Figure 10 As shown, the control electrode of the first transistor T1 and the control electrode of the second transistor T2 are electrically connected to different control signal lines 8.

[0198] In some embodiments, such as Figure 8 , Figure 9 , Figure 10 As shown, the multiple control signal lines 8 include: multiple first control signal lines 12 and multiple second control signal lines 13;

[0199] The control electrode of the first transistor T1 is electrically connected to the first control signal line 12, and the control electrode of the second transistor T2 is electrically connected to the second control signal line 13.

[0200] In practical implementation, when the control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines, the first transistor can be an N-type transistor or a P-type transistor, and the second transistor can be an N-type transistor or a P-type transistor.

[0201] In some embodiments, such as Figure 7 , Figure 8 As shown, the control circuit 10 is located between two adjacent sub-pixels 4 in the first direction X;

[0202] Multiple fixed potential lines 9 extend along the first direction X and are arranged along the second direction Y.

[0203] That is, Figure 7 , Figure 8 As shown, the control circuit 10 is located between two adjacent columns of sub-pixels 4.

[0204] In some embodiments, such as Figure 7 , Figure 8 As shown, each control signal line 8 extends along the second direction Y, and multiple control circuits 10 are arranged in an array, with the control circuit corresponding to each pixel island located in the same column.

[0205] Alternatively, when the control circuit is located between two adjacent columns of sub-pixels, in some embodiments, such as Figure 9 As shown, at least a portion of the multiple control signal lines 8 include: multiple portions 57 extending in a second direction and multiple portions 58 extending in a first direction; the portions 57 extending in the second direction and the portions 58 extending in the first direction are alternately connected.

[0206] In the display panel provided in this embodiment, the control signal line includes a portion extending along a first direction and a portion extending along a second direction, so that the control signal line does not extend along the second direction in a regular manner. When multiple signal lines are arranged along the first direction, optical unevenness (mura) caused by the regular longitudinal arrangement of the signal lines can be avoided.

[0207] In some embodiments, such as Figure 9 The multiple control circuits corresponding to each pixel island shown are arranged in multiple columns in the second direction. That is, the control circuits are distributed, which can further avoid optical mura.

[0208] Alternatively, in some embodiments, such as Figure 10 As shown, the control circuit 10 is located between two adjacent sub-pixels 4 in the second direction Y;

[0209] Multiple fixed potential lines 9 extend along the second direction Y and are arranged along the first direction X.

[0210] That is, the control circuit 10 is located between adjacent sub-pixel rows.

[0211] In some embodiments, the control circuits corresponding to each pixel island are arranged in a row in the first direction X.

[0212] Of course, it is also possible that the control circuits corresponding to each pixel island are arranged in multiple rows in the first direction X.

[0213] In some embodiments, the display panel further includes: a gate driving circuit;

[0214] The gate drive circuit includes multiple cascaded shift registers (GOAs), each GOA being electrically connected to one of the scan signal input lines in a row control area. The gate drive circuit is also electrically connected to the clock signal line (CLK) and the start signal line (STV).

[0215] This allows for zoned control of multiple rows of pixel islands using the gate driving circuit, i.e., horizontal zoned control. Specifically, each pixel island in the display panel can be controlled in both the first and second directions. In practice, by applying appropriate timing to the gate driving circuit, it is possible to control the pixel islands in the display area to open row by row, or to control multiple rows of pixel islands to open simultaneously.

[0216] In some embodiments, the gate driving circuit of the display panel includes multiple gate driving groups, each gate driving group includes B gate driving subgroups, and each gate driving subgroup includes C shift registers; wherein B and C are integers greater than 1; the start signal line STV is electrically connected to the C shift registers in the first gate driving subgroup.

[0217] In some embodiments, such as Figure 11 As shown, the display panel is divided into a display area 59 and a peripheral area 60 surrounding the display area 59. Pixel island 5 is located in the display area 59, and scan line 2 and data line 4 extend from the display area 59 to the peripheral area 60.

[0218] In a practical implementation, the gate drive circuit can be located, for example, in the peripheral region.

[0219] In some embodiments, such as Figure 11 , Figure 12 As shown, the display panel also includes:

[0220] Located in the surrounding area 60 are multiple first data selection control lines MUX, multiple first data input lines D, and multiple first data selection circuits 15;

[0221] Each first data selection circuit 15 includes at least two multiplexers 16; in each first data selection circuit 15, the input terminals of different multiplexers 16 are electrically connected to different first data input lines D, the control terminals of different multiplexers 16 are electrically connected to different first data selection control lines MUX, and the i-th output terminal of different multiplexers 16 is electrically connected to the same data line 3, where i is a positive integer; in two adjacent first data selection circuits 15, the two multiplexers 16 electrically connected to different first data selection control lines MUX are electrically connected to the same first data input line D; the first data selection circuit 15 is used to: under the control of the signals of multiple first data selection control lines MUX, provide the signals of the corresponding first data input lines D to each electrically connected data line 3 respectively.

[0222] The display panel provided in this embodiment utilizes a first data selection circuit to provide signals from the first data input line to the data line, thereby reducing the number of first data input lines compared to the number of data lines and thus reducing the amount of data input.

[0223] Each first data selection circuit in the display panel provided in this disclosure includes at least two multiplexers, and different multiplexers in each first data selection circuit are electrically connected to different first data input lines. For a first data selection circuit, under the control of signals from multiple first data selection control lines, the signal of the same first data input line can be provided to each electrically connected data line respectively, or the signals of different first data input lines can be provided to the corresponding data lines respectively through different multiplexers. Multiple data lines connected to the same first data selection circuit can input the same data signal or input different data signals. In this way, each sub-pixel in each pixel island can be displayed individually or multiple sub-pixels in a row can be merged for display, thereby achieving adjustable resolution of the display panel. Furthermore, when multiple sub-pixels in the same row of each pixel island are merged for display, the merged display sub-pixels also change when the position of the human eye changes. Through the first data selection circuit of the display panel provided in this disclosure, the display information of the merged display sub-pixels can be changed accordingly, allowing the display information of the sub-pixels to transition smoothly with the movement of the human eye, improving the display effect and enhancing the user experience.

[0224] It should be noted that, Figure 12 The display area is not shown, and Figure 11 , Figure 12 Only a portion of the data lines, scan lines, sub-pixels, first data input lines, and first data selection circuitry are shown.

[0225] In some embodiments, such as Figure 11 As shown, the pixel island 5 includes multiple sub-pixel rows 6 arranged along the first direction X; each sub-pixel row 6 includes h sub-pixels 4 arranged along the second direction Y; each sub-pixel row 6 is divided into a sub-pixel groups 17, and each sub-pixel group 17 includes f sub-pixels 4, where a = h / f, and a, h, and f are all positive integers greater than 1.

[0226] In a sub-pixel row 6, each sub-pixel group 17 is electrically connected to a first data selection circuit 15 via a data line 3, and different sub-pixel groups 17 are electrically connected to different first data selection circuits 15 via data lines 3.

[0227] Each multiplexer 16 includes f outputs, 1 input, and f control inputs.

[0228] Thus, for each sub-pixel group in a sub-pixel row, under the control of signals from multiple first data selection control lines, the signal from the same first data input line can be provided to each electrically connected data line through its corresponding first data selection circuit. Alternatively, signals from different first data input lines can be provided to each electrically connected data line through their corresponding first data selection circuits. In other words, each sub-pixel in a sub-pixel group can input the same display information through the first data selection circuit, or it can input slightly different display information.

[0229] It should be noted that, in practical implementation, sub-pixels are electrically connected to both the scan lines and data lines. A column of sub-pixels arranged in the first direction X is electrically connected to the same data line, and a row of sub-pixels arranged in the second direction Y is electrically connected to the same scan line. That is, in practical implementation, a first data selection circuit is electrically connected to a column of sub-pixels via f data lines.

[0230] In some embodiments, the number of first data selection circuits is equal to the number of sub-pixel groups in a row of sub-pixels arranged in the second direction.

[0231] This allows the first data selection circuit to provide data signals to the sub-pixel groups in the corresponding pixel island.

[0232] In some embodiments, each first data selection circuit includes j multiplexers;

[0233] The number of first data selection control lines is j*f, the number of first data selection circuits is m, and the number of first data input lines is n; m and n satisfy: n=m+j-1;

[0234] In each of the j consecutive first data selection circuits, the j multiplexers, which are electrically connected to different first data selection control lines, are electrically connected to one first data input line, where j is a positive integer less than m.

[0235] In some embodiments, such as Figure 11 , Figure 12 As shown, each first data selection circuit 15 includes two multiplexers, namely: a first multiplexer 18 and a second multiplexer 19.

[0236] The number m of the first data selection circuit 15 and the number n of the first data input lines D satisfy: n = m + 1.

[0237] In practical implementation, the numbering of the first data input line D can start from 0, for example, meaning the n first data input lines are numbered D0 to Dm respectively. Figure 11 As shown, Figure 11The leftmost first data selection circuit 15 is the first first data selection circuit. The first multiplexer 18 of the first first data selection circuit 15 and the second multiplexer 19 of the second first data selection circuit 15 are electrically connected to the first first data input line D1. In a specific implementation, the second multiplexer 19 of the first first data selection circuit 15 is electrically connected to the 0th first data input line D0. The first multiplexer 18 of the m-th first data selection circuit 15 is electrically connected to the m-th first data input line Dm.

[0238] In some embodiments, a multiplexer includes f switching transistors; control stages of different switching transistors are electrically connected to different first data selection control lines; first terminals of different switching transistors are electrically connected to the same first data input line; and second terminals of different switching transistors are electrically connected to different data lines.

[0239] In each first data selection circuit, the second terminal of the i-th switching transistor in different multiplexers is electrically connected to the same data line.

[0240] In some embodiments, when the first data selection circuit includes two multiplexers, such as Figure 11 As shown, the first multiplexer 18 includes f third transistors T3; the control stages of different third transistors T3 are electrically connected to different first data selection control lines MUX; the first terminals of different third transistors T3 are electrically connected to the same first data input line D; and the second terminals of different third transistors T3 are electrically connected to different data lines 3.

[0241] The second multiplexer 19 includes f fourth transistors T4; the control stages of different fourth transistors T4 are electrically connected to different first data selection control lines MUX; the first terminals of different fourth transistors T4 are electrically connected to the same first data input line D; and the second terminals of different fourth transistors T4 are electrically connected to different data lines 3.

[0242] In each first data selection circuit 15, the second terminal of the i-th third transistor T3i in the first multiplexer 18 and the second terminal of the i-th fourth transistor T4i in the second multiplexer 13 are electrically connected to the same data line 3.

[0243] In some embodiments, the third transistor and the fourth transistor are both P-type transistors or both are N-type transistors. This facilitates control of the first data selection circuit using the first data selection control line.

[0244] Of course, it could also be either a P-type transistor or an N-type transistor, either the third or fourth transistor.

[0245] In some embodiments, the display panel includes 2f first data selection control lines.

[0246] Among them, f first data selection control lines are electrically connected to the control stage of each third transistor in the first data selector, and the remaining f first data selection control lines are electrically connected to the control stage of each fourth transistor in the second data selector.

[0247] In some embodiments, such as Figure 11 As shown, the control stage of the i-th third transistor T3i in different first data selection circuits 15 is electrically connected to the same first data selection control line MUX;

[0248] The control stage of the i-th fourth transistor T4i in different first data selection circuits is electrically connected to the same first data selection control line MUX.

[0249] It should be noted that, Figure 11 The example illustrates this by connecting the control level of the i-th third transistor T3i in different first data selection circuits to the same first data selection control line MUX; connecting the control level of the i-th fourth transistor T4i in different first data selection circuits to the same first data selection control line MUX; and including 2f first data selection control lines in the display panel. Of course, in actual implementation, the control level of the i-th third transistor T3i in different first data selection circuits can also be connected to different first data selection control lines MUX, and the control level of the i-th fourth transistor T4i in different first data selection circuits can also be connected to different first data selection control lines MUX. The number of first data selection control lines included in the display panel is an integer multiple of 2f.

[0250] In some embodiments, such as Figure 11 As shown, each sub-pixel row 6 in pixel island 5 includes 16 sub-pixels 4; each sub-pixel row 6 is divided into 4 sub-pixel groups 17, and each sub-pixel group 17 includes 4 sub-pixels 4.

[0251] Each multiplexer 16 includes 4 inputs, 1 control input, and 4 outputs.

[0252] Next, taking an example where each sub-pixel group includes 4 sub-pixels, the embodiments provided in this disclosure will be discussed further. Figure 11 The display panel shown is used as an example.

[0253] In specific implementation, such as Figure 11 As shown, the first multiplexer 18 includes four third transistors, namely T31, T32, T33, and T34. The second multiplexer 19 includes four fourth transistors, namely T41, T42, T43, and T44.

[0254] In specific implementation, such as Figure 11As shown, the display panel includes eight first data selection control lines MUX, namely MUX1, MUX2, MUX3, MUX4, MUX5, MUX6, MUX7, and MUX8. Specifically, the control terminal of the first third transistor T31 in each first data selection circuit 15 is electrically connected to MUX1; the control terminal of the first fourth transistor T41 in each first data selection circuit 15 is electrically connected to MUX2; the control terminal of the second third transistor T32 in each first data selection circuit 15 is electrically connected to MUX3; the control terminal of the second fourth transistor T42 in each first data selection circuit 15 is electrically connected to MUX4; the control terminal of the third third transistor T33 in each first data selection circuit 15 is electrically connected to MUX5; the control terminal of the third fourth transistor T43 in each first data selection circuit 15 is electrically connected to MUX6; the control terminal of the fourth third transistor T34 in each first data selection circuit 15 is electrically connected to MUX7; and the control terminal of the fourth fourth transistor T44 in each first data selection circuit 15 is electrically connected to MUX8.

[0255] In specific implementation, such as Figure 11 As shown, in each first data selection circuit 15, the output terminals of the first third transistor T31 and the first fourth transistor T41 are electrically connected to the same data line 3, the output terminals of the second third transistor T32 and the second fourth transistor T42 are electrically connected to the same data line 3, the output terminals of the third third transistor T33 and the third fourth transistor T43 are electrically connected to the same data line 3, and the output terminals of the fourth third transistor T34 and the fourth fourth transistor T44 are electrically connected to the same data line 3.

[0256] In specific implementation, such as Figure 11 As shown, in each first data selection circuit 15, the input terminals of each third transistor T31, T32, T33, and T34 are electrically connected to the same first data input line D, and the input terminals of each fourth transistor T41, T42, T43, and T44 are electrically connected to the same first data input line D. However, the input terminals of the third transistors T31, T32, T33, and T34 and the input terminals of the fourth transistors T41, T42, T43, and T44 are electrically connected to different first data input lines D. For example, Figure 11In the first data selection circuit 15 from left to right, the input terminals of the third transistors T31, T32, T33, and T34 are electrically connected to D1, and the input terminals of the fourth transistors T41, T42, T43, and T44 are electrically connected to D0. In the second data selection circuit 15, the input terminals of the third transistors T31, T32, T33, and T34 are electrically connected to D2, and the input terminals of the fourth transistors T41, T42, T43, and T44 are electrically connected to D1. In the third data selection circuit 15, the input terminals of the third transistors T31, T32, T33, and T34 are electrically connected to D3, and the input terminals of the fourth transistors T41, T42, T43, and T44 are electrically connected to D2. This pattern continues, and will not be elaborated further.

[0257] It should be noted that in practice, the viewpoint needs to correspond to the red, blue, and green sub-pixels. The following example, using a sub-pixel row of a pixel island comprising 16 sub-pixels, illustrates the correspondence between sub-pixels and viewpoints.

[0258] When a pixel island corresponds to 16 viewpoints, the sub-pixels in the same row of each sub-pixel group within the pixel island need to display different display information. In some display scenarios, for example, it could be as follows: Figure 16 As shown, the i-th viewpoint Pi corresponds to Ri, Gi, and Bi in the first pixel island 22, where i is a positive integer less than or equal to 16. The first pixel island and... Figure 11 Taking the electrical connection of the first four first data selection circuits arranged from left to right as an example, in specific implementation, data signals corresponding to viewpoints Pi to P4i can be provided to Di in sequence, and the third transistors T31, T32, T33, and T34 in the first data selection circuit can be turned on in sequence through the first data selection control lines MUX1, MUX3, MUX5, and MUX7. At the same time, the fourth transistors T41, T42, T43, and T44 in the first data selection circuit can be turned off through the first data selection control lines MUX2, MUX4, MUX6, and MUX8.

[0259] When a pixel island corresponds to 4 viewpoints, that is, the four sub-pixels in each row of the pixel island are displayed together. In some display cases, for example, it can be as follows: Figure 17As shown, the i-th viewpoint Pi corresponds to R4i-3~R4i, G4i-3~G4i, and B4i-3~B4i in the first pixel island 22, where i is a positive integer less than or equal to 4. In specific implementation, data signals corresponding to viewpoint Pi can be provided to Di sequentially, and the third transistors T31, T32, T33, and T34 in the first data selection circuit can be turned on simultaneously through the first data selection control lines MUX1, MUX3, MUX5, and MUX7, while the fourth transistors T41, T42, T43, and T44 in the first data selection circuit can be turned off through the first data selection control lines MUX2, MUX4, MUX6, and MUX8.

[0260] In some display scenarios, such as when the user's eye moves, the subpixel corresponding to the viewpoint shifts... Figure 17 When a rightward translation occurs, when the translation is one sub-pixel, the sub-pixels corresponding to the user's gaze area viewpoint can be as follows: Figure 18 As shown, the first viewpoint P1 corresponds to R2-R5, G2-G5, and B2-B5 in the first pixel island 22; the second viewpoint P2 corresponds to R6-R9, G6-G9, and B6-B9 in the first pixel island 22; the third viewpoint P3 corresponds to R10-R13, G10-G13, and B10-B13 in the first pixel island 22; and the fourth viewpoint P4 corresponds to R14-R16, G14-G16, and B14-B16 in the first pixel island 22 and R1, G1, and B1 in the second pixel island 23. Specifically, d4 data signal is input to D0, d1 data signal is input to D1, d2 data signal is input to D2, d3 data signal is input to D3, and d4 data signal is input to D4. Simultaneously, a first data selection control signal is provided to MUX2, MUX3, MUX5, and MUX7 to control T41, T32, T33, and T34 in each first data selection circuit to be turned on simultaneously. At the same time, a second data selection control signal is provided to MUX1, MUX4, MUX6, and MUX8 to control T31, T42, T43, and T44 in each first data selection circuit to be turned off.

[0261] In some display scenarios, such as when the user's eye continues to move, the subpixel corresponding to the viewpoint shifts... Figure 18 When the viewpoint is shifted one subpixel to the right again, the subpixels corresponding to the user's gaze area viewpoint can be as follows: Figure 19As shown, the first viewpoint P1 corresponds to R3-R6, G3-G6, and B3-B6 in the first pixel island 22; the second viewpoint P2 corresponds to R7-R10, G7-G10, and B7-B10 in the first pixel island 22; the third viewpoint P3 corresponds to R11-R14, G11-G14, and B11-B14 in the first pixel island 22; and the fourth viewpoint P4 corresponds to R15-R16, G15-G16, and B15-B16 in the first pixel island 22 and R1, R2, G1, G2, B1, and B2 in the second pixel island 23. Specifically, a d4 data signal is input to D0, a d1 data signal is input to D1, a d2 data signal is input to D2, a d3 data signal is input to D3, and a d4 data signal is input to D4. Simultaneously, a first data selection control signal is provided to MUX2, MUX4, MUX5, and MUX7 to control T41, T42, T33, and T34 in each first data selection circuit to be turned on simultaneously. At the same time, a second data selection control signal is provided to MUX1, MUX3, MUX6, and MUX8 to control T31, T32, T43, and T44 in each first data selection circuit to be turned off.

[0262] Alternatively, in some embodiments, such as Figure 12 As shown, a multiplexer 16 includes f switching circuits 20.

[0263] In practical implementation, when the first data selection circuit 15 includes two multiplexers, such as... Figure 12 As shown, the first multiplexer 18 includes f first switching circuits 22; the second multiplexer 19 includes f second switching circuits 24.

[0264] In the same first data selection circuit 15, the control stages of different switching circuits 20 are electrically connected to different first data selection control lines MUX, the input terminals of different first switching circuits 22 are electrically connected to the same first data input line D, the input terminals of different second switching circuits 24 are electrically connected to the same first data input line D, the output terminals of different first switching circuits 22 are electrically connected to different data lines 3, the output terminals of different second switching circuits 24 are electrically connected to different data lines 3, and the output terminals of the i-th first switching circuit 22 and the i-th second switching circuit 24 are electrically connected to the same data line 3.

[0265] In some embodiments, such as Figure 12 As shown, the i-th first switch circuit 22 in different first data selection circuits 15 is electrically connected to the same first data selection control line MUX, and the i-th second switch circuit 24 in different first data selection circuits 15 is electrically connected to the same first data selection control line MUX. That is, the display panel includes 2f first data selection control lines MUX.

[0266] In some embodiments, such as Figure 13 As shown, each switching circuit 20 includes: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1;

[0267] The control stage of the fifth transistor T5 is electrically connected to the first data selection control line MUX. The first terminal of the fifth transistor T5 and the first terminal of the sixth transistor T6 are both electrically connected to the first data input line D. The second terminal of the fifth transistor T5 is electrically connected to the control stage of the sixth transistor T6, the control stage of the seventh transistor T7, and the first terminal of the first capacitor C1. The second terminals of the sixth transistor T6 and the seventh transistor T7 are electrically connected to the data line 3. The second terminal of the first capacitor C1 is grounded.

[0268] The display panel also includes:

[0269] A dummy signal line L0 is electrically connected to the first terminal of the seventh transistor T7.

[0270] In practice, the first terminal of the seventh transistor in each switching circuit can be electrically connected to the same dummy signal line.

[0271] In practice, the dummy signal line has no signal input.

[0272] In a practical implementation, one of the sixth and seventh transistors is an N-type transistor and the other is a P-type transistor, so that one of the sixth and seventh transistors is turned on and the other is turned off, so as to connect the first data input line to the data line or the data line to the dummy signal line.

[0273] When each switching circuit includes, for example Figure 13 The circuit structure shown is illustrated in the following timing diagram: Figure 14 As shown. Stage A1 is the display stage within a frame, and stage A2 is the black insertion stage within a frame. The signal transmitted on the first data input line D contains a strobe level, which determines which data line the first data input line will be connected to in the next frame. For example, for... Figure 14 Each first data selection control line MUX provides a signal to scan each first data selection circuit line by line, based on the signal transmitted by the first data input line D, such as Figure 15 As shown, when the switching circuit electrically connected to MUX4 is activated, specifically, the second data line da2 out of the h data lines corresponding to each pixel island is activated, then in the next frame, the second data line da2 out of the h data lines corresponding to each pixel island transmits a grayscale signal, while the remaining data lines da1, da3 to daah out of the h data lines corresponding to each pixel island transmit DC signals. The first data selection circuit is controlled via the first data input control line using the following... Figure 14 By controlling the timing shown, the charging sampling time can be kept constant, thus saving system resources.

[0274] It should be noted that, Figure 14 The diagram only uses the signals of the first data selection control lines MUX1 to MUX4 for illustration.

[0275] Next, taking an example where each sub-pixel group includes 4 sub-pixels, the embodiments provided in this disclosure will be discussed further. Figure 12 The display panel shown is used as an example.

[0276] In specific implementation, such as Figure 12 As shown, the first multiplexer 18 includes four first switch circuits 22, and the second multiplexer 19 includes four second switch circuits 24. The display panel includes eight first data selection control lines MUX, namely MUX1, MUX2, MUX3, MUX4, MUX5, MUX6, MUX7, and MUX8.

[0277] Specifically, the control terminal of the fifth transistor T5 in the first first switching circuit 22 of each first data selection circuit 15 is electrically connected to MUX1; the control terminal of the first second switching circuit 24 of each first data selection circuit 15 is electrically connected to MUX2; the control terminal of the fifth transistor T5 in the second first switching circuit 22 of each first data selection circuit 15 is electrically connected to MUX3; the control terminal of the fifth transistor T5 in the second second switching circuit 24 of each first data selection circuit 15 is electrically connected to MUX4; the control terminal of the fifth transistor T5 in the third first switching circuit 22 of each first data selection circuit 15 is electrically connected to MUX5; the control terminal of the fifth transistor T5 in the third second switching circuit 24 of each first data selection circuit 15 is electrically connected to MUX6; the control terminal of the fifth transistor T5 in the fourth first switching circuit 22 of each first data selection circuit 15 is electrically connected to MUX7; and the control terminal of the fifth transistor T5 in the fourth second switching circuit 24 of each first data selection circuit 15 is electrically connected to MUX8.

[0278] In each first data selection circuit 15, the second terminals of the sixth transistor T6 and the seventh transistor T7 in the first first switching circuit 22 and the second terminals of the sixth transistor T6 and the seventh transistor T7 in the first second switching circuit 24 are electrically connected to the same data line 3. The second terminals of the sixth transistor T6 and the seventh transistor T7 in the second first switching circuit 22 and the second terminals of the sixth transistor T6 and the seventh transistor T7 in the second second switching circuit 24 are electrically connected to the same data line 3. The second terminals of the sixth transistor T6 and the seventh transistor T7 in the third first switching circuit 22 and the second terminals of the sixth transistor T6 and the seventh transistor T7 in the third second switching circuit 24 are electrically connected to the same data line 3. The second terminals of the sixth transistor T6 and the seventh transistor T7 in the fourth first switching circuit 22 and the second terminals of the sixth transistor T6 and the seventh transistor T7 in the fourth second switching circuit 24 are electrically connected to the same data line 3.

[0279] In each first data selection circuit 15, the first terminal of the fifth transistor T5 and the first terminal of the sixth transistor T6 in each first switching circuit 22 are electrically connected to the same first data input line D, and the first terminal of the fifth transistor T5 and the first terminal of the sixth transistor T6 in each second switching circuit 24 are electrically connected to the same first data input line D.

[0280] When a pixel island corresponds to 16 viewpoints, the sub-pixels in the same row of each sub-pixel group within the pixel island need to display different display information. In some display scenarios, for example, it could be as follows: Figure 16 As shown, the i-th viewpoint Pi corresponds to Ri, Gi, and Bi in the first pixel island 22, where i is a positive integer less than or equal to 16. The first pixel island and... Figure 12 Taking the electrical connection of the first four first data selection circuits arranged from left to right as an example, in specific implementation, data signals corresponding to viewpoints Pi to P4i and containing strobe levels can be provided to Di sequentially. The fifth transistor T5 of each switch circuit 20 in the first data selection circuit is controlled to turn on sequentially via the first data selection control lines MUX1, MUX3, MUX5, and MUX7. The sixth transistor T6 in each first switch circuit 22 is controlled to turn on sequentially, and the seventh transistor T7 is controlled to turn off sequentially via the data signals containing strobe levels. Simultaneously, the fifth transistor T5 of each second switch circuit 24 is controlled to turn off via the first data selection control lines MUX2, MUX4, MUX6, and MUX8.

[0281] When a pixel island corresponds to 4 viewpoints, the four sub-pixels in each row of the pixel island are displayed together. In some display scenarios, such as... Figure 17As shown, the i-th viewpoint Pi corresponds to R4i-3~R4i, G4i-3~G4i, and B4i-3~B4i in the first pixel island 22, where i is a positive integer less than or equal to 4. In specific implementation, data signals corresponding to viewpoint Pi and containing strobe levels can be sequentially provided to Di. The fifth transistors T5 in the first switching circuit are simultaneously turned on through the first data selection control lines MUX1, MUX3, MUX5, and MUX7. Under the control of the data signals containing strobe levels transmitted through the first data input line, the sixth transistor T6 in the switching circuit electrically connected to MUX1, MUX3, MUX5, and MUX7 is simultaneously turned on, and the seventh transistor T7 is turned off. The fifth transistors T5 in each of the second switching circuits 24 are turned off through the first data selection control lines MUX2, MUX4, MUX6, and MUX8.

[0282] In some display scenarios, such as when the user's eye moves, the subpixel corresponding to the viewpoint shifts... Figure 17 When a rightward translation occurs, when the translation is one sub-pixel, the sub-pixels corresponding to the user's gaze area viewpoint are as follows: Figure 18 As shown. Specifically, a d4 data signal containing a strobe level is input to D0, a d1 data signal containing a strobe level is input to D1, a d2 data signal containing a strobe level is input to D2, a d3 data signal containing a strobe level is input to D3, and a d4 data signal containing a strobe level is input to D4. Simultaneously, a first data selection control signal is provided to MUX2, MUX3, MUX5, and MUX7 to control the fifth transistor T5 in the switching circuit electrically connected to MUX2, MUX3, MUX5, and MUX7 to simultaneously turn on, and under the control of the data signal containing the strobe level, to control the sixth transistor T6 in the switching circuit electrically connected to MUX2, MUX3, MUX5, and MUX7 to simultaneously turn on. Simultaneously, a second data selection control signal is provided to MUX1, MUX4, MUX6, and MUX8 to control the fifth transistor T5 in the switching circuit electrically connected to MUX1, MUX4, MUX6, and MUX8 to turn off.

[0283] In some display scenarios, such as when the user's eye continues to move, the subpixel corresponding to the viewpoint shifts... Figure 18 When the viewpoint is shifted one subpixel to the right again, the subpixels corresponding to the user's gaze area are as follows: Figure 19Specifically, as shown, a data signal containing a strobe level (d4) is input to D0, a data signal containing a strobe level (d1) is input to D1, a data signal containing a strobe level (d2) is input to D2, a data signal containing a strobe level (d3) is input to D3, and a data signal containing a strobe level (d4) is input to D4. Simultaneously, a first data selection control signal is provided to MUX2, MUX4, MUX5, and MUX7 to control the fifth transistor T5 in the switching circuits electrically connected to MUX2, MUX4, MUX5, and MUX7 to turn on simultaneously, and under the control of the data signal containing the strobe level, to control the sixth transistor T6 in the switching circuits electrically connected to MUX2, MUX4, MUX5, and MUX7 to turn on simultaneously. Simultaneously, a second data selection control signal is provided to MUX1, MUX3, MUX6, and MUX8 to control the fifth transistor T5 in the switching circuits electrically connected to MUX1, MUX3, MUX6, and MUX8 to turn off.

[0284] In specific implementation, the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, and seventh transistor mentioned above can all be metal-oxide-semiconductor field-effect transistors (MOS), complementary metal-oxide-semiconductor transistors (CMOS), or thin film transistors (TFT).

[0285] This disclosure provides a display device, as shown in the figure, comprising:

[0286] The display panel provided in the embodiments of this disclosure;

[0287] A cylindrical lens structure is located on the light-emitting side of the display panel; the cylindrical lens structure includes multiple cylindrical lenses arranged in an array.

[0288] The controller, connected to the display panel, is configured to provide independent drive signals to each control zone.

[0289] Based on the same inventive concept, this disclosure also provides a display device, such as... Figure 20 As shown, it includes:

[0290] The display panel 51 provided in this embodiment of the disclosure;

[0291] The cylindrical lens structure 52 is located on the light-emitting side of the display panel 51; the cylindrical lens structure 52 includes multiple cylindrical lenses arranged in an array.

[0292] A controller (not shown), connected to the display panel, is configured to provide independent drive signals to each control zone.

[0293] In some embodiments, such as Figure 20 As shown, the display device also includes:

[0294] A light-transmitting insulating layer 53 is located between the display panel 51 and the lenticular lens structure 52;

[0295] The planarization layer 54 is located on the side of the cylindrical lens structure 52 opposite to the light-transmitting insulating layer 53.

[0296] In some embodiments, when the display panel is a liquid crystal display panel, the display device may further include, for example, a backlight module located away from the cylindrical lens structure of the display panel.

[0297] In some embodiments, it also includes:

[0298] Eye-tracking systems are used to determine in real time where a user's eyes are focused on a display device.

[0299] In practical implementation, during image display, for areas requiring refresh, the controller can drive the control circuit to input normal scanning signals to the scan lines corresponding to the pixel islands. For areas not requiring refresh, the controller can drive the control circuit to input fixed potential signals transmitted via fixed potential lines to the scan lines corresponding to the pixel islands, thereby achieving partitioned driving of the pixel islands and saving display device power consumption. Furthermore, the controller can provide corresponding signals to the first data selection control line and the first data input line to control the independent display of sub-pixels of each pixel island in areas requiring high-resolution display, and to control the combined display of multiple sub-pixels in areas requiring low-resolution display, further saving display device power consumption. In practical implementation, for example, the area the human eye is focused on corresponds to a high refresh rate, high-resolution display area, while the non-focused area corresponds to a low refresh rate, low-resolution display area.

[0300] In practical implementation, since the subpixel subdivision is performed within a pixel island (which can be displayed as a pixel in a two-dimensional image (2D)), the resolution can be maintained in 3D image (3D) display mode, just like in 2D display. Combined with eye-tracking, it can achieve multi-view display with a wide viewing angle and higher pixel density (PPI) 3D display, resulting in more information, lower color crosstalk between adjacent viewpoints, and reduced dizziness when viewing 3D images, thus improving the user experience. When the display device is equipped with a lenticular lens array, the lenticular lens array can not only perform pixel mapping on the subpixels in the pixel island, but also modulate the light field of the emitted light from the pixel island, thereby forming multiple viewpoints from the emitted light of the final pixel island, thus realizing light field 3D display.

[0301] In some embodiments, each pixel island corresponds to M viewpoints; each pixel island corresponds to N cylindrical lenses; where M and N are both positive integers, M>N, and M / N is a non-integer.

[0302] It should be noted that the aperture P of a cylindrical lens, relative to the resolution of the human eye, can achieve a resolution smaller than that of the retina at the point of near-vision distance. This allows it to address the visual fatigue and dizziness caused by convergence conflict, while simultaneously reducing the impact of fixed lenses on 2D displays at the closest viewing range, meeting the requirement that each eye needs to simultaneously receive at least two viewpoints. Where L is the viewing distance, which is typically 250 mm. In practice, each sub-pixel row in a pixel island includes h sub-pixels. Each pixel island can render h corresponding 3D viewpoint maps through multi-grayscale driving. The width P of the pixel island in the direction of the cylindrical lens arrangement is set to achieve the optimal Retina resolution at the 3D viewing distance. To ensure that retinal 3D angular resolution can be obtained.

[0303] In a specific implementation, the display device provided in this embodiment can use a lens unit to divide the pilot point corresponding to the pixel island N times, where M / N is a non-integer, and the aperture of each lens D = N × (L + H), where H is the distance between the display panel and the cylindrical lens.

[0304] In practical implementation, the sub-pixels in the pixel island can be set to emit light continuously. When the colors of all sub-pixels arranged in a row in the first direction are the same, a continuously emitting surface can be formed in the first direction. This can reduce crosstalk between viewpoints while realizing multi-viewpoint light field display, and can also eliminate moiré patterns in 3D display.

[0305] Example 1: For a continuously emitting sub-pixel segmentation unit, when the number of sub-pixels in a pixel island is 16 (i.e., M = h = 16), and when N is 3, the arrangement of a row of sub-pixels in the pixel island and their spatial and temporal distribution are as follows: Figure 21 As shown, for one sub-pixel row of the pixel island, two of the three cylindrical lenses correspond to 5 viewpoints, and the other cylindrical lens corresponds to 6 viewpoints. From Figure 21 As can be seen, when M / N is not an integer, the viewpoints corresponding to each lens do not completely overlap in space, which can avoid interference between viewpoints. Taking viewpoints 1, 2, and 3 as examples, viewpoints 2 and 3 can compensate for the lack of light emission from viewpoint 1 by misaligning the lenses, thereby achieving the effect of avoiding moiré patterns.

[0306] Of course, the sub-pixels in the pixel island can be configured to emit light discontinuously, with the area between adjacent sub-pixels in the first direction X corresponding to a light-blocking area. Taking a liquid crystal display panel as an example, the sub-pixels can be configured to emit light discontinuously, for example, as shown in the example of a liquid crystal display panel. Figure 4 , Figure 5 As shown.

[0307] In some embodiments, each sub-pixel row in the pixel island includes a light-shielding area, and the ratio of the area of ​​the sub-pixel to the area of ​​the light-shielding area is X, where X = N-1.

[0308] When the number of sub-pixels in the pixel island is 16 (M = h = 16), and the ratio of sub-pixels to the light-blocking area is 2:1 (X = 2, N = 3), the arrangement of a row of sub-pixels in the pixel island and their spatial and temporal distribution are as follows: Figure 23 As shown, for one sub-pixel row of the pixel island, two of the three cylindrical lenses correspond to 5 viewpoints, and the other cylindrical lens corresponds to 6 viewpoints. From Figure 22 As can be seen, when M / N is not an integer, the viewpoints corresponding to each lens do not completely overlap in space, which can avoid crosstalk between viewpoints. Taking viewpoints 1, 2, and 3 as examples, ... Figure 22 As shown, the spatial positions of viewpoint 2 in the third lens and viewpoint 1 in the first lens do not completely overlap. At the same time, the spatial positions of viewpoint 2 and viewpoint 3 do not completely overlap. Viewpoint 2 and viewpoint 3 compensate for the lack of light emission from viewpoint 1 by misaligning relative to the lenses, thereby achieving the effect of avoiding moiré patterns.

[0309] It should be noted that, however, the development of 3D display technology is greatly limited by the capabilities of display and optical devices. As a result, naked-eye 3D displays in related technologies generally suffer from limitations such as the inability to move freely while viewing and a limited viewing range. In particular, light field displays have a very small viewing area and range. For medium and large-sized display products, it is usually difficult to achieve close-range viewing of the light field. In addition, there is a trade-off between naked-eye 3D resolution and viewpoint continuity, and the crosstalk between viewpoints is quite serious, which makes the 3D viewpoint image of a single eye relatively blurry and has low contrast.

[0310] In some embodiments, the aperture D of the cylindrical lens and the width P of the pixel island in the cylindrical lens arrangement direction also satisfy the following relationship:

[0311]

[0312] In some embodiments, the width Q of the independent visual area viewed by the user's left and right eyes satisfies the following condition:

[0313]

[0314] Where E is the interpupillary distance of the user's eyes, and A is the number of cylindrical lenses between the pixel islands corresponding to the left and right eye viewpoints.

[0315] In some embodiments, the width Q of the independent visual area viewed by the user's left and right eyes also satisfies the following condition:

[0316]

[0317] Where e represents the user's pupil size. The typical pupil size e is approximately 3mm to 5mm.

[0318] In some embodiments, each sub-pixel row in a pixel island includes h sub-pixels of the same color. When using a single pupil 2-view, i.e., when h = 16, M = 2, e = 5mm, and one viewpoint corresponds to one cylindrical lens, then Q = 125mm, meaning that the left and right eye viewpoint pixels can be projected through the spacer lens to the independent visual areas Q corresponding to the left and right eyes respectively. The specific optical path is as follows... Figure 23 As shown in the diagram, the pixel island is divided into 16 sub-pixels, with 8 sub-pixels corresponding to the left and right eyes respectively. In the diagram, the black sub-pixels represent the left eye, and the white sub-pixels represent the right eye. The images are projected onto the left and right eyes through two lenses spaced two lenses apart. Figure 23 As shown, the central area between the left and right eyes is 4Q, which means the central area between the left and right eyes is 60mm.

[0319] In some embodiments, each sub-pixel row in a pixel island includes h sub-pixels of the same color. When using a single pupil 4-view, i.e., when h = 16, M = 4, and e = 5mm, then Q = 10mm. The left and right eye viewpoint pixels can be projected through a spacer lens to the independent visual areas Q corresponding to the left and right eyes, respectively. The specific optical path is as follows: Figure 24 As shown, each eye corresponds to 8 sub-pixels. In the diagram, the black sub-pixels represent the left eye, and the white sub-pixels represent the right eye. The images are projected onto the left and right eyes through two lenses spaced two lenses apart. Figure 24 As shown, the central area between the left and right eyes is 6Q, which means the central area between the left and right eyes is 60mm.

[0320] Regardless of how many viewpoints a single pixel island corresponds to, the display device provided in this embodiment can achieve a light field display of approximately 60mm in the central area between the left and right eyes. This allows for the generation of multi-depth light field images when viewed in the central area, enabling single-eye focus adjustment, and achieving low-crosstalk, multi-viewpoint 3D display outside the central area, thus reproducing 3D information from different angles. In specific implementations, a human eye tracking system can be used to provide feedback on the user's viewing position. The eye coordinates received by the feedback unit from the tracking system are used to adjust the panel drive, thereby adjusting the image rendering mode and achieving low-crosstalk, multi-viewpoint 3D display in both the central light field and outside the central area.

[0321] In some embodiments, such as Figure 25 , Figure 27 As shown, the controller 40 includes:

[0322] The data parsing circuit 36 ​​is configured to parse the image to be displayed and obtain image parsing data;

[0323] Data configuration circuit 37 is configured to generate a data drive signal corresponding to the control area of ​​the display panel based on the current display mode and image parsing data;

[0324] The timing control circuit 38 is configured to generate a gate drive signal for the gate drive circuit based on the current display mode and the viewing area and non-viewing area of ​​the display panel.

[0325] In a practical implementation, the controller also includes a display mode setting circuit 39, which is used to determine the current display mode based on image parsing data.

[0326] In practice, the display mode can be either 2D or 3D. 3D displays include light field displays and multi-viewpoint light field displays.

[0327] In some embodiments, such as Figure 25As shown, the controller is a Field Programmable Gate Array (FPGA) chip.

[0328] In practical implementation, the output of the FPGA's timing control circuit is electrically connected to the gate drive circuit in the display panel. The FPGA's data configuration circuit can, for example, provide corresponding signals to the first data input line and the first data selection control line in the display panel.

[0329] Alternatively, in some embodiments, such as Figure 26 As shown, the controller is a timing controller (TCON).

[0330] In practical implementation, the TCON display mode setting circuit is also used to perform coordinate analysis and image processing based on image analysis data, and the data configuration circuit decompresses the processed data and configures the data drive signal corresponding to the control area of ​​the display panel.

[0331] In practical implementation, the output of the timing control circuit of TCON is electrically connected to the gate drive circuit in the display panel. The data configuration circuit of TCON can, for example, provide corresponding signals to the first data input line and the first data selection control line in the display panel.

[0332] In specific implementation, such as Figure 27 As shown, the controller can first drive and refresh the gaze area 41 (while the non-gaze area is not refreshed), and then drive and refresh the two non-gaze areas 42 on both sides. Image coordinates, display mode, and lens data are encoded using a 1-line display. The gaze area resolution is not compressed, while the non-gaze area resolution is compressed by 1 / 4 in horizontal / vertical pixels. These three are then concatenated and transmitted from top to bottom. This scheme allows the gaze area and non-gaze area to be driven independently, achieving a maximum data compression ratio of 1:10.7.

[0333] Taking a 16-viewpoint multi-view light field 3D display as an example, the resolution of the non-focused area is compressed by 1 / 4. That is, the system compresses 4x4 pixel islands into 1 pixel island and transmits the data to the controller. The controller copies the data of the pixel island to the three adjacent pixel islands, and the four rows of pixel islands in the second direction are activated simultaneously, so that the 4x4 pixel islands in the non-focused area are written with the same pixel island data.

[0334] In practical implementation, for 2D displays and multi-viewpoint light field 3D displays, a controller can be used to implement row-driven, column-driven, and control area selection-driven modes. Row-driven mode allows the gaze area to open row by row, while multiple rows in the non-gaze area can open simultaneously. Column-driven mode controls multiple columns to open simultaneously or shift between columns via a first data selection circuit. Control area selection-driven mode uses a control circuit for area selection control. For ordinary light field 3D displays, a controller can also implement row-driven, column-driven, and control area selection-driven modes. Row-driven mode allows the gaze area to open row by row, while multiple rows in the non-gaze area can open simultaneously. Column-driven mode opens column by column via a first data selection circuit. Control area selection-driven mode uses a control circuit for area selection control. In practical implementation, the controller can be used to adjust the driving mode in real time.

[0335] In some embodiments, the eye-tracking system includes:

[0336] An image acquisition circuit includes: multiple first cameras and at least one second camera; the resolution of the first cameras is greater than the resolution of the second camera; the first cameras are configured to acquire images of the user's pupils, and the second camera is configured to acquire images of the user's face;

[0337] The camera calibration circuit is configured to calibrate the first camera and the second camera to obtain the internal parameter matrix and external parameter matrix of the first camera and the second camera;

[0338] The camera time-division and zone control circuit is configured to control the shooting sequence of multiple first cameras, so as to realize that multiple first cameras can acquire images in a cyclical and alternating manner;

[0339] The face detection circuit is configured to: search for face bounding boxes in the image captured by the second camera, detect face feature points, obtain the eye region within the face bounding box, and then obtain the spatial coordinate transformation matrix of the eye region through the mapping relationship between the face feature points and the standard face model;

[0340] The image coordinate system transformation circuit is configured to: transform the face image coordinate system into the pupil image coordinate system, or transform the pupil coordinate system into the face image coordinate system;

[0341] The pupil detection circuit is configured to: calculate the pupil coordinates in the image captured by the first camera; based on the eye region coordinates obtained by the face detection circuit, transform them to the pupil image coordinate system through the coordinate transformation circuit to obtain the eye region on the pupil image; perform pupil detection within the eye region to obtain the pupil coordinates in the pupil image coordinate system.

[0342] The spatial coordinate calculation circuit is configured to: transform the pupil coordinates to the face image coordinate system, and then calculate the pupil coordinates in three-dimensional space through the spatial coordinate transformation matrix obtained by the face detection circuit;

[0343] The spatial gaze tracking circuit is configured to: determine the eyeball center coordinates based on the pupil coordinates and a preset human eye model; calculate the direction vectors of the pupil coordinates and the eyeball center coordinates as line vectors; obtain the gaze intersection point between the human eye and the display panel based on the distance from the human eye to the display panel and the equation of the plane on which the display panel is located; and obtain the coordinates of the human eye's gaze point on the display panel based on the gaze focus.

[0344] The eye-tracking system for a display device provided in this disclosure, combined with multiple cameras, enables variable-rate spatial pupil detection and 3D coordinate calculation. The image acquisition circuit includes multiple cameras of different resolutions. Utilizing face detection algorithms, pupil detection algorithms, and coordinate system transformation algorithms, it can accurately and quickly obtain the pupil coordinates in 3D space. This solves the problems of low frame rate, poor detection accuracy, and small detection area in traditional single-camera pupil detection. It improves detection accuracy, thereby increasing the accuracy of gaze area determination.

[0345] In practical implementation, the image acquisition circuit may include, for example, three first cameras and one second camera. The first cameras may be infrared (IR) cameras, and the second camera may be a red-green-blue (RGB) camera. For example, the RGB camera has a field of view (FOV) of 80°, a frame rate of 120 frames per second (fps), and a resolution of 640×480. Among the three IR cameras, the cameras on both sides have an FOV of 60°, and the camera in the middle has an FOV of 30°. The resolution of each IR camera is 1280×960, and the frame rate is 30fps. In addition, four infrared LED light sources may be arranged around each IR camera.

[0346] In practical implementation, the camera time-division and zone control circuit controls the shooting sequence of multiple first cameras, enabling multiple first cameras to acquire images in a cyclical alternation, while ensuring that the human eye tracking system can continuously output spatial pupil coordinates at equal intervals.

[0347] In some embodiments, such as Figure 28 The human eye tracking system includes cameras 43, each of which is mounted on the top of the display device.

[0348] In some embodiments, such as Figure 28 As shown, the display device also includes an image rendering system 44 electrically connected to the controller 40 and the display panel 51.

[0349] In some embodiments, the image rendering system includes:

[0350] The coordinate extraction circuit is configured to: determine the three-dimensional spatial coordinates of the human eye relative to the display panel based on the position of the human eye's line of sight on the display panel in the display device, which is determined by the human eye tracking system;

[0351] The lens bonding detection circuit is configured to: obtain the bonding error of the cylindrical lens, adjust the bonding parameters of the cylindrical lens according to the bonding error, and obtain the viewpoint crosstalk curve.

[0352] The image rendering circuit is configured to: generate a multi-view initial image based on the image to be displayed; and to optimize the multi-view initial image based on the human eye position, fit detection parameters, and crosstalk curve to obtain an optimized multi-view image as the image to be displayed.

[0353] The display device provided in this embodiment includes an image rendering system paired with an eye-tracking system to determine the three-dimensional spatial coordinates of the human eye relative to the display panel. It also includes a lens fitting detection circuit that can detect lens fitting based on the display device's vision, obtaining fitting errors and crosstalk, and providing corresponding parameters for subsequent image rendering optimization. This results in more accurate image rendering and improved display performance.

[0354] In some embodiments, the image rendering system further includes: a subpixel mapping and control circuit: for mapping 3D image subpixels to the controller and determining control rules for the image to be displayed after optimization by the image rendering circuit.

[0355] In practical implementation, the lens bonding detection circuit works as follows: First, the lens bonding parameters are designed based on grating bonding theory; then, after determining the display mode, the camera shooting position is initialized. Next, the lens bonding parameters and the viewpoint crosstalk curve are simultaneously determined.

[0356] The determination of lens bonding parameters includes:

[0357] Repeat the following steps until the image analysis results meet the preset requirements: adjust the fitting parameters according to the camera acquisition results, acquire images again using the camera, and perform image analysis including brightness uniformity analysis;

[0358] If the analysis results meet the preset requirements, the current bonding parameters will be determined as the final lens bonding parameters.

[0359] The determination of the viewpoint crosstalk curve includes:

[0360] Repeat the following steps until the image analysis results meet the preset conditions: For images displaying different viewpoints, acquire images through a camera and perform image analysis including crosstalk curve fitting;

[0361] If the image analysis results meet the preset conditions, the currently fitted crosstalk curve will be used as the viewpoint crosstalk curve.

[0362] In practical implementation, for example, the following viewpoint crosstalk surface formula can be used to fit the crosstalk curve:

[0363]

[0364] Where x is the position coordinate of the sub-pixel in the first direction, and y is the position coordinate of the sub-pixel in the second direction.

[0365] It should be noted that when the controller determines the display mode to be 3D, 3D image rendering is required using the image rendering system. When the controller determines the display mode to be 2D, image rendering is not required.

[0366] The display device provided in this disclosure is any product or component with display function, such as a television or monitor. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure. Implementation of this display device can be referred to the above-described embodiments of the display panel; repeated details will not be elaborated upon.

[0367] Based on the same inventive concept, this disclosure also provides a driving method for a display device, such as... Figure 29 As shown, the method includes:

[0368] S101. Real-time determination of the user's gaze area and non-gaze area on the display device;

[0369] S102, independently drive the control area corresponding to the gaze region to display the image at a first resolution, and drive the control area corresponding to the non-gaze region to display the image at a second resolution; wherein, the first resolution is higher than the second resolution.

[0370] In some embodiments, step S101 determines in real time the user's gaze area and non-gaze area on the display device, specifically including:

[0371] The system uses eye-tracking technology to determine the area where the user's eyes are focused on the display device.

[0372] The area in the display device other than the gaze area is defined as the non-gaze area.

[0373] In some embodiments, obtaining the area of ​​the user's gaze on the display device through an eye-tracking system specifically includes:

[0374] The system controls the first camera in the eye-tracking system to alternately acquire images of the user's pupils, and controls the second camera in the eye-tracking system to acquire images of the user's face.

[0375] Search for face bounding boxes in the images captured by the second camera, detect face feature points, obtain the eye region within the face bounding box, and then obtain the spatial coordinate transformation matrix of the eye region through the mapping relationship between face feature points and the standard face model.

[0376] Transform the face image coordinate system into the pupil image coordinate system, or convert the pupil coordinate system into the face image coordinate system;

[0377] Calculate the pupil coordinates in the image captured by the first camera; transform the coordinates of the human eye region to the pupil image coordinate system to obtain the human eye region on the pupil image; perform pupil detection within the human eye region on the pupil image to obtain the pupil coordinates in the pupil image coordinate system.

[0378] The pupil coordinates are transformed to the face image coordinate system, and then the spatial coordinate transformation matrix is ​​used to calculate the pupil coordinates in three-dimensional space.

[0379] The coordinates of the eyeball center are determined based on the pupil coordinates and a preset human eye model.

[0380] Calculate the direction vectors of the pupil coordinates and the eyeball center coordinates, and use them as line vectors;

[0381] The intersection of the line of sight between the human eye and the display panel is obtained based on the distance from the human eye to the display panel and the equation of the plane on which the display panel is located;

[0382] Based on the focal point of the gaze, the coordinates of the human eye's gaze point on the display panel are obtained, and the area where the human eye's gaze point coordinates are located on the display panel is determined as the gaze area.

[0383] In practical implementation, for example, while the second camera is acquiring images, the shooting sequence of multiple first cameras can be controlled by the camera time-division and zone control circuit, so that multiple first cameras can acquire images in a cyclical alternation.

[0384] In some embodiments, independently driving the control area corresponding to the gaze region to display an image at a first resolution, and driving the control area corresponding to the non-gaze region to display an image at a second resolution, specifically includes:

[0385] Based on the display mode, the gaze area, and the non-gaze area, determine the display information of each sub-pixel in the pixel island of the control area corresponding to the gaze area, and determine the display information of each sub-pixel in the pixel island of the control area corresponding to the non-gaze area.

[0386] Based on the displayed information, a data signal corresponding to the displayed information is provided to the first data input line, and a first data selection control signal is provided to the first data selection control line. Through the first data selection circuit, the data signal provided by the first data write line is provided to the data line corresponding to the first data selection circuit.

[0387] When the multiplexer includes f switching transistors:

[0388] In some embodiments, when each sub-pixel in a sub-pixel row of a pixel island corresponds to a viewpoint, and each first data selection circuit includes a first multiplexer and a second multiplexer, the first multiplexer includes f third transistors, and the second multiplexer includes f fourth transistors; a first data selection control signal is provided to the first data selection control line, and the data signal provided by the first data write line is provided to the data line corresponding to the first data selection circuit through the first data selection circuit, specifically including:

[0389] A first data selection control signal is provided to multiple first data selection control lines electrically connected to each third transistor to control f third transistors in each first data selection circuit to turn on sequentially, transmitting the data signal of the first data input line electrically connected to the first electrode of the f third transistors to the data line electrically connected to the second electrode of the f third transistors; at the same time, a second data selection control signal is provided to multiple first data selection control lines electrically connected to each fourth transistor to control f fourth transistors in each first data selection circuit to turn off.

[0390] In some embodiments, when the third transistor in the third transistor and the fourth transistor in the fourth transistor are transistors of the same type, the first data selection control signal that controls the selection switch to turn on is a high-level signal, and the second data selection control signal that controls the selection switch to turn off is a low-level signal; or the first data selection control signal that controls the selection switch to turn on is a low-level signal, and the second data selection control signal that controls the selection switch to turn off is a high-level signal.

[0391] In some embodiments, each row of subpixels in a pixel island is divided into a subpixel groups, where a = h / f, and each subpixel group includes f adjacent subpixels; when f adjacent subpixels in a subpixel row of a pixel island correspond to a viewpoint, and each first data selection circuit includes a first multiplexer and a second multiplexer, the first multiplexer includes f third transistors, and the second multiplexer includes f fourth transistors; a first data selection control signal is provided to the first data selection control line, and the data signal provided by the first data write line is provided to the data line corresponding to the first data selection circuit through the first data selection circuit, specifically including:

[0392] When the display information of each sub-pixel in each sub-pixel group is the same, a first data selection control signal is provided to f first data selection control lines electrically connected to each third transistor to control the f third transistors in each first data selection circuit to be turned on simultaneously, and the data signal of the first data input line electrically connected to the first electrode of the f third transistors is transmitted to the data line electrically connected to the second electrode of the f third transistors; at the same time, a second data selection control signal is provided to f first data selection control lines electrically connected to each fourth transistor to control the f fourth transistors in each first data selection circuit to be turned off.

[0393] In some embodiments, each row of subpixels in a pixel island is divided into a subpixel groups, where a = h / f, and each subpixel group includes f adjacent subpixels; when f adjacent subpixels in a subpixel row of a pixel island correspond to a viewpoint, and each first data selection circuit includes a first multiplexer and a second multiplexer, the first multiplexer includes f third transistors, and the second multiplexer includes f fourth transistors; providing a first data selection control signal to the first data selection control line, and providing the data signal provided by the first data write line to the data line corresponding to the first data selection circuit through the first data selection circuit, further comprising:

[0394] When the display information of the first to the (g-1)th sub-pixels in a group of sub-pixels is the same, the display information of the g to the fth sub-pixels is the same, and the display information of the (g-1)th sub-pixel is different from the display information of the gth sub-pixel, a first data selection control signal is provided to the first data selection control line electrically connected to the first to the (g-1)th fourth transistors and the g to the fth third transistors to control the first to the (g-1)th fourth transistors and the g to the fth third transistors in each first data selection circuit to be turned on simultaneously, and the data signal of the first data input line electrically connected to the first pole of the first to the (g-1)th fourth transistors and the first pole of the g to the fth third transistors is transmitted to the data line electrically connected to the second pole of the first to the (g-1)th fourth transistors and the second pole of the g to the fth third transistors.

[0395] Simultaneously, a second data selection control signal is provided to the first data selection control line electrically connected to the 1st to g-1st third transistors and the gth to fth fourth transistors to control the 1st to g-1st third transistors and the gth to fth fourth transistors in each first data selection circuit to turn off.

[0396] The driving method for the display device provided in this disclosure can not only make the display information of the sub-pixels smoothly transition with the movement of the human eye when the position of the human eye changes, but also improve the display effect and enhance the user experience.

[0397] When the multiplexer includes f switching circuits:

[0398] In some embodiments, providing a data signal corresponding to the displayed information to the first data input line specifically includes:

[0399] Provide a data signal corresponding to the display information and containing a strobe level to the first data input line.

[0400] In some embodiments, when each sub-pixel in a sub-pixel row of a pixel island corresponds to a viewpoint, and each first data selection circuit includes a first multiplexer and a second multiplexer, the first multiplexer includes f first switching circuits, and the second multiplexer includes f second switching circuits; a first data selection control signal is provided to the first data selection control line, and the data signal provided by the first data write line is provided to the data line corresponding to the first data selection circuit through the first data selection circuit, specifically including:

[0401] A first data selection control signal is provided to multiple first data selection control lines electrically connected to each first switching circuit to control the fifth transistor in each of the f first switching circuits to turn on sequentially. Under the control of a data signal containing a pass level, the data signal of the first data input line electrically connected to the f first switching circuits is transmitted to the data line electrically connected to the f first switching circuits. At the same time, a second data selection control signal is provided to multiple first data selection control lines electrically connected to each second switching circuit to control the fifth transistor in each of the f second switching circuits to turn off.

[0402] In some embodiments, the first data selection control signal for turning on the fifth transistor in the control switch circuit is a high-level signal, and the second data selection control signal for turning off the fifth transistor in the control switch circuit is a low-level signal; or the first data selection control signal for turning on the fifth transistor in the control switch circuit is a low-level signal, and the second data selection control signal for turning off the fifth transistor in the control switch circuit is a high-level signal.

[0403] In some embodiments, each row of subpixels in a pixel island is divided into a subpixel groups, where a = h / f, and each subpixel group includes f adjacent subpixels; when f adjacent subpixels in a subpixel row of a pixel island correspond to a viewpoint, and each first data selection circuit includes a first multiplexer and a second multiplexer, the first multiplexer includes f first switching circuits, and the second multiplexer includes f second switching circuits; a first data selection control signal is provided to the first data selection control line, and the data signal provided by the first data write line is provided to the data line corresponding to the first data selection circuit through the first data selection circuit, specifically including:

[0404] When the display information of each sub-pixel in each sub-pixel group is the same, a first data selection control signal is provided to the f first data selection control lines electrically connected to each first switch circuit to control the fifth transistors in the f first switch circuits in each first data selection circuit to be turned on simultaneously. Under the control of the data signal containing the strobe level, the data signal of the first data input line electrically connected to the f first switch circuits is transmitted to the data line electrically connected to the f first switch circuits. At the same time, a second data selection control signal is provided to the f first data selection control lines electrically connected to each second switch circuit to control the fifth transistors in the f second switch circuits in each first data selection circuit to be turned off.

[0405] In some embodiments, each row of subpixels in a pixel island is divided into a subpixel groups, where a = h / f, and each subpixel group includes f adjacent subpixels; when f adjacent subpixels in a subpixel row of a pixel island correspond to a viewpoint, and each first data selection circuit includes a first multiplexer and a second multiplexer, the first multiplexer includes f first switching circuits, and the second multiplexer includes f second switching circuits; providing a first data selection control signal to the first data selection control line, and providing the data signal provided by the first data write line to the data line corresponding to the first data selection circuit through the first data selection circuit, further comprising:

[0406] When the display information of the first to the (g-1)th sub-pixels in a group of sub-pixels is the same, the display information of the g to the fth sub-pixels is the same, and the display information of the (g-1)th sub-pixel is different from that of the gth sub-pixel, a first data selection control signal is provided to the first data selection control line electrically connected to the first to the (g-1)th second switch circuits and the g to the fth first switch circuits, so as to control the fifth transistor T5 of the first to the (g-1)th second switch circuits and the fifth transistor T5 of the g to the fth first switch circuits in each first data selection circuit to be turned on simultaneously. Under the control of the data signal containing the strobe level, the data signal of the first data input line electrically connected to the first to the (g-1)th second switch circuits and the g to the fth first switch circuits is transmitted to the data line electrically connected to the first to the (g-1)th second switch circuits and the g to the fth first switch circuits.

[0407] Simultaneously, a second data selection control signal is provided to the first data selection control line electrically connected to the first to g-1 first switching circuits and the g to f second switching circuits to control the fifth transistor T5 in the first to g-1 first switching circuits and the fifth transistor T5 in the g to f second switching circuits in each first data selection circuit to be turned off.

[0408] In some embodiments, independently driving the gaze region to display an image at a first resolution and driving the non-gaze region to display an image at a second resolution further includes:

[0409] The controller of the display device provides a gate driving signal to the gate driving circuit of the display panel to control the corresponding multi-row pixel islands in the viewing area to open row by row, and control the F rows of pixel islands in the corresponding multi-row pixel islands in the non-viewing area to open synchronously, where F is a positive integer and F is equal to the ratio of the first resolution to the second resolution.

[0410] In some embodiments, such as Figure 30 As shown, the gate driving circuit of the display panel includes multiple gate driving groups, each gate driving group includes B gate driving subgroups, and each gate driving subgroup includes C shift registers; where B and C are integers greater than 1.

[0411] The controller of the display device provides gate drive signals to the gate drive circuit of the display panel, specifically including:

[0412] The controller provides clock control signals to the gate drive groups so that in each gate drive group, the multiple shift registers in the gate drive subgroup are sequentially input with enable signals in the order of the first to the Bth gate drive subgroups.

[0413] In practical implementation, taking an example where each sub-pixel row in a pixel island includes 12 sub-pixels, such as... Figure 30 As shown, one gate drive group includes, for example, three gate drive subgroups, each including four shift registers (GOA). Specifically, the first gate drive subgroup includes GOA1, GOA4, GOA7, and GOA10; the second gate drive subgroup includes GOA2, GOA5, GOA8, and GOA11; and the third gate drive subgroup includes GOA3, GOA6, GOA9, and GOA12. In a specific implementation, as... Figure 30 As shown, the first gate driver subgroup is electrically connected to eight start / stop signal lines CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8. The enable signal line STV is electrically connected to GOA1, GOA4, GOA7, and GOA10 in the first gate driver subgroup. This means that the pixel islands corresponding to GOA1, GOA4, GOA7, and GOA10 are enabled row by row, followed by the pixel islands corresponding to GOA2, GOA5, GOA8, and GOA11, and then the pixel islands corresponding to GOA3, GOA6, GOA9, and GOA12. This configuration saves system resources in the display device.

[0414] The timing diagram when the pixel islands are driven row by row using the gate driving circuit is as follows: Figure 31 As shown, the timing diagram when the gate driving circuit drives two rows of pixel islands to be turned on simultaneously is as follows: Figure 32 As shown.

[0415] In some embodiments, the driving method further includes:

[0416] The gaze area is driven to display an image at a first refresh rate, and the non-gaze area is driven to display an image at a second refresh rate, wherein the first refresh rate is higher than the second refresh rate.

[0417] In some embodiments, driving the gaze area to display an image at a first refresh rate and driving the non-gaze area to display an image at a second refresh rate specifically includes:

[0418] Drive each sub-pixel within the gaze area to refresh Z times;

[0419] Drive each sub-pixel within the non-focused area to refresh Y times;

[0420] Where Z and Y are positive integers, and Z is greater than Y.

[0421] In some embodiments, driving each sub-pixel within the gaze area to refresh specifically includes:

[0422] Each scan signal input line corresponding to the driving gaze area sequentially transmits an effective level signal;

[0423] Control each control signal line to transmit control signals, and transmit the signal provided by the scan signal input line to the scan line corresponding to the gaze area to the scan line corresponding to the non-gaze area.

[0424] Drive the refresh of each sub-pixel within the non-focused region, including:

[0425] Each scan signal input line within the drive display panel sequentially transmits a valid level signal;

[0426] When the scan detects each sub-pixel row corresponding to the gaze area, the control signal lines transmit control signals, transmitting the signal provided by the fixed potential line to the scan line corresponding to the gaze area, and transmitting the signal provided by the scan signal input line to the scan line corresponding to the non-gaze area.

[0427] In practical implementation, when the control stage of the first transistor and the control stage of the second transistor are electrically connected to the same control signal line;

[0428] Controlling the transmission of control signals on each control signal line involves transmitting the signal provided by the scan signal input line to the scan line corresponding to the gaze area, and transmitting the signal provided by the fixed potential line to the scan line corresponding to the non-gaze area. Specifically, this includes:

[0429] The control signal lines driving the gaze area transmit the first control signal, and the control signal lines driving the non-gazing area transmit the second control signal, so as to control the first transistor in the gaze area to turn on and the second transistor to turn off, and the first transistor in the non-gazing area to turn off and the second transistor to turn on. The signal provided by the scan signal input line is transmitted to the scan line corresponding to the control area through the first transistor in the control area, and the signal provided by the fixed potential line is transmitted to the scan line corresponding to the non-gazing area through the second transistor in the non-gazing area.

[0430] When the scan detects each sub-pixel row corresponding to the gaze area, the control signal lines transmit control signals, transferring the signal provided by the fixed potential line to the scan line corresponding to the gaze area and the signal provided by the scan signal input line to the scan line corresponding to the non-gaze area. Specifically, this includes:

[0431] The control signal lines driving the gaze area transmit the second control signal, and the control signal lines driving the non-gazing area transmit the first control signal, so as to control the first transistor in the gaze area to turn off and the second transistor to turn on, and the first transistor in the non-gazing area to turn on and the second transistor to turn off. The signal provided by the scan signal input line is transmitted to the scan line corresponding to the non-control area through the first transistor in the non-control area, and the signal provided by the fixed potential line is transmitted to the scan line corresponding to the gaze area through the second transistor in the gaze area.

[0432] In specific implementation, when the first transistor is a P-type transistor and the second transistor is an N-type transistor, the first control signal is a low-level signal and the second control signal is a high-level signal; when the first transistor is an N-type transistor and the second transistor is a P-type transistor, the first control signal is a high-level signal and the second control signal is a low-level signal.

[0433] In a specific implementation, when the control stage of the first transistor is electrically connected to the first control signal line and the control stage of the second transistor is electrically connected to the second control signal line;

[0434] Controlling the transmission of control signals on each control signal line involves transmitting the signal provided by the scan signal input line to the scan line corresponding to the gaze area, and transmitting the signal provided by the fixed potential line to the scan line corresponding to the non-gaze area. Specifically, this includes:

[0435] Each first control signal line driving the gaze area transmits a first control signal, and each second control signal line driving the non-gazing area transmits a third control signal, and each second control signal line driving the non-gazing area transmits a fourth control signal, so as to control the first transistor in the gaze area to turn on and the second transistor to turn off, and the first transistor in the non-gazing area to turn off and the second transistor to turn on. The signal provided by the scan signal input line is transmitted to the scan line corresponding to the control area through each first transistor in the control area, and at the same time the signal provided by the fixed potential line is transmitted to the scan line corresponding to the non-gazing area through the second transistor in the non-gazing area.

[0436] When the scan detects each sub-pixel row corresponding to the gaze area, the control signal lines transmit control signals, transferring the signal provided by the fixed potential line to the scan line corresponding to the gaze area and the signal provided by the scan signal input line to the scan line corresponding to the non-gaze area. Specifically, this includes:

[0437] Each first control signal line driving the gaze area transmits a third control signal, and each second control signal line driving the non-gazing area transmits a first control signal, and each second control signal line driving the non-gazing area transmits a second control signal. This controls the first transistor in the gaze area to turn off and the second transistor to turn on, and the first transistor in the non-gazing area to turn on and the second transistor to turn off. The signal provided by the scan signal input line is transmitted to the scan line corresponding to the non-control area through each first transistor in the non-control area. At the same time, the signal provided by the fixed potential line is transmitted to the scan line corresponding to the gaze area through the second transistor in the gaze area.

[0438] In some embodiments, when both the first transistor and the second transistor are P-type transistors, the first control signal and the fourth control signal are low-level signals, and the second control signal and the third control signal are high-level signals. When both the first transistor and the second transistor are N-type transistors, the first control signal and the fourth control signal are high-level signals, and the second control signal and the third control signal are low-level signals. When the first transistor is a P-type transistor and the second transistor is an N-type transistor, the first control signal and the second control signal are low-level signals, and the third control signal and the fourth control signal are high-level signals; when the first transistor is an N-type transistor and the second transistor is a P-type transistor, the first control signal and the second control signal are high-level signals, and the third control signal and the fourth control signal are low-level signals.

[0439] Based on the same inventive concept, this disclosure also provides an image rendering method for a display device, such as... Figure 33 As shown, the method includes:

[0440] S201. Determine the position of the human eye's line of sight on the display panel in the display device, and determine the three-dimensional spatial coordinates of the human eye relative to the display panel;

[0441] S202. Generate a multi-viewpoint initial image based on the image to be displayed;

[0442] S203. Perform cylindrical lens array bonding test on the display device to obtain the bonding error of the cylindrical lens and the viewpoint crosstalk curve.

[0443] S204. Optimize the initial multi-view image based on the human eye position, fit detection parameters, and crosstalk curve to obtain the optimized multi-view image;

[0444] S205. Transmit the optimized multi-view image to the controller.

[0445] The image rendering method for a display device provided in this disclosure utilizes an image rendering system in conjunction with an eye-tracking system to determine the three-dimensional spatial coordinates of the human eye relative to the display panel. Through a lens bonding detection circuit, lens bonding detection based on the display device's vision is performed to obtain bonding errors and crosstalk, providing corresponding parameters for subsequent image rendering optimization. This results in more accurate image rendering and improved display performance.

[0446] In summary, the display panel, display device, driving method for the display device, and image rendering method for the display device provided in this disclosure, since multiple pixel islands are divided into multiple control areas, and each control area is driven to emit light independently, can achieve zoned control of the resolution and refresh rate of the display panel according to the display screen. When the resolution of the display panel is zoned, it can be divided into high-definition and low-definition areas, with the high-definition area having a higher resolution than the low-definition area. For example, this can improve the resolution of the area viewed by the human eye, thereby enhancing the display effect. When the refresh rate of the display panel is zoned, it can be divided into high-refresh-rate and low-refresh-rate areas, thereby saving power consumption of the display product.

[0447] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0448] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A display panel, wherein, The display panel includes: First substrate; Multiple scan lines are located on one side of the first substrate, extending along a first direction and arranged along a second direction; the first direction and the second direction intersect. Multiple data lines are located on the same side of the first substrate as the scan lines, and the multiple data lines extend along the second direction and are arranged along the first direction; Multiple sub-pixels are located in areas divided by multiple scan lines and multiple data lines; the multiple sub-pixels constitute multiple pixel islands; the multiple pixel islands are divided into multiple control regions, each control region includes at least one pixel island, and each control region is independently driven to emit light; The display panel is divided into a display area and a peripheral area surrounding the display area. The pixel island is located in the display area, and the scan line and the data line extend from the display area to the peripheral area. The display panel also includes: Multiple first data selection control lines, multiple first data input lines, and multiple first data selection circuits are located in the surrounding area; Each first data selection circuit includes at least two multiplexers; in each first data selection circuit, the input terminals of different multiplexers are electrically connected to different first data input lines, the control terminals of different multiplexers are electrically connected to different first data selection control lines, and the i-th output terminal of different multiplexers is electrically connected to the same data line, where i is a positive integer; in two adjacent first data selection circuits, the two multiplexers electrically connected to different first data selection control lines are electrically connected to the same first data input line; the first data selection circuit is configured to: under the control of multiple first data selection control lines, provide the signal of the corresponding first data input line to each of the electrically connected data lines respectively.

2. The display panel according to claim 1, wherein, The display panel also includes: Multiple scan signal input lines, each corresponding to a scan line, extend along the first direction and are arranged along the second direction; Multiple control signal lines are arranged along the first direction; Multiple fixed potential lines; Multiple control circuits are located between adjacent sub-pixels; each pixel island is connected to at least n control circuits, where n is the number of sub-pixel rows included in the pixel island; each control circuit corresponds to a row of sub-pixels in the pixel island. The control circuit is configured to transmit the signal provided by the scan signal input line or the signal provided by the fixed potential line to the scan line under the control of the control signal line; At least a portion of the multiple control signal lines includes: multiple portions extending along the second direction and multiple portions extending along the first direction; the portions extending along the second direction and the portions extending along the first direction are alternately connected.

3. The display panel according to claim 2, wherein, The control circuit includes: a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to a control signal line, the first electrode of the first transistor is electrically connected to the scan signal input line, and the second electrode of the first transistor is electrically connected to the scan line. The control electrode of the second transistor is electrically connected to a control signal line, the first electrode of the second transistor is electrically connected to the fixed potential line, and the second electrode of the second transistor is electrically connected to the scan line.

4. The display panel according to claim 3, wherein, The control electrode of the first transistor and the control electrode of the second transistor are electrically connected to the same control signal line; The first transistor is an N-type transistor and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

5. The display panel according to claim 3, wherein, The control electrode of the first transistor and the control electrode of the second transistor are electrically connected to different control signal lines.

6. The display panel according to any one of claims 2 to 5, wherein, The display panel further includes: a gate driving circuit; The gate drive circuit includes multiple cascaded shift registers, one of which is electrically connected to each of the scan signal input lines in a row of the control area.

7. The display panel according to claim 6, wherein, Each scan line includes a plurality of sub-scan lines arranged along the first direction and disconnected from each other; the number of sub-scan lines in each scan line is the same as the number of control regions arranged in the first direction, and each sub-scan line corresponds to a row of sub-pixels of one control region.

8. The display panel according to claim 2, wherein, Each sub-pixel row in the pixel island includes h sub-pixels, and each sub-pixel row is divided into a sub-pixel groups, each sub-pixel group including f sub-pixels, where a = h / f, and a, h, and f are all positive integers greater than 1. Each sub-pixel group is connected to a plurality of data lines electrically connected to a first data selection circuit, and different sub-pixel groups are connected to a plurality of data lines electrically connected to different first data selection circuits. Each of the multiplexers includes f outputs, one input, and f control inputs.

9. The display panel according to claim 8, wherein, Each of the first data selection circuits includes j multiplexers; The number of first data selection control lines is j. f, the number of the first data selection circuits is m, and the number of the first data input lines is n; m and n satisfy: n=m+j-1; In every j consecutive first data selection circuits, j multiplexers that are electrically connected to different first data selection control lines are determined, and are all electrically connected to the same first data input line, where j is a positive integer less than m.

10. The display panel according to claim 9, wherein, One of the multiplexers includes f switching transistors; control stages of different switching transistors are electrically connected to different first data selection control lines; first terminals of different switching transistors are electrically connected to the same first data input line; second terminals of different switching transistors are electrically connected to different data lines. In each of the first data selection circuits, the second terminal of the i-th switching transistor in different multiplexers is electrically connected to the same data line.

11. The display panel according to claim 9, wherein, One of the multiplexers includes f switching circuits; Each of the aforementioned switching circuits includes: a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor; The control stage of the fifth transistor is electrically connected to the first data selection control line; the first terminal of the fifth transistor and the first terminal of the sixth transistor are both electrically connected to the first data input line; the second terminal of the fifth transistor is electrically connected to the control stage of the sixth transistor, the control stage of the seventh transistor, and the first terminal of the first capacitor; the second terminals of the sixth transistor and the seventh transistor are electrically connected to the data line; the second terminal of the first capacitor is grounded. The display panel also includes: A dummy signal line is electrically connected to the first electrode of the seventh transistor.

12. The display panel according to claim 1, wherein, All the sub-pixels in a row arranged in the first direction have the same color; The display panel further includes a light-shielding layer, which comprises only a plurality of light-shielding portions extending along the first direction and arranged along the second direction.

13. A display device, wherein, include: The display panel according to any one of claims 1 to 12; A cylindrical lens structure is located on the light-emitting side of the display panel; The cylindrical lens structure includes multiple cylindrical lenses arranged in an array; The controller, connected to the display panel, is configured to provide independent drive signals to each of the control zones.

14. The display device according to claim 13, wherein, Each sub-pixel row in the pixel island includes: h sub-pixels; each pixel island corresponds to N cylindrical lenses; where h and N are both positive integers, h>N, and h / N is a non-integer.

15. The display device according to claim 14, wherein, Each sub-pixel row in the pixel island includes a light-shielding area, and the ratio of the area of ​​the sub-pixel to the area of ​​the light-shielding area is X, where X = N-1.

16. The display device according to claim 15, wherein, The controller includes: The data parsing circuit is configured to parse the image to be displayed and obtain image parsing data. The data configuration circuit is configured to generate a data drive signal corresponding to the control area of ​​the display panel based on the current display mode and the image parsing data; The timing control circuit is configured to generate a gate drive signal for the gate drive circuit based on the current display mode and the viewing area and non-viewing area of ​​the display panel.

17. The display device according to claim 16, wherein, Also includes: An eye-tracking system is used to determine in real time where the user's eyes are focused on the display device.

18. The display device according to claim 17, wherein, The human eye tracking system includes: An image acquisition circuit includes: a plurality of first cameras and at least one second camera; the resolution of the first cameras is greater than the resolution of the second camera; the first cameras are configured to acquire images of a user's pupils, and the second camera is configured to acquire images of a user's face; A camera calibration circuit is configured to calibrate the first camera and the second camera to obtain the internal parameter matrix and external parameter matrix of the first camera and the second camera; The camera time-division and zone control circuit is configured to control the shooting sequence of multiple first cameras, so as to realize that multiple first cameras cyclically and alternately acquire images; The face detection circuit is configured to: search for face bounding boxes in the image captured by the second camera, detect face feature points, obtain the eye region within the face bounding box, and then obtain the spatial coordinate transformation matrix of the eye region through the mapping relationship between the face feature points and the standard face model; The image coordinate system transformation circuit is configured to: transform the face image coordinate system into the pupil image coordinate system, or transform the pupil coordinate system into the face image coordinate system; The pupil detection circuit is configured to: calculate the pupil coordinates in the image captured by the first camera; based on the eye region coordinates obtained by the face detection circuit, transform them to the pupil image coordinate system through the coordinate transformation circuit to obtain the eye region on the pupil image; perform pupil detection in the eye region to obtain the pupil coordinates in the pupil image coordinate system. The spatial coordinate calculation circuit is configured to: transform the pupil coordinates to the face image coordinate system, and then calculate the pupil coordinates in three-dimensional space through the spatial coordinate transformation matrix obtained by the face detection circuit; The spatial gaze tracking circuit is configured to: determine the eyeball center coordinates based on the pupil coordinates and a preset human eye model; calculate the direction vectors of the pupil coordinates and the eyeball center coordinates as line vectors; obtain the gaze intersection point between the human eye and the display panel based on the distance from the human eye to the display panel and the equation of the plane on which the display panel is located; and obtain the coordinates of the human eye's gaze point on the display panel based on the gaze intersection point.

19. The display device according to claim 18, wherein, The display device further includes: an image rendering system electrically connected to the controller, comprising: The coordinate extraction circuit is configured to: determine the three-dimensional spatial coordinates of the human eye relative to the display panel in the display device based on the position of the human eye's line of sight in the display panel determined by the human eye tracking system; The lens bonding detection circuit is configured to: obtain the bonding error of the cylindrical lens, adjust the bonding parameters of the cylindrical lens according to the bonding error, and obtain the viewpoint crosstalk curve; The image rendering circuit is configured to: generate a multi-view initial image based on the image to be displayed; and further configured to: optimize the multi-view initial image based on the human eye position, the fitting parameters, and the crosstalk curve to obtain an optimized multi-view image as the image to be displayed.

20. A driving method for a display device according to any one of claims 13 to 19, wherein, The method includes: Real-time determination of the user's gaze area and non-gaze area on the display device; The control area corresponding to the gaze region is independently driven to display an image at a first resolution, and the control area corresponding to the non-gaze region is driven to display an image at a second resolution; wherein the first resolution is higher than the second resolution.

21. The method according to claim 20, wherein, Determining the user's gaze area and non-gaze area on the display device specifically includes: The user's gaze area on the display device is obtained through an eye-tracking system; The area in the display device other than the gaze area is defined as the non-gaze area.

22. The method according to claim 21, wherein, The eye-tracking system acquires the area of ​​the user's gaze on the display device, specifically including: The system controls the first camera in the eye-tracking system to alternately acquire images of the user's pupils and controls the second camera in the eye-tracking system to acquire images of the user's face. Search for face bounding boxes in the image captured by the second camera, detect face feature points, obtain the eye region within the face bounding box, and then obtain the spatial coordinate transformation matrix of the eye region through the mapping relationship between the face feature points and the standard face model; Transform the face image coordinate system into the pupil image coordinate system, or convert the pupil coordinate system into the face image coordinate system; Calculate the pupil coordinates in the image captured by the first camera; transform the coordinates of the human eye region to the pupil image coordinate system to obtain the human eye region on the pupil image; perform pupil detection within the human eye region on the pupil image to obtain the pupil coordinates in the pupil image coordinate system. The pupil coordinates are transformed to the face image coordinate system, and then the pupil coordinates in three-dimensional space are calculated using the spatial coordinate transformation matrix. The coordinates of the eyeball center are determined based on the pupil coordinates and the preset human eye model. Calculate the direction vectors of the pupil coordinates and the eyeball center coordinates, and use them as line vectors; The intersection of the line of sight between the human eye and the display panel is obtained based on the distance from the human eye to the display panel and the equation of the plane in which the display panel is located; The coordinates of the human eye's gaze point on the display panel are obtained based on the intersection of the lines of sight, and the area where the coordinates of the human eye's gaze point on the display panel are located is determined as the gaze area.

23. The method according to any one of claims 22, wherein, Independently driving the control area corresponding to the gaze region to display the image at a first resolution, and driving the control area corresponding to the non-gaze region to display the image at a second resolution, specifically including: Based on the display mode, the gaze area, and the non-gaze area, determine the display information of each sub-pixel in the pixel island of the control area corresponding to the gaze area, and determine the display information of each sub-pixel in the pixel island of the control area corresponding to the non-gaze area; According to the displayed information, a first data selection control signal is provided to the first data selection control line, and the data signal provided by the first data write line is provided to the data line corresponding to the first data selection circuit through the first data selection circuit.

24. The method according to claim 23, wherein, The method further includes independently driving the gaze region to display an image at a first resolution and driving the non-gaze region to display an image at a second resolution, and also includes: The controller of the display device provides a gate driving signal to the gate driving circuit of the display panel to control the corresponding multiple rows of pixel islands in the gaze area to open row by row, and to control F rows of pixel islands in the corresponding multiple rows of pixel islands in the non-gaze area to open synchronously, where F is a positive integer and F is equal to the ratio of the first resolution to the second resolution.

25. The method according to claim 24, wherein, The display panel includes a gate driving circuit comprising a plurality of gate driving groups, each gate driving group comprising B gate driving subgroups, and each gate driving subgroup comprising C shift registers; wherein B and C are integers greater than 1. The controller of the display device provides a gate drive signal to the gate drive circuit of the display panel, specifically including: The controller provides a clock control signal to the gate drive group so that in each gate drive group, in the order of the first to the Bth gate drive subgroups, the multiple shift registers in the gate drive subgroup are sequentially input with an enable signal.

26. The method of claim 25, wherein, Also includes: The gaze area is driven to display an image at a first refresh rate, and the non-gaze area is driven to display an image at a second refresh rate, wherein the first refresh rate is higher than the second refresh rate.

27. The method according to claim 26, wherein, Driving the gaze area to display an image at a first refresh rate, and driving the non-gaze area to display an image at a second refresh rate, specifically includes: Drive each sub-pixel within the gaze area to be refreshed Z times; Drive each sub-pixel within the non-focused area to refresh Y times; Where Z and Y are positive integers, and Z is greater than Y.

28. The method according to claim 27, wherein, Driving each sub-pixel within the gaze area to refresh specifically includes: The scanning signal input lines corresponding to the gaze area are driven to transmit valid level signals sequentially. Control each control signal line to transmit control signals, transmit the signal provided by the scan signal input line to the scan line corresponding to the gaze area, and transmit the signal provided by the fixed potential line to the scan line corresponding to the non-gaze area; Driving each of the sub-pixels within the non-focused region to refresh includes: The scanning signal input lines within the display panel are driven to sequentially transmit valid level signals. When the scan detects each of the sub-pixel rows corresponding to the gaze region, the control signal lines are controlled to transmit control signals, the signals provided by the fixed potential lines are transmitted to the scan lines corresponding to the gaze region, and the signals provided by the scan signal input lines are transmitted to the scan lines corresponding to the non-gaze region.

29. An image rendering method for a display device according to any one of claims 13 to 19, wherein, The method includes: Determine the position of the human eye's line of sight on the display panel in the display device, and determine the three-dimensional spatial coordinates of the human eye relative to the display panel; Generate a multi-viewpoint initial image based on the image to be displayed; The display device is subjected to bonding detection of the cylindrical lens array to obtain the bonding error of the cylindrical lens and the viewpoint crosstalk curve; The initial multi-view image is optimized based on the human eye position, the fit detection parameters, and the crosstalk curve to obtain an optimized multi-view image. The optimized multi-view image is transmitted to the controller.

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