Light-emitting diode display pixel

Abstract

This specification relates to a display pixel (12 i,j ), comprising at least one light-emitting diode (LED), a circuit (40) for driving the light-emitting diode, and a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad (36). The driver circuit is powered by a first supply voltage (Vdd) received between the first conductive pad and the second conductive pad. The light-emitting diode is powered by a first binary signal (Vcc i , Vee i ) received between the third conductive pad and the second conductive pad, and alternates between a second supply voltage (Vcc) that is strictly greater than the first voltage and a third voltage that is strictly less than the first voltage. The driver circuit (40) is configured to determine a digital signal (R, G, B) based on the value of a second binary signal (Data j ) received on the fourth conductive pad during each first pulse of the first binary signal at the third voltage, and to control the light-emitting diode according to the digital signal.

Description

Technical Field

[0001] The present disclosure relates to a display screen, the display pixels of which include light-emitting diodes. Background Art

[0002] The pixels of an image correspond to the unit elements of the image displayed by the display screen. For the display of a color image, for the display of each pixel of the image, the display screen generally includes at least three components, also referred to as display sub-pixels, each of which emits light radiation of a substantially single color (e.g., red, green, and blue). The superposition of the radiations emitted by the three display sub-pixels provides the observer with the color sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels for the pixel of the displayed image is referred to as the display pixel of the display screen. Each display sub-pixel may include a light source, in particular a light-emitting diode.

[0003] The display pixels may be distributed in an array, each display pixel being located at the intersection of a row (or line) and a column of the array. Generally, each row of display pixels is successively selected, and the display pixels of the selected row are programmed to display the desired image pixels.

[0004] An active array is a screen driving architecture capable of keeping all pixel rows active throughout the duration of an image, as opposed to an array referred to as passive, in which each row is active only for a time T = Tframe / N (where Tframe is the duration of the image and N is the number of rows of the screen). This makes it possible to increase the brightness of the display screen. In addition, low voltage or low current levels can be sent on the array control lines, which makes it possible to display a larger data stream.

[0005] In the context of a screen based on light-emitting diodes formed on an electronic circuit with a micron-scale size, due to the high intrinsic luminosity of the light-emitting diodes, the size of the light-emitting diode circuit is generally smaller than the size of the image pixel. Thus, one of the solutions used is to deposit these unit light-emitting diodes on a support (also referred to as a panel) containing the driving electronics. Another solution consists of using display pixels including light-emitting diodes and circuits for controlling the light-emitting diodes. It is then referred to as a smart pixel. This makes it possible to simplify the formation of an active array in particular because most of the control electronics of the light-emitting diodes of the display pixels are embedded in the display pixels. Document WO 2018 / 185433 describes an example of a smart pixel.

[0006] For smart pixels, the number of conductive pads of the smart pixel that electrically connect the smart pixel to the support affects the size of the smart pixel, in particular due to the minimum size of these pads and the minimum space provided between these pads. To limit the number of conductive pads, it is known to supply a single power supply voltage to the display pixels, and one or more reduced power supply voltages are generated inside each display pixel, in particular for biasing components of the control electronics.

[0007] The static power consumption of a display pixel corresponds to the electrical power consumed by the display pixel when the display pixel is not emitting light. It can be formed by the leakage current of the components or the current necessary for the internal operation of the display pixel control circuit. In the context of smart pixels, a large part of the static power consumption stems from the generation of the internal power supply voltage of the smart pixel.

[0008] It is conceivable to provide additional conductive pads on each smart pixel to supply a reduced power supply voltage to the smart pixel, so that it is not generated inside the smart pixel. However, this may lead to an increase in the size of the smart pixel, which is undesirable.

[0009] The trend is to increase the number of display pixels of the display screen. The static power consumption of the display pixel can then become a key factor. In fact, for a so-called 4K display screen with a resolution of 2160×3840 display pixels, the static power consumption of the display screen may be greater than 150W.

[0010] There is a need to reduce the static power consumption of the display screen. Summary of the Invention

[0011] An object of an embodiment is to provide a display screen including light-emitting diodes, which overcomes all or part of the disadvantages of existing display screens including light-emitting diodes.

[0012] Another object of an embodiment is to make the display pixel have a size less than 200μm, which limits the number of interconnections between the display pixel and the support of the display pixel.

[0013] An embodiment provides a display pixel for a display screen, including at least one light-emitting diode, a circuit for driving the light-emitting diode, and a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad. The driver circuit is at least partially powered by a first power supply voltage received between the first conductive pad and the second conductive pad. The light-emitting diode is powered by a first binary signal received between the third conductive pad and the second conductive pad. The first binary signal alternates between a second power supply voltage greater than the first power supply voltage and a third voltage less than the first power supply voltage. The driver circuit is configured to determine a digital signal based on the value of a second binary signal on the fourth conductive pad during each first pulse of the first binary signal at the third voltage, and to control the light-emitting diode according to the digital signal.

[0014] According to one embodiment, the driver circuit is configured to control a light-emitting diode by pulse-width modulation from a digital signal.

[0015] According to an embodiment, the display pixel includes only a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad.

[0016] According to one embodiment, the driver circuit is configured to turn on or off the light-emitting diode at the rate of a second pulse of a first binary signal at a third voltage.

[0017] According to one embodiment, the driver circuit is configured to determine a clock signal and a third binary signal based on a second binary signal.

[0018] According to one embodiment, the driver circuit includes a circuit for storing binary data determined based on the third binary signal during each first pulse.

[0019] According to one embodiment, the second binary signal is intended to include a mixture of a third pulse having the same duration and a fourth pulse having the same duration longer than the duration of each third pulse. The driver circuit is configured to transmit the clock signal at the same rate as the third pulse and the fourth pulse, and the third binary signal is equal to the first state or the second state according to the succession of the third pulse and the fourth pulse.

[0020] One embodiment also provides a display screen including a display pixel array such as previously defined. The display screen further includes a circuit for transmitting a first power supply voltage between the first conductive pad and the second conductive pad, a first binary signal between the third conductive pad and the second conductive pad, and a second binary signal on the fourth conductive pad for each display pixel.

[0021] According to one embodiment, the transmission circuit is configured to hold the first conductive pad at a first substantially constant potential, hold the second conductive pad at a second substantially constant potential, and place the third conductive pad at a third potential that alternates between a first value and a second value, where either the first value is greater than the first potential and the second value is equal to the second potential, or the first value is equal to the first potential and the second value is less than the second potential.

[0022] According to one embodiment, the transmission circuit is configured to transmit a third voltage equal to zero volts.

[0023] According to one embodiment, the transmission circuit is configured to transmit a second binary signal that alternates between two potentials, the absolute value difference between the two potentials being less than a second power supply voltage.

[0024] According to one embodiment, a transmission circuit is configured to transmit a first binary signal, the first binary signal including a first pulse of a third voltage for a first duration for image display and successive second pulses, each second pulse having a second duration shorter than the first duration.

[0025] According to one embodiment, the duration between two pairs of successive second pulses increases or decreases. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0027] Figure 1 Partially schematically shows a known example of a display screen;

[0028] Figure 2 is a very simplified cross-sectional view of a known example of a display pixel;

[0029] Figure 3 is Figure 2 a bottom view of the display pixel of

[0030] Figure 4 shows Figure 2 a known example of a block diagram of the display pixel of

[0031] Figure 5 shows Figure 4 a known example of a timing diagram of the signals of the display pixel of

[0032] Figure 6 Partially schematically shows an embodiment of a display screen according to the present invention;

[0033] Figure 7 shows an embodiment of Figure 6 a block diagram of a display pixel of the display screen according to the present invention;

[0034] Figure 8 shows Figure 7 a timing diagram of the signals of the display pixel;

[0035] Figure 9 shows an embodiment of Figure 6 another display pixel of the display screen according to the present invention; and

[0036] Figure 10 shows Figure 9 a timing diagram of the signals of the display pixel. DETAILED DESCRIPTION

[0037] In the different drawings, the same features are designated by the same reference numerals. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may have exactly the same structure, dimensions, and material properties. For clarity, only the steps and elements that contribute to an understanding of the embodiments described herein are shown and described in detail.

[0038] In the following description, when referring to terms that define an absolute position (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.) or a relative position (such as the terms "above", "below", "upper", "lower", etc.), or terms that define a direction (such as the terms "horizontal", "vertical", etc.), unless otherwise indicated, it refers to the direction of the drawing or the display screen in the normal use position.

[0039] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate elements other than a conductor, and when referring to two elements coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements. In addition, a signal that alternates between a first constant state (e.g., a low state, labeled "0") and a second constant state (e.g., a high state, labeled "1") is called a "binary signal". The high and low states of different binary signals in the same electronic circuit may be different. In practice, a binary signal may correspond to a voltage or current that may not be completely constant in the high or low state. In addition, in the following description, the source and drain of a MOS transistor are referred to as the "power terminals" of an insulated-gate field-effect transistor or a MOS transistor.

[0040] In addition, unless otherwise indicated, when referring to the voltage at a conductive pad, the difference between the potential of the conductive pad and a reference potential (e.g., ground potential) is considered to be equal to 0V.

[0041] Unless otherwise specified, the expressions "about", "approximate", "substantially", and "roughly" mean within 10%, and preferably within 5%. In addition, the expression "substantially constant" means that the change with time relative to a reference value is less than 10%.

[0042] Figure 1 Partially schematically shows a known example of the display screen 10. The display screen 10 includes, for example, display pixels 12 arranged in M rows and N columns i,j , where M is an integer that varies from 1 to 8000, and N is an integer that varies from 1 to 16000, i is an integer that varies from 1 to M, and j is an integer that varies from 1 to N. For example, in Figure 1 , M and N are equal to 6. Each display pixel 12 i,j is connected via an electrode 14i a source coupled to a low reference potential Gnd (e.g., ground), and via an electrode 16 j a source coupled to a high reference potential Vcc. For example, in Figure 1 electrode 14 i is shown aligned along a row, and electrode 16 j is shown aligned along a column, and the opposite layout is possible. The power supply voltage of the display screen corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd. The power supply voltage depends in particular on the arrangement of the light-emitting diodes and the technology for manufacturing the light-emitting diodes. For example, the power supply voltage can be approximately from 4V to 5V.

[0043] For each row, the display pixels 12 in that row i,j are coupled to a row electrode 18 i . For each column, the display pixels 12 in that column i,j are coupled to a column electrode 20 j . The display screen 10 includes a selection circuit 22, which is coupled to the row electrode 18 i and is adapted to transmit selection and timing signals Com i on each row electrode 18 i . The display screen 10 includes a data transmission circuit 24, which is coupled to the column electrode 20 j and is adapted to transmit data signals Data j on each column electrode 20 j . The selection circuit 22 and the control circuit 24 are controlled by a circuit 26 including, for example, a microprocessor.

[0044] Figure 2 is a very simplified cross-sectional view of a known example of a display pixel 12 i,j , and Figure 3 is a bottom view of a display pixel 12 i,j . Each display pixel 12 i,j includes a control circuit 30 covered with a display circuit 32. The display circuit 32 includes at least one light-emitting diode LED, preferably at least three light-emitting diodes. The display pixel includes a lower surface 34 and an upper surface 35 opposite to the lower surface 34, and the surfaces 34 and 35 are preferably planar and parallel. The control circuit 30 further includes a conductive pad 36 on the lower surface 34, Figure 2is not shown. The control circuit 30 may correspond to an integrated circuit including electronic components, in particular an insulated gate field effect transistor, also known as a MOS transistor, or a thin film transistor, also known as a TFT. Preferably, the display circuit 32 only includes light emitting diodes LED and the conductive elements of these light emitting diodes LED, and the control circuit 30 includes all the electronic components necessary to control the light emitting diodes LED of the display circuit 32. As a variant, the display circuit 32 may also include other electronic components in addition to the light emitting diodes LED. The light emitting diodes LED may be 2D light emitting diodes, also known as planar light emitting diodes, including a stack of planar layers, or 3D light emitting diodes, each including a three-dimensional semiconductor element covered with an active region. In Figure 2 the light emitting diodes are shown connected to a common anode. However, it may be desirable to arrange the light emitting diodes LED according to another configuration. For example, the light emitting diodes may be connected to a common cathode, or connected independently of each other.

[0045] According to one embodiment, the display pixel 12 i,j includes three display sub-pixels that emit light of a first, second, and third wavelength. According to one embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0046] Each conductive pad 36 is intended to be connected to Figure 2 the electrodes 14 i shown schematically in j 16 i 18 j 20 i one of them. The first conductive pad 36 is coupled to the source of a low reference potential Gnd. The second conductive pad is coupled to the source of a high reference potential Vcc. The third conductive pad 36 is coupled to the row electrode 18 i and receives a selection and timing signal Com j j . The fourth conductive pad 36 is coupled to the column electrode 20 and receives a data signal Data i,j The size of the conductive pads 36 and the layout of the conductive pads 36 on the surface 34 are particularly determined by the design rules of the display pixel 12 i,j and the assembly method of the display pixels 12

[0047] Figure 4 shows a known example of a block diagram of the display pixel 12 i,j of the display screen 10. In Figure 4In the figure, above each block, the power supply voltage for powering the electronic components of the block has been indicated.

[0048] According to one example, display pixel 12 i,j includes at least three light-emitting diodes, a single light-emitting diode LED, as Figure 4 shown. Each light-emitting diode LED is coupled in series to a controllable current source CS, which includes, for example, a MOS transistor. In this example, for each light-emitting diode LED, the anode of the light-emitting diode LED is coupled, for example, to a conductive pad 36 that receives a high reference potential Vcc, and the cathode of the light-emitting diode LED is coupled, for example, to a terminal of the controllable current source CS, and the other terminal of the controllable current source CS is coupled to a conductive pad 36 that receives a low reference potential Gnd.

[0049] Display pixel 12 i,j also includes a circuit 40 for driving the controllable current source CS. The driver circuit 40 can particularly include electronic components such as MOS transistors. It may be desirable to use a reduced power supply voltage of less than 4V, for example, approximately 1V or 1.8V, to power the electronic components of the driver circuit 40, and this reduced power supply voltage corresponds, for example, to the voltage that may be applied between the power supply terminals of the MOS transistor. For this purpose, display pixel 12 i,j includes a circuit 42 (Vdd generation) for transferring a reduced power supply voltage Vdd specifically for the power supply of the driver circuit 40 from the power supply voltage Vcc. The circuit 42 includes, for example, a voltage divider.

[0050] According to one embodiment, at one of the conductive pads 36 of each display pixel 12 i,j the detection and timing signal Com received i is a binary signal that alternates between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd, and the high state "1" corresponding to a low voltage, for example, approximately 1V, less than the reduced power supply voltage Vdd. The data signal Data j is a binary signal that alternates between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd, and the high state "1" corresponding to a low voltage, for example, approximately 1V, less than the reduced power supply voltage Vdd.

[0051] The driver circuit 40 includes a circuit 44 (Clk and data separation) coupled to the conductive pad 36, which receives the data signal Data j and transfers a clock signal Clk and data Data from the data signal Data j The driver circuit 40 includes a circuit 46 (mode selection) that receives the signals Clk and Data, which is coupled to receive the selection and timing signal Com iThe conductive pad 36 and is configured to transfer the signals Clk and Data to the storage circuit 48 (color data register) or transfer the PWM signal to the circuit 50 (LED driver) for controlling the controllable current source CS associated with each light emitting diode LED. The storage circuit 48 is configured to store the color signals R, G, B representing the image pixels to be displayed. The circuit 50 is adapted to control the controllable current source CS coupled to the light emitting diode LED with the signals I_red, I_green, and I_blue obtained from the color signals R, G, B and the signal PWM.

[0052] As will be described below, in order to limit the number of conductive pads 36 of each display pixel 12 i,j the data signal Data j enables each display pixel 12 i,j to determine the clock signal and the color signals R, G, B representing the light intensities required for the radiation of the first, second, and third wavelengths.

[0053] Figure 5 During the display of an image on the display screen 10, the display pixel 12 Figure 4 having the structure shown i,j receives the timing diagram of the signals.

[0054] The potentials Vcc and Gnd are substantially constant. The image pixels of the new image to be displayed are sequentially displayed from the first row to the Mth row. The frame duration T is called the duration separating two consecutive selections of the same row of the display screen 10. The timing diagram of the signals Com1 and Data1 will be described in detail for the first row. The timing diagram of the known signal Com i is similar to the timing table of the signal Com1, although shifted in time. The display pixels 12 i,j (where j varies from 1 to N) of the first row for the display of the new image pixels include a first stage P1, followed by a second stage P2. During stage P1, the data signal Data j is transmitted to each display pixel 12 i,j of the first row Figure 5 and only the signal Data1 is shown. During the second stage P2, the light emitting diodes of each display pixel 12 i,j are controlled according to the color signals R, G, B determined based on the data signal Data j .

[0055] During the first stage P1, the selection and timing signal Com1 is set to the state "1". The circuit 46 of each display pixel 12 i,j of the first row detects that the signal Com1 is set to the state "1" for a long duration, and thus enables the selection of the display pixels 12 of that rowi,j , rather than selecting the display pixels of other rows. During the first stage P1, data signals Data are transmitted on the column electrodes 20 j . j For each display pixel 12 i,j , the circuit 44 determines the clock signal Clk and the data Data based on the pulses of the data signal Data j . For example, each pulse of the data signal Data j can have a first duration or a second duration longer than the first duration. The signal Clk can correspond to a sequence of pulses with the same duration, and its rising edge coincides with the rising edge of the pulses of the data signal Data within a possible constant offset j . When the pulses of the signal Data j have the first duration, the data Data can correspond to a binary signal in the state "0", and when the pulses of the signal Data j have the second duration, the data Data can correspond to a binary signal in the state "1". The circuit 46 selected by the signal Com i in the state "1" transmits the data Data at the rate of the clock signal Clk, and the data Data is stored in the circuit 50 in the form of digital signals R, G, B, and its bits are provided by the consecutive values of the signal Data. The end of the first period P1 of one row corresponds to the start of the first period P1 of the next row.

[0056] According to one embodiment, the light-emitting diodes of the display pixels 12 are controlled by pulse-width modulation or control PWM i,j . For this purpose, during the second stage P2, the selection and timing signal Com1 exhibits a repetition of consecutive pulses in the state "1", and these pulses are transmitted by the circuit 46 of each display pixel 12 i,j in the first row to the circuit 50 (signal PWM) to rate the operating circuit 50 for controlling the light-emitting diodes LED by pulse-width modulation. The number of consecutive pulses corresponds to the number of bits of each digital signal R, G, and B. For example, when the current source CS corresponds to a MOS transistor, the transistor is turned on or off at the rate of PWM pulses according to the value "0" or "1" of each bit of the color signal R, G, or B starting from the most significant bit, and the transistor remains on or off until the next pulse of the signal Com1. The duration between two consecutive pulses of the signal Com1 is divided by 2 each time, so that the total duration for which the light-emitting diode is on depends on the value of the color signal R, G, or B. The consecutive pulses of the signal Com1 are repeated until the next first stage P1 of the first row, Figure 5 and a single repetition is illustrated therein.

[0057] Display pixel 12i,j The static power consumption is to a large extent due to electronic components other than the MOS transistors of the driver circuit 40, in particular the circuit 42 for delivering the reduced supply voltage Vdd. The current trend is to increase the number of display pixels 12 of the display screen 10 i,j . The static power consumption of the display pixels can then become a key factor. In fact, for a so-called 4K display screen 10 with a resolution of 2160×3840 display pixels, the static power consumption of the display screen 10 can be greater than 150W.

[0058] It is conceivable that, in addition to those shown in Figure 3 , additional conductive pads 36 are provided on each display pixel 12 i,j to deliver an additional high reference potential Vdd to the display pixel 12 i,j such that the reduced supply voltage Vdd is not generated within the display pixel 12 i,j . However, it is not possible to add additional conductive pads 36 without increasing the lateral dimension of the display pixel 12 i,j , which may be undesirable.

[0059] According to an embodiment of the present invention, one of the conductive pads 36 is used to receive the high supply voltage Vcc, and another conductive pad 26 is used to receive the reduced supply voltage Vdd, without modifying the total number of conductive pads. Thus, the generation of the reduced supply voltage is no longer performed within each display pixel 12 i,j , and the static power consumption of the display screen is reduced. In addition, the lateral dimension of the display pixel 12 i,j can be not modified. However, in order to operate with the same number of conductive pads 36, the structure of the driver circuit 40 of the display pixel 12 i,j is modified, and some of the signals supplied to the display pixel 12 i,j are modified.

[0060] Figure 6 Partially schematically shows an embodiment of the display screen 60. The display screen 60 includes Figure 1 all elements of the display screen 10, except that the electrodes 16 j (j varying from 1 to N) deliver the reduced supply voltage Vdd, and the row electrodes 18 i (i varying from 1 to M) deliver the high supply voltage Vcc i , which includes a part of the timing signal. The column electrodes 20 j deliver the data signal Data j , and the electrodes 14 i deliver the low reference potential, in the same manner as the display screen 10.

[0061] Figure 7Shows the display pixels 12 of the display screen 60 i,j Block diagram example. The display pixels 12 of the display screen 60 i,j And Figure 4 The display pixels 12 of the display screen 10 shown i,j Have the same structure, except that it does not include the circuit 42 for transmitting the reduced power supply voltage Vdd, and it also includes a circuit 62 for detecting the pulse of the signal Vcc i (Vcc pulse detection), which transfers the selection and timing signal Com i To the selection circuit 46. The reduced power supply voltage Vdd is directly transferred by one of the conductive pads 36.

[0062] Figure 8 Shows the timing diagram of the signals received by the display pixels 12 having the structure shown Figure 7 During the display of an image on the display screen 60 i,j Received signals.

[0063] The potentials Vdd and Gnd are substantially constant. Each signal Vcc i (where i varies from 1 to M) is a binary signal that varies between the state "1" and the state "0". In the state "1", the signal Vcc i Is equal to the previously described high power supply voltage Vcc, for example, approximately from 4V to 5V. In the state "0", the signal Vcc i Is substantially equal to the low reference potential GND. Each signal Vcc i Exhibits a first phase P1, followed by a second phase P2. During the phase P1, the data signal Data j Is transmitted to each display pixel 12 in the i-th row i,j , Figure 8 Only the signal Data1 is displayed. During the second phase P2, the light-emitting diodes of each display pixel 12 i,j Are controlled according to the color signals R, G, B determined based on the data signal Data j .

[0064] The signal Com provided by the circuit 62 of each display pixel 12 i,j Therefore varies between the state "0" and the state "1" complementary to the signal Vcc i . The state "0" corresponds to the low reference potential GND, for example, and the state "1" corresponds to a low voltage, for example, approximately 1V, for example, equal to the reduced power supply voltage Vdd. Therefore, the operation of the rest of the driver circuit 40 is the same as that previously described with respect to i . In particular, during the first phase P1, the signal Vcc Figure 5 Described iis set to the state “0”. The circuit 62 and 46 of each display pixel 12 in the i-th row i,j detect the signal Vcc i set to the state “0” for a long duration, and thus enables the selection of the display pixels 12 of that row i,j , without selecting the display pixels of other rows. During the first phase P1, the data signal Data j is transmitted on the column electrode 20 j . For each display pixel 12 i,j , the circuit 44 determines the clock signal Clk and the data Data based on the pulses of the data signal Data j , for example, as described above. The circuit 46 selected by the signal Com i in the state “1” transmits the data Data at the rate of the clock signal Clk, and the data Data is stored in the circuit 50 in the form of digital signals R, G, B, and its bits are provided by the consecutive values of the signal Data.

[0065] During the second phase P2, the signal Vcc i exhibits a repetition of consecutive pulses in the state “0”, and these pulses are converted by the circuit 62 of each display pixel 12 in the i-th row i,j into pulses of the state “1” of the signal Com i . These pulses are transmitted by the circuit 46 of each display pixel 12 in the i-th row i,j to the circuit 50 (PWM signal) to rate the operation of the circuit 50 for controlling, for example, the light-emitting diode LED by pulse-width modulation, as described above.

[0066] Advantageously, during phases P1 and P2, each signal Vcc i has a pulse duration in the state “0” that is shorter than at least 75%, preferably at least 80%, more preferably at least 85% of the duration of the frame T. Thus, the signal Vcc i is equal to the high supply voltage Vcc most of the time, and the supply voltage of the light-emitting diode LED is substantially not interfered with by the pulses of the signal Vcc i . This would not be the case if the high supply voltage was transmitted by the data signal Data j , and the data signal Data j would change substantially permanently between the high and low states.

[0067] In the embodiment described above Figure 7 , the light-emitting diode LED is in a common anode configuration. However, it may be desirable to arrange the light-emitting diode LED in a common cathode configuration.

[0068] Figure 9 Shows the display pixels 12 of the display screen 60 i,j in a block diagram example, where the display pixel 12 i,j has its light-emitting diode LED in a common cathode configuration. Figure 9 The display pixel 12 shown in i,j has the same structure as Figure 7 the display pixel 12 shown in i,j except that the signal Vcc i is replaced by the signal Vee i and the cathode of the light-emitting diode LED is coupled, for example, to the conductive pad 36 that receives the signal Vee i and the anode of the light-emitting diode LED is coupled, for example, to the terminal of the controllable current source CS, and the other terminal of the controllable current source CS is connected to the conductive pad 36 that receives the reduced supply voltage Vdd.

[0069] Figure 10 Shows the timing diagram of the signals received when the display pixel 12 with the Figure 9 shown structure displays an image on the display screen 60. Each signal Vee i,j (where i varies from 1 to M) is a binary signal that varies between the state "1" and the state "0", and in the state "1", the signal Vee i is equal to the previously described reduced supply voltage Vdd, for example, approximately 1V or 1.8V, and in the state "0", the signal Vee i is at a reference potential less than the reference potential GND, for example, at a negative potential, particularly approximately -2.2V or -3V, such that the difference between the potentials Vdd and Vee is equal to the previously described high supply voltage Vcc. According to one embodiment, the signal Vee i varies in the same way as the previously described signal Com i . In this embodiment, there is no circuit 62 because, since the signal Vee i varies like the signal Comi, it can be directly used by the circuit 46. However, since the dynamic characteristics of the signal Vee i are different from those of the signal Comi, it may be desirable to provide a circuit 62 to adapt to transmit the signal Com i from the signal Vee i . i

[0070] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will occur to those skilled in the art. In particular, PWM modulation can be internally generated in the control circuit 30 of the display pixel 12 i,j to avoid using the signal Com ito generate it. Other embodiments may also not use PWM modulation, but instead use a linear drive of a light-emitting diode LED. Other embodiments may also use other electro-optical components, such as organic light-emitting diodes.

[0071] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of those skilled in the art. In particular, with regard to Figure 9 the second embodiment described in, it may be advantageous to use a structure of the SOI (silicon-on-insulator) type to facilitate the management of negative voltages.

Claims

1. A display pixel (12) for a display screen (60) i,j ), comprising at least one light-emitting diode (LED), a driver circuit (40) for driving the light-emitting diode, and a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad (36), wherein the driver circuit is at least partially powered by a first power supply voltage (Vdd) received between the first conductive pad and the second conductive pad, and the light-emitting diode is powered by a first binary signal (Vcc i , Vee i ) received between the third conductive pad and the second conductive pad, the first binary signal alternating between a second power supply voltage (Vcc) greater than the first power supply voltage and a third voltage less than the first power supply voltage, and the driver circuit (40) is configured to determine a digital signal (R, G, B) based on the value of a second binary signal (Data j ) on the fourth conductive pad received during each first pulse of the first binary signal at the third voltage, and to control the light-emitting diode according to the digital signal.

2. The display pixel according to claim 1, wherein, The driver circuit (40) is configured to control the light emitting diode (LED) by pulse width modulation from the digital signals (R, G, B).

3. The display pixel according to claim 1 or 2 comprises only the first conductive pad, the second conductive pad, the third conductive pad and the fourth conductive pad (36).

4. The display pixel according to claim 1, wherein, The driver circuit (40) is configured to turn on or off the light emitting diode (LED) at the rate of a second pulse of the first binary signal (Vcc i , Vee i ) at the third voltage.

5. The display pixel according to claim 1, wherein, The driver circuit (40) is configured to determine a clock signal (Clk) and a third binary signal (Data) based on the second binary signal (Data j ).

6. The display pixel according to claim 5, wherein, The driver circuit (40) includes a storage circuit (50) for storing binary data (Data) determined at each first pulse based on the third binary signal.

7. The display pixel according to claim 5 or 6, wherein, The second binary signal (Data j ) is intended to include a mixture of third pulses having the same duration and fourth pulses having the same duration that is longer than the duration of each third pulse, the driver circuit (40) is configured to transmit the clock signal (Clk) at the same rate as the third pulses and the fourth pulses, and the third binary signal (Data) is equal to a first state or a second state continuously according to the third pulses and the fourth pulses.

8. A display screen (60), which comprises an array of display pixels (12 i,j ) according to any one of claims 1 to 7, and the display screen further comprises a transmission circuit (22, 24) for transmitting a first power supply voltage (Vdd) between the first conductive pad and the second conductive pad, the first binary signal (Vcc i , Vee i ) between the third conductive pad and the second conductive pad, and a second binary signal (Data j ) on the fourth conductive pad for each display pixel.

9. The display screen according to claim 8, wherein, The transfer circuit (22, 24) is configured to hold the first conductive pad (36) at a substantially constant first potential (Vdd), hold the second conductive pad at a substantially constant second potential (GND), and hold the third conductive pad at a third potential that alternates between a first value and a second value, the first value being greater than the first potential and the second value being equal to the second potential.

10. The display screen according to claim 8 or 9, wherein, The transfer circuit (22, 24) is configured to transfer a third voltage equal to zero volts.

11. The display screen according to claim 8, wherein, The transfer circuits (22, 24) are configured to transfer the second binary signal (Data j ) that alternates between two potentials, and the absolute value difference between the two potentials is less than the first supply voltage (Vdd).

12. The display screen according to claim 8, wherein, The transfer circuits (22, 24) are configured to transfer the first binary signal (Vcc i , Vee i ) that includes a first pulse at a third voltage for a first duration and successive second pulses for displaying an image, each second pulse having a second duration shorter than the first duration.

13. The display screen according to claim 12, wherein, The duration between two pairs of second consecutive pulses increases or decreases.

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