Nand flash address mapping management method, management system, terminal device and medium

Abstract

The application provides a Nand Flash address mapping management method, a management system, equipment and a medium, relates to the field of Nand Flash storage, wherein the management method sets a first area and a second area in the Flash storage, sets an initial write threshold value of the first area and a set usage rate, judges the data size of an obtained cache data packet and the size of the initial write threshold value, and stores the cache data packet in the first area or the second area according to a judgment result, obtains the page usage rate of the first area after storage, and calculates an update through the page usage rate, the set usage rate and the initial write threshold value to obtain an updated write threshold value, and compares the data size of the cache data packet with the updated write threshold value when the cache data packet is stored next time. The application updates the write threshold value through the page usage rate, guarantees that the first area has sufficient reserved space, avoids the case that the first area is filled, and improves the read-write speed of the first area.

Description

Technical Field

[0001] This invention relates to the field of Nand Flash storage technology, specifically to Nand Flash address mapping management methods, management systems, terminal devices, and media. Background Technology

[0002] Compared to traditional hard disks, NAND Flash storage devices feature low latency, low power consumption, high storage density, low noise, and small size, making them widely used in the storage field. A typical NAND Flash storage device consists of a host interface logic unit, DRAM, a controller chip, and multiple flash memory chips. NAND Flash storage devices implement logical / physical address mapping and garbage collection through a flash translation layer (FTL). Common mapping methods include block mapping, page mapping, and hybrid mapping. Hybrid mapping employs multi-level mapping, combining multiple regions for read and write operations. Existing NAND Flash storage devices partition the flash memory chips into a second region and a first region. The second region is used to store large amounts of data, while the first region is used to store small amounts of data.

[0003] However, the storage and retrieval of small batches of data are relatively frequent. Excessive use can easily lead to an unexpected situation where the first area is filled up. If data is written to the first area in this case, it is necessary to wait for the data transfer and block erasure operations in the first area before continuing, which reduces the writing speed of the first area. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, the present invention aims to provide a Nand Flash address mapping management method, management system, device and medium.

[0005] In a first aspect, the present invention provides a Nand Flash address mapping management method, comprising the following steps:

[0006] S100. A first area and a second area are configured in the Flash storage. The first area includes a first data block, and the first data block includes a plurality of first data pages. The second area includes a plurality of second data blocks, and each second data block includes a plurality of second data pages.

[0007] S200. Set the initial write threshold and usage rate for the first region;

[0008] S300. Obtain the cached data packet and obtain the data size of the cached data packet;

[0009] S400. Determine the size of the data and the size of the initial write threshold. If the data size is less than or equal to the initial write threshold, store the cached data packet in the first area. If the data size is greater than the initial write threshold, store the cached data packet in the second area.

[0010] S500. Obtain the page utilization rate of the first area;

[0011] S600. Calculate and update the initial write threshold based on the page utilization rate, the set utilization rate, and the initial write threshold to obtain the updated write threshold;

[0012] S700. Update the initial write threshold to the updated write threshold, and repeat steps S300-S700.

[0013] According to the technical solution provided by the present invention, step S600 includes the following steps:

[0014] S601. Establish a write threshold relationship, as shown below:

[0015] S t new = S t + K(u set -u)

[0016] Among them, S t u represents the initial write threshold; u represents the page utilization rate; u set S represents the set usage rate; t new This represents the update write threshold, where K is the write coefficient, and 0 < K ≤ 1;

[0017] S602. Substitute the page utilization rate, the set utilization rate, and the initial write threshold into the write threshold formula to obtain the update write threshold.

[0018] According to the technical solution provided by the present invention, the following steps are further included after step S100:

[0019] S101. Obtain the logical address;

[0020] S102. Search the first area and determine whether the first area has a first address that is the same as the logical address. If it does, proceed to step S103; otherwise, proceed to step S104.

[0021] S103. Extract the data corresponding to the first address;

[0022] S104. Search the second region, obtain the second address in the second region that is the same as the logical address, and extract the data corresponding to the second address.

[0023] According to the technical solution provided by the present invention, the second data block includes a free block and a non-free block, wherein the non-free block includes a first invalid data page and a first valid data page, and the following steps are further included after step S100:

[0024] S111. Set the free block threshold for the second region and obtain the number of free blocks in the second region;

[0025] S112. When it is determined that the number of free blocks is less than the free block threshold, compare the number of the first invalid data pages in the non-free blocks, obtain the non-free block with the largest number of the first invalid data pages, and set it as the largest non-free block;

[0026] S113. Write the data of all the first valid data pages in the largest non-free block into the free block;

[0027] S114. Erase the largest non-free block.

[0028] According to the technical solution provided by the present invention, the first data page includes occupied pages and free pages. The occupied pages are the number of pages in the first area that store the cached data packets, including the second invalid data page and the second valid data page. After step S100, the following steps are further included:

[0029] S121. Set the threshold for invalid data pages in the first region, and obtain the number of invalid data pages in the second region;

[0030] S122. If the number of the second invalid data pages is greater than the invalid data page threshold, write the data of the second valid data page into the free page;

[0031] S123. Erase the occupied page.

[0032] According to the technical solution provided by the present invention, step S500 includes the following steps:

[0033] S501. Obtain the total number of the first data pages in the first region, which is the first total number;

[0034] S502. Obtain the total number of occupied pages, which is the number of occupied pages;

[0035] S503. Divide the number of occupied pages by the first total number to obtain the page utilization rate.

[0036] Secondly, the present invention provides a management system based on the above-described Nand Flash address mapping management method, comprising:

[0037] A first setting module is configured to set a first area and a second area in Flash storage. The first area includes a first data block, and the first data block includes a plurality of first data pages. The second area includes a plurality of second data blocks, and each second data block includes a plurality of second data pages.

[0038] The second setting module is configured to set the initial write threshold and the usage rate of the first area;

[0039] A data acquisition module is configured to acquire cached data packets and obtain the data size of the cached data packets.

[0040] The judgment module is configured to judge the data size and the initial write threshold size. If the data size is less than or equal to the initial write threshold, the cached data packet is stored in the first area. If the data size is greater than the initial write threshold, the cached data packet is stored in the second area.

[0041] A first calculation module is configured to obtain the page utilization rate of the first area;

[0042] The second calculation module is configured to calculate and update the initial write threshold based on the page utilization rate, the set utilization rate and the initial write threshold, to obtain the updated write threshold.

[0043] A writing module is configured to update the initial writing threshold to the updated writing threshold and repeat steps S300-S700.

[0044] Thirdly, the present invention provides a terminal device including a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of the Nand Flash address mapping management method described above.

[0045] Fourthly, the present invention provides a readable storage medium on which a program or instruction is stored, and when the program or instruction is executed by a processor, it implements the Nand Flash address mapping management method as described above.

[0046] In summary, this invention proposes a Nand Flash address mapping management method. By setting a first zone and a second zone in the Flash storage, and setting an initial write threshold and a set utilization rate for the first zone, the method determines the data size of the acquired cached data packet and the initial write threshold. Based on the determination result, the cached data packet is stored in either the first or second zone. After storage, the page utilization rate of the first zone is obtained. An updated write threshold is calculated using the page utilization rate, the set utilization rate, and the initial write threshold. The data size of the cached data packet is compared with the updated write threshold the next time it is stored. This application ensures that the first zone has sufficient reserved space by updating the write threshold using the page utilization rate, avoiding the first zone from becoming full and improving the read / write speed of the first zone. Attached Figure Description

[0047] Figure 1 A flowchart illustrating the Nand Flash address mapping management method provided in an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of the structure of the Nand Flash address mapping management method provided in an embodiment of the present invention;

[0049] Figure 3 This is a schematic diagram of the terminal device structure provided in an embodiment of the present invention. Detailed Implementation

[0050] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0051] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0052] Example 1

[0053] As mentioned in the background section, to address the problems in the prior art, this invention proposes a Nand Flash address mapping management method, such as... Figure 1 As shown, it includes the following steps:

[0054] S100. A first area and a second area are set in the Flash storage 4. The first area includes a first data block, and the first data block includes a plurality of first data pages. The second area includes a plurality of second data blocks, and each second data block includes a plurality of second data pages.

[0055] Please refer to Figure 2As shown, it includes Cache 1, FTL2 (Flash Translation Layer), DRAM3 (Dynamic Random Access Memory), and Flash storage 4. Cache 1 is used to send or receive data packets. One physical block in the Flash storage 4 space is used as the first area, and the remaining physical blocks are used as the second area. The first area is used to read / write small batches of data, and the second area is used to read / write large batches of data.

[0056] S200. Set the initial write threshold and usage rate for the first region;

[0057] Optionally, the initial write threshold S is set. t = 0.5, setting the set utilization rate u set = 80%.

[0058] S300. Obtain the cached data packet and obtain the data size of the cached data packet;

[0059] The cached data packets are first stored in the Cache 1. The data in the cached data packets is divided into n data packets of size s, where s is the size of one of the first data pages or the second data page.

[0060] S400. Determine the size of the data and the size of the initial write threshold. If the data size is less than or equal to the initial write threshold, store the cached data packet in the first area. If the data size is greater than the initial write threshold, store the cached data packet in the second area.

[0061] The FTL2 compares the data size n*s of the cached data packet with the initial write threshold St, and after the comparison is completed, stores the cached data packet in the Cache 1 into the first area or the second area.

[0062] S500. Obtain the page utilization rate of the first area;

[0063] If the cached data packet is stored in the first area, the page utilization rate will change; if the cached data packet is stored in the second area, the page utilization rate will not change.

[0064] S600. Calculate and update the initial write threshold based on the page utilization rate, the set utilization rate, and the initial write threshold to obtain the updated write threshold; including the following steps:

[0065] S601. Establish a write threshold relationship, as shown below:

[0066] S t new = S t + K(u set -u)

[0067] Among them, S t u represents the initial write threshold; u represents the page utilization rate; u set S represents the set usage rate; t new This represents the update write threshold, where K is the write coefficient, and 0 < K ≤ 1;

[0068] S602. Substitute the page utilization rate, the set utilization rate, and the initial write threshold into the write threshold formula to obtain the update write threshold.

[0069] S700. Update the initial write threshold to the updated write threshold, and repeat steps S300-S700.

[0070] Specifically, Cache 1 sends the cached data packet to FTL2, according to formula S. t new = S t +K(u set -u), the writing process is as follows:

[0071] in u set >Before u, K(u set -u) is a positive value, therefore S t new Gradually increase the size to ensure that more of the cached data packets conform to n*s≤S t The data is stored in the first area according to the given conditions, making full use of the first area to read and write small batches of data;

[0072] in u set After ≤u, K(u) set -u) is negative, therefore S t new Gradually decrease the size of the cached data packets so that n*s > S t The data is stored in the second area according to the conditions, so as to avoid small batches of data from entering the first area again, and to ensure that the first area has sufficient reserved space.

[0073] This invention divides the Flash storage into a first area and a second area. By determining the size of the cache data packet to be stored, the cache data packet is stored in either the first area or the second area. Small batches of data are stored in the first area, which improves the speed of reading small batches of data. In addition, the concept of page utilization is introduced. The update write threshold is obtained by adaptively updating after each data storage, which controls the write data stored in the first area and the second area. This makes full use of the space in the first area and ensures that the first area has sufficient reserved space to avoid the first area being full, which further improves the read and write speed of the first area.

[0074] Example 2

[0075] Example 1 specifically explains the data writing process. Based on Example 1, this example specifically explains the data extraction process. After step S100, the following steps are also included:

[0076] S101. Obtain the logical address;

[0077] The access instruction issued by the Cache 1 to the FTL 2 includes a logical address;

[0078] S102. Search the first area and determine whether the first area has a first address that is the same as the logical address. If it does, proceed to step S103; otherwise, proceed to step S104.

[0079] S103. Extract the data corresponding to the first address;

[0080] The DRAM3 is a dynamic random access memory used to store mapping tables, which include a first page mapping table, a second block mapping table, and multiple second page mapping tables.

[0081] Before sending the logical address to the DRAM, the logical address needs to be converted into a first page logical address, and then retrieved from the first page mapping table based on the first page logical address; the format of the first page mapping table is shown in Table-1:

[0082] Table 1

[0083]

[0084] Wherein, LPN is the page logical address, PPN is the page physical address on Flash storage 4, and the data storage format of the first area is shown in Table-2:

[0085] Table 2

[0086]

[0087] For example, if the logical address is converted to the first page logical address LPN=3, according to Table-1, then PPN=1, and according to Table-2, the corresponding data is data 2. Then, FTL2 will extract data 2 and send it to the Cache cache 1.

[0088] S104. Search the second region, obtain the second address in the second region that is the same as the logical address, and extract the data corresponding to the second address.

[0089] If the first page logical address is not found in the first region, FTL2 converts the page logical address into a second block logical address and a second page logical address, and performs a search in the second region; the second region block mapping table is shown in Table-3:

[0090] Table 3

[0091]

[0092] Wherein, LBN is the block logical address and PBN is the block physical address of the second region. For ease of description and illustration, when the logical address is converted to the second block logical address LBN=3 and the second page logical address LPN=0, then according to Table-3, the corresponding second region page mapping table with PBN=2 is shown in Table-4:

[0093] Table 4

[0094]

[0095] The data storage format of the second zone is shown in Table 5:

[0096] Table 5

[0097]

[0098] When the second page logical address LPN=0, according to Table-4, PPN=15, and according to Table-5, the corresponding data is data 19. Then, FTL2 will extract data 19 and send it to the Cache cache 1.

[0099] Example 3

[0100] Based on Embodiment 1, the present invention also proposes a method for garbage collection of invalid data, wherein the second data block includes a free block and a non-free block, the non-free block includes a first invalid data page and a first valid data page, and the following steps are included after step S100:

[0101] S111. Set the free block threshold for the second region and obtain the number of free blocks in the second region;

[0102] S112. When it is determined that the number of free blocks is less than the free block threshold, compare the number of the first invalid data pages in the non-free blocks, obtain the non-free block with the largest number of the first invalid data pages, and set it as the largest non-free block;

[0103] S113. Write the data of all the first valid data pages in the largest non-free block into the free block;

[0104] S114. Erase the largest non-free block.

[0105] The above steps perform garbage collection on the second area. The free blocks are unoccupied blocks, and the non-free blocks are blocks occupied by stored data. When the number of free blocks is less than the free block threshold, it indicates that the storage space of the second area is too small and garbage collection is required. After erasing the largest non-free block, the largest non-free block becomes a free block, increasing the amount of data that can be written to the free blocks. This avoids data transfer and erasure operations during the writing process, ensuring the writing speed of the second area.

[0106] In a preferred embodiment, the first data page includes occupied pages and free pages. The occupied pages are the number of pages in the first region that store the cached data packets, including the second invalid data page and the second valid data page. After step S100, the following steps are further included:

[0107] S121. Set the threshold for invalid data pages in the first region, and obtain the number of invalid data pages in the second region;

[0108] S122. If the number of the second invalid data pages is greater than the invalid data page threshold, write the data of the second valid data page into the free page;

[0109] S123. Erase the occupied page.

[0110] The above steps perform garbage collection on the first area. The free page is an unoccupied page, and the occupied page is a page occupied by stored data. When there are many second invalid data pages, garbage collection needs to be performed on the first area to avoid the situation where the first area cannot be written to after being occupied by the second invalid data pages. This also avoids the situation where, during writing, the first area is occupied by the second invalid data pages, and it is necessary to wait for the data in the first area to be transferred and erased, which would reduce the writing speed.

[0111] Furthermore, the DRAM3 is also used to store a log table, which includes a block log table for recording the number of block erases and a page log table for recording the physical location status of pages. After the garbage collection operation is completed, the block log table in the DRAM3 is updated to record the number of block erases, which is used by other algorithms to optimize the erase lifetime. The block log table is shown in Table-6.

[0112] Table 6

[0113]

[0114] In a preferred embodiment, step S500 includes the following steps:

[0115] S501. Obtain the total number of the first data pages in the first region, which is the first total number;

[0116] S502. Obtain the total number of occupied pages, which is the number of occupied pages;

[0117] S503. Divide the number of occupied pages by the first total number to obtain the page utilization rate.

[0118] Specifically, FTL2 obtains the number of occupied pages and the first total number through the page log table, as shown in Table-7:

[0119] Table 7

[0120]

[0121] 0 represents that no data has been written to the first data page, and it is marked as a free page; 1 represents that data has been written to the first data page and the data is valid, and it is marked as a second valid data page; 2 represents that data has been written to the first data page but the data is invalid, and it is marked as a second invalid data page. When the size of the cached data packet is less than or equal to the initial write threshold, the cached data packet is stored in the first area, and the state of the written first data page is 1. When the first data page in state 1 needs to be deleted, the minimum erase unit should be a block, so it will not be deleted immediately. The state of the first data page will be changed from 1 to 2, waiting for garbage collection to delete it. Therefore, the first total and the number of occupied pages can be obtained through Table-7. The first total is the sum of the first data pages with current states of 0, 1, and 2, and the number of occupied pages is the sum of the first data pages with current states of 1 and 2.

[0122] Example 4

[0123] Based on Example 1, this invention proposes a management system based on a Nand Flash address mapping management method, comprising:

[0124] A first setting module is configured to set a first area and a second area in Flash storage. The first area includes a first data block, and the first data block includes a plurality of first data pages. The second area includes a plurality of second data blocks, and each second data block includes a plurality of second data pages.

[0125] The second setting module is configured to set the initial write threshold and the usage rate of the first area;

[0126] A data acquisition module is configured to acquire cached data packets and obtain the data size of the cached data packets.

[0127] The judgment module is configured to judge the data size and the initial write threshold size. If the data size is less than or equal to the initial write threshold, the cached data packet is stored in the first area. If the data size is greater than the initial write threshold, the cached data packet is stored in the second area.

[0128] A first calculation module is configured to obtain the page utilization rate of the first area;

[0129] The second calculation module is configured to calculate and update the initial write threshold based on the page utilization rate, the set utilization rate and the initial write threshold, to obtain the updated write threshold.

[0130] A writing module is configured to update the initial writing threshold to the updated writing threshold and repeat steps S300-S700.

[0131] This invention proposes a Nand Flash address mapping management method. By setting a first area and a second area in the Flash storage 4, and setting an initial write threshold and a set utilization rate for the first area, the method determines the data size of the acquired cached data packet and the size of the initial write threshold. Based on the determination result, the cached data packet is stored in the first area or the second area. After storage, the page utilization rate of the first area is obtained. An update write threshold is calculated using the page utilization rate, the set utilization rate, and the initial write threshold. The data size of the cached data packet is compared with the update write threshold the next time it is stored. This application updates the write threshold using the page utilization rate, ensuring that the first area has sufficient reserved space, avoiding the first area from becoming full, and improving the read / write speed of the first area. The management system provided by this invention can implement the various processes implemented in the above method embodiments, and has corresponding functional modules and beneficial effects. To avoid repetition, these will not be elaborated further here.

[0132] Example 5

[0133] This invention proposes a terminal device, such as... Figure 3 As shown, the computer system 700 of the terminal device includes a CPU (Central Processing Unit) 701, which can perform various appropriate actions and processes according to programs stored in ROM (Read-Only Memory) 702 or programs loaded from storage section 708 into RAM (Random Access Memory) 703. RAM 703 also stores various programs and data required for system operation. The CPU 701, ROM 702, and RAM 703 are interconnected via bus 704. An I / O (Input / Output) interface 705 is also connected to bus 704. The following components are connected to I / O interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. Drivers are also connected to I / O interface 705 as needed. Removable media 711, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on drive 710 as needed so that computer programs read from them can be installed into storage section 708 as needed.

[0134] In particular, according to embodiments of the present invention, the above-described reference process Figure 1 The described process can be implemented as a computer software program. For example, Embodiment 1 of the present invention includes a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by CPU 701, it performs the functions defined in the computer system 700 described above.

[0135] Example 6

[0136] The present invention also provides a computer-readable medium carrying one or more programs, which, when executed by an electronic device, cause the electronic device to implement the Nand Flash address mapping management method as described in the above embodiments.

[0137] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments disclosed in this invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0138] Furthermore, although the steps of the method in this invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented in software or in combination with necessary hardware.

Claims

1. A Nand Flash address mapping management method, characterized in that, Includes the following steps: S100. A first area and a second area are configured in the Flash storage. The first area includes a first data block, and the first data block includes a plurality of first data pages. The second area includes a plurality of second data blocks, and each second data block includes a plurality of second data pages. S200. Set the initial write threshold and usage rate for the first region; S300. Obtain the cached data packet and obtain the data size of the cached data packet; S400. Determine the size of the data and the size of the initial write threshold. If the data size is less than or equal to the initial write threshold, store the cached data packet in the first area. If the data size is greater than the initial write threshold, store the cached data packet in the second area. S500. Obtain the page utilization rate of the first area; S600. Calculate and update the initial write threshold based on the page utilization rate, the set utilization rate, and the initial write threshold to obtain the updated write threshold; S700. Update the initial write threshold to the updated write threshold, and repeat steps S300-S700.

2. The Nand Flash address mapping management method according to claim 1, characterized in that, Step S600 includes the following steps: S601. Establish a write threshold relationship, as shown below: WITH t new = S t + K(in set -in) Among them, S t u represents the initial write threshold; u represents the page utilization rate; u set S represents the set usage rate; t new This represents the update write threshold, where K is the write coefficient, and 0 < K ≤ 1; S602. Substitute the page utilization rate, the set utilization rate, and the initial write threshold into the write threshold formula to obtain the update write threshold.

3. The Nand Flash address mapping management method according to claim 1, characterized in that, Step S100 is followed by the following steps: S101. Obtain the logical address; S102. Search the first area and determine whether the first area has a first address that is the same as the logical address. If it does, proceed to step S103; otherwise, proceed to step S104. S103. Extract the data corresponding to the first address; S104. Search the second region, obtain the second address in the second region that is the same as the logical address, and extract the data corresponding to the second address.

4. The Nand Flash address mapping management method according to claim 1, characterized in that, The second data block includes free blocks and non-free blocks, wherein the non-free blocks include a first invalid data page and a first valid data page. Following step S100, the following steps are also included: S111. Set the free block threshold for the second region and obtain the number of free blocks in the second region; S112. When it is determined that the number of free blocks is less than the free block threshold, compare the number of the first invalid data pages in the non-free blocks, obtain the non-free block with the largest number of the first invalid data pages, and set it as the largest non-free block; S113. Write the data of all the first valid data pages in the largest non-free block into the free block; S114. Erase the largest non-free block.

5. The Nand Flash address mapping management method according to claim 4, characterized in that, The first data page includes occupied pages and free pages. The occupied page is the number of pages in the first area that store the cached data packet, including the second invalid data page and the second valid data page. After step S100, the following steps are also included: S121. Set the threshold for invalid data pages in the first region, and obtain the number of invalid data pages in the second region; S122. If the number of the second invalid data pages is greater than the invalid data page threshold, write the data of the second valid data page into the free page; S123. Erase the occupied page.

6. The Nand Flash address mapping management method according to claim 5, characterized in that, Step S500 includes the following steps: S501. Obtain the total number of the first data pages in the first region, which is the first total number; S502. Obtain the total number of occupied pages, which is the number of occupied pages; S503. Divide the number of occupied pages by the first total number to obtain the page utilization rate.

7. A management system based on the Nand Flash address mapping management method according to any one of claims 1-6, characterized in that, include: A first setting module is configured to set a first area and a second area in Flash storage. The first area includes a first data block, and the first data block includes a plurality of first data pages. The second area includes a plurality of second data blocks, and each second data block includes a plurality of second data pages. The second setting module is configured to set the initial write threshold and the usage rate of the first area; A data acquisition module is configured to acquire cached data packets and obtain the data size of the cached data packets. The judgment module is configured to judge the data size and the initial write threshold size. If the data size is less than or equal to the initial write threshold, the cached data packet is stored in the first area. If the data size is greater than the initial write threshold, the cached data packet is stored in the second area. A first calculation module is configured to obtain the page utilization rate of the first area; The second calculation module is configured to calculate and update the initial write threshold based on the page utilization rate, the set utilization rate and the initial write threshold, to obtain the updated write threshold. A writing module is configured to update the initial writing threshold to the updated writing threshold and repeat steps S300-S700.

8. A terminal device, characterized in that, The device includes a processor and a memory, wherein the memory stores a computer program that, when executed by the processor, causes the processor to perform the steps of the Nand Flash address mapping management method according to any one of claims 1-6.

9. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions, which, when executed by a processor, implement the Nand Flash address mapping management method as described in any one of claims 1-6.

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