A method, system, and apparatus for block convolution computation for vision tasks

By employing a block-based convolutional computation method and edge padding technology, the resource limitations of embedded devices were addressed, enabling high-precision and high-efficiency convolutional neural network computation and improving the user experience of the devices.

CN117152516BActive Publication Date: 2026-05-29INST OF AUTOMATION CHINESE ACAD OF SCI

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
INST OF AUTOMATION CHINESE ACAD OF SCI
Filing Date
2023-08-31
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

In existing technologies, embedded devices, due to resource limitations, find it difficult to deploy convolutional neural network models with large numbers of parameters and computational demands, resulting in reduced model accuracy and impacting user experience.

Method used

The block convolution calculation method is adopted, which breaks down the convolution calculation into multiple independent block calculations and converts it into a block convolution model by padding the edges with zeros. The weight parameters are optimized to maintain accuracy and adapt to the memory limitations of embedded devices.

Benefits of technology

It achieves high-precision and high-efficiency computing on embedded devices, improves user experience, and is suitable for devices such as robot vacuum cleaners, smart door locks, and home cameras.

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Abstract

The application belongs to the field of image processing, and particularly relates to a block convolution calculation method, system and device for a visual task, aiming to solve the problem that the calculation resource occupation of the existing graphic processing method is too large, resulting in that the neural network model is difficult to apply in an embedded device with insufficient size or performance. The application comprises the following steps: acquiring a to-be-processed feature map by an image acquisition device, and marking the feature map as a 0th layer feature map; marking the layer number of the current feature map as i, at this time i=0; equally dividing the current feature map into a plurality of original blocks with a preset size; performing edge zero padding based on the original blocks to obtain zero padding blocks; and performing calculation on the zero padding blocks one by one through a convolution layer to obtain an (i+1)th layer feature map. According to the application, the calculation of each layer of convolution is split into several independent block convolution calculations, and compared with an ordinary convolution model, the required memory is smaller in the case of the same model accuracy.
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