Gate driving circuit and driving method, display panel, gate driver, driving chip

Abstract

Disclosed are a gate driving circuit and driving method, a display panel, a gate driver, and a driving chip. The gate driving circuit comprises: a first gate driving module configured to generate a row scanning signal of a next row according to a row scanning signal of a previous row; and a second gate driving module connected with the first gate driving module and configured to generate a row scanning signal of a current row according to the row scanning signal of the next row, wherein the second gate driving module enables or disables the row scanning signal of the current row according to a control signal, thereby controlling a refresh rate of the display panel, and the control signal comprises a first control signal and a second control signal. The gate driving circuit and driving method, the display panel, and the gate driver provided by the present application can control the output waveform of the row scanning signal of the current row by adding the second gate driving module to the gate driving circuit, thereby enabling the corresponding row of pixels to enter a refresh frame or a hold frame, and thus the refresh rate control precision is in units of rows.

Description

Technical Field

[0001] This invention relates to the field of gate driving technology, and in particular to a gate driving circuit and driving method, a display panel, a gate driver, and a driving chip. Background Technology

[0002] Flexible organic light-emitting diode (OLED) display panels have developed rapidly in recent years, evolving from curved displays to foldable displays. The bending angle has increased from within 90° to 180° of opposite folding, and the size has gradually increased from 5.5 inches to 8 inches.

[0003] With the emergence of technologies supporting low refresh rates, such as LTPO, it has become possible for OLED or LCD to achieve multiple frame rate drives. The advent of foldable screens has led to a continuous increase in display area, and terminals are placing new demands on the use of foldable screens, such as partitioning to achieve different refresh rates. Summary of the Invention

[0004] In view of the above problems, the purpose of the present invention is to provide a gate driving circuit and driving method, a display panel, a gate driver, and a driving chip. By adding a second gate driving module to the gate driving circuit, the output waveform of the row scanning signal of the current row can be controlled, thereby controlling the corresponding row pixels to enter the refresh frame or hold frame, so that the refresh rate control accuracy is in the row unit.

[0005] According to one aspect of the present invention, a gate driving circuit for a display panel is provided, comprising: a first gate driving module for generating a next row scanning signal based on a previous row scanning signal; and a second gate driving module connected to the first gate driving module for generating a current row scanning signal based on the next row scanning signal, wherein the second gate driving module enables or disables the current row scanning signal based on a control signal to control the refresh rate of the display panel, the control signal including a first control signal and a second control signal.

[0006] Optionally, the disable includes clamping the output of the second gate drive module to a fixed low or high level.

[0007] Optionally, the first gate drive module includes N-type and P-type gates.

[0008] Optionally, the first gate driving module includes: an input module for receiving the row scan signal of the previous row according to a first clock signal; a latch module for latching the row scan signal of the previous row according to a first clock signal and a second clock signal; and a driving module for outputting the row scan signal of the next row according to the row scan signal of the previous row.

[0009] Optionally, the second gate driving module includes: a first switch transistor, the first path terminal of which receives the row scan signal of the next row; and a second switch transistor, the first path terminal of which is connected to the second path terminal of the first switch transistor, wherein the connection point of the first switch transistor and the second switch transistor outputs the row scan signal of the current row.

[0010] Optionally, the control terminal of the first switch is connected to one of the first control signal and the second control signal, and the control terminal of the second switch is connected to the other of the second control signal and the first control signal.

[0011] Optionally, the first switch and the second switch are not turned on at the same time; when the first switch is turned on, the row scan signal of the current row controls the corresponding pixel row to enter the refresh frame; when the second switch is turned on, the row scan signal of the current row controls the corresponding pixel row to enter the hold frame.

[0012] Optionally, the first switching transistor is an N-type transistor and the second switching transistor is a P-type switching transistor; or both the first switching transistor and the second switching transistor are P-type switching transistors.

[0013] Optionally, the second gate driving module includes: a third switch transistor, the control terminal of which is connected to the first output terminal of the latch module, and the first path terminal of which is connected to the first power supply terminal; a fourth switch transistor, the control terminal of which is connected to the second output terminal of the latch module, and the first path terminal of which is connected to the second path terminal of the third switch transistor; a fifth switch transistor, the control terminal of which is connected to a second control signal, the first path terminal of which is connected to the second path terminal of the fourth switch transistor, and the second path terminal of which is connected to the first power supply terminal; a sixth switch transistor, the control terminal of which is connected to the first control signal, the first path terminal of which is connected to the second path terminal of the fourth switch transistor, and the second path terminal of which is connected to a second clock signal; a sixth capacitor, one end of which is connected to the control terminal of the third switch transistor, and the other end of which is connected to the first path terminal of the third switch transistor; and a seventh capacitor, one end of which is connected to the control terminal of the fourth switch transistor, and the other end of which is connected to the first path terminal of the fourth switch transistor, wherein the connection point of the third switch transistor and the fourth switch transistor outputs the row scan signal of the current row.

[0014] Optionally, the control terminal of the fifth switch is connected to one of the first control signal and the second control signal, and the control terminal of the sixth switch is connected to the other of the second control signal and the first control signal.

[0015] Optionally, the fifth switch and the sixth switch are not turned on at the same time. When the sixth switch is turned on, the row scan signal of the current row controls the corresponding pixel row to enter the refresh frame; when the fifth switch is turned on, the row scan signal of the current row controls the corresponding pixel row to enter the hold frame.

[0016] Optionally, the fifth switch is an N-type transistor and the sixth switch is a P-type switch; or both the fifth and sixth switches are P-type switches.

[0017] Optionally, when the gate driving circuit is a first stage, the first gate driving module generates the row scanning signal for the next row based on the input signal NSVT or GSVT.

[0018] According to another aspect of the present invention, a gate driving method is provided, wherein the gate driving method is used in the above-described gate driving circuit.

[0019] According to another aspect of the present invention, a display panel is provided, wherein the current pixel row of the display panel is connected to the row scan signal of the current row of the aforementioned gate driving circuit.

[0020] According to another aspect of the present invention, a gate driver is provided, comprising a plurality of cascaded gate driving circuits as described above, wherein the row scan signal of the previous row of the gate driving circuit of the current stage is the row scan signal of the next row of the gate driving circuit of the previous stage.

[0021] According to another aspect of the present invention, a driver chip is provided, wherein the above-described gate driver is included.

[0022] The gate driving circuit and driving method, display panel, gate driver, and driving chip provided by this invention achieve control of the gate output waveform by adding a second gate driving module to the gate driving circuit, thereby controlling different pixel rows to have different refresh rates, and thus making the refresh rate control precision in rows.

[0023] Furthermore, the gate driving circuit and driving method, display panel, gate driver, and driving chip provided in this application allow the gate driving circuit to control the refresh rate of each line simply by pulling the first control signal high or low according to the pre-written refresh rate information. Attached Figure Description

[0024] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram of a gate driver according to the prior art is shown;

[0026] Figure 2a and Figure 2b Schematic diagrams of two gate drive circuits according to the prior art are shown;

[0027] Figures 3a to 3c A schematic diagram of the gate driving circuit according to a first embodiment of the present invention and a corresponding waveform diagram are shown.

[0028] Figures 4a to 4c A schematic diagram of the gate driving circuit according to a second embodiment of the present invention and a corresponding waveform diagram are shown.

[0029] Figure 5 A schematic diagram of a gate driving circuit according to a third embodiment of the present invention is shown;

[0030] Figure 6 A schematic diagram of a gate driving circuit according to a fourth embodiment of the present invention is shown;

[0031] Figure 7a and Figure 7b Waveform diagrams corresponding to the gate drive circuits according to the third and fourth embodiments of the present invention are shown;

[0032] Figure 8 A schematic diagram of a gate driving circuit according to a fifth embodiment of the present invention is shown;

[0033] Figure 9 A schematic diagram of a gate driving circuit according to a sixth embodiment of the present invention is shown;

[0034] Figure 10a and Figure 10b Waveform diagrams corresponding to the gate drive circuits according to the fifth and sixth embodiments of the present invention are shown;

[0035] Figure 11 A schematic diagram of the structure of a display device according to an embodiment of this application is shown. Detailed Implementation

[0036] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0037] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0038] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0039] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The ordinal numbers such as "first," "second," and "third" used in the embodiments of this disclosure do not indicate any order, quantity, or importance, and are provided to avoid confusion of constituent elements, not to limit in terms of quantity. Words such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0040] Those skilled in the art will understand that the transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Preferably, the thin-film transistors used in the embodiments of this application can be oxide semiconductor transistors. Since the source and drain of the transistors used here are symmetrical, their source and drain can be interchanged. In the embodiments of this application, the gate of the transistor is referred to as the control terminal. To distinguish the two ends of the transistor other than the gate, one end is referred to as the first path terminal and the other end as the second path terminal. The first path terminal can be the source or the drain, and the second path terminal can be the drain or the source.

[0041] Figure 1 A schematic diagram of a gate driver according to the prior art is shown; Figure 2a and Figure 2b A schematic diagram of two gate drive circuits according to the prior art is shown.

[0042] refer to Figure 1 The gate driver 100 includes n gate driving circuits 110 cascaded in sequence. Each gate driving circuit 110 includes an input terminal INPUT, a first clock terminal CLK1, a second clock terminal CLK2, a first power supply terminal VGH, a second power supply terminal VGL, and an output terminal Vout. In the gate driver 100, the input terminal INPUT of the second to nth stage gate driving circuits 110 is sequentially connected to the output terminal Vout of the previous stage gate driving circuit 110; the input terminal of the first stage gate driving circuit 110 is connected to GSTV or NSTV.

[0043] exist Figure 1 In the gate driver 100 shown, n gate driving circuits 110 connected in sequence are divided into multiple display areas, for example, each display area is a display panel of a foldable screen.

[0044] Figure 2a A schematic diagram of a gate driving circuit is shown, wherein the gate driving circuit 110-N is, for example, an N-type gate driving circuit, used for driving an N-type transistor display panel.

[0045] refer to Figure 2a The gate drive circuit 110-N includes an input module 111, a latch module 112, and a drive module 113, which are connected in sequence.

[0046] Specifically, the input module 111 includes a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 are connected in series, and the control terminals of both transistors T1 and T2 are connected to the first clock signal CLK1. The first path terminal of the first transistor T1 (i.e., the input terminal INPUT of the gate drive circuit 110-N) is connected to the row scan signal of the previous row. If the gate drive circuit 110-N is the first-stage gate drive circuit in the gate driver 100, then the first path terminal of the first transistor T1 is connected to NSTV. In this embodiment, the second path terminal of the second transistor T2 is the output terminal of the input module 111.

[0047] The latch module 112 includes transistors T3 through T12, and a first capacitor C1. Transistors T3 and T4 are connected in series, and the control terminals of both transistors T3 and T4 are connected to the first clock signal CLK1. The first path terminal of transistor T3 is connected to the second power supply terminal VGL. The control terminal of transistor T5 is connected to the output terminal of input module 111, its first path terminal is connected to the first clock signal CLK1, and its second path terminal is connected to the second path terminal of transistor T4. The control terminal of transistor T6 is connected to the second power supply terminal VGL, and its first path terminal is connected to the second path terminal of transistor T4. The control terminal of transistor T7 is connected to the second path terminal of transistor T6, and its first path terminal is connected to the second clock signal CLK2. The control terminal of transistor T8 is connected to the second path terminal of transistor T4, and its first path terminal is connected to the first power supply terminal VGH. The control terminal of transistor T9 is connected to the second clock signal CLK2, its first path terminal is connected to the second path terminal of transistor T8, and its second path terminal is connected to the output terminal of input module 111. The control terminal of the tenth transistor T10 is connected to the second clock signal CLK2, and its first path terminal is connected to the second path terminal of the seventh transistor T7. The control terminal of the eleventh transistor T11 is connected to the output terminal of the input module 111, its first path terminal is connected to the second path terminal of the tenth transistor T10, and its second path terminal is connected to the first power supply terminal VGH. The control terminal of the twelfth transistor T12 is connected to the second power supply terminal VGL, and its first path terminal is connected to the output terminal of the input module 111. One end of the first capacitor C1 is connected to the control terminal of the seventh transistor T7, and the other end is connected to the second path terminal of the seventh transistor T7. In this embodiment, the second path terminal of the tenth transistor T10 serves as the first output terminal of the latch module 112, and the second path terminal of the twelfth transistor T12 serves as the second output terminal of the latch module 112.

[0048] The driving module 113 includes a thirteenth transistor T13 and a fourteenth transistor T14, as well as a second capacitor C2 and a third capacitor C3. The control terminal of the thirteenth transistor T13 is connected to the first output terminal of the latch module 112, and its first path terminal is connected to the first power supply terminal VGH. The control terminal of the fourteenth transistor T14 is connected to the second output terminal of the latch module 112, its first path terminal is connected to the second path terminal of the thirteenth transistor T13, and its second path terminal is connected to the second power supply terminal VGL. One end of the second capacitor C2 is connected to the second output terminal of the latch module 112, and its second end is connected to the second clock signal CLK2. One end of the third capacitor C3 is connected to the first output terminal of the latch module 112, and its other end is connected to the first path terminal of the thirteenth transistor T13. In this embodiment, the connection point of the thirteenth transistor T13 and the fourteenth transistor T14 is the output terminal of the driving module 113, used to output the gate drive signal Vout, which serves as the row scan signal for the current row.

[0049] Figure 2b A schematic diagram of another gate driving circuit is shown, wherein the gate driving circuit 110-P is, for example, a P-type gate driving circuit used for driving a display panel with P-type transistors.

[0050] refer to Figure 2b The gate drive circuit 110-P includes an input module 111, a latch module 112, and a drive module 113, which are connected in sequence.

[0051] Specifically, the input module 111 includes a fifteenth transistor T15. The control terminal of the fifteenth transistor T15 is connected to the first clock signal CLK1, and its first path terminal (i.e., the input terminal of the gate drive circuit 110-P) is connected to the row scan signal of the previous row. If the gate drive circuit 110-P is the first-stage gate drive circuit in the gate driver 100, then the first path terminal of the fifteenth transistor T15 is connected to NSTV. In this embodiment, the second path terminal of the fifteenth transistor T15 is the output terminal of the input module 111.

[0052] The latch module 112 includes sixteenth transistor T16 to twentieth transistor T20. The control terminal of the sixteenth transistor T16 is connected to the first clock signal CLK1, and its first path terminal is connected to the second power supply terminal VGL. The control terminal of the seventeenth transistor T17 is connected to the output terminal of the input module 111, its first path terminal is connected to the second path terminal of the sixteenth transistor T16, and its second path terminal is connected to the first clock signal CLK1. The control terminal of the eighteenth transistor T18 is connected to the second path terminal of the sixteenth transistor T16, and its first path terminal is connected to the first power supply terminal VGH. The control terminal of the nineteenth transistor T19 is connected to the second clock signal CLK2, its first path terminal is connected to the second path terminal of the eighteenth transistor T18, and its second path terminal is connected to the output terminal of the input module 111. The control terminal of the twentieth transistor T20 is connected to the second power supply terminal VGL, and its first path terminal is connected to the output terminal of the input module 111. In this embodiment, the second path terminal of the sixteenth transistor T16 serves as the first output terminal of the latch module 112, and the second path terminal of the twentieth transistor T20 serves as the second output terminal of the latch module 112.

[0053] The driving module 113 includes a twenty-first transistor T21 and a twenty-second transistor T22, as well as a fourth capacitor C4 and a fifth capacitor C5. The control terminal of the twenty-first transistor T21 is connected to the first output terminal of the latch module 112, and its first path terminal is connected to the first power supply terminal VGH. The control terminal of the twenty-second transistor T22 is connected to the second output terminal of the latch module 112, its first path terminal is connected to the second path terminal of the twenty-first transistor T21, and its second path terminal is connected to the second clock signal CLK2. One end of the fourth capacitor C4 is connected to the first output terminal of the latch module 112, and its second end is connected to the first path terminal of the twenty-first transistor T21. One end of the fifth capacitor C5 is connected to the second output terminal of the latch module 112, and its other end is connected to the first path terminal of the twenty-second transistor T22. In this embodiment, the connection point of the twenty-first transistor T21 and the twenty-second transistor T22 is the output terminal of the driving module 113, used to output the gate drive signal Vout.

[0054] Since multiple gate drive circuits 110 are cascaded, the waveforms of the gate drive signals Vout output by the multiple gate drive circuits 110 are the same, so the refresh rate of the display panel is also the same when displaying the image.

[0055] To enable different frame rates for the gate driver, the input voltage GSTV or NSTV of the first-stage gate driver circuit needs to be converted to a DC voltage VGH or VGL. As a result, under the cascading effect, the output of all gate driver circuits becomes a DC voltage, the image is no longer refreshed, and a hold frame is maintained, thereby saving display driver (DDIC) power.

[0056] However, with the emergence of foldable screens, people have put forward new requirements for the use of terminals, such as partitioning to achieve different refresh rates.

[0057] The inventors of this application have noticed the above problems and proposed a gate driving circuit and driving method, and a display panel. By adding a second gate driving module to the gate driving circuit, the gate output waveform can be controlled, thereby controlling the periodic differences in the entry of different rows of pixels into the frame skipping, so that the refresh rate control precision is in the row unit.

[0058] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0059] Figures 3a to 3c A schematic diagram and corresponding waveform diagram of a gate driving circuit according to a first embodiment of the present invention are shown. In this embodiment, the gate driving circuit is, for example, an N-type.

[0060] refer to Figure 3a The gate drive circuit 210-N1 (N1 represents the first embodiment of the N-type gate drive circuit) of the first embodiment of this application includes a first gate drive module 110 and a second gate drive module 220. The first gate drive module 110 includes an input module 111, a latch module 112 and a drive module 113.

[0061] In this stage, the first output terminal Vout1 of the driving module 113 of the gate driving circuit 210 outputs the row scan signal of the next row, which serves as the input signal of the next-stage gate driving circuit 210, i.e., the row scan signal of the previous row. The input terminal of the second gate driving module 220 is connected to the first output terminal Vout1 of the driving module 113, and the output terminal of the second gate driving module 220 is connected to the corresponding pixel row of the display panel. The row scan signal of the current row output by the second gate driving module 220 is used to control the refresh rate of the corresponding pixel row of the display panel and the gate driving circuit 210. That is, the second gate driving module 220 enables or disables the row scan signal of the current row according to the control signal, thereby controlling the refresh rate of the display panel. The control signal includes a first control signal EN and a second control signal ENB. Enabling or disabling the row scan signal of the current row according to the control signal includes clamping the output terminal of the second gate driving module 220 to a fixed low level or high level. Figure 3a In the illustrated embodiment, for example, the clamp is located at a fixed low level.

[0062] Specifically, refer to Figure 3aThe second gate drive module 220 includes a first switch M1 and a second switch M2. The control terminal of the first switch M1 is connected to a first control signal EN, its first path terminal is connected to the output terminal Vout1 of the drive module 113, and its second path terminal is connected to the output terminal Vout2 of the second gate drive module 220. The control terminal of the second switch M2 is connected to a second control signal ENB, its first path terminal is connected to the second path terminal of the first switch M1, and its second path terminal is connected to the second power supply terminal VGL.

[0063] In this embodiment, the first switch M1 is, for example, an N-type switch, including IGZO (indium gallium zinc oxide), LTPS (Low Temperature Polysilicon), etc.; the second switch M2 is, for example, a P-type switch, including LTPS (Low Temperature Polysilicon).

[0064] Furthermore, Figure 3b and Figure 3c It shows Figure 3a The timing diagram of the gate drive circuit 210 is shown. The timing diagram shows the first clock signal CLK1, the second clock signal CLK2, the first control signal EN, the second control signal ENB, the row scan signal INPUT of the previous row, the row scan signal Vout1 of the next row, and the row scan signal Vout2 of the current row.

[0065] In this embodiment, since the first switch M1 is an N-type switch, the turn-on signal of the first switch M1 is high and the turn-off signal is low; the second switch M2 is a P-type switch, and the turn-on signal of the second switch M2 is low and the turn-off signal is high.

[0066] refer to Figure 3b Under the drive of the row scan signal INPUT, the first clock signal CLK1 and the second clock signal CLK2 of the previous row, the gate drive circuit 210 drives the drive module 113 to output the row scan signal Vout1 of the next row.

[0067] The second gate drive module 220 is connected to the drive module 113. Since the first control signal EN is high at time t1, the first switch M1 is turned on, and the second control signal ENB is high at time t1, the second switch M2 is turned off. Therefore, the current row scan signal Vout2 output by the gate drive circuit 210 has the same waveform as the next row scan signal Vout1.

[0068] refer to Figure 3cWhen at time t1, the first control signal EN is low and the first switch M1 is turned off; the second control signal ENB is low and the second switch M2 is turned on, so the row scan signal Vout2 of the current row output by the gate drive circuit 210 is the second power supply signal VGL of the second path terminal of the second switch M2.

[0069] In this embodiment, in order for the second switch M2 to use the second power supply signal VGL as the row scan signal Vout2 of the current row output by the gate drive circuit 210, the low level VGL1 of the second control signal ENB needs to be less than the second power supply signal VGL.

[0070] In this embodiment, the waveform of the driving signal of the gate driving circuit 210 relative to the corresponding pixel row in the display panel can be controlled by the first control signal EN and the second control signal ENB, thereby controlling the refresh rate of the corresponding row.

[0071] Figures 4a to 4c A schematic diagram of the gate driving circuit according to a second embodiment of the present invention and a corresponding waveform diagram are shown; in this embodiment, the gate driving circuit is, for example, N-type. Compared with the gate driving circuit of the first embodiment, the structure of the second gate driving module of the gate driving circuit 210-N2 in the second embodiment is different, where N2 represents the second embodiment of the N-type gate driving circuit.

[0072] refer to Figure 4a The second gate drive module 220 includes a first switch M1 and a second switch M2. The control terminal of the first switch M1 is connected to the second control signal ENB, the first path terminal is connected to the output terminal Vout1 of the drive module 113, and the second path terminal is connected to the output terminal Vout2 of the second gate drive module 220. The control terminal of the second switch M2 is connected to the first control signal EN, the first path terminal is connected to the second path terminal of the first switch M1, and the second path terminal is connected to the second power supply terminal VGL.

[0073] In this embodiment, the first switch M1 and the second switch M2 are, for example, P-type switches, including LTPS (Low Temperature Polysilicon).

[0074] Further, refer to Figure 4b At time t1, the first control signal EN is high and the second switch M2 is off; the second control signal ENB is low and the first switch M1 is on. Therefore, the current row scan signal Vout2 output by the gate drive circuit 210 has the same waveform as the next row scan signal Vout1.

[0075] refer to Figure 4cIf at time t1, the first control signal EN is low and the second switch M2 is turned on; and the second control signal ENB is high and the first switch M1 is turned off, then the row scan signal Vout2 of the current row output by the gate drive circuit 210 is the second power supply signal VGL of the second path terminal of the second switch M2.

[0076] Figure 5 A schematic diagram of the gate drive circuit according to a third embodiment of the present invention is shown; Figure 7a and Figure 7b The waveform diagram corresponding to the gate drive circuit of the third embodiment of the present invention is shown.

[0077] In the third embodiment, the gate drive circuit is, for example, a P-type. Compared with the first and second embodiments, the connection method of the second gate drive module 220 of the gate drive circuit 210 in the third embodiment is different, and the circuit structure of the second gate drive module 220 is also different.

[0078] refer to Figure 5 The second gate drive module 220 includes a third switch M3 to a sixth switch M6, a sixth capacitor C6, and a seventh capacitor C7. The control terminal of the third switch M3 is connected to the first output terminal of the latch module 112, and its first path terminal is connected to the first power supply terminal VGH. The control terminal of the fourth switch M4 is connected to the second output terminal of the latch module 112, and its first path terminal is connected to the second path terminal of the third switch M3. The control terminal of the fifth switch M5 is connected to a second control signal, its first path terminal is connected to the second path terminal of the fourth switch M4, and its second path terminal is connected to the first power supply terminal VGH. The control terminal of the sixth switch M6 is connected to a first control signal, its first path terminal is connected to the second path terminal of the fourth switch M4, and its second path terminal is connected to the second clock signal CLK2. One end of the sixth capacitor C6 is connected to the first output terminal of the latch module 112, and its second end is connected to the first path terminal of the third switch M3. One end of the seventh capacitor C7 is connected to the second output terminal of the latch module 112, and its other end is connected to the first path terminal of the fourth switch M4. In this embodiment, the connection point between the third switch M3 and the fourth switch M4 is the output terminal of the second gate drive module 220, which is used to output the gate drive signal Vout2.

[0079] In this embodiment, the fifth switch M5 is, for example, an N-type switch, including IGZO (indium gallium zinc oxide), LTPS (Low Temperature Poly-silicon), etc.; the sixth switch M6 is, for example, a P-type switch, including LTPS (Low Temperature Poly-silicon).

[0080] Further, refer to Figure 7a At time t1, the second control signal ENB is low, and the fifth switch M5 is turned off; the first control signal EN is low, and the sixth switch M6 is turned on. The second path terminal of the fourth switch M4 is connected to the second clock signal CLK2 via the sixth switch M6. Thus, the equivalent circuit structure of the second gate drive module 220 is the same as the equivalent circuit structure of the drive module 113. The row scan signal Vout2 of the current row output by the second gate drive module 220 is the same as the row scan signal Vout1 of the next row output by the drive module 113.

[0081] refer to Figure 7b At time t1, the first control signal EN is high, and the sixth switch M6 is off; the second control signal ENB is high, and the fifth switch M5 is on. Therefore, the second path terminal of the fourth switch M4 is connected to the first power supply terminal VGH via the fifth switch M5, resulting in the row scan signal Vout2 of the current row output by the second gate drive module 220 being a DC voltage VGH. In this embodiment, in order for the fifth switch M5 to electrically connect the first power supply terminal VGH to the second path terminal of the fourth switch M4, the high level VGH1 of the second control signal ENB should be greater than the first power supply terminal VGH.

[0082] Figure 6 A schematic diagram of the gate drive circuit according to a fourth embodiment of the present invention is shown.

[0083] In the fourth embodiment, the gate drive circuit is, for example, P-type. Compared with the first embodiment, the connection method of the second gate drive module 220 of the gate drive circuit 210 in the fourth embodiment is different; compared with the third embodiment, the circuit structure of the second gate drive module 220 of the gate drive circuit 210 in the fourth embodiment is also different.

[0084] refer to Figure 6 The second gate drive module 220 includes a first switch M1 and a second switch M2. The control terminal of the first switch M1 is connected to a first control signal EN, its first path terminal is connected to the output terminal Vout1 of the drive module 113, and its second path terminal is connected to the output terminal Vout2 of the second gate drive module 220. The control terminal of the second switch M2 is connected to a second control signal ENB, its first path terminal is connected to the second path terminal of the first switch M1, and its second path terminal is connected to the first power supply terminal VGH.

[0085] In this embodiment, the second switch M2 is, for example, an N-type switch, including IGZO (indium gallium zinc oxide), LTPS (Low Temperature Polysilicon), etc.; the first switch M1 is, for example, a P-type switch, including LTPS (Low Temperature Polysilicon).

[0086] Specifically, the waveform diagram of the gate drive circuit in the fourth embodiment can be referred to Figure 7a and Figure 7b When both the first control signal EN and the second control signal ENB are low, the first switch M1 is turned on and the second switch M2 is turned off; the current row scan signal Vout2 output by the second gate drive module 220 is the same as the next row scan signal Vout1 output by the drive module 113. When both the first control signal EN and the second control signal ENB are high, the first switch M1 is turned off and the second switch M2 is turned on; the current row scan signal Vout2 output by the second gate drive module 220 is a DC voltage VGH.

[0087] Figure 8 and Figure 9 A schematic diagram of the gate drive circuit according to the fifth and sixth embodiments of the present invention is shown; Figure 10a and Figure 10b A waveform diagram corresponding to the gate drive circuit according to the fifth embodiment of the present invention is shown.

[0088] In the fifth embodiment, the gate drive circuit is, for example, P-type. The second gate drive module 220 of the gate drive circuit 210 in the fifth embodiment differs from that in the third embodiment.

[0089] refer to Figure 8The second gate drive module 220 includes a third switch M3 to a sixth switch M6, a sixth capacitor C6, and a seventh capacitor C7. The control terminal of the third switch M3 is connected to the first output terminal of the latch module 112, and its first path terminal is connected to the first power supply terminal VGH. The control terminal of the fourth switch M4 is connected to the second output terminal of the latch module 112, and its first path terminal is connected to the second path terminal of the third switch M3. The control terminal of the fifth switch M5 is connected to the second control signal ENB, its first path terminal is connected to the second path terminal of the fourth switch M4, and its second path terminal is connected to the first power supply terminal VGH. The control terminal of the sixth switch M6 is connected to the first control signal EN, its first path terminal is connected to the second path terminal of the fourth switch M4, and its second path terminal is connected to the second clock signal CLK2. One end of the sixth capacitor C6 is connected to the first output terminal of the latch module 112, and its second end is connected to the first path terminal of the third switch M3. One end of the seventh capacitor C7 is connected to the second output terminal of the latch module 112, and its other end is connected to the first path terminal of the fourth switch M4. In this embodiment, the connection point between the third switch M3 and the fourth switch M4 is the output terminal of the second gate drive module 220, which is used to output the gate drive signal Vout2 of this stage.

[0090] In this embodiment, the fifth switch M5 and the sixth switch M6 are, for example, P-type switches, including LTPS (Low Temperature Polysilicon).

[0091] Further, refer to Figure 10a At time t1, the first control signal EN is low, and the sixth switch M6 is turned on; the second control signal ENB is high, and the fifth switch M5 is turned off. The second path terminal of the fourth switch M4 is connected to the second clock signal CLK2 via the sixth switch M6. Thus, the equivalent circuit structure of the second gate drive module 220 is the same as the equivalent circuit structure of the drive module 113. The row scan signal Vout2 of the current row output by the second gate drive module 220 is the same as the row scan signal Vout1 of the next row output by the drive module 113.

[0092] refer to Figure 10b At time t1, the first control signal EN is high and the second control signal ENB is low. Therefore, the fifth switch M5 is turned on, and the sixth switch M6 is turned off. The second path terminal of the fourth switch M4 is then connected to the first power supply terminal VGH via the fifth switch M5. Consequently, the row scan signal Vout2 output by the second gate drive module 220 is a DC voltage VGH. In this embodiment, in order for the fifth switch M5 to electrically connect the first power supply terminal VGH to the second path terminal of the fourth switch M4, the high level VGH1 of the second control signal ENB should be greater than the first power supply terminal VGH.

[0093] In the sixth embodiment, the gate drive circuit is, for example, P-type. The second gate drive module 220 of the gate drive circuit 210-P4 in the sixth embodiment differs from that in the fourth embodiment.

[0094] refer to Figure 9 The second gate drive module 220 includes a first switch M1 and a second switch M2. The control terminal of the first switch M1 is connected to the second control signal ENB, the first path terminal is connected to the output terminal Vout1 of the drive module 113, and the second path terminal is connected to the output terminal Vout2 of the second gate drive module 220. The control terminal of the second switch M2 is connected to the first control signal EN, the first path terminal is connected to the second path terminal of the first switch M1, and the second path terminal is connected to the first power supply terminal VGH.

[0095] In this embodiment, the first switch M1 and the second switch M2 are, for example, P-type switches, including LTPS (Low Temperature Polysilicon).

[0096] Further, refer to Figure 10a At time t1, the first control signal EN is low and the first switch M1 is turned on. The second control signal ENB is high at time t1 and the second switch M2 is turned off. Therefore, the current row scan signal Vout2 output by the gate drive circuit 210 has the same waveform as the next row scan signal Vout1.

[0097] refer to Figure 10b ,refer to Figure 10b At time t1, the first control signal EN is high, the first switch M1 is off, the second control signal ENB is low, the second switch M2 is on, and thus the row scan signal Vout2 of the current row output by the second gate drive module 220 is a DC voltage VGH.

[0098] The above embodiments are only some embodiments of this application. Those skilled in the art can make other variations of the embodiments based on the technical solutions of this application.

[0099] Furthermore, this application also provides a gate driving method, wherein the gate driving method is used in the gate driving circuit as described above.

[0100] Furthermore, this application also provides a display panel in which the pixel rows of the display panel receive the row scan signal of the current row of the aforementioned gate driving circuit.

[0101] Furthermore, this application also provides a gate driver including a plurality of cascaded gate driving circuits as described above, wherein the row scan signal of the previous row of the gate driving circuit of the current stage is the row scan signal of the next row of the gate driving circuit of the previous stage.

[0102] This invention modifies the existing gate drive circuit (Pscan / Nscan) to achieve the goal of display panels having different refresh rates between different rows.

[0103] The gate drive circuit of this application can optimize the power consumption of the display panel. As the display panel size increases, there is a phenomenon of coexistence of application scenarios. For scenarios such as video games, a high refresh rate can be provided, while for apps such as reading / social networking, a low refresh rate can be provided. In the past, the display panel could only use one refresh rate for all lines in the same frame, thus failing to optimize the power consumption of the display panel to the greatest extent.

[0104] Furthermore, the structure of a display device employing the gate driving circuit of this application is, for example, as shown below. Figure 11 As shown, it includes the processor AP, the driver DDIC, and the display panel.

[0105] The processor AP provides simple and efficient control over the display panel. The display panel only requires two additional control lines, ENB / EN. The processor AP writes the refresh rate information of each line into the driver DDIC using a micro-packet format. After the driver DDIC decodes the refresh rate information, it only needs to pull the corresponding row's synchronized EN / ENB high or low to control the refresh rate of each line.

[0106] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A gate driving circuit for a display panel, wherein, include: The first gate driving module generates the next row scanning signal based on the row scanning signal of the previous row. The first gate driving module includes N-type and P-type. The second gate driving module, connected to the first gate driving module, is used to generate the current row scanning signal based on the row scanning signal of the next row. The second gate driving module enables or disables the row scan signal of the current row according to a control signal, thereby controlling the refresh rate of the display panel. The disabling includes clamping the output of the second gate driving module to a fixed low or high level. The control signal includes a first control signal and a second control signal. The first gate driving module includes: an input module for receiving the row scan signal of the previous row according to a first clock signal; a latch module for latching the row scan signal of the previous row according to a first clock signal and a second clock signal; and a driving module for outputting the row scan signal of the next row according to the row scan signal of the previous row. The second gate driving module includes: a third switch transistor, the control terminal of which is connected to the first output terminal of the latch module, and the first path terminal of which is connected to the first power supply terminal; a fourth switch transistor, the control terminal of which is connected to the second output terminal of the latch module, and the first path terminal of which is connected to the second path terminal of the third switch transistor; a fifth switch transistor, the control terminal of which is connected to a second control signal, the first path terminal of which is connected to the second path terminal of the fourth switch transistor, and the second path terminal of which is connected to the first power supply terminal; a sixth switch transistor, the control terminal of which is connected to the first control signal, the first path terminal of which is connected to the second path terminal of the fourth switch transistor, and the second path terminal of which is connected to a second clock signal; a sixth capacitor, one end of which is connected to the control terminal of the third switch transistor, and the other end of which is connected to the first path terminal of the third switch transistor; and a seventh capacitor, one end of which is connected to the control terminal of the fourth switch transistor, and the other end of which is connected to the first path terminal of the fourth switch transistor. The connection point between the third switch transistor and the fourth switch transistor outputs the row scan signal of the current row.

2. The gate driving circuit according to claim 1, wherein, The control terminal of the fifth switch is connected to one of the first control signal and the second control signal, and the control terminal of the sixth switch is connected to the other of the second control signal and the first control signal.

3. The gate driving circuit according to claim 2, wherein, The fifth switch and the sixth switch are not turned on at the same time; When the sixth switch is turned on, the row scan signal of the current row controls the corresponding pixel row to enter the refresh frame; When the fifth switch is turned on, the row scan signal of the current row controls the corresponding pixel row to enter the holding frame.

4. The gate driving circuit according to claim 2, wherein, The fifth switch is an N-type transistor, and the sixth switch is a P-type switch; or both the fifth and sixth switches are P-type switches.

5. The gate driving circuit according to claim 1, wherein, When the gate driving circuit is in the first stage, the first gate driving module generates the row scanning signal for the next row based on the input signal NSVT or GSVT.

6. A gate driving method, wherein, The gate driving method is used in the gate driving circuit as described in any one of claims 1-5.

7. A display panel, wherein, The current pixel row of the display panel is connected to the row scan signal of the current row of the gate driving circuit according to any one of claims 1-5.

8. A gate driver, wherein, The system includes multiple cascaded gate drive circuits as described in any one of claims 1-5, wherein the row scan signal of the previous row of the gate drive circuit in this stage is the row scan signal of the next row of the gate drive circuit in the previous stage.

9. A driver chip, wherein, Includes the gate driver as described in claim 8.

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