Driving reset circuit, array substrate row driving circuit and liquid crystal display panel

Abstract

The application discloses a driving reset circuit, an array substrate row driving circuit and a liquid crystal display panel, and belongs to the technical field of display. The driving reset circuit provided by the application comprises a voltage dividing module, the voltage dividing module is connected with a gate driving voltage and connected with a low voltage end, and the voltage dividing module is used for providing a reset driving voltage under the driving of the gate driving voltage; a reset switch module is connected with the voltage dividing module, a reset signal line, an output signal line and the low voltage end, and the reset switch module is used for resetting the reset signal line and the output signal line under the driving of the reset driving voltage, thereby improving the durability of TFT tube reset noise reduction.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to drive reset circuits, array substrate row drive circuits, and liquid crystal display panels. Background Technology

[0002] With the rapid development of LCD displays, users have increasingly higher requirements for the reset of the internal drive reset circuit of LCD displays. Traditional drive reset circuits directly use two TFTs (Thin Film Transistors) to reset and reduce noise at the Q point and output of the circuit. This type of drive reset circuit has a major drawback: it requires both TFTs to be turned on almost all the time. As a result, the characteristics of the TFTs drift due to prolonged operation, making it impossible for the same voltage to drive both TFTs to work normally. In other words, this type of drive reset circuit will cause the characteristics of the TFTs to drift due to prolonged operation, resulting in low durability of TFT reset noise reduction. Summary of the Invention

[0003] The main purpose of this application is to provide a drive reset circuit, an array substrate row drive circuit, and a liquid crystal display panel, aiming to solve the technical problem of low durability of TFT tube reset noise reduction.

[0004] To achieve the above objectives, this application provides a drive reset circuit, the drive reset circuit comprising:

[0005] A voltage divider module is provided, wherein the voltage divider module is connected to the gate drive voltage and is connected to a low-level voltage terminal, and the voltage divider module is used to divide the gate drive voltage to obtain a reset drive voltage;

[0006] A reset switch module is connected to the voltage divider module, the reset signal line, the output signal line, and the low-level voltage terminal. The reset switch module is used to reset the reset signal line and the output signal line under the drive of the reset drive voltage.

[0007] Optionally, the voltage divider module includes:

[0008] A voltage divider resistor, the first end of which is connected to the gate drive voltage, and the second end of which is connected to the reset switch module.

[0009] Optionally, the voltage divider module further includes:

[0010] A first thin-film transistor, wherein the control terminal of the first thin-film transistor is connected to the gate drive voltage, the first terminal of the first thin-film transistor is connected to the second terminal of the voltage divider resistor, and the second terminal of the first thin-film transistor is connected to the low-level voltage terminal.

[0011] Optionally, the reset switch module includes:

[0012] The second thin-film transistor has its control terminal connected to the second terminal of the voltage divider resistor, its first terminal connected to the reset signal line, and its second terminal connected to the low-level voltage terminal.

[0013] Optionally, the reset switch module further includes:

[0014] The third thin-film transistor has its control terminal connected to the second terminal of the voltage divider resistor, its first terminal connected to the output signal line, and its second terminal connected to the low-level voltage terminal.

[0015] Optionally, the first thin-film transistor, the second thin-film transistor, and the third thin-film transistor are thin-film transistors with the same drift characteristics.

[0016] Optionally, when the first thin-film transistor is turned on, the second thin-film transistor and the third thin-film transistor are also turned on.

[0017] Optionally, when the first thin-film transistor is turned off, the second thin-film transistor and the third thin-film transistor are also turned off.

[0018] In addition, to achieve the above objectives, this application also provides an array substrate row driving circuit, which includes the array substrate row driving circuit described above.

[0019] In addition, to achieve the above objectives, this application also provides a liquid crystal display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the pixel structure as described above.

[0020] This application proposes a drive reset circuit, an array substrate row drive circuit, and a liquid crystal display panel. The drive reset circuit is optimized to provide a drive reset circuit comprising a voltage divider module and a reset switch module. Since the drive reset circuit in the liquid crystal display panel requires two TFT transistors to be almost always on, prolonged on-time operation causes TFT transistor characteristic drift, making it impossible for the same voltage to drive both TFT transistors to function normally. This application combines the aforementioned modules: the voltage divider module divides the gate drive voltage to obtain a reset drive voltage; then, the reset switch module, driven by the reset drive voltage, resets the reset signal line and the output signal line; and finally, the voltage divider module divides the gate drive voltage to obtain the reset drive voltage for the reset operation, improving the durability of TFT transistor reset noise reduction. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0022] Figure 1 This is a functional module diagram of an embodiment of the drive reset circuit of this application;

[0023] Figure 2 This is a circuit connection diagram of one embodiment of the drive reset circuit of this application;

[0024] Figure 3 This is a schematic diagram of the existing array substrate row drive circuit connection;

[0025] Figure 4 This is a schematic diagram of the array substrate row drive circuit connection in this application;

[0026] Figure 5 This is a schematic diagram of the structure of the liquid crystal display panel involved in the embodiments of this application.

[0027] Explanation of icon numbers:

[0028] label name label name 1001 processor 1002 Communication bus 1003 User Interface 1004 Network interface 1005 memory 10 Voltage divider module 20 Reset switch module Q Reset signal line out Output signal line Vdata Gate drive voltage R1 Voltage divider resistor T1 First thin-film transistor T2 Second thin-film transistor T3 Third thin-film transistor C1 First capacitor T4-T12 Fourth to twelfth thin-film transistors VGL low-level voltage terminal

[0029] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0030] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0031] This application provides a drive reset circuit, referring to... Figure 1 , Figure 1 This is a functional module diagram of an embodiment of a drive reset circuit according to this application.

[0032] In this embodiment, the drive reset circuit includes:

[0033] A voltage divider module 10 is connected to the gate drive voltage Vdata and a low-level voltage terminal VGL. The voltage divider module 10 is used to divide the gate drive voltage Vdata to obtain a reset drive voltage.

[0034] A reset switch module 20 is connected to the voltage divider module 10, the reset signal line Q, the output signal line out, and the low-level voltage terminal VGL. The reset switch module 20 is used to reset the reset signal line Q and the output signal line out under the drive of the reset driving voltage.

[0035] It should be noted that in a standard 11T1C (11 TFT transistors and one capacitor) GDL circuit, two TFT transistors are used to reset the Q-point (i.e., reset signal line Q) and the out (i.e., output signal line out) respectively, to prevent noise from affecting the Q-point and out waveforms. Because the charging time of the Q-point is very short, a reset is necessary, meaning the two TFT transistors are essentially on for 100% of their operating time. During prolonged operation, the TFT characteristics of the two transistors will drift, reducing their on-state capability (i.e., higher voltage is required to turn on both TFT transistors), resulting in a loss of noise reduction capability and causing display problems during the product's RA process or long-term use.

[0036] In this embodiment, the voltage divider module 10 divides the control terminal driving voltage Vdata, which originally needs to drive two TFT transistors, to obtain the reset driving voltage. Here, the gate driving voltage Vdata refers to the voltage used to drive the two TFT transistors for reset in the original circuit, and the reset driving voltage is the voltage after being divided by the voltage divider module 10. Therefore, the reset signal line Q and the output signal line out can be reset under the drive of the reset driving voltage. The core of this application is: using the divided voltage as the voltage to drive the two TFT transistors for reset, and then using different voltage controls based on the drift of the TFT characteristics to achieve reset, thereby improving the durability of TFT transistor reset noise reduction.

[0037] Furthermore, referring to Figure 2 , Figure 2 This is a circuit connection diagram of one embodiment of the drive reset circuit of this application.

[0038] like Figure 2 As shown, in some feasible embodiments, the voltage divider module 10 includes:

[0039] The voltage divider resistor R1 has its first end connected to the gate drive voltage Vdata, and its second end connected to the reset switch module 20.

[0040] Furthermore, in some feasible embodiments, the voltage divider module 10 further includes:

[0041] A first thin-film transistor T1 has its control terminal connected to the gate drive voltage Vdata. The first terminal of the first thin-film transistor T1 is connected to the second terminal of the voltage divider resistor R1, and the second terminal of the first thin-film transistor T1 is connected to the low-level voltage terminal VGL.

[0042] Furthermore, in some feasible embodiments, the reset switch module 20 includes:

[0043] The second thin-film transistor T2 has its control terminal connected to the second terminal of the voltage divider resistor R1, its first terminal connected to the reset signal line, and its second terminal connected to the low-level voltage terminal.

[0044] Furthermore, in some feasible embodiments, the reset switch module 20 further includes:

[0045] The third thin-film transistor T3 has its control terminal connected to the second terminal of the voltage divider resistor R1, its first terminal connected to the output signal line out, and its second terminal connected to the low-level voltage terminal VGL.

[0046] Furthermore, in some feasible embodiments, the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 are thin-film transistors with the same drift characteristics.

[0047] In this embodiment, the drive reset circuit can be applied to all circuits that are directly reset by the TFT transistor. This embodiment takes the GDL circuit of 11T1C as an example, which can be referred to... Figure 3 , Figure 3 The diagram shows the connection of a row drive circuit on an existing array substrate. The reset circuit in the diagram is directly composed of two TFT transistors, T2 and T3. This leads to TFT characteristic drift, causing the original turn-on voltage QB to fail to properly turn on the two TFTs. This results in low durability of the TFT reset noise reduction capability of the entire circuit, necessitating adjustments to the turn-on voltage based on usage time. This application improves the durability of the GDL circuit's noise reduction capability by adding a voltage divider resistor R1 and a first thin-film transistor T1. (Refer to...) Figure 4 , Figure 4This is a schematic diagram of the array substrate row driving circuit connection. During charging, the potential at point Q is high, turning on T10, which in turn lowers the potential at point A, causing the gate voltage of the drive reset circuit to be low and inactive. When not charging, the potential at point Q is low, T10 is not turned on, and the voltage at point A is high. At this time, the voltage at point QB is also high, turning on the second thin-film transistor T2 and the third thin-film transistor T3 to reduce noise for the reset signal line Q and the output signal line out. At this time, the first thin-film transistor T1 is also turned on due to the voltage at point A. Since the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 have the same turn-on time, their TFT characteristic drift levels are similar. When the TFT characteristics of the second thin-film transistor T2 and the third thin-film transistor T3 drift, the characteristics of the first thin-film transistor T1 also drift. Since the voltage at point QB is the result of the voltage divider resistor R0 and the voltage divider of the first thin-film transistor T1, when the characteristics of the first thin-film transistor T1 drift, the equivalent resistance of the first thin-film transistor T1 increases, the voltage at point QB rises, and thus increases the turn-on voltage of the two TFT transistors to improve the turn-on capability of the second thin-film transistor T2 and the third thin-film transistor T3. This further improves the noise reduction capability of the entire GDL circuit and extends the durability of the noise reduction capability of the TFT transistors in the drive reset circuit within the GDL circuit.

[0048] It should be noted that the transistors used in all embodiments of this application can be TFTs (Thin Film Transistors), field-effect transistors, or other devices with similar characteristics. Since the second terminal and drain of the transistors used here are symmetrical, their source and drain terminals are interchangeable. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source, and the other is called the drain. Figure 2 In the diagram, the characteristics of each port of the first thin-film transistor T1 can be determined according to the G, D, and S markings. G is the control terminal of T1, S is the second terminal of T1, and D is the first terminal of T1. Alternatively, G can be the control terminal of T1, S the first terminal of T1, and D the second terminal of T1. The characteristics of the remaining transistors can be determined according to... Figure 2 The configuration of the transistors is defined as follows: the middle terminal of each transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the transistors used in this application embodiment may include both P-type and N-type transistors. P-type transistors conduct when the gate is low and are cut off when the gate is high, while N-type transistors conduct when the gate is high and are cut off when the gate is low. The conduction modes of the first gate drive voltage Vgate and the second gate drive voltage Share_Vgate differ for N-type and P-type transistors, and the corresponding control methods also differ. The specific control depends on the actual transistor and is not limited here.

[0049] Furthermore, in some feasible embodiments, the first thin-film transistor T1 to the third thin-film transistor T3 can be low-temperature polycrystalline silicon thin-film transistors, oxide semiconductor thin-film transistors, or amorphous silicon thin-film transistors. The transistors in the driving circuit provided in this application are all made of the same material, thereby avoiding the impact of differences between transistors of different materials on the driving circuit.

[0050] Furthermore, in some feasible embodiments, when the first thin-film transistor T1 is turned on, the second thin-film transistor T2 and the third thin-film transistor T3 are also turned on.

[0051] Furthermore, in some feasible embodiments, when the first thin-film transistor T1 is turned off, the second thin-film transistor T2 and the third thin-film transistor T3 are also turned off.

[0052] In this embodiment, since the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 are thin-film transistors with the same drift characteristics, based on the connection relationship of the three TFT transistors, it is known that when the first thin-film transistor T1 is turned on, the second thin-film transistor T2 and the third thin-film transistor T3 are also turned on, and their on-time is the same as that of the first thin-film transistor T1. Because the three have the same drift characteristics, the turn-on voltage of the second thin-film transistor T2 and the third thin-film transistor T3 is linked to the voltage divider of the first thin-film transistor T1. Therefore, the voltage divider of the first thin-film transistor T1 can be used to turn on the two TFT transistors according to the drift characteristics of the second thin-film transistor T2 and the third thin-film transistor T3, thereby performing a reset. Ensuring that the turn-on voltage changes with the drift characteristics can extend the durability of the noise reduction capability of the TFT transistors in the drive reset circuit.

[0053] This embodiment proposes a drive reset circuit, an array substrate row drive circuit, and a liquid crystal display panel. This application optimizes the drive reset circuit, resulting in a drive reset circuit comprising a voltage divider module and a reset switch module. Since the drive reset circuit in the liquid crystal display panel requires two TFT transistors to be almost always on, prolonged on-time operation causes TFT transistor characteristic drift, making it impossible for the same voltage to drive both TFT transistors to function normally. This application combines the aforementioned modules: the voltage divider module divides the gate drive voltage to obtain a reset drive voltage; then, the reset switch module, driven by the reset drive voltage, resets the reset signal line and the output signal line; and finally, the voltage divider module divides the gate drive voltage to obtain the reset drive voltage for the reset operation, improving the durability of TFT transistor reset noise reduction.

[0054] Furthermore, this application also proposes an array substrate row driving circuit, which includes the aforementioned driving reset circuit.

[0055] Furthermore, this application also proposes a liquid crystal display panel, which includes at least a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the pixel structure described above. The liquid crystal display panel may also include the pixel structure described above, see reference... Figure 5 , Figure 5 This is a schematic diagram of the structure of the liquid crystal display panel involved in the embodiments of this application.

[0056] like Figure 5 As shown, the liquid crystal display panel may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0057] Those skilled in the art will understand that Figure 5 The structure shown does not constitute a limitation on the liquid crystal display panel and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0058] like Figure 5 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a data storage module, a network communication module, a user interface module, and computer programs.

[0059] exist Figure 5 In the liquid crystal display panel shown, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in this embodiment can be set in the liquid crystal display panel. The liquid crystal display panel calls the computer program stored in the memory 1005 through the processor 1001 and controls the above-mentioned drive reset circuit.

[0060] The various embodiments of the liquid crystal display panel of this application can be referred to the various embodiments of the drive reset circuit of this application, and will not be repeated here.

[0061] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0062] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0063] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0064] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A drive reset circuit, characterized in that, The drive reset circuit includes: A voltage divider module is provided, wherein the voltage divider module is connected to the gate drive voltage and a low-level voltage terminal, and the voltage divider module is used to divide the gate drive voltage to obtain a reset drive voltage. The voltage divider module includes: A voltage divider resistor, wherein the first end of the voltage divider resistor is connected to the gate drive voltage, and the second end of the voltage divider resistor is connected to the reset switch module; A first thin-film transistor, wherein the control terminal of the first thin-film transistor is connected to the gate drive voltage, the first terminal of the first thin-film transistor is connected to the second terminal of the voltage divider resistor, and the second terminal of the first thin-film transistor is connected to the low-level voltage terminal; A reset switch module is connected to the voltage divider module, the reset signal line, the output signal line, and the low-level voltage terminal. The reset switch module is used to reset the reset signal line and the output signal line under the drive of the reset drive voltage.

2. The drive reset circuit as described in claim 1, characterized in that, The reset switch module includes: The second thin-film transistor has its control terminal connected to the second terminal of the voltage divider resistor, its first terminal connected to the reset signal line, and its second terminal connected to the low-level voltage terminal.

3. The drive reset circuit as described in claim 2, characterized in that, The reset switch module also includes: The third thin-film transistor has its control terminal connected to the second terminal of the voltage divider resistor, its first terminal connected to the output signal line, and its second terminal connected to the low-level voltage terminal.

4. The drive reset circuit as described in claim 3, characterized in that, The first thin-film transistor, the second thin-film transistor, and the third thin-film transistor are thin-film transistors with the same drift characteristics.

5. The drive reset circuit as described in claim 4, characterized in that, When the first thin-film transistor is turned on, the second thin-film transistor and the third thin-film transistor are also turned on.

6. The drive reset circuit as described in claim 5, characterized in that, When the first thin-film transistor is turned off, the second thin-film transistor and the third thin-film transistor are also turned off.

7. A row driving circuit for an array substrate, characterized in that, The array substrate row driving circuit includes the driving reset circuit as described in any one of claims 1-6.

8. A liquid crystal display panel, characterized in that, The liquid crystal display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes the array substrate row driving circuit as described in claim 7.

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