An adaptive biasing circuit and fast transient response fully integrated LDO circuit

Abstract

The application provides a self-adaptive bias circuit and a fast transient response fully integrated LDO circuit. The self-adaptive bias circuit is applied to the fast transient response fully integrated LDO circuit and comprises a self-adaptive bias module, a first port, a second port and an output port. The first port is used for receiving an external reference voltage VREF. The second port is used for receiving a feedback voltage VFB of the LDO circuit. The self-adaptive bias module is used for generating a bias current according to the relationship between the external reference voltage VREF and the feedback voltage VFB and transmitting the bias current to an error amplifier in the LDO circuit through the output port. When the load of the LDO circuit changes and causes the feedback voltage VFB to change, the self-adaptive bias module can adaptively adjust the generated bias current according to the changed feedback voltage VFB, so that the LDO circuit can quickly respond. When applied to the fast transient response fully integrated LDO circuit, the response speed of the LDO is improved under overcharge or undercharge, and the low power consumption of the LDO circuit is ensured.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, specifically to an adaptive bias circuit and a fast transient response fully integrated LDO circuit. Background Technology

[0002] With the rapid development of integrated circuit technology, the requirements for the integration of electronic circuits are becoming increasingly stringent, making power management increasingly important. Low dropout regulators (LDOs), as a crucial component of power management systems, offer advantages such as fewer external components, smaller chip footprint, low output noise, good transient performance, and low quiescent power consumption, playing a vital role in various medical electronic devices. In practical applications, especially in mixed-signal circuits, the quiescent current in the LDO circuit affects other performance parameters, such as the transient response of the load. When high-frequency load changes occur in the circuit, the fast transient performance of the LDO as a power supply becomes particularly critical.

[0003] Compared to traditional LDOs, capacitor-less LDOs do not require large external capacitors, making them easier to integrate into systems. However, due to the lack of external capacitors for stabilization, fully integrated LDOs can experience large overshoot and undershoot voltages during rapid load changes, resulting in a slower transient response. To improve the transient response of an LDO circuit, additional auxiliary detection circuits, suppression circuits, and / or adaptive bias circuits are needed, which undoubtedly increases the chip area and power consumption. Summary of the Invention

[0004] This application proposes an adaptive bias circuit and a fast transient response fully integrated LDO circuit to solve the technical problem that existing LDO circuits without external capacitors require additional auxiliary circuits to improve their transient response capability.

[0005] In one aspect, an adaptive bias circuit is provided in one embodiment, applied to a fast transient response fully integrated LDO circuit; the adaptive bias circuit includes an adaptive bias module, a first port, a second port, and an output port;

[0006] The first port is used to receive an external reference voltage VREF and transmit it to the adaptive bias module;

[0007] The second port is used to receive the feedback voltage VFB of the LDO circuit and transmit it to the adaptive bias module;

[0008] The adaptive bias module generates a bias current based on the relationship between the external reference voltage VREF and the feedback voltage VFB of the LDO circuit, and transmits the bias current to the error amplifier in the LDO circuit through the output port. When the load of the LDO circuit changes, causing the feedback voltage VFB to change, the adaptive bias module can adaptively adjust the bias current it generates according to the changed feedback voltage VFB, so that the error amplifier in the LDO circuit can respond quickly.

[0009] Secondly, one embodiment provides a fast transient response fully integrated LDO circuit, including an error amplifier, a buffer, a power transistor circuit, a feedback circuit, and an adaptive bias circuit as described in the various embodiments herein;

[0010] The feedback circuit is used to acquire the feedback voltage VFB at the output of the LDO circuit;

[0011] The error amplifier is used to receive the external reference voltage VREF, the feedback voltage VFB, and the bias current provided by the adaptive bias circuit. After comparing the external reference voltage VREF and the feedback voltage VFB, it amplifies the error and outputs the first voltage signal.

[0012] The buffer is used to receive the first voltage signal and output a drive signal after buffering.

[0013] The power transistor circuit responds to the drive signal to achieve a fast transient response at the LDO output when the load changes.

[0014] This application provides an adaptive bias circuit and a fast transient response fully integrated LDO circuit. The adaptive bias circuit, applied to the LDO circuit, includes an adaptive bias module, a first port, a second port, and an output port. The adaptive bias module generates a bias current based on the relationship between the external reference voltage VREF received at the first port and the feedback voltage VFB of the LDO circuit received at the second port. This bias current is then transmitted to the error amplifier in the LDO circuit through the output port, providing an adaptive bias current to the error amplifier. This allows the adaptive bias module to adaptively adjust its generated bias current according to the changed feedback voltage VFB when the load of the LDO circuit changes. The adaptive bias circuit proposed in this application can provide the error amplifier with an adaptive large current proportional to the overcharge or undercharge voltage, improving the charging and discharging response speed of the error amplifier to the gate of the power transistor in the LDO circuit. It suppresses overcharge and undercharge states without the need for additional detection and / or suppression circuits, and the adaptive bias current is very small in the static state, ensuring low power consumption and fast transient response of the LDO circuit. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0016] Figure 1 This is a schematic diagram of the structure of an adaptive bias circuit provided in one embodiment of this application;

[0017] Figure 2 This is a schematic diagram of the structure of an adaptive bias module provided in one embodiment of this application;

[0018] Figure 3 A circuit diagram of an adaptive bias module provided in one embodiment of this application;

[0019] Figure 4 A simulation diagram of the adaptive bias circuit current provided in one embodiment of this application;

[0020] Figure 5 This is a schematic diagram of the structure of a fast transient response fully integrated LDO circuit provided in one embodiment of this application;

[0021] Figure 6 A circuit diagram of an error amplifier provided in one embodiment of this application;

[0022] Figure 7 A circuit diagram of a buffer provided in one embodiment of this application.

[0023] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0025] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0026] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages).

[0027] Low dropout regulators (LDOs), as an important component of power management systems, offer advantages such as fewer external components, smaller chip area, low output noise, good transient performance, and low quiescent power consumption, playing a crucial role in various medical electronic devices. In practical applications, especially in mixed-signal circuits, the quiescent current in the LDO circuit affects other performance parameters, such as the transient response of the load. When high-frequency load changes occur in the circuit, the fast transient performance of the LDO as a power supply becomes particularly important.

[0028] Compared to traditional LDOs, capacitorless LDOs do not require large external capacitors, making them easier to integrate into systems. However, due to the lack of external capacitors for stabilization, fully integrated LDOs can generate large overshoot and undershoot voltages during transients with rapidly changing loads, resulting in a slower transient response.

[0029] Therefore, H. Qiao et al. (H. Qiao, C. Zhan, Q. Pan, Y. Chen and N. Zhang, "AnArea-Efficient Low Quiescent Current Output Capacitor-Less LDO with FastTransient Response," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-4, doi: 10.1109 / ISCAS51556.2021.9401095.) proposed a method based on auxiliary detection circuits and adaptive bias circuits to simultaneously reduce voltage under overshoot and undershoot conditions, thereby improving the transient response of LDO circuits.

[0030] However, a new problem has emerged. Due to its adaptive bias structure, the bias current is small under light load conditions, which cannot extend the bandwidth of the error amplifier. It is also necessary to add overshoot or undershoot detection circuits to improve the transient response of the LDO, which undoubtedly increases the chip area and power consumption.

[0031] Therefore, after multiple theoretical studies and experimental verifications, the applicant has addressed the issue that the adaptive bias structure in the aforementioned circuit structure cannot provide sufficient bias current to improve transient response under light load, and requires additional overcharge detection and suppression circuitry. This application proposes an adaptive bias module based on a differential flip-flop voltage follower to provide adaptive bias current to the error amplifier under both heavy load and light load conditions. This expands the bandwidth of the error amplifier under transient response, improves the transient response speed of the LDO circuit, reduces output overshoot and undershoot voltage, and lowers power consumption.

[0032] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0033] Figure 1 This is a schematic diagram of the adaptive bias circuit provided in one embodiment of this application. Please refer to [link / reference]. Figure 1 The adaptive bias circuit provided in this embodiment is applied to a fast transient response fully integrated LDO circuit. The adaptive bias circuit 100 includes: an adaptive bias module 101, a first port 102, a second port 103, and an output port 104.

[0034] The first port 102 is used to receive the external reference voltage VREF and transmit it to the adaptive bias module 101, and the second port 103 is used to receive the feedback voltage VFB of the LDO circuit and transmit it to the adaptive bias module 101.

[0035] The adaptive bias module 101 generates a bias current IBIAS based on the relationship between the received external reference voltage VREF and the feedback voltage VFB of the LDO circuit, and transmits it to the error amplifier in the LDO circuit through the output port 104. When the load of the LDO circuit changes, causing the feedback voltage VFB to change, the adaptive bias module 101 can adaptively adjust the bias current IBIAS it generates according to the changed feedback voltage VFB, so that the error amplifier in the LDO circuit can respond quickly.

[0036] The aforementioned adaptive bias circuit is applied to a fast transient response fully integrated LDO circuit. It directly receives the external reference voltage VREF and the feedback voltage VFB of the LDO circuit, and generates a bias current IBIAS based on their relationship, outputting it to the error amplifier in the LDO circuit. When the load of the LDO circuit changes, causing a change in the feedback voltage VFB, the adaptive bias module can adaptively adjust its generated bias current IBIAS according to the changed feedback voltage VFB. Unlike existing adaptive bias structures, it does not output bias current to the power transistor circuit. The adaptive bias circuit proposed in this application can provide the error amplifier with an adaptive large current IBIAS proportional to the overcharge or undercharge voltage, improving the charging and discharging response speed of the error amplifier to the gate of the power transistor in the LDO circuit. It can suppress overcharge and undercharge states without the need for additional detection and / or suppression circuits, and the adaptive bias current is very small in the static state, ensuring low power consumption and fast transient response of the LDO circuit.

[0037] When the load of the LDO circuit changes from heavy load to light load, that is, when the feedback voltage VFB is greater than the external reference voltage VREF, the bias current IBIAS is proportional to the square of the difference between the feedback voltage VFB and the external reference voltage VREF.

[0038] When the load on the LDO circuit changes from light load to heavy load, i.e., the feedback voltage VFB is less than the external reference voltage VREF, the bias current IBIAS is proportional to the square of the difference between the external reference voltage VREF and the feedback voltage VFB.

[0039] Figure 2 This is a schematic diagram of the adaptive bias module provided in one embodiment of this application. Please refer to [link / reference]. Figure 2In this embodiment, the adaptive bias electrical module 101 includes at least two differential flip voltage follower circuits 201, current sources 202 that are the same number as and correspond one-to-one with the differential flip voltage follower circuits 201, and a current mirror 203.

[0040] Each differential flip voltage follower circuit 201 receives an external reference voltage VREF and a feedback voltage VFB. Based on the relationship between the external reference voltage VREF and the feedback voltage VFB, it outputs a follower current signal to the current mirror 203.

[0041] The current source 202, which corresponds one-to-one with the differential flip voltage follower circuit 201, is used to provide quiescent current to its corresponding differential flip voltage follower circuit 201, and the current value of each current source 202 is equal.

[0042] The current mirror 203 is used to receive the follower current signals output by all differential flip voltage follower circuits 202. By mirroring all the follower current signals, it outputs an adaptive bias current IBIAS to the error amplifier.

[0043] Figure 3 This is a circuit diagram of an adaptive bias module provided in one embodiment of this application. Please refer to [link / reference]. Figure 3 In this embodiment, the adaptive bias module 101 includes a first differential flip voltage follower circuit 301, a second differential flip voltage follower circuit 302, a first current source 303, a second current source 304, and a current mirror 305. The first current source 303 provides bias current to the first differential flip voltage follower circuit 301, and the second current source 304 provides bias current to the second differential flip voltage follower circuit 302. The current values ​​of the first current source 303 and the second current source 304 are equal.

[0044] In some embodiments, the first differential flip voltage follower circuit 301 includes a first terminal, a second terminal, a third terminal, and an output terminal. The first terminal is used to receive an external reference voltage VREF, the second terminal is used to receive a feedback voltage VFB from the LDO circuit, the third terminal is used to receive a quiescent current provided by the first current source 303, and the output terminal is used to output a first follower current signal according to the relationship between the external reference voltage VREF and the feedback voltage VFB.

[0045] In some embodiments, the first differential flip voltage follower circuit 301 includes transistors M2a, M1a, and M3a.

[0046] Transistor M2a includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor M2a is connected to the first input power supply, and the control terminal of transistor M2a is connected to the third terminal of the first differential flip voltage follower circuit 301, that is, it receives the static current provided by the first current source 303.

[0047] Transistor M1a includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor M1a is connected to the second terminal of transistor M2a. The second terminal of transistor M1a is connected to the third terminal of the first differential flip voltage follower circuit 301, that is, it receives the quiescent current provided by the first current source 303. The control terminal of transistor M1a is connected to the first terminal of the first differential flip voltage follower circuit 301, that is, it receives the external reference voltage VREF.

[0048] Transistor M3a includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor M3a is connected to the second terminal of transistor M2a. The control terminal of transistor M3a is connected to the second terminal of the first differential flip voltage follower circuit 301, that is, it receives the feedback voltage VFB of the LDO circuit. The second terminal of transistor M3a is connected to the output terminal of the first differential flip voltage follower circuit 301, and outputs the first follower current signal.

[0049] In some embodiments, the second differential flip voltage follower circuit 302 includes a first terminal, a second terminal, and a third terminal. The first terminal is used to receive the feedback voltage VFB from the LDO circuit, the second terminal is used to receive the external reference voltage VREF, the third terminal is used to receive the quiescent current provided by the second current source 304, and the output terminal is used to output a second follower current signal according to the relationship between the external reference voltage VREF and the feedback voltage VFB.

[0050] In some embodiments, the second differential flip voltage follower circuit 302 includes transistors M2b, M1b, and M3b.

[0051] Transistor M2b includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor M2b is connected to the second input power supply, and the control terminal of transistor M2b is connected to the third terminal of the second differential flip voltage follower circuit 302, that is, it receives the static current provided by the second current source 304.

[0052] Transistor M1b includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor M1b is connected to the second terminal of transistor M2b. The second terminal of transistor M1b is connected to the third terminal of the second differential voltage follower circuit 302, that is, it receives the quiescent current provided by the second current source 304. The control terminal of transistor M1b is connected to the first terminal of the second differential voltage follower circuit 302, that is, it receives the feedback voltage VFB of the LDO circuit.

[0053] Transistor M3b includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor M3b is connected to the second terminal of transistor M2b. The control terminal of transistor M3b is connected to the second terminal of the second differential flip voltage follower 302 circuit, i.e., it receives the external reference voltage VREF. The second terminal of transistor M3b is connected to the output terminal of the second differential flip voltage follower circuit 302, and outputs the second follower current signal.

[0054] In some embodiments, the current mirror 305 includes a first terminal and a second terminal. The first terminal is used to receive a first follower current signal and a second follower current signal, and to sum and mirror the first follower current signal and the second follower current signal. The generated bias current IBIAS is output through the second terminal of the current mirror 305 to the error amplifier.

[0055] In some embodiments, the current mirror 305 includes transistors M4a and M4b.

[0056] Transistor M4a includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor M4a is grounded, the second terminal of transistor M4a is connected to the first terminal of current mirror 305, and the control terminal of transistor M4a is shorted to the second terminal of transistor M4a.

[0057] Transistor M4b includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor M4b is grounded. The control terminal of transistor M4b is connected to the control terminal of transistor M4a. The second terminal of transistor M4b is connected to the second terminal of the current mirror and is used to output bias current IBIAS.

[0058] In some embodiments, transistors M1a, M3a, M1b, and M3b are PMOS transistors and have the same size.

[0059] Please refer to Figure 3 The adaptive bias circuit shown works on the following principle:

[0060] Because the source impedances of transistors M1a and M1b are very small, the source voltages of transistors M1a and M1b can remain constant even when a large current flows through them.

[0061] Under static conditions, when the feedback voltage VFB is equal to the external reference voltage VREF, the drain currents of transistors M3a and M3b are equal because the current values ​​of the current sources are equal, i.e., Ioa = Iob. Therefore, under static conditions, the output current is very small, resulting in a low-power, fast transient response.

[0062] When the feedback voltage VFB is not equal to the external reference voltage VREF, the follower currents Ioa and Iob output by the transistors M3a and M3b are respectively related to (VREF - VFB) and (VFB - VREF). Through further experimental simulation, their relationship is obtained, that is, the follower currents Ioa and Iob are respectively proportional to the square of (VREF - VFB) and (VFB - VREF).

[0063] Before the current enters the drain of the current mirror transistor M4a, the follower currents Ioa and Iob are summed, and after mirroring, the adaptive bias current IBIAS is output. Therefore, whether in the overcharge case (VREF < VFB) or the undercharge case (VREF > VFB), the bias current IBIAS is proportional to the square of the difference between VREF and VFB, and can provide an adaptive large current proportional to the overcharge or undercharge voltage to the error amplifier, improving the charging and discharging response speed of the error amplifier to the gate terminal of the power transistor, and effectively suppressing the overcharge and undercharge situations.

[0064] Figure 4 This is the current simulation diagram of the adaptive bias circuit provided by an embodiment of the present application. From Figure 4 it can be more intuitively seen that when the feedback voltage VFB is equal to the external reference voltage VREF, the follower currents output by the drains of the transistors M3a and M3b are equal, that is, Ioa = Iob. Under static conditions, the output current is very small, forming a low-power fast transient response; when the feedback voltage VFB is not equal to the external reference voltage VREF, the follower currents Ioa and Iob output by the transistors M3a and M3b are respectively proportional to the square of (VREF - VFB) and (VFB - VREF). Whether in the overcharge case (VREF < VFB) or the undercharge case (VREF > VFB), the bias current IBIAS can provide an adaptive large current proportional to the overcharge or undercharge voltage to the error amplifier, improving the charging and discharging response speed of the error amplifier to the gate terminal of the power transistor.

[0065] Figure 5 This is the structural schematic diagram of the fast transient response fully integrated LDO circuit provided by an embodiment of the present application. Please refer to Figure 5 . The fast transient response fully integrated LDO circuit of this embodiment includes an adaptive bias circuit 100, an error amplifier 200, a buffer 300, a power transistor circuit 400, and a feedback circuit 500.

[0066] Among them, for the structure and function of the adaptive bias circuit 100, there may be the same or similar concepts or processes in some embodiments, which will not be elaborated here.

[0067] Error amplifier 200 is used to receive external reference voltage VREF, feedback voltage VFB and bias circuit IBIAS provided by adaptive bias circuit 100, and after comparing external reference voltage VREF and feedback voltage VFB, it amplifies the error and outputs a first voltage signal.

[0068] Buffer 300 is used to receive the first voltage signal output by error amplifier 200, and output the drive signal after buffering.

[0069] The power transistor circuit 400 responds to the drive signal output by the buffer 300 to achieve a fast transient response of the LDO output when the load changes.

[0070] Feedback circuit 500 is used to acquire the feedback voltage VFB at the output of the LDO circuit and transmit it to adaptive bias circuit 100 and error amplifier 200.

[0071] Figure 6 This is a circuit diagram of an error amplifier provided in one embodiment of this application. Please refer to... Figure 6 In this embodiment, the error amplifier 200 includes transistors MP0, MP1, MP2, MP3, MP4, MN0, MN1, MN2, MP5, MP6, MP7, MP8, MN3, MN4, MN5, and MN6.

[0072] The transistor MP0 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP0 is connected to the first input power supply. The second terminal of the transistor MP0 is shorted to its control terminal. The second terminal of the transistor MP0 is connected to the bias current input terminal of the error amplifier 200. That is, the second terminal of the transistor MP0 is used to receive the bias current output by the adaptive bias circuit 100.

[0073] Transistor MP1 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP1 is connected to a first input power supply, and the control terminal of transistor MP1 is connected to the second terminal of transistor MP0.

[0074] Transistor MP2 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP2 is connected to the first input power supply, and the control terminal of transistor MP2 is connected to the control terminal of transistor MP1.

[0075] Transistor MP3 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP3 is connected to the second terminal of transistor MP2. The control terminal of transistor MP3 is connected to the non-inverting input terminal of error amplifier 200, which is used to receive external reference voltage VREF.

[0076] Transistor MP4 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP4 is connected to the second terminal of transistor MP2. The control terminal of transistor MP3 is connected to the inverting input terminal of error amplifier 200, i.e., it is used to receive feedback voltage VFB.

[0077] Transistor MN0 includes a first terminal, a second terminal, and a control terminal. The second terminal of transistor MN0 is connected to the second terminal of transistor MP1 and short-circuited with its control terminal.

[0078] Transistor MN1 includes a first terminal, a second terminal, and a control terminal. The second terminal of transistor MN1 is connected to the first terminal of transistor MN0 and short-circuited to its control terminal.

[0079] Transistor MN2 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MN2 is grounded, and the second terminal of transistor MN2 is connected to the first terminal of transistor MN1 and short-circuited with its control terminal.

[0080] Transistor MP5 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP5 is connected to a first input power supply.

[0081] Transistor MP6 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP6 is connected to the first input power supply, and the control terminal of transistor MP6 is connected to the control terminal of transistor MP5.

[0082] Transistor MP7 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP7 is connected to the second terminal of transistor MP5, and the second terminal of transistor MP7 is connected to the control terminal of transistor MP5.

[0083] Transistor MP8 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP8 is connected to the second terminal of transistor MP6. The control terminal of transistor MP8 is connected to the control terminal of transistor MP7 and to the control terminal of transistor MN2. The second terminal of transistor MP8 is connected to the output terminal of error amplifier 200, that is, the first voltage signal is output to buffer 300 through the second terminal of transistor MP8.

[0084] Transistor MN3 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MN3 is connected to the second terminal of transistor MP4, and the second terminal of transistor MN3 is connected to the second terminal of transistor MP7.

[0085] Transistor MN4 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MN4 is connected to the second terminal of transistor MP3, the second terminal of transistor MN4 is connected to the second terminal of transistor MP8, and the control terminal of transistor MN4 is connected to the control terminal of transistor MN3 and also to the control terminal of transistor MN1.

[0086] Transistor MN5 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MN5 is grounded, and the second terminal of transistor MN5 is connected to the first terminal of transistor MN3.

[0087] Transistor MN6 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MN6 is grounded. The second terminal of transistor MN6 is connected to the first terminal of transistor MN4. The control terminal of transistor MN6 is connected to the control terminal of transistor MN5 and to the control terminal of transistor MN0.

[0088] Figure 7 This is a circuit diagram of a buffer provided in one embodiment of this application. Please refer to... Figure 7 In this embodiment, the buffer 300 includes transistors MP9, MP10, MP12, MP11, MN7, MN8, and MN9.

[0089] The transistor MP9 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP9 is connected to a first input power supply.

[0090] Transistor MP10 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP10 is connected to the first input power supply, and the control terminal of transistor MP10 is connected to the control terminal of transistor MP9.

[0091] Transistor MP12 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP12 is connected to the first input power supply. The second terminal of transistor MP12 is shorted to its control terminal. The control terminal of transistor MP12 is connected to the second terminal of buffer 300, which is used to output a drive signal to power transistor circuit 400.

[0092] Transistor MP11 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MP11 is connected to the second terminal of transistor MP10 and the second terminal of transistor MP12. The control terminal of transistor MP11 is connected to the first terminal of buffer 300, which is used to receive the first voltage signal output by error amplifier 200.

[0093] Transistor MN7 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MN7 is grounded, the second terminal of transistor MN7 is connected to the second terminal of transistor MP9, and the second terminal of transistor MN7 is shorted to its control terminal.

[0094] Transistor MN8 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MN8 is grounded, the second terminal of transistor MN8 is connected to the second terminal of transistor MP11, and the control terminal of transistor MN8 is connected to the control terminal of transistor MN7.

[0095] Transistor MN9 includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MN9 is grounded, the second terminal of transistor MN9 is connected to the second terminal of transistor MP12, and the control terminal of transistor MN9 is connected to the second terminal of transistor MP11.

[0096] In some embodiments, the power transistor circuit 400 includes a transistor MP.

[0097] The transistor MP includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP is connected to the input power supply, the second terminal of the transistor MP serves as the output of the LDO circuit, and the control terminal of the transistor MP is connected to the output of the buffer 300 to receive the drive signal output by the buffer 300.

[0098] In some embodiments, the feedback circuit 500 includes resistors Rf1, Rf2, and Rf3 connected in series.

[0099] One end of resistor Rf1 is connected to the output terminal of power transistor 400, and the other end of resistor Rf3 is grounded. The feedback terminal of feedback circuit 500 is located at the series node of resistors Rf1 and Rf2.

[0100] In some embodiments, the fast transient response fully integrated LDO circuit also includes a compensation circuit 600.

[0101] The compensation circuit 600 is connected across the output of the error amplifier 200 and the output stage of the LDO circuit.

[0102] In some embodiments, the compensation circuit 600 includes a capacitor CC connected between the output of the error amplifier 200 and the output stage of the LDO circuit for compensation.

[0103] The fast transient response fully integrated LDO circuits provided in the above embodiments are based on adaptive bias circuits. Regardless of whether it is overcharged or undercharged, they can provide a proportional adaptive large current to the error amplifier, which improves the charging and discharging response speed of the error amplifier to the gate of the power transistor in the LDO circuit. They can suppress overcharge and undercharge states without the need to add additional detection circuits and / or suppression circuits. Moreover, the adaptive bias current in the static state is very small, which can ensure the low power consumption and fast transient response of the LDO circuit.

[0104] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art, under the guidance of this application, can make several simple deductions, modifications or substitutions based on the spirit of this application and the scope of protection of the claims without departing from the spirit of this application and the claims. All of these are within the protection scope of this application.

Claims

1. A fast transient response fully integrated LDO circuit, characterized in that, This includes an error amplifier, buffer, power transistor circuit, feedback circuit, and adaptive bias circuit; The feedback circuit is used to acquire the feedback voltage VFB at the output of the LDO circuit; The error amplifier is used to receive the external reference voltage VREF, the feedback voltage VFB, and the bias current provided by the adaptive bias circuit. After comparing the external reference voltage VREF and the feedback voltage VFB, it amplifies the error and outputs the first voltage signal. The buffer is used to receive the first voltage signal and output a drive signal after buffering. The power transistor circuit responds to the drive signal to achieve a fast transient response of the LDO output when the load changes. The adaptive bias circuit includes an adaptive bias module, a first port, a second port, and an output port; the first port is used to receive an external reference voltage VREF and transmit it to the adaptive bias module. The second port is used to receive the feedback voltage VFB of the LDO circuit and transmit it to the adaptive bias module; The adaptive bias module is used to generate a bias current based on the relationship between the external reference voltage VREF and the feedback voltage VFB of the LDO circuit, and transmit the bias current to the error amplifier in the LDO circuit through the output port; when the load of the LDO circuit changes, causing the feedback voltage VFB to change, the adaptive bias module can adaptively adjust the bias current it generates according to the changed feedback voltage VFB, so that the error amplifier in the LDO circuit can respond quickly. The adaptive bias module includes at least two differential flip voltage follower circuits, a current source and a current mirror that are the same number as and correspond one-to-one with the differential flip voltage follower circuits. Each of the differential flip voltage follower circuits is used to receive the external reference voltage VREF and the feedback voltage VFB of the LDO circuit, and outputs a follower current signal according to the relationship between the external reference voltage VREF and the feedback voltage VFB. Each of the current sources is used to provide a quiescent current for its corresponding differential flip-flop voltage follower circuit; and the current value of each of the current sources is equal. The current mirror is used to receive the following current signal output by each of the differential flip voltage follower circuits, and outputs the bias current to the error amplifier by mirroring the following current signal; The error amplifier includes transistors MP0, MP1, MP2, MP3, MP4, MN0, MN1, MN2, MP5, MP6, MP7, MP8, MN3, MN4, MN5, and MN6. The transistor MP0 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP0 is connected to a first input power supply, the second terminal of the transistor MP0 is shorted to its control terminal, and the second terminal of the transistor MP0 is connected to the bias current input terminal of the error amplifier. The transistor MP1 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP1 is connected to the first input power supply, and the control terminal of the transistor MP1 is connected to the second terminal of the transistor MP0. The transistor MP2 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP2 is connected to the first input power supply, and the control terminal of the transistor MP2 is connected to the control terminal of the transistor MP1. The transistor MP3 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP3 is connected to the second terminal of the transistor MP2. The control terminal of the transistor MP3 is used to receive an external reference voltage VREF. The transistor MP4 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP4 is connected to the second terminal of the transistor MP2. The control terminal of the transistor MP3 is used to receive the feedback voltage VFB. The transistor MN0 includes a first terminal, a second terminal, and a control terminal. The second terminal of the transistor MN0 is connected to the second terminal of the transistor MP1 and short-circuited with its control terminal. The transistor MN1 includes a first terminal, a second terminal, and a control terminal. The second terminal of the transistor MN1 is connected to the first terminal of the transistor MN0 and short-circuited to its control terminal. The transistor MN2 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MN2 is grounded, and the second terminal of the transistor MN2 is connected to the first terminal of the transistor MN1 and short-circuited with its control terminal. The transistor MP5 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor MP5 is connected to the first input power supply. The transistor MP6 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP6 is connected to the first input power supply, and the control terminal of the transistor MP6 is connected to the control terminal of the transistor MP5. The transistor MP7 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP7 is connected to the second terminal of the transistor MP5, and the second terminal of the transistor MP7 is connected to the control terminal of the transistor MP5. The transistor MP8 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP8 is connected to the second terminal of the transistor MP6. The control terminal of the transistor MP8 is connected to the control terminals of the transistor MP7 and the transistor MN2. The second terminal of the transistor MP8 is used to output a first voltage signal. The transistor MN3 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MN3 is connected to the second terminal of the transistor MP4, and the second terminal of the transistor MN3 is connected to the second terminal of the transistor MP7. The transistor MN4 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MN4 is connected to the second terminal of the transistor MP3, the second terminal of the transistor MN4 is connected to the second terminal of the transistor MP8, and the control terminal of the transistor MN4 is connected to the control terminals of the transistor MN3 and the transistor MN1. The transistor MN5 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MN5 is grounded, and the second terminal of the transistor MN5 is connected to the first terminal of the transistor MN3. The transistor MN6 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MN6 is grounded, the second terminal of the transistor MN6 is connected to the first terminal of the transistor MN4, and the control terminal of the transistor MN6 is connected to the control terminals of the transistor MN5 and the transistor MN0.

2. The fast transient response fully integrated LDO circuit according to claim 1, characterized in that, The adaptive bias current is proportional to the square of the difference between the external reference voltage VREF and the feedback voltage VFB of the LDO circuit.

3. The fast transient response fully integrated LDO circuit according to claim 1, characterized in that, The adaptive bias module includes a first differential flip voltage follower circuit, a second differential flip voltage follower circuit, a first current source, and a second current source. The first differential flip voltage follower circuit includes a first terminal, a second terminal, a third terminal, and an output terminal. The first terminal of the first differential flip voltage follower circuit is used to receive the external reference voltage VREF. The second terminal of the first differential flip voltage follower circuit is used to receive the feedback voltage VFB of the LDO circuit. The output terminal of the first differential flip voltage follower circuit is used to output a first follower current signal according to the relationship between the external reference voltage VREF and the feedback voltage VFB. The second differential flip voltage follower circuit includes a first terminal, a second terminal, a third terminal, and an output terminal. The first terminal of the second differential flip voltage follower circuit is used to receive the feedback voltage VFB of the LDO circuit. The second terminal of the second differential flip voltage follower circuit is used to receive the external reference voltage VREF. The output terminal of the second differential flip voltage follower circuit is used to output a second follower current signal according to the relationship between the external reference voltage VREF and the feedback voltage VFB. The first current source includes a first terminal and a second terminal. The first terminal of the first current source is connected to the third terminal of the first differential flip voltage follower circuit, and the second terminal of the first current source is grounded. The second current source includes a first terminal and a second terminal. The first terminal of the second current source is connected to the third terminal of the second differential flip voltage follower circuit, and the second terminal of the second current source is grounded. The current values ​​of the first current source and the second current source are equal.

4. The fast transient response fully integrated LDO circuit according to claim 3, characterized in that, The first differential flip voltage follower circuit includes transistors M2a, M1a, and M3a; The transistor M2a includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor M2a is connected to a first input power supply, and the control terminal of the transistor M2a is connected to the third terminal of the first differential flip voltage follower circuit. The transistor M1a includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor M1a is connected to the second terminal of the transistor M2a. The second terminal of the transistor M1a is connected to the third terminal of the first differential flip voltage follower circuit. The control terminal of the transistor M1a is connected to the first terminal of the first differential flip voltage follower circuit. The transistor M3a includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor M3a is connected to the second terminal of the transistor M2a. The second terminal of the transistor M3a is connected to the output terminal of the first differential flip voltage follower circuit. The control terminal of the transistor M3a is connected to the second terminal of the first differential flip voltage follower circuit. as well as, The second differential flip voltage follower circuit includes transistors M2b, M1b, and M3b; The transistor M2b includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor M2b is connected to the second input power supply, and the control terminal of the transistor M2b is connected to the third terminal of the second differential flip voltage follower circuit. The transistor M1b includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor M1b is connected to the second terminal of the transistor M2b, the second terminal of the transistor M1b is connected to the third terminal of the second differential flip voltage follower circuit, and the control terminal of the transistor M1b is connected to the first terminal of the second differential flip voltage follower circuit. The transistor M3b includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor M3b is connected to the second terminal of the transistor M2b. The second terminal of the transistor M3b is connected to the output terminal of the second differential flip voltage follower circuit. The control terminal of the transistor M3b is connected to the second terminal of the second differential flip voltage follower circuit.

5. The fast transient response fully integrated LDO circuit according to claim 1, characterized in that, The current mirror includes transistors M4a and M4b; The transistor M4a includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor M4a is grounded, the second terminal of the transistor M4a is connected to the first terminal of the current mirror, and the control terminal of the transistor M4a is short-circuited to the second terminal of the transistor M4a. The transistor M4b includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor M4b is grounded, the second terminal of the transistor M4b is connected to the second terminal of the current mirror, and the control terminal of the transistor M4b is connected to the control terminal of the transistor M4a.

6. The fast transient response fully integrated LDO circuit according to claim 1, characterized in that, It also includes a compensation circuit; the compensation circuit is connected between the output of the error amplifier and the output stage of the LDO circuit.

7. The fast transient response fully integrated LDO circuit according to claim 1, characterized in that, The buffer includes transistors MP9, MP10, MP12, MP11, MN7, MN8, and MN9. The transistor MP9 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor MP9 is connected to the first input power supply. The transistor MP10 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP10 is connected to the first input power supply, and the control terminal of the transistor MP10 is connected to the control terminal of the transistor MP9. The transistor MP12 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP12 is connected to the first input power supply, the second terminal of the transistor MP12 is shorted to its control terminal, and the control terminal of the transistor MP12 is used to output the drive signal. The transistor MP11 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MP11 is connected to the second terminal of the transistor MP10 and the second terminal of the transistor MP12. The control terminal of the transistor MP11 is used to receive the first voltage signal. The transistor MN7 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MN7 is grounded, the second terminal of the transistor MN7 is connected to the second terminal of the transistor MP9, and the second terminal of the transistor MN7 is shorted to its control terminal. The transistor MN8 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MN8 is grounded, the second terminal of the transistor MN8 is connected to the second terminal of the transistor MP11, and the control terminal of the transistor MN8 is connected to the control terminal of the transistor MN7. The transistor MN9 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor MN9 is grounded, the second terminal of the transistor MN9 is connected to the second terminal of the transistor MP12, and the control terminal of the transistor MN9 is connected to the second terminal of the transistor MP11.

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