The sense amplifier reference voltage of the device is latched by the sense amplifier

Abstract

The present application relates to latching a sense amplifier reference voltage for a device via a sense amplifier. A sense amplifier for a memory device includes latch transistors configured to latch a value based on charge in a memory cell. A first latch transistor applies a reference voltage to a first critical node of the sense amplifier via one of the latch transistors. The sense amplifier also applies charge from the memory cell corresponding to the sense amplifier to a second critical node. The sense amplifier also latches a value in the sense amplifier based on a relationship between the reference voltage and the charge.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 348,345, filed on June 2, 2022, entitled “Sense Amplifier Reference Voltage Through Sense Amplifier Latch Devices,” the entire disclosure of which is incorporated by reference for all purposes. Technical Field

[0003] Embodiments of the present disclosure generally relate to memory devices and, more particularly, to sense amplifiers of memory devices. Background Art

[0004] Generally, a computing system may include electronic devices that communicate information via electrical signals during operation. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random access memory (DRAM) device, a ferroelectric random access memory (FeRAM) device, another random access memory (RAM) device, and / or a hybrid device incorporating more than one type of RAM. In this manner, the processor can communicate with the memory device, for example, to retrieve executable instructions, retrieve data to be processed by the processor, and / or store data output from the processor. In some embodiments, data approximation memory can be used to improve energy efficiency. However, approximate memory can expose data elements to errors. One mechanism for interfacing with approximate data is AxRAM, which is configured to reduce the likelihood of execution crashes.

[0005] AxRAM (and other types of) memory devices utilize sense amplifiers for use by the memory device during read operations. Specifically, the memory device's read circuitry utilizes sense amplifiers to receive low-voltage signals and amplify the smaller voltage to enable the memory device to correctly interpret the data. However, due to the large number of sense amplifiers in a memory device, any excessive consumption of resources (e.g., power and / or area) in the sense amplifiers, even when the variation in a single sense amplifier is relatively small, can affect the efficiency of the memory device's resources. Furthermore, some sense amplifiers may be sensitive to threshold voltage mismatches between the sense amplifier latch devices (e.g., NMOS and / or PMOS transistors).

[0006] Embodiments of the present disclosure may address one or more of the issues set forth above. Summary of the Invention

[0007] In one aspect, the present disclosure provides a method of operating a sense amplifier of a memory device, comprising: applying a reference voltage to a first gut node of the sense amplifier via a latch transistor; passing a charge from a memory cell corresponding to the sense amplifier to a second gut node; and using the latch transistor to latch a value in the sense amplifier based on a relationship between the reference voltage and the charge.

[0008] In another aspect, the present disclosure provides a sense amplifier comprising: a first latch transistor comprising: a first terminal of the first latch transistor coupled to a top node; a second terminal of the first latch transistor coupled to a first key node; and a third terminal of the first latch transistor coupled to a second key node, wherein the first latch transistor is configured to supply a first reference voltage from the top node to the first key node through the first latch transistor when the second key node is to receive a first charge for readout from one or more memory cells corresponding to the sense amplifier, and the first reference voltage is used to interpret a first logic value of the first charge; and a second latch transistor comprising: a first terminal of the second latch transistor coupled to the top node; a second terminal of the second latch transistor coupled to the second key node; and a third terminal of the second latch transistor coupled to the first key node, wherein the second latch transistor is configured to supply a second reference voltage from the top node to the second key node through the second latch transistor when the first key node is to receive a second charge for readout from the one or more memory cells corresponding to the sense amplifier, and the second reference voltage is used to interpret a second logic value of the second charge.

[0009] In another aspect, the present disclosure provides a memory device comprising: one or more memory cells configured to store data; a pair of digit lines coupled to the one or more memory cells; and a sense amplifier coupled to the digit line pair and comprising: a cross-coupled transistor coupled to a first node; a first critical node coupled to a first transistor of the cross-coupled transistors, wherein the first critical node corresponds to a first digit line of the digit line pair, and the first transistor is configured to supply a first reference voltage to the first critical node; and a second critical node coupled to a second transistor of the cross-coupled transistors, wherein the second critical node corresponds to the a second digit line of the digit line pair, and the second transistor is configured to supply a second reference voltage to the second critical node; a third transistor coupled to the first critical node; a fourth transistor coupled to the second critical node; a first isolation transistor coupled between the first digit line and the first critical node to selectively decouple the first digit line from the first critical node when amplifying a voltage on the first or second critical node; and a second isolation transistor coupled between the second digit line and the second critical node to selectively decouple the second digit line from the second critical node when amplifying the voltages on the first and second critical nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a simplified block diagram illustrating certain features of a memory device having a sense amplifier according to an embodiment of the present disclosure;

[0011] Figure 2 is a reference transistor / switch according to an embodiment of the present disclosure Figure 1 A circuit diagram of an embodiment of a sense amplifier;

[0012] Figure 3 There is no explicit reference transistor / switch in the sense amplifier according to an embodiment of the present disclosure Figure 1 A circuit diagram of an alternative embodiment of a sense amplifier;

[0013] Figure 4 The present invention is a device having a threshold voltage compensation circuit system according to an embodiment of the present invention. Figure 3 A circuit diagram of an embodiment of a sense amplifier;

[0014] Figure 5 The use of the embodiment according to the present disclosure Figure 4 A graph of an embodiment of the operation of a sense amplifier; and

[0015] Figure 6 is a device having multiple offset drive signals for threshold compensation circuitry according to an embodiment of the present disclosure Figure 4 An alternative embodiment of a sense amplifier. DETAILED DESCRIPTION

[0016] One or more specific embodiments are described below. To provide a brief description of these embodiments, not all features of an actual implementation are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. Furthermore, it should be understood that such development work may be complex and time-consuming, but will nevertheless be a routine task of design, fabrication, and production for those of ordinary skill having the benefit of this disclosure.

[0017] As previously discussed, the read circuitry of a memory device utilizes a sense amplifier to receive low-voltage (e.g., low differential) signals and amplify smaller voltage differences so that the memory device can correctly interpret the data. However, some embodiments of the sense amplifier consume excessive resources (e.g., power and / or area). Therefore, as taught herein, the sense amplifier can be modified to omit a dedicated reference voltage transistor for charging a key node to a reference voltage level, thereby determining a logic value from the voltage used to charge the other key nodes. In other words, in a key node pair, the first key node stores a charge proportional to the charge stored in the memory cell, while the second key node stores a reference voltage. When the charge of the first key node is greater than the charge of the second key node, the data can be interpreted as a logic high value. However, when the charge of the first key node is less than the charge of the first key node, the data can be interpreted as a logic low level. As described, the reference voltage can use a dedicated reference transistor to charge the second key node. However, these transistors consume space. To reduce the area consumed by the sense amplifier, the reference transistor can be omitted. Instead of a dedicated reference transistor, a latch transistor (e.g., a PMOS transistor) can be used to deliver the reference voltage to the appropriate critical node. By using a latch transistor that also serves for latching and amplification, the sense amplifier can be smaller and consume less area in the memory device while maintaining timing and / or operational capabilities.

[0018] Now turning to the accompanying drawings, Figure 1 is a simplified block diagram illustrating certain features of memory device 10. Specifically, Figure 1 The block diagram is a functional block diagram illustrating certain functionality of memory device 10. According to one embodiment, memory device 10 may be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, greater bandwidth, and greater storage capacity compared to previous generations of DDR SDRAM.

[0019] Memory device 10 may include several memory banks 12. For example, memory banks 12 may be DDR5 SDRAM memory banks. Memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). As will be appreciated, each DIMM may include several SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may include one or more memory banks 12. Memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having several memory banks 12. For DDR5, memory banks 12 may be further arranged to form memory bank groups. For example, for an 8-gigabyte (Gb) DDR5 SDRAM, a memory chip may include 16 memory banks 12 arranged in eight memory bank groups, each memory bank group including two memory banks. For example, for a 16-Gb DDR5 SDRAM, a memory chip may include 32 memory banks 12 arranged in eight memory bank groups, each memory bank group including four memory banks. Various other configurations, organizations, and sizes of banks 12 on memory device 10 may be utilized depending on the application and design of the overall system.

[0020] The memory bank 12 and / or the memory bank control block 22 include sense amplifiers 13. As previously described, the sense amplifiers 13 are used by the memory device 10 during read operations. Specifically, the read circuitry of the memory device 10 utilizes the sense amplifiers 13 to receive low voltage (e.g., low differential) signals from the memory cells of the memory bank 12 and amplify the small voltage differences so that the memory device 10 can correctly interpret the data.

[0021] Memory device 10 may include a command interface 14 and an input / output (I / O) interface 16. Command interface 14 is configured to provide a number of signals (e.g., signal 15) from an external (e.g., host) device (not shown), such as a processor or controller. The processor or controller may provide various signals 15 to memory device 10 to facilitate the transmission and reception of data to be written to or read from memory device 10.

[0022] As will be appreciated, the command interface 14 may include several circuits, such as clock input circuitry 18 and command address input circuitry 20, to ensure proper handling of the signal 15, for example. The command interface 14 may receive one or more clock signals from an external device. Typically, double data rate (DDR) memory utilizes a differential system clock signal pair, a true clock signal Clk_t and a bar / complementary clock signal Clk_c. A positive clock edge in DDR refers to the point where a rising true clock signal Clk_t crosses a falling complementary clock signal Clk_c, while a negative clock edge indicates a transition between a falling true clock signal Clk_t and a rising complementary clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0023] The clock input circuit 18 receives the true clock signal Clk_t and the complementary clock signal Clk_c and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay-locked loop (DLL) circuit 30. The DLL circuit 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, the I / O interface 16 and used as a timing signal for determining the output timing of read data. In some embodiments, the clock input circuit 18 may include circuitry that divides the clock signal into multiple (e.g., four) phases. The clock input circuit 18 may also include phase detection circuitry to detect which phase receives the first pulse when multiple sets of pulses occur too frequently, allowing the clock input circuit 18 to reset between the multiple sets of pulses.

[0024] The internal clock signal(s) / phase CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from a command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide the command signals to the DLL circuit 30 via bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. For example, the phase-controlled internal clock signal LCLK may be used to clock data passing through the IO interface 16.

[0025] Furthermore, the command decoder 32 may decode commands, such as read commands, write commands, mode register set commands, activate commands, etc., and provide access to the specific memory bank 12 corresponding to the command via the bus path 40. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks 12. In one embodiment, each memory bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) as well as other features (e.g., timing control and data control) to facilitate execution of commands to and from the memory banks 12.

[0026] The memory device 10 performs operations, such as read and write commands, based on command / address signals received from an external device, such as a processor. In one embodiment, the command / address bus may be a 14-bit bus to accommodate the command / address signals (CA<13:0>). Clock signals (Clk_t and Clk_c) are used to clock the command / address signals to the command interface 14. The command interface may include a command and address input circuit 20 configured to receive and transmit commands, such as to provide access to the memory banks 12 via a command decoder 32. Additionally, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands incoming on the CA<13:0> bus. Access to a specific memory bank 12 within the memory device 10 is encoded on the CA<13:0> bus using commands.

[0027] In addition, the command interface 14 can be configured to receive several other command signals. For example, a command / address on-die termination (CA_ODT) signal can be provided to facilitate proper impedance matching within the memory device 10. For example, a reset command (RESET_n) can be used during power-up to reset the command interface 14, status registers, state machines, etc. The command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to, for example, invert the state of the command / address signals CA<13:0> on the command / address bus, depending on the command / address routing of a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a particular application, the MIR signal can be used to multiplex signals so that they can be swapped to achieve specific routing of signals to the memory device 10. Various signals that facilitate testing of the memory device 10, such as a test enable (TEN) signal, can also be provided. For example, the TEN signal can be used to place the memory device 10 in a test mode for connectivity testing.

[0028] The command interface 14 can also be used to provide an alert signal (ALERT_n) to the system processor or controller for certain errors that may be detected. For example, if a cyclic redundancy check (CRC) error is detected, an alert signal (ALERT_n) can be transmitted from the memory device 10. Other alert signals can also be generated. In addition, the bus and pins used to transmit the alert signal (ALERT_n) from the memory device 10 can be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal, as described above.

[0029] By transmitting and receiving data signals 44 through IO interface 16, data can be sent to and from memory device 10 using the command and timing signals discussed above. More specifically, data can be sent to and retrieved from memory bank 12 via data path 46, which includes multiple bidirectional data buses. Data IO signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For some memory devices, such as DDR5 SDRAM memory devices, IO signals can be divided into upper and lower bytes. For example, for a x16 memory device, IO signals can be divided into upper and lower IO signals (e.g., DQ<15:8> and DQ<7:0>), corresponding to the upper and lower bytes of the data signals, for example.

[0030] To allow for higher data rates within the memory device 10, some memory devices, such as DDR memory devices, may utilize a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller sending the data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is actually an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal is used as a clock signal to capture the corresponding input data. Like the clock signals (Clk_t and Clk_c), the DQS signal can be provided as a differential data strobe signal pair (DQS_t and DQS_c) to provide differential pair signaling during reads and writes. For some memory devices, such as DDR5 SDRAM memory devices, the differential DQS signal pair can be divided into upper and lower data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c), corresponding to the upper and lower bytes of data sent to and from the memory device 10.

[0031] An impedance (ZQ) calibration signal may also be provided to the memory device 10 via the IO interface 16. The ZQ calibration signal may be provided to a reference pin and used to tune the output driver and ODT value by adjusting the pull-up and pull-down resistors of the memory device 10 across variations in process, voltage, and temperature (PVT) values. Because PVT characteristics may affect the ZQ resistor value, the ZQ calibration signal may be provided to the ZQ reference pin for adjusting the resistor to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor serves as a reference for adjusting the internal ODT and drive strength of the IO pins.

[0032] Additionally, a loopback data signal (LBDQ) and a loopback strobe signal (LBDQS) may be provided to the memory device 10 via the IO interface 16. The loopback data signal and the loopback strobe signal may be used during a test or debug phase to set the memory device 10 into a mode in which signals are looped back through the memory device 10 via the same pin. For example, the loopback signal may be used to set up the memory device 10 to test the data output (DQ) of the memory device 10. The loopback may include both the LBDQ and LBDQS pins, or perhaps only the loopback data pin. This is generally intended for monitoring data captured by the memory device 10 at the IO interface 16. The LBDQ may indicate the data operation of a target memory device, such as the memory device 10, and thus, may be analyzed to monitor the data operation of the target memory device (e.g., to debug and / or perform diagnostics on it). Additionally, the LBDQS may indicate the strobing operation (e.g., the timing of the data operation) of the target memory device, such as the memory device 10, and thus, may be analyzed to monitor the strobing operation of the target memory device (e.g., to debug and / or perform diagnostics on it).

[0033] As will be appreciated, various other components, such as power supply circuits (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 10), etc., may also be incorporated into the memory device 10. Therefore, it should be understood that Figure 1 The block diagram is provided only to highlight certain functional features of the memory device 10 to assist in the subsequent detailed description. Furthermore, although the foregoing discusses the memory device 10 as a DDR5 device, the memory device 10 may be any suitable device (e.g., a low-power double data rate (LPDDR) device, a double data rate type 4 DRAM (DDR4) device, a ferroelectric RAM device, or a combination of different types of memory devices).

[0034] Figure 2 It can be implemented as Figure 1 1 is a circuit diagram of a sense amplifier 50 of an embodiment of the sense amplifier 13. Although only a single sense amplifier 50 is shown, multiple sense amplifiers 13 are included in the memory device 10 that operate similarly and may share at least some control signals and / or supply voltages.

[0035] As illustrated, sense amplifier 50 receives an ACT signal 52 at terminals (e.g., source terminals) of PMOS transistors 54 and 55 via a "top node." Although the illustrated embodiment shows both PMOS transistors 54 and 55 coupled to the same ACT signal 52 and therefore receiving the same voltage, some embodiments of sense amplifier 50 may connect PMOS transistors 54 and 55 to different ACT signals to enable driving the source terminals of PMOS transistors 54 and 55 at different voltage levels. ACT signal 52 is typically used to control data movement and control of sense amplifier 50. The other terminal (e.g., drain) of PMOS transistor 54 is coupled to critical node a (GUTa) 56, and the other terminal (e.g., drain) of PMOS transistor 55 is coupled to critical node b (GUTb) 58. The gate terminal of PMOS transistor 54 is also coupled to critical node b 58, and the gate terminal of PMOS transistor 55 is also coupled to critical node a 56. In other words, the PMOS transistors 54 and 55 are cross-coupled PMOS transistors coupled between the key node and the ACT signal 52 .

[0036] Sense amplifier 50 also includes an NMOS transistor 60 having a terminal (e.g., a source terminal) coupled to critical node a 56, while an NMOS transistor 62 has its gate terminal coupled to critical node b 58. Similarly, sense amplifier 50 also includes an NMOS transistor 62 having a terminal (e.g., a source terminal) coupled to critical node b 58, while an NMOS transistor 62 has its gate terminal coupled to critical node a 56. The other terminals of NMOS transistors 60 and 62 are coupled together to a signal 98. Signal 98 (e.g., an NMOS select signal) can be a selectable voltage that can gate NMOS transistors 60 and 62 to a voltage level (e.g., ground) to complete latching once amplification in sense amplifier 50 has amplified the relatively low voltage from the memory cell.

[0037] In some memory devices (e.g., AxRAM devices), one of the critical nodes (critical node a 56 or critical node b 58) can be charged by the memory cell, while the other critical node can be used as a reference voltage to interpret the charge from the memory cell. Either critical node can be a reference for the other critical node. Therefore, to enable critical node a 56 to carry a reference voltage for comparison with the charge on critical node b 58, sense amplifier 50 includes transistor 64 (e.g., an NMOS transistor) that utilizes an ARREFa signal 66 to apply a reference voltage 68 to critical node a 56. Similarly, to enable critical node b 58 to carry a reference voltage 68 for comparison with the charge on critical node a 56, sense amplifier 50 includes transistor 70 (e.g., an NMOS transistor) that utilizes an ARREFb signal 72 to apply a reference voltage 68 to critical node b 58. Furthermore, although the illustrated embodiment shows reference voltage 68 being the same for both critical nodes via transistors 64 and 70 , in some embodiments, transistors 64 and 70 may apply different reference voltage levels.

[0038] Furthermore, in some embodiments (e.g., AxRAM devices), the sense amplifier 50 may charge / discharge the key nodes to a specific level (e.g., 0V or some other voltage) before the memory cell charges the first key node and charges the second key node to a reference voltage 68. To charge / discharge key node a 56, the sense amplifier 50 includes a transistor 74 (e.g., an NMOS transistor) that selectively couples key node a 56 to VSS 78 (e.g., 0V or some other voltage) using an ARPREa signal 76. Similarly, to charge / discharge key node b 58, the sense amplifier 50 includes a transistor 80 (e.g., an NMOS transistor) that selectively couples key node b 58 to VSS 84 (e.g., 0V or some other voltage) using an ARPREb signal 82. VSS 78 and VSS 84 may be the same value or different values.

[0039] Critical node a 56 can receive charge from a memory cell via a local IO line (LIOa) 86. Critical node a 56 can also apply an amplified voltage from the sense amplifier back to LIOa 86 after amplification. To control when critical node a 56 receives charge from a memory cell and / or transmits it via LIOa 86, sense amplifier 50 includes a transistor 88 (e.g., an NMOS transistor / isolation transistor) that selectively couples critical node a 56 to LIOa 86 and decouples critical node a 56 from LIOa 86. Transistor 88 uses an ARLIOEn signal 90 to enable or disable the connection between LIOa 86 and critical node a 56.

[0040] Similarly, critical node b 58 can receive charge from a memory cell via a local IO line (LIOb) 92. Critical node b 58 can also apply an amplified voltage from the sense amplifier back to LIOb 92 after amplification. To control when critical node b 58 receives charge from a memory cell and / or transmits it via LIOb 92, sense amplifier 50 includes a transistor 94 (e.g., an NMOS transistor / isolation transistor) that selectively couples critical node b 58 to LIOb 92 and decouples critical node b 58 from LIOb 92. Transistor 94 uses ARLIOEn signal 90 to enable or disable the connection between LIOb 92 and critical node b 58.

[0041] To reduce the size of the memory device 10, a reference voltage 68 can be applied via the ACT signal 52 through one of the PMOS latch devices (e.g., PMOS transistors 54 and 55) to charge any key node. Using such a technique, the overall size of the sense amplifier 50 can be reduced. As can be appreciated, there are a large number of sense amplifiers 13 in the memory device 10. Therefore, even a small improvement in power or area consumption can have a significant impact on the overall design of the memory device 10. Therefore, as Figure 3 As illustrated in sense amplifier 100 of FIG. 1 , when sense amplifier 100 is used to implement sense amplifier 13 instead of sense amplifier 50 , removing transistors 64 and 70 from sense amplifier 50 reduces the size of sense amplifier 13 .

[0042] like Figure 3 As illustrated in FIG, sense amplifier 100 operates identically to sense amplifier 50, except that transistors 64 and 70 are omitted and the reference voltage is applied to ACT signal 52 when charging one of the critical nodes. By applying reference voltage 68 via ACT signal 52, sense amplifier 100 can have two fewer transistors than sense amplifier 50 with the same read window (e.g., without the timing penalty in exchange for reduced size).

[0043] In some memory devices, latch devices (e.g., PMOS transistors 54 and 55) may be mismatched with different threshold voltages. For example, due to PVT variations, the latch devices may have different corresponding threshold voltages. To address these mismatches, some embodiments of memory device 10 may include threshold voltage compensation (VTC) circuitry. For example, Figure 4 is a circuit diagram of a sense amplifier 120, which is similar to Figure 3 Sense amplifier 100 operates as described above, except that sense amplifier 120 includes VTC circuitry 121. As illustrated, VTC circuitry 121 is disposed between PMOS transistors 54 and 55 and NMOS transistors 60 and 62 and utilizes offset signal 122 for controlling when VTC is applied. Specifically, VTC circuitry 121 includes transistor 124 (e.g., an NMOS transistor) that selectively couples the gate and drain terminals of PMOS transistor 54 together based on the value of offset signal 122. VTC circuitry 121 also includes transistor 126 (e.g., a PMOS transistor) between the drain terminal of PMOS transistor 54 and critical node a 56. Transistor 124 and transistor 126 may have different doping types to cause one transistor to function as an open switch and the other transistor to function as a closed switch in response to assertion of offset signal 122. Thus, when transistor 124 acts as a closed switch to configure PMOS transistor 54 into a diode configuration, transistor 126 disconnects PMOS transistor 54 from critical node a 56 .

[0044] Similarly, VTC circuitry 121 includes transistor 128 (e.g., an NMOS transistor) that selectively couples the gate and drain terminals of PMOS transistor 55 together based on the value of offset signal 122. VTC circuitry 121 also includes transistor 130 (e.g., a PMOS transistor) between the drain terminal of PMOS transistor 55 and critical node b 58. Transistor 128 and transistor 130 may have different doping types to cause one transistor to function as an open switch and the other transistor to function as a closed switch in response to assertion of offset signal 122. Thus, when transistor 128 functions as a closed switch to configure PMOS transistor 55 into a diode configuration, transistor 130 disconnects PMOS transistor 55 from critical node b 58.

[0045] With the PMOS transistors 54 and 55 in a diode configuration, the critical node is charged with a voltage proportional to the respective threshold voltages of the PMOS transistors 54 and 55. When the VTC is disabled by deasserting the offset signal 122 after it has been enabled, the functional connections of the VTC circuitry 121 of the sense amplifier 120 are exactly the same as those of the sense amplifier 100 without the VTC circuitry 121, except that the critical nodes of the sense amplifier 120 store charge to compensate for the threshold voltages of the PMOS transistors 54 and 55 such that any mismatch in PVT variations is compensated by the stored charge on the critical nodes.

[0046] Figure 5 Graph 150 is a graph illustrating an embodiment of operation using sense amplifier 120. As illustrated, graph 150 includes lines 152 and 154 corresponding to voltages of respective word lines. Line 152 corresponds to a word line close to its word line driver, and line 154 corresponds to a word line far from its word line driver. Graph 150 also includes line 156 corresponding to the voltage carried as ACT signal 52. Furthermore, graph 150 includes line 158 corresponding to offset signal 122. Graph 150 further includes line 160 corresponding to ARPREa signal 76 and line 162 corresponding to ARPREb signal 82. Graph 150 also includes lines 164, 166, 168, and 170 corresponding to voltages on key nodes of sense amplifier 120. In some embodiments, lines 164 and 166 correspond to a first iteration of sense amplifier 120 in memory device 10, while lines 168 and 170 correspond to a second iteration of sense amplifier 120 in memory device 10. Alternatively, lines 164 , 166 , 168 , and 170 correspond to the same sense amplifier 120 , but lines 164 and 166 correspond to readings of different values ​​stored in the memory cell than lines 168 and 170 .

[0047] Regardless of which sense amplifier 120 is represented by lines 164, 166, 168, and 170, lines 164 and 168 correspond to key nodes (e.g., key node a 56) for reading from the cell. Similarly, lines 166 and 170 correspond to key nodes (e.g., key node b 58) for carrying a reference voltage. With respect to line 164, the corresponding memory cell stores a logic low value. With respect to line 168, the corresponding memory cell stores a logic high value.

[0048] At time 172, ARPREa signal 76 and ARPREb signal 82 are asserted causing critical node a 56 and critical node b 58 to be discharged to VSS (e.g., to 0V), as illustrated by lines 164, 166, 168, and 170. In a particular embodiment, the discharged critical nodes may be pulled below 0V to lower the overall voltage to provide a larger window in interpreting data in exchange for increased power consumption in sense amplifier 120. In some embodiments, ACT signal 52 may begin at some non-zero voltage prior to time 172, while in other embodiments, ACT signal 52 may begin at 0V prior to time 172.

[0049] Regardless, at time 174, the ACT signal 52 stabilizes to a reference voltage to be applied to the corresponding key node (e.g., key node b 58) for interpreting data from the memory cell used to charge other key nodes (e.g., key node a 56). Also at time 174, the ARPREb signal 82 used to precharge key node b 58 is deasserted to enable key node b 58 to be charged to the reference voltage.

[0050] Furthermore, at time 174, offset signal 122 remains asserted to enable VTC circuitry 121 to apply VTC while the far word line corresponding to line 154 remains stable. Thus, using the aforementioned signals, critical node a 56 (lines 164 and 168) is precharged to 0V while critical node b 58 (lines 166 and 170) undergoes VTC and is charged to the reference voltage.

[0051] At time 176, offset signal 122 and ARPREa signal 76 are deasserted, and key node a 56 is charged using the corresponding memory cell. Consequently, lines 164 and 168 are charged to their respective voltages. In other words, line 168 increases above the reference voltage stored in the key node corresponding to line 170, while line 164 remains below line 166. Consequently, when NMOS transistors 60 and 62 are enabled using signal 98 at latch time 178, sense amplifiers 120 corresponding to lines 164 and 166 latch at a logic low value. Similarly, when NMOS transistors 60 and 62 are enabled using signal 98 at latch time 178, sense amplifiers 120 corresponding to lines 168 and 170 latch at a logic high value. Based on which key node voltage is higher at the time of latch, an output value is then output via an input / output line (e.g., LIOa 86 or LIOb 92) at time 180.

[0052] Some embodiments of the sense amplifier 13 may include various variations that operate similarly but may have different configurations. For example, Figure 6 The sense amplifier 200 is described as Figure 4Sense amplifier 120 operates similarly to sense amplifier 120 in FIG. 1 , except that transistors 126 and 130 have been replaced by transistors 202 and 204. As previously mentioned, transistors 124 and 126 are doped differently from each other, just as transistors 128 and 130 are doped differently from each other. In sense amplifier 200, transistors 124, 128, 202, and 204 are all of the same type. However, to ensure that critical node a 56 is disconnected from NMOS transistor 60 during VTC, which is performed by coupling the drain and gate terminals of PMOS transistor 54 together, different offset signals are used to control transistors 124 and 202. For example, offset signal a 206 may be used to control transistor 202, and offset signal b 208 may be used to control transistor 124. These signals may be complementary signals, but in some embodiments, offset signal a 206 may be used to connect PMOS transistor 54 to critical node a 56 only after the gate and drain terminals of PMOS transistor 54 are disconnected from each other. In other words, offset signal a 206 is de-asserted only after offset signal b 208 is de-asserted. In some embodiments, offset signal a 206 and offset signal b 208 may be asserted simultaneously when the VTC is activated. Alternatively, in other embodiments, offset signal a 206 may be asserted before offset signal b 208.

[0053] Similarly, to ensure that critical node b 58 is disconnected from NMOS transistor 62 during VTC, which is performed by coupling the drain and gate terminals of PMOS transistor 54 together, different offset signals are used to control transistors 128 and 204. For example, transistor 204 may be controlled by offset signal a 206, and transistor 128 may be controlled by offset signal b 208. These signals may be complementary signals, but in some embodiments, offset signal a 206 may be used to connect PMOS transistor 55 to critical node b 58 only after the gate and drain terminals of PMOS transistor 55 are disconnected from each other.

[0054] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the following claims.

[0055] The techniques presented and claimed herein are cited and applied to substantial objects and specific examples that arguably improve the practical nature of the art and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "a step for [performing] [the function] ...", such elements are intended to be interpreted under 35 U.S.C. § 112(f). However, for any claim containing elements designated in any other manner, such elements are not intended to be interpreted under 35 U.S.C. § 112(f).

Claims

1. A method of operating a sense amplifier of a memory device, comprising: applying a reference voltage to a first critical node of the sense amplifier via a latch transistor; applying charge from a memory cell corresponding to the sense amplifier to a second critical node, wherein the latch transistor includes a first latch PMOS transistor coupled to the first critical node and a second latch PMOS transistor coupled to the second critical node; Applying voltage threshold compensation to the first and second latching PMOS transistors comprises: decoupling the first latch PMOS transistor from the first key node; decoupling the second latch PMOS transistor from the second key node; coupling two terminals of the first latch PMOS transistor together; and coupling two terminals of the second latch PMOS transistor together; and The latch transistor is used to latch a value in the sense amplifier based on a relationship between the reference voltage and the charge.

2. The method of claim 1 , wherein coupling the two terminals of the first latch PMOS transistor together comprises: The gate terminal of the first latch PMOS transistor and the drain terminal of the first latch PMOS transistor are coupled together via a first compensation transistor, and wherein coupling the two terminals of the second latch PMOS transistor together includes: coupling the gate terminal of the second latch PMOS transistor and the drain terminal of the second latch PMOS transistor together via a second compensation transistor.

3. The method of claim 1 , wherein decoupling the first latching PMOS transistor from the first critical node is performed before coupling the two terminals of the first latching PMOS transistor together, and decoupling the second latching PMOS transistor from the second critical node is performed before coupling the two terminals of the second latching PMOS transistor together.

4. The method of claim 3 , wherein decoupling the first latching PMOS transistor from the first critical node and decoupling the second latching PMOS transistor from the second critical node are performed using a first control signal, and coupling the two terminals of the first latching PMOS transistor together and coupling the terminals of the second latching PMOS transistor together are performed using a second control signal different from the first control signal.

5. The method according to claim 1, comprising: decoupling the two terminals of the first latching PMOS transistor from each other after applying voltage threshold compensation; decoupling the two terminals of the second latching PMOS transistor from each other after applying voltage threshold compensation; recoupling the first latching PMOS transistor to the first critical node after applying voltage threshold compensation; and The second latching PMOS transistor is recoupled to the second critical node after applying voltage threshold compensation.

6. The method of claim 5 , wherein recoupling the first latching PMOS transistor to the first critical node is performed after decoupling the two terminals of the first latching PMOS transistor, and recoupling the second latching PMOS transistor to the second critical node is performed after decoupling the two terminals of the second latching PMOS transistor.

7. The method according to claim 1, comprising: precharging the first critical node to a voltage level using a first precharge transistor; The second critical node is precharged to the voltage level using a second precharge transistor. The method of claim 7 , wherein the voltage level comprises 0V. 9 . The method of claim 7 , wherein precharging the first critical node and the second critical node to the voltage level occurs before applying the reference voltage to the first critical node and before applying the charge to the second critical node.

10. A sense amplifier comprising: A first latch transistor comprising: a first terminal of the first latch transistor coupled to the top node; a second terminal of the first latch transistor coupled to a first critical node; and a third terminal of the first latch transistor coupled to a second critical node, wherein the first latch transistor is configured to supply a first reference voltage from the top node to the first critical node through the first latch transistor when the second critical node is about to receive a first charge from one or more memory cells corresponding to the sense amplifier for readout, and the first reference voltage is used to interpret a first logic value of the first charge; A second latch transistor comprising: a first terminal of the second latch transistor coupled to the top node; a second terminal of the second latch transistor coupled to the second critical node; and a third terminal of the second latch transistor coupled to the first critical node, wherein the second latch transistor is configured to supply a second reference voltage from the top node to the second critical node through the second latch transistor when the first critical node is about to receive a second charge from the one or more memory cells corresponding to the sense amplifier for readout, and the second reference voltage is used to interpret a second logic value of the second charge; a first precharge transistor configured to precharge the first critical node to a voltage level; and A second precharge transistor is configured to precharge the second critical node to the voltage level.

11. The sense amplifier of claim 10, wherein precharging the first critical node to the voltage level and precharging the second critical node to the voltage level occur before charging the first critical node with the first reference voltage and charging the second critical node with the first charge.

12. The sense amplifier of claim 10, wherein precharging the first critical node to the voltage level and precharging the second critical node to the voltage level occur before charging the second critical node with the second reference voltage and charging the first critical node with the second charge. 13 . The sense amplifier of claim 10 , wherein the first latch transistor comprises a first PMOS transistor, and the second latch transistor comprises a second PMOS transistor.

14. The sense amplifier according to claim 10, comprising: a first compensation transistor configured to selectively couple together the second and third terminals of the first latch transistor during threshold voltage compensation; a second compensation transistor configured to selectively decouple the first latch transistor from the first critical node during threshold voltage compensation; a third compensation transistor configured to selectively couple together the second and third terminals of the second latch transistor during threshold voltage compensation; and A fourth compensation transistor is configured to selectively decouple the second latch transistor from the second critical node during threshold voltage compensation.

15. The sense amplifier of claim 14, wherein a single control signal is used to control the first, second, third, and fourth compensation transistors, the first and third compensation transistors having a first doping type, and the second and fourth compensation transistors having a second doping type different from the first doping type.

16. The sense amplifier of claim 14, wherein the first, second, third, and fourth compensation transistors are all of the same doping type, a first control signal is used to control the first and third compensation transistors, and a second control signal is used to control the second and fourth compensation transistors.

17. A memory device comprising: one or more memory cells configured to store data; a pair of digit lines coupled to the one or more memory cells; and a sense amplifier coupled to the digital line pair and comprising: a cross-coupled transistor coupled to the first node; a first critical node coupled to a first transistor of the cross-coupled transistors, wherein the first critical node corresponds to a first digit line of the digit line pair and the first transistor is configured to supply a first reference voltage to the first critical node; a second critical node coupled to a second transistor of the cross-coupled transistors, wherein the second critical node corresponds to a second digit line of the digit line pair and the second transistor is configured to supply a second reference voltage to the second critical node; a third transistor coupled to the first critical node; a fourth transistor coupled to the second critical node; a first isolation transistor coupled between the first digit line and the first critical node to selectively decouple the first digit line from the first critical node when amplifying a voltage on the first or second critical node; a second isolation transistor coupled between the second digit line and the second critical node to selectively decouple the second digit line from the second critical node while amplifying the voltages on the first and second critical nodes; a first compensation transistor configured to selectively couple the first transistor in a diode configuration by coupling the gate and drain terminals of the first transistor during voltage threshold compensation; a second compensation transistor configured to selectively decouple the first transistor from the first critical node during voltage threshold compensation; a third compensation transistor configured to selectively couple the second transistor in a diode configuration by coupling the gate and drain terminals of the second transistor during voltage threshold compensation; and A fourth compensation transistor is configured to selectively decouple the second transistor from the second critical node during voltage threshold compensation.

18. The memory device of claim 17, wherein the first and second transistors comprise PMOS transistors.

19. The memory device of claim 17, wherein the threshold voltage compensation comprises: charging the first critical node to a first charge level proportional to a threshold voltage of the first transistor; and The second critical node is charged to a second charge level proportional to a threshold voltage of the second transistor.

20. The memory device of claim 17, wherein threshold voltage compensation occurs when a word line voltage in the memory device is ramped up.

21. The memory device of claim 17, comprising a first precharge transistor coupled to the first critical node and configured to charge the first critical node to a voltage level as part of a precharge.

22. The memory device of claim 21, comprising a second precharge transistor coupled to the second critical node and configured to charge the second critical node to the voltage level as part of the precharge.

23. The memory device of claim 22, wherein the voltage level comprises 0V.

Images