Bias current generation circuit

Abstract

Embodiments of this disclosure provide a bias current generating circuit, comprising: a current generating circuit, a current mirror circuit, a charge control circuit, and first and second transistors. The current generating circuit generates a first current. When a sleep indicator signal is at an active level, the first current equals a first value. When the sleep indicator signal is at an inactive level, the first current equals a second value. The first value is less than the second value. The current mirror circuit generates a second current based on the first current. The charge control circuit provides the second current to the second terminal of the first transistor, stores charge from the second current when the sleep indicator signal is at an active level, and provides the stored charge to the control terminal of the first transistor when the sleep indicator signal is at an inactive level. The control terminal and the second terminal of the first transistor are coupled to the control terminal of the second transistor. The first terminal of the first transistor is coupled to a second voltage terminal and the first terminal of the second transistor. The second terminal of the second transistor is coupled to the output terminal of the bias current generating circuit.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to bias current generation circuits. Background Technology

[0002] DC-DC (Direct-to-Direct-to-Direct-Time) converters are commonly used in various electronic devices for DC-DC voltage conversion. In light-load mode, to improve efficiency, some internal circuits need to be switched to low-power mode or even shut down to reduce quiescent current and thus improve efficiency. When switching from light-load to heavy-load mode, these shut-down circuits need to be woken up, and circuits in low-power mode need to be switched back to normal high-current mode. The quiescent current of some circuits in a DC-DC converter can be controlled by a bias current generation circuit. However, the output of existing bias current generation circuits cannot quickly switch from low current to high current, resulting in a large drop in the load transient response of the DC-DC converter. Summary of the Invention

[0003] The embodiments described herein provide a bias current generating circuit.

[0004] According to a first aspect of this disclosure, a bias current generating circuit is provided. The bias current generating circuit includes: a current generating circuit, a current mirror circuit, a charge control circuit, a first transistor, and a second transistor. The current generating circuit is configured to: generate a first current under the control of a sleep indicator signal and provide the first current to the current mirror circuit via a first node. When the sleep indicator signal is at an active level, the first current equals a first value. When the sleep indicator signal is at an inactive level, the first current equals a second value. The first value is less than the second value. The current mirror circuit is configured to: generate a second current based on the first current and provide the second current to the charge control circuit via a second node. The second current is proportional to the first current. The charge control circuit is configured to: provide the second current to the second terminal of the first transistor via a third node; store charge from the second current when the sleep indicator signal is at an active level; and provide the stored charge to the control terminal of the first transistor via the third node when the sleep indicator signal is at an inactive level. The control terminal of the first transistor is coupled to the second terminal of the first transistor and the control terminal of the second transistor. The first terminal of the first transistor is coupled to a second voltage terminal. The first terminal of the second transistor is coupled to the second voltage terminal. The second transistor's second terminal is coupled to the output of the bias current generation circuit.

[0005] In some embodiments of this disclosure, the charge control circuit includes: an energy storage circuit, a differential voltage control circuit, and an energy release control circuit. The energy storage circuit is configured to store charge from a second current. The differential voltage control circuit is configured to control the voltage of the second node to be higher than the voltage of the third node by means of the second current. The energy release control circuit is configured to short-circuit the second node and the third node when the sleep indicator signal is at an invalid level, so that the charge stored in the energy storage circuit is provided to the control electrode of the first transistor via the third node.

[0006] In some embodiments of this disclosure, the energy storage circuit includes a first capacitor. A first terminal of the first capacitor is coupled to a second node. A second terminal of the first capacitor is coupled to a second voltage terminal.

[0007] In some embodiments of this disclosure, the energy storage circuit includes a third transistor. The control electrode of the third transistor is coupled to a second node. The first and second electrodes of the third transistor are coupled to a second voltage terminal.

[0008] In some embodiments of this disclosure, the differential pressure control circuit includes a first resistor. A first end of the first resistor is coupled to a second node. A second end of the first resistor is coupled to a third node.

[0009] In some embodiments of this disclosure, the differential pressure control circuit includes a fourth transistor. The control electrode and second electrode of the fourth transistor are coupled to a second node. The first electrode of the fourth transistor is coupled to a third node.

[0010] In some embodiments of this disclosure, the energy release control circuit includes a first voltage-controlled switch. The controlled terminal of the first voltage-controlled switch is provided with a sleep indication signal. A first terminal of the first voltage-controlled switch is coupled to a second node. A second terminal of the first voltage-controlled switch is coupled to a third node.

[0011] In some embodiments of this disclosure, the bias current generating circuit further includes a fifth transistor. The control electrode of the fifth transistor is coupled to a third node. The first and second electrodes of the fifth transistor are coupled to a second voltage terminal.

[0012] In some embodiments of this disclosure, the bias current generating circuit further includes a second voltage-controlled switch and a third voltage-controlled switch. The controlled terminal of the second voltage-controlled switch is provided with a sleep indicator signal. A first terminal of the second voltage-controlled switch is coupled to a third node. A second terminal of the second voltage-controlled switch is coupled to the control electrode of a second transistor. The controlled terminal of the third voltage-controlled switch is provided with an inverted signal of the sleep indicator signal. A first terminal of the third voltage-controlled switch is coupled to the control electrode of the second transistor. A second terminal of the third voltage-controlled switch is coupled to a second voltage terminal.

[0013] In some embodiments of this disclosure, the bias current generating circuit further includes a supplementary charging circuit. The supplementary charging circuit is configured to provide supplementary charge to the charge control circuit via a second node during a predetermined time period starting from the start of the sleep indicator signal flipping to an active level.

[0014] In some embodiments of this disclosure, the power supply circuit includes: a sixth transistor, a fourth voltage-controlled switch, and a transient detection circuit. The control electrode of the sixth transistor is coupled to a first node. The first electrode of the sixth transistor is coupled to a first voltage terminal. The second electrode of the sixth transistor is coupled to a first terminal of the fourth voltage-controlled switch. The transient detection circuit is configured to output a transient indication signal at an effective level within a predetermined time period. The controlled terminal of the fourth voltage-controlled switch is provided with the transient indication signal. The second terminal of the fourth voltage-controlled switch is coupled to a second node.

[0015] In some embodiments of this disclosure, the transient detection circuit includes an inverter, a delay circuit, and a NOR gate. The input of the inverter is provided with a sleep indicator signal. The output of the inverter is coupled to the input of the delay circuit. An inverted signal of the sleep indicator signal is output from the output of the inverter. The delay circuit is configured to delay the inverted signal of the sleep indicator signal for a certain period of time before outputting it. The output of the delay circuit is coupled to the first input of the NOR gate. The second input of the NOR gate is provided with the sleep indicator signal. A transient indicator signal is output from the output of the NOR gate.

[0016] In some embodiments of this disclosure, the current generation circuit includes: an operational amplifier, a seventh transistor, an eighth transistor, a second capacitor, a second resistor, and a third resistor. The first input terminal of the operational amplifier is coupled to a reference voltage terminal. The second input terminal of the operational amplifier is coupled to the first terminal of the seventh transistor, the first terminal of the second resistor, and the first terminal of the third resistor. The output terminal of the operational amplifier is coupled to the first terminal of the second capacitor and the control terminal of the seventh transistor. The second terminal of the second capacitor is coupled to a second voltage terminal. The second terminal of the seventh transistor is coupled to a first node. The second terminal of the second resistor is coupled to the second terminal of the eighth transistor. The second terminal of the third resistor is coupled to the second voltage terminal. The control terminal of the eighth transistor is provided with a sleep indication signal. The first terminal of the eighth transistor is coupled to the second voltage terminal.

[0017] In some embodiments of this disclosure, the current mirror circuit includes a ninth transistor and a tenth transistor. The control electrode of the ninth transistor is coupled to the second electrode of the ninth transistor, the control electrode of the tenth transistor, and a first node. The first electrode of the ninth transistor is coupled to the first electrode of the tenth transistor and a first voltage terminal. The second electrode of the tenth transistor is coupled to a second node.

[0018] According to a second aspect of this disclosure, a bias current generating circuit is provided. The bias current generating circuit includes: a first transistor to a tenth transistor, a first voltage-controlled switch to a fourth voltage-controlled switch, a second capacitor, a second resistor, a third resistor, an operational amplifier, an inverter, a delay circuit, and a NOR gate. The control electrode of the first transistor is coupled to its second terminal, the second terminal of the first voltage-controlled switch, the first terminal of the second voltage-controlled switch, and the first electrode of the fourth transistor. The first electrode of the first transistor is coupled to a second voltage terminal. The control electrode of the second transistor is coupled to the second terminal of the second voltage-controlled switch. The first electrode of the second transistor is coupled to the second voltage terminal. The second electrode of the second transistor is coupled to the output terminal of the bias current generating circuit. The control electrode of the fifth transistor is coupled to the control electrode of the first transistor. The first and second electrodes of the fifth transistor are coupled to the second voltage terminal. A sleep indicator signal is provided at the controlled terminal of the second voltage-controlled switch. An inverted signal of the sleep indicator signal is provided at the controlled terminal of the third voltage-controlled switch. The first terminal of the third voltage-controlled switch is coupled to the control electrode of the second transistor. The second terminal of the third voltage-controlled switch is coupled to the second voltage terminal. The first input terminal of the operational amplifier is coupled to a reference voltage terminal. The second input terminal of the operational amplifier is coupled to the first terminal of the seventh transistor, the first terminal of the second resistor, and the first terminal of the third resistor. The output terminal of the operational amplifier is coupled to the first terminal of the second capacitor and the control terminal of the seventh transistor. The second terminal of the second capacitor is coupled to the second voltage terminal. The second terminal of the seventh transistor is coupled to the control terminal and the second terminal of the ninth transistor. The second terminal of the second resistor is coupled to the second terminal of the eighth transistor. The second terminal of the third resistor is coupled to the second voltage terminal. The control terminal of the eighth transistor is provided with a sleep indicator signal. The first terminal of the eighth transistor is coupled to the second voltage terminal. The first terminal of the ninth transistor is coupled to the first terminal of the tenth transistor and the first voltage terminal. The control terminal of the tenth transistor is coupled to the control terminal of the ninth transistor. The second terminal of the tenth transistor is coupled to the control terminal and the second terminal of the fourth transistor, the first terminal of the first voltage-controlled switch, the control terminal of the third transistor, and the second terminal of the fourth voltage-controlled switch. The first and second terminals of the third transistor are coupled to the second voltage terminal. The controlled terminal of the first voltage-controlled switch is provided with a sleep indicator signal. The control terminal of the sixth transistor is coupled to the control terminal of the ninth transistor. The first terminal of the sixth transistor is coupled to the first voltage terminal. The second terminal of the sixth transistor is coupled to the first terminal of the fourth voltage-controlled switch. The inverter's input is provided with a sleep indicator signal. The inverter's output is coupled to the input of a delay circuit. The inverted sleep indicator signal is output from the inverter's output. The delay circuit is configured to delay the output of the inverted sleep indicator signal for a specified period. The delay circuit's output is coupled to the first input of a NOR gate. The second input of the NOR gate is provided with the sleep indicator signal. The NOR gate's output is coupled to the controlled terminal of a fourth voltage-controlled switch.

[0019] According to a third aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes a bias current generating circuit as described in a first or second aspect of this disclosure.

[0020] According to a fourth aspect of this disclosure, a chip is provided. The chip includes the DC-DC converter described in a third aspect of this disclosure.

[0021] According to a fifth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a fourth aspect of this disclosure. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0023] Figure 1 This is an exemplary circuit diagram of a bias current generating circuit;

[0024] Figure 2 This is a schematic block diagram of a bias current generating circuit according to an embodiment of the present disclosure;

[0025] Figure 3 This is an exemplary circuit diagram of a bias current generating circuit according to an embodiment of the present disclosure;

[0026] Figure 4 This is another exemplary circuit diagram of a bias current generating circuit according to an embodiment of the present disclosure;

[0027] Figure 5 This is yet another exemplary circuit diagram of a bias current generating circuit according to an embodiment of the present disclosure;

[0028] Figure 6 This is yet another exemplary circuit diagram of a bias current generating circuit according to an embodiment of the present disclosure;

[0029] Figure 7 yes Figure 6 An exemplary circuit diagram of the transient detection circuit in the example;

[0030] Figure 8 This is a timing diagram of some signals used in a bias current generation circuit according to an embodiment of the present disclosure.

[0031] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0034] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0035] Figure 1 An exemplary circuit diagram of a bias current generating circuit 100 is shown. The bias current generating circuit 100 can be used to provide bias current to a DC-DC converter. Figure 1 The bias current generating circuit 100 shown includes: transistors Mn1, Mn2, Mn3, Mn4, Mp1, Mp2, operational amplifier A1, capacitor Cf1, resistor r1, and resistor r2. Figure 1 The equivalent parasitic capacitor Cr of transistors Mn3 and Mn4 is also shown.

[0036] The resistance of resistor r1 is much smaller than that of resistor r2. The sleep indicator signal S controls whether transistor Mn1 is turned on. During normal operation of the DC-DC converter (non-sleep period), the sleep indicator signal S is at an inactive level (high level), transistor Mn1 is turned on, and the current flowing through transistor Mn2 is equal to Vref / r1. Here, r1 represents the resistance of resistor r1. During the sleep period of the DC-DC converter, the sleep indicator signal S is at an active level (low level), transistor Mn1 is turned off, and the current flowing through transistor Mn2 is equal to Vref / r2. Here, r2 represents the resistance of resistor r2. Since r1 is much smaller than r2, the current flowing through transistor Mn2 during the sleep period (Vref / r2) is much smaller than the current flowing through transistor Mn2 during the non-sleep period (Vref / r1). Transistors Mp1 and Mp2 form a current mirror. The current flowing through transistor Mn2 is mirrored to transistor Mn3. Transistors Mn3 and Mn4 form a current mirror. The current flowing through transistor Mn3 is mirrored onto transistor Mn4. Transistors Mp1 and Mp2 can have the same width-to-length ratio. The width-to-length ratio of transistors Mn3 and Mn4 can be 1:k, so that the bias current Ibias_old output from transistor Mn4 is k times the current flowing through transistor Mn2.

[0037] Because of the parasitic capacitance (equivalent to capacitor Cr) between the gate and source of transistors Mn3 and Mn4, current is needed to charge capacitor Cr as the voltage across Cr switches from its steady-state value during the dormant period to its steady-state value during the non-dormant period. The larger the value of k, the larger the value of capacitor Cr, and the longer the charging time, resulting in a longer time for the bias current Ibias_old to reach steady state. This increases the settling time of the circuit using the bias current Ibias_old, causing the DC-DC converter to be unable to respond quickly enough to transients, leading to a drop in output voltage.

[0038] This disclosure proposes a bias current generation circuit designed to shorten the time for the bias current to reach a steady state, thereby facilitating the operation of the next stage circuit. Figure 2 A schematic block diagram of a bias current generating circuit 200 according to an embodiment of the present disclosure is shown. The bias current generating circuit 200 includes: a current generating circuit 210, a current mirror circuit 220, a charge control circuit 230, a first transistor M1, and a second transistor M2.

[0039] The current generation circuit 210 is coupled to the current mirror circuit 220 via a first node N1. The current generation circuit 210 is also coupled to a sleep indicator signal output terminal S. A sleep indicator signal S is output from the sleep indicator signal output terminal S. During the sleep period, the sleep indicator signal S is at an active level (e.g., low level). During the non-sleep period, the sleep indicator signal S is at an inactive level (e.g., high level). The current generation circuit 210 is configured to generate a first current I1 under the control of the sleep indicator signal S and provide the first current I1 to the current mirror circuit 220 via the first node N1. Wherein, when the sleep indicator signal S is at an active level, the first current I1 is equal to a first value. When the sleep indicator signal S is at an inactive level, the first current I1 is equal to a second value. The first value is less than the second value. In a further embodiment of this disclosure, the first value is much smaller than the second value. In one example of this disclosure, the ratio of the first value to the second value is less than 1 / 100.

[0040] The current mirror circuit 220 is coupled to the current generation circuit 210 via a first node N1. The current mirror circuit 220 is coupled to the charge control circuit 230 via a second node N2. The current mirror circuit 220 is configured to generate a second current I2 based on a first current I1 and provide the second current I2 to the charge control circuit 230 via the second node N2. The second current I2 is proportional to the first current I1. In some embodiments of this disclosure, the ratio of the second current I2 to the first current I1 is n, i.e., I2 = n × I1. n is greater than 0.

[0041] The charge control circuit 230 is coupled to the current mirror circuit 220 via the second node N2. The charge control circuit 230 is coupled to the second terminal of the first transistor M1 via the third node N3. The charge control circuit 230 is also coupled to the sleep indicator signal output terminal S. The charge control circuit 230 is configured to: provide a second current I2 to the second terminal of the first transistor M1 via the third node N3; store the charge from the second current I2 when the sleep indicator signal S is at an active level; and provide the stored charge to the control terminal of the first transistor M1 via the third node N3 when the sleep indicator signal S is at an inactive level.

[0042] The control electrode of the first transistor M1 is coupled to the second electrode of the first transistor M1 and the control electrode of the second transistor M2. The first electrode of the first transistor M1 is coupled to the second voltage terminal V2. The first electrode of the second transistor M2 is coupled to the second voltage terminal V2. The second electrode of the second transistor M2 is coupled to the output terminal of the bias current generating circuit 200. The bias current Ibias is output from the output terminal of the bias current generating circuit 200.

[0043] The first transistor M1 and the second transistor M2 form a current mirror. When the ratio of the width-to-length ratio of the second transistor M2 to that of the first transistor M1 is k, the ratio of the bias current Ibias to the second current I2 is also k, i.e., Ibias = k × I2. k is greater than 0.

[0044] exist Figure 2 In the example, the second voltage terminal V2 is grounded. The first transistor M1 and the second transistor M2 are NMOS transistors. Those skilled in the art will understand that, based on the above inventive concept... Figure 2 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 2 The examples shown have different settings.

[0045] During the sleep period, the sleep indicator signal S is at an active level, the bias current Ibias is a small current, and the charge control circuit 230 stores the charge from the second current I2. When switching to the non-sleep period, the sleep indicator signal S flips to an inactive level, and the charge control circuit 230 provides the stored charge to the control electrode of the first transistor M1. Since the speed of directly transferring charge to the capacitor is faster than the speed of current charging the capacitor, the parasitic capacitances of the first transistor M1 and the second transistor M2 can be charged quickly in this way, thereby causing the bias current Ibias to rise to a large current more quickly. In this way, the quiescent current of the DC-DC converter using the bias current Ibias remains unchanged during the sleep period, but the switching time from sleep mode to normal mode is greatly shortened, resulting in better transient response.

[0046] In some embodiments of this disclosure, the charge control circuit 230 may include: an energy storage circuit, a differential pressure control circuit, and an energy release control circuit.

[0047] The energy storage circuit is coupled to the second node N2. The energy storage circuit is configured to store the charge from the second current I2.

[0048] The differential pressure control circuit is coupled to the second node N2 and the third node N3. The differential pressure control circuit is configured to control the voltage of the second node N2 to be higher than the voltage of the third node N3 by means of a second current I2.

[0049] The energy release control circuit is coupled to the second node N2 and the third node N3. The energy release control circuit is configured to short-circuit the second node N2 and the third node N3 when the sleep indicator signal S is at an invalid level, so that the charge stored in the energy storage circuit is provided to the control electrode of the first transistor M1 via the third node N3.

[0050] The charge control circuit 230 can be implemented in various ways. Figure 3 and Figure 4 The examples show two exemplary implementations of the charge control circuit 230.

[0051] Figure 3 An exemplary circuit diagram of a bias current generating circuit 300 according to an embodiment of the present disclosure is shown. Figure 3 In the example, the energy storage circuit 331 includes a first capacitor C1. A first terminal of the first capacitor C1 is coupled to a second node N2. A second terminal of the first capacitor C1 is coupled to a second voltage terminal V2.

[0052] The differential pressure control circuit 333 includes a first resistor R1. The first end of the first resistor R1 is coupled to the second node N2. The second end of the first resistor R1 is coupled to the third node N3.

[0053] The energy release control circuit 332 includes: a first voltage-controlled switch K1. The controlled terminal of the first voltage-controlled switch K1 is provided with a sleep indication signal S. The first terminal of the first voltage-controlled switch K1 is coupled to a second node N2. The second terminal of the first voltage-controlled switch K1 is coupled to a third node N3.

[0054] The current generation circuit 310 includes: an operational amplifier A1, a seventh transistor M7, an eighth transistor M8, a second capacitor Cf1, a second resistor R2, and a third resistor R3. The first input terminal of operational amplifier A1 is coupled to a reference voltage terminal Vref. A reference voltage Vref is output from the reference voltage terminal Vref. The second input terminal of operational amplifier A1 is coupled to the first terminal of the seventh transistor M7, the first terminal of the second resistor R2, and the first terminal of the third resistor R3. The output terminal of operational amplifier A1 is coupled to the first terminal of the second capacitor Cf1 and the control terminal of the seventh transistor M7. The second terminal of the second capacitor Cf1 is coupled to a second voltage terminal V2. The second terminal of the seventh transistor M7 is coupled to a first node N1. The second terminal of the second resistor R2 is coupled to the second terminal of the eighth transistor M8. The second terminal of the third resistor R3 is coupled to the second voltage terminal V2. The control terminal of the eighth transistor M8 is provided with a sleep indicator signal S. The first terminal of the eighth transistor M8 is coupled to the second voltage terminal V2.

[0055] In some embodiments of this disclosure, the resistance value of the second resistor R2 is much smaller than the resistance value of the third resistor R3. In one example, the ratio of the resistance values ​​of the second resistor R2 to the third resistor R3 is less than 1 / 100.

[0056] The current mirror circuit 320 includes a ninth transistor M9 and a tenth transistor M10. The control electrode of the ninth transistor M9 is coupled to the second electrode of the ninth transistor M9, the control electrode of the tenth transistor M10, and the first node N1. The first electrode of the ninth transistor M9 is coupled to the first electrode of the tenth transistor M10 and the first voltage terminal V1. The second electrode of the tenth transistor M10 is coupled to the second node N2.

[0057] exist Figure 3 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1, the second transistor M2, the seventh transistor M7, and the eighth transistor M8 are NMOS transistors. The ninth transistor M9 and the tenth transistor M10 are PMOS transistors. The first input terminal of operational amplifier A1 is the non-inverting input terminal. The second input terminal of operational amplifier A1 is the inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 3 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 3 The examples shown have different settings.

[0058] Based on the virtual short characteristics of operational amplifiers, the voltages at the first and second input terminals of operational amplifier A1 are equal. Therefore, the voltage at the first terminal of the seventh transistor M7 is equal to the reference voltage Vref. During the sleep period, the sleep indicator signal S is low, the eighth transistor M8 is off, and the first current I1 flowing through the seventh transistor M7 is equal to Vref / R3. The second current I2 = n × I1 = n × Vref / R3. Since the sleep indicator signal S is low, the first voltage-controlled switch K1 is off, and the second current I2 charges the first capacitor C1. Due to the presence of the first resistor R1, the voltage at the second node N2 is higher than the voltage at the third node N3. As mentioned above, the bias current Ibias = k × I2, therefore Ibias = k × n × Vref / R3.

[0059] During the non-sleep period, the sleep indicator signal S is at a high level, the eighth transistor M8 is closed, and the first current I1 flowing through the seventh transistor M7 is equal to Vref / R2. The second current I2 = n × I1 = n × Vref / R2. Because the sleep indicator signal S is at a high level, the first voltage-controlled switch K1 is closed. At this time, the voltage of the second node N2 is higher than the voltage of the third node N3, and the charge stored on the first capacitor C1 is quickly transferred to the parasitic capacitances of the first transistor M1 and the second transistor M2. This causes the voltage of the third node N3 to rise rapidly, and the bias current Ibias is quickly established, eventually reaching Ibias = k × n × Vref / R2.

[0060] Figure 4 Another exemplary circuit diagram of a bias current generating circuit 400 according to an embodiment of the present disclosure is shown. Figure 4 and Figure 3 The difference lies in the internal structure of the energy storage circuit 431 and the differential pressure control circuit 433, which differs from the internal structure of the energy storage circuit 331 and the differential pressure control circuit 333. Figure 4In the example, the energy storage circuit 431 includes a third transistor M3. The control electrode of the third transistor M3 is coupled to the second node N2. The first and second electrodes of the third transistor M3 are coupled to the second voltage terminal V2. In this case, the parasitic capacitance of the third transistor M3 is used to store charge. The differential voltage control circuit 433 includes a fourth transistor M4. The control electrode and second electrode of the fourth transistor M4 are coupled to the second node N2. The first electrode of the fourth transistor M4 is coupled to the third node N3. The fourth transistor M4, connected in a diode configuration, is able to maintain a voltage at the second node N2 higher than the voltage at the third node N3 during the sleep period.

[0061] exist Figure 4 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1 to the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are NMOS transistors. The ninth transistor M9 and the tenth transistor M10 are PMOS transistors. The first input terminal of operational amplifier A1 is the non-inverting input terminal. The second input terminal of operational amplifier A1 is the inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 4 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 4 The examples shown have different settings.

[0062] In some embodiments of this disclosure, the first transistor M1 through the fourth transistor M4 are transistors of the same type. Thus, the parasitic capacitance of the third transistor M3 and the parasitic capacitances of the first transistor M1 and the second transistor M2 change synchronously with the process. Compared to Figure 3 The first capacitor C1 shown has a fixed capacitance value. Figure 4 The charge stored in the energy storage circuit 431 changes synchronously with the parasitic capacitance values ​​of the first transistor M1 and the second transistor M2, thereby transferring sufficient charge to the parasitic capacitors of the first transistor M1 and the second transistor M2. On the other hand, the threshold voltage of the fourth transistor M4 changes synchronously with the threshold voltages of the first transistor M1 and the second transistor M2, so that the charge stored in the energy storage circuit 431 can reflect the changes in the threshold voltages of the first transistor M1 and the second transistor M2, thus reducing the variation in the settling time of the bias current Ibias caused by process fluctuations.

[0063] In some embodiments of this disclosure, in order to enhance the noise immunity of the bias current Ibias, a filter capacitor can be added to the control electrode of the second transistor M2. The larger the size of the filter capacitor, the better the filtering effect. Figure 5 An exemplary circuit diagram of a bias current generating circuit 500 employing this implementation is shown. Figure 4 Based on the example, Figure 5 The bias current generating circuit 500 shown may further include a fifth transistor M5. The control electrode of the fifth transistor M5 is coupled to the third node N3. The first and second electrodes of the fifth transistor M5 are coupled to the second voltage terminal V2. The parasitic capacitor of the fifth transistor M5 can act as a filter capacitor.

[0064] In some embodiments of this disclosure, the fifth transistor M5 is also the same type of transistor as the first transistors M1 to the fourth transistors M4. Thus, the parasitic capacitance value of the fifth transistor M5 changes synchronously with the parasitic capacitance value of the third transistor M3, achieving better filtering performance without causing changes in the settling time of the bias current Ibias under different process technologies.

[0065] In some embodiments of this disclosure, the bias current generating circuit 200 may further include: a second voltage-controlled switch K2 and a third voltage-controlled switch K3. The second voltage-controlled switch K2 and the third voltage-controlled switch K3 are in... Figure 5 The example is shown. In this example, the controlled terminal of the second voltage-controlled switch K2 is provided with a sleep indicator signal S. The first terminal of the second voltage-controlled switch K2 is coupled to the third node N3. The second terminal of the second voltage-controlled switch K2 is coupled to the control electrode of the second transistor M2. The controlled terminal of the third voltage-controlled switch K3 is provided with an inverted signal SN of the sleep indicator signal S. The first terminal of the third voltage-controlled switch K3 is coupled to the control electrode of the second transistor M2. The second terminal of the third voltage-controlled switch K3 is coupled to the second voltage terminal V2.

[0066] During non-sleep periods, the sleep indicator signal S is at a high level, and its inverted signal SN is at a low level. At this time, the second voltage-controlled switch K2 is closed, and the third voltage-controlled switch K3 is open. The bias current Ibias is output normally.

[0067] During the sleep period, the sleep indicator signal S is at a low level, and its inverted signal SN is at a high level. At this time, the second voltage-controlled switch K2 is open, and the third voltage-controlled switch K3 is closed. The bias current Ibias is zero, enabling the downstream circuit to achieve lower quiescent current.

[0068] exist Figure 5 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1 to the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 are NMOS transistors. The ninth transistor M9 and the tenth transistor M10 are PMOS transistors. The first input terminal of operational amplifier A1 is the non-inverting input terminal. The second input terminal of operational amplifier A1 is the inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 5Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 5 The examples shown have different settings.

[0069] Furthermore, this disclosure also considers the case where the bias current Ibias switches rapidly between high-current and low-current modes. If the bias current Ibias switches back to low-current mode very quickly after switching from low-current mode to high-current mode, the charge stored in the charge control circuit 230 in high-current mode may not reach its maximum value. Thus, when switching back to low-current mode, the charge provided by the charge control circuit 230 to the control electrode of the first transistor M1 is insufficient, affecting the speed at which the bias current Ibias reaches its steady-state value.

[0070] To address this situation, embodiments of this disclosure propose increasing the speed at which charge is stored in the charge control circuit 230 after the bias current Ibias switches from a low-current mode to a high-current mode. Figure 6 An exemplary circuit diagram of a bias current generating circuit 600 according to this embodiment is shown. Figure 5 Based on the example, Figure 6 The bias current generating circuit 600 further includes a supplementary charge circuit 640. The supplementary charge circuit 640 is configured to provide supplementary charge to the charge control circuit 430 via the second node N2 during a predetermined time period starting from the start of the sleep indicator signal S flipping to an active level.

[0071] exist Figure 6 In the example, the power supply circuit 640 includes: a sixth transistor M6, a fourth voltage-controlled switch K4, and a transient detection circuit 641. The control electrode of the sixth transistor M6 is coupled to the first node N1. The first electrode of the sixth transistor M6 is coupled to the first voltage terminal V1. The second electrode of the sixth transistor M6 is coupled to the first terminal of the fourth voltage-controlled switch K4. The transient detection circuit 641 is configured to output a transient indication signal S1 at an active level during a predetermined time period starting from the transition of the sleep indication signal S to an active level. The controlled terminal of the fourth voltage-controlled switch K4 is provided with the transient indication signal S1. The second terminal of the fourth voltage-controlled switch K4 is coupled to the second node N2.

[0072] exist Figure 6 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1 to the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 are NMOS transistors. The sixth transistor M6, the ninth transistor M9, and the tenth transistor M10 are PMOS transistors. The first input terminal of operational amplifier A1 is the non-inverting input terminal. The second input terminal of operational amplifier A1 is the inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 6 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 6 The examples shown have different settings.

[0073] Figure 7 Show Figure 6 An exemplary circuit diagram of the transient detection circuit 641 is provided. In some embodiments of this disclosure, the transient detection circuit 641 includes: an inverter NG, a delay circuit 7411, and a NOR gate. The input of the inverter NG is provided with a sleep indicator signal S. The output of the inverter NG is coupled to the input of the delay circuit 7411. The inverted signal of the sleep indicator signal S is output from the output of the inverter NG. The delay circuit 7411 is configured to output the inverted signal of the sleep indicator signal S after a certain delay. The output of the delay circuit 7411 is coupled to the first input of the NOR gate. The second input of the NOR gate is provided with the sleep indicator signal S. A transient indicator signal S1 is output from the output of the NOR gate.

[0074] refer to Figure 8 The timing diagrams shown indicate that at time T1, the sleep indicator signal S flips to an inactive level (high level), and the bias current Ibias begins to build up. Because the charge control circuit rapidly transfers charge to the parasitic capacitors of the first transistor M1 and the second transistor M2, the build-up speed of the bias current Ibias is faster than... Figure 1 The bias current Ibias_old builds up faster. At time T2, the sleep indicator signal S toggles to an active level (low). (Reference) Figure 7 Due to the delay effect of the delay circuit 7411, the first input of the NOR gate is at a low level at this time, therefore the transient indication signal S1 is at a high level. After the delay period of the delay circuit 7411, the first input of the NOR gate flips to a high level, therefore the transient indication signal S1 flips to a low level. Figure 8 The duration for which the transient indicator signal S1 is at a high level is equal to the delay duration of the delay circuit 7411.

[0075] Since the transient indication signal S1 is at a high level for a period of time after time T2, therefore, during this period, Figure 6 When the fourth voltage-controlled switch K4 is closed, the current flowing through the sixth transistor M6, together with the second current I2, provides charge to the charge control circuit 430, thereby accelerating the charging speed and allowing the charge stored in the charge control circuit 430 to reach its maximum value more quickly.

[0076] Embodiments of this disclosure also provide a DC-DC converter. This DC-DC converter includes a bias current generation circuit according to embodiments of this disclosure.

[0077] Embodiments of this disclosure also provide a chip. This chip includes a DC-DC converter according to embodiments of this disclosure. This chip is, for example, a power management chip.

[0078] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer or smartphone.

[0079] In summary, the bias current generation circuit according to the embodiments of this disclosure can shorten the settling time when the bias current switches from a small current to a large current, achieving rapid switching between small and large currents. The DC-DC converter employing the bias current generation circuit according to the embodiments of this disclosure can shorten the settling time when switching from sleep mode to non-sleep mode without increasing additional quiescent current. Furthermore, the bias current generation circuit according to the embodiments of this disclosure also considers the influence of process technology on the bias current settling time, which can greatly reduce the variation in bias current settling time caused by process fluctuations. Accordingly, the settling time of the DC-DC converter according to the embodiments of this disclosure when switching from sleep mode to non-sleep mode is also less susceptible to the influence of process fluctuations.

[0080] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0081] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0082] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A bias current generation circuit, comprising: The current generation circuit, the current mirror circuit, the charge control circuit, the first transistor and the second transistor, The current generation circuit is configured to generate a first current under the control of a sleep indication signal and provide the first current to the current mirror circuit via a first node, wherein the first current equals a first value when the sleep indication signal is at an active level, and the first current equals a second value when the sleep indication signal is at an inactive level, the first value being less than the second value. The current mirror circuit is configured to generate a second current according to the first current and provide the second current to the charge control circuit via a second node, the second current being proportional to the first current. The charge control circuit is configured to provide the second current to a second electrode of the first transistor via a third node, store charges from the second current when the sleep indication signal is at the active level, and provide the stored charges to a control electrode of the first transistor via the third node when the sleep indication signal is at the inactive level. A control electrode of the first transistor is coupled to the second electrode of the first transistor and a control electrode of the second transistor, and a first electrode of the first transistor is coupled to a second voltage terminal. A first electrode of the second transistor is coupled to the second voltage terminal, and a second electrode of the second transistor is coupled to an output terminal of the bias current generation circuit.

2. The bias current generation circuit according to claim 1, wherein The charge control circuit includes an energy storage circuit, a differential voltage control circuit, and a discharge control circuit, The energy storage circuit is configured to store charges from the second current. The differential voltage control circuit is configured to control the voltage of the second node to be higher than the voltage of the third node by means of the second current. The discharge control circuit is configured to short the second node and the third node when the sleep indication signal is at the inactive level, so that the stored charges of the energy storage circuit are provided to the control electrode of the first transistor via the third node.

3. The bias current generation circuit according to claim 2, wherein The energy storage circuit includes a first capacitor, wherein a first terminal of the first capacitor is coupled to the second node, and a second terminal of the first capacitor is coupled to the second voltage terminal; or The energy storage circuit includes a third transistor, wherein a control electrode of the third transistor is coupled to the second node, and a first electrode and a second electrode of the third transistor are coupled to the second voltage terminal.

4. The bias current generation circuit according to claim 2, wherein The differential voltage control circuit includes a first resistor, wherein a first terminal of the first resistor is coupled to the second node, and a second terminal of the first resistor is coupled to the third node; or The differential voltage control circuit includes a fourth transistor, wherein a control electrode and a second electrode of the fourth transistor are coupled to the second node, and a first electrode of the fourth transistor is coupled to the third node.

5. The bias current generation circuit according to claim 2, wherein The discharge control circuit includes a first voltage-controlled switch, The first voltage-controlled switch is provided with the sleep indication signal at a controlled terminal, a first terminal of the first voltage-controlled switch is coupled to the second node, and a second terminal of the first voltage-controlled switch is coupled to the third node.

6. The bias current generation circuit according to any one of claims 1 to 5, further comprising: The fifth transistor, The control electrode of the fifth transistor is coupled to the third node, and the first electrode and the second electrode of the fifth transistor are coupled to the second voltage terminal.

7. The bias current generation circuit according to any one of claims 1 to 5, further comprising: The second voltage-controlled switch and the third voltage-controlled switch, The controlled terminal of the second voltage-controlled switch is provided with the sleep indication signal, the first terminal of the second voltage-controlled switch is coupled to the third node, and the second terminal of the second voltage-controlled switch is coupled to the control electrode of the second transistor. The controlled terminal of the third voltage-controlled switch is provided with the inverse signal of the sleep indication signal, the first terminal of the third voltage-controlled switch is coupled to the control electrode of the second transistor, and the second terminal of the third voltage-controlled switch is coupled to the second voltage terminal.

8. The bias current generation circuit according to any one of claims 1 to 5, further comprising: The power supply circuit, The power supply circuit is configured to provide supplemental charges to the charge control circuit via the second node within a predetermined time period starting from the sleep indication signal turning to the active level.

9. The bias current generation circuit of claim 8, wherein, The power supply circuit comprises a sixth transistor, a fourth voltage-controlled switch, and a transient detection circuit, The control electrode of the sixth transistor is coupled to the first node, the first electrode of the sixth transistor is coupled to a first voltage terminal, and the second electrode of the sixth transistor is coupled to the first terminal of the fourth voltage-controlled switch. The transient detection circuit is configured to output a transient indication signal at an active level within the predetermined time period. The controlled terminal of the fourth voltage-controlled switch is provided with the transient indication signal, and the second terminal of the fourth voltage-controlled switch is coupled to the second node.

10. A bias current generating circuit comprising: The first transistor to the tenth transistor, the first voltage-controlled switch to the fourth voltage-controlled switch, the second capacitor, the second resistor, the third resistor, the operational amplifier, the inverter, the delay circuit, or the NOR gate, The control electrode of the first transistor is coupled to the second electrode of the first transistor, the second terminal of the first voltage-controlled switch, the first terminal of the second voltage-controlled switch, and the first electrode of the fourth transistor, and the first electrode of the first transistor is coupled to a second voltage terminal. The control electrode of the second transistor is coupled to the second terminal of the second voltage-controlled switch, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the output terminal of the bias current generation circuit. The control electrode of the fifth transistor is coupled to the control electrode of the first transistor, and the first electrode and the second electrode of the fifth transistor are coupled to the second voltage terminal. The controlled terminal of the second voltage-controlled switch is provided with the sleep indication signal. The controlled terminal of the third voltage-controlled switch is provided with the inverse signal of the sleep indication signal, the first terminal of the third voltage-controlled switch is coupled to the control electrode of the second transistor, and the second terminal of the third voltage-controlled switch is coupled to the second voltage terminal. The first input terminal of the operational amplifier is coupled to a reference voltage terminal, the second input terminal of the operational amplifier is coupled to the first electrode of the seventh transistor, the first terminal of the second resistor, and the first terminal of the third resistor, and the output terminal of the operational amplifier is coupled to the first terminal of the second capacitor and the control electrode of the seventh transistor. The second terminal of the second capacitor is coupled to the second voltage terminal. The second electrode of the seventh transistor is coupled to the control electrode and the second electrode of the ninth transistor. a second end of the second resistor is coupled to a second terminal of the eighth transistor; a second end of the third resistor is coupled to the second voltage terminal; a control terminal of the eighth transistor is provided with the hibernate indication signal, a first terminal of the eighth transistor is coupled to the second voltage terminal; a first terminal of the ninth transistor is coupled to a first terminal of the tenth transistor and the first voltage terminal; a control terminal of the tenth transistor is coupled to a control terminal of the ninth transistor, a second terminal of the tenth transistor is coupled to a control terminal and a second terminal of the fourth transistor, a first terminal of the first voltage-controlled switch, a control terminal of the third transistor and a second terminal of the fourth voltage-controlled switch; a first terminal and a second terminal of the third transistor are coupled to the second voltage terminal; a controlled terminal of the first voltage-controlled switch is provided with the hibernate indication signal; a control terminal of the sixth transistor is coupled to a control terminal of the ninth transistor, a first terminal of the sixth transistor is coupled to the first voltage terminal, and a second terminal of the sixth transistor is coupled to a first terminal of the fourth voltage-controlled switch; an input terminal of the inverter is provided with the hibernate indication signal, an output terminal of the inverter is coupled to an input terminal of the delay circuit, and an inverted signal of the hibernate indication signal is output from the output terminal of the inverter; the delay circuit is configured to output the inverted signal of the hibernate indication signal after a period of time, and an output terminal of the delay circuit is coupled to a first input terminal of the NAND gate; a second input terminal of the NAND gate is provided with the hibernate indication signal, and an output terminal of the NAND gate is coupled to a controlled terminal of the fourth voltage-controlled switch.

Images