Pin naming verification method, system, and computer-readable storage medium

Abstract

The application provides a pin naming verification method, system and computer readable storage medium. The pin naming verification method comprises the following steps: storing information of a plurality of parts; running a to-be-verified circuit and generating a part pin report; comparing the part pin report with the stored information of the plurality of parts to confirm whether the pin naming of the parts in the to-be-verified circuit is correct; when the comparison shows that the part pin report is different from the stored information of the plurality of parts, it is confirmed that the pin naming of the parts in the to-be-verified circuit is incorrect; and when the comparison shows that the part pin report is the same as the stored information of the plurality of parts, it is confirmed that the pin naming of the parts in the to-be-verified circuit is correct. Therefore, the efficiency and accuracy of verifying the pin naming are improved.

Description

Technical Field

[0001] This application relates to the field of circuit design technology, and in particular to a method, system, and computer-readable storage medium for verifying pin naming. Background Technology

[0002] Typically, when naming chip pins in circuit design, pins performing bit operations are usually named with "N" as a suffix, while pins performing high-level bit operations are usually not named with "N" as a suffix. During circuit development, naming errors are prone to occur, leading to circuit modifications. Therefore, manual verification is necessary to minimize errors. However, manual verification is inefficient and prone to omissions or misjudgments. Therefore, a method is needed to accurately and quickly verify the correctness of chip pin names in a designed circuit. Summary of the Invention

[0003] In view of this, it is necessary to propose a method, system and computer-readable storage medium for verifying pin naming to solve the above problems.

[0004] This application proposes a method for verifying pin naming. The method includes: storing information of several components; running the circuit to be verified and generating a component pin report; comparing the component pin report with the stored information of several components to confirm whether the pin naming of the components in the circuit to be verified is correct; if the comparison shows that the component pin report is different from the stored information of several components, then the pin naming of the components in the circuit to be verified is incorrect; if the comparison shows that the component pin report is the same as the stored information of several components, then the pin naming of the components in the circuit to be verified is correct.

[0005] Furthermore, the method also includes, before running the circuit to be verified, detecting the components in the circuit to be verified and confirming whether there is any component information in the circuit to be verified that has not been preset and stored; when it is confirmed that there is any component information in the circuit to be verified that has not been preset and stored, then the information of the unpreset and unstored components is preset and stored according to the component list; when it is confirmed that all the components in the circuit to be verified have been stored, the circuit to be verified is run.

[0006] Furthermore, the method also includes the component pin report including the component pins and their names; when the component pins are named with a preset letter as a suffix, the signal transmitted by the pins is a first signal; when the component pins are not named with a preset letter as a suffix, the signal transmitted by the pins is a second signal.

[0007] Furthermore, the method also includes confirming whether the pin naming is correct based on the logic output mode of the component and the pin signal; when the signal transmitted by the input pin of the component is the same as the signal transmitted by the output pin, the logic output mode of the component is to perform in-direction logic output; when the signal transmitted by the input pin of the component is different from the signal transmitted by the output pin, the logic output mode of the component is to perform in-verse logic output.

[0008] Furthermore, the method also includes the following: when the logic output mode of the stored component is the same as the logic output mode of the component in the circuit to be verified, the pin naming of the component in the circuit to be verified is correct; when the logic output mode of the stored component is different from the logic output mode of the component in the circuit to be verified, the pin naming of the component in the circuit to be verified is incorrect.

[0009] Furthermore, the method also includes issuing a prompt when it is determined that the pin names of the components in the circuit to be verified are incorrect, indicating that the circuit to be verified needs to be modified.

[0010] This application also proposes a pin naming verification system, which is used to implement a pin naming verification method. The pin naming verification system includes: a storage module for pre-setting and storing information of several parts; a first running module for running the circuit to be verified and generating a part pin report; and a verification module for comparing the part pin report generated in the first running module with the information of several parts stored in the storage module.

[0011] Furthermore, the pin naming verification system also includes a second operation module; the second operation module is used to generate a parts list, which includes information on various parts.

[0012] Furthermore, when the storage module lacks component information in the circuit to be verified, the storage module obtains the missing component information from the second operating module and presets and stores it.

[0013] This application also proposes a computer-readable storage medium storing at least one computer instruction, which is loaded and executed by a processor to verify a pin-named method.

[0014] The pin naming verification method proposed in this application involves pre-setting and storing component information in a storage module, combining this with the operation of a first running module (which is also a second running module), and then using a detection module to determine whether the component's pin naming conforms to the preset information. Specifically, the first running module runs the circuit to be verified, generating a component pin report. The detection module then compares this report with the preset component specifications to determine if the pin naming is correct. Simultaneously, the component list generated by the second running module's program supplements the component information needed for verification. This improves the efficiency and accuracy of pin naming verification. Attached Figure Description

[0015] Figure 1 This is a flowchart of a pin naming verification method according to an embodiment of this application;

[0016] Figure 2 This is an architecture diagram of the pin naming verification system according to an embodiment of this application;

[0017] Figure 3 This is a schematic diagram of the structure of the verification system according to an embodiment of this application;

[0018] Figure 4 This is a schematic diagram of the structure of the first part in an embodiment of this application;

[0019] Figure 5 This is a schematic diagram of the structure of the second part in an embodiment of this application.

[0020] Explanation of main component symbols

[0021] Verification System 1

[0022] Storage Module 10

[0023] First running module 20

[0024] Second running module 30

[0025] Detection module 40

[0026] Memory 50

[0027] Processor 60

[0028] First part S1

[0029] First pin A

[0030] Second pin B

[0031] Second part S2

[0032] Third pin C

[0033] fourth pin D

[0034] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] The terms "first" and "second," etc., used in the specification and accompanying drawings of this application are used to distinguish different objects and not to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to such process, method, product, or apparatus.

[0038] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0039] This application proposes a method for verifying pin naming. This method generates a component pin report by running the circuit to be verified using the AllegroPCB Designer program. The component pin report includes the component's location, pins, and pin names. The component pin report is compared with preset component specifications to verify whether the pin names are correct. This method also supplements the verification process with a parts list generated by running the OrCAD program.

[0040] Generally, when a component's pin is named with an "N" suffix, the signal of that pin is a low-level signal. When a component's pin is not named with an "N" suffix, the signal of that pin is a high-level signal.

[0041] When both the input and output signals of a component are low-level or high-level signals, the component's logic output mode is a same-direction logic output. When the input and output signals of a component are different, for example, the output signal is low-level while the output signal is high-level, the component's logic output mode is an inverse logic output. Based on the component's logic output mode and the pin signals, it is possible to determine whether the pin names are correct.

[0042] Please see Figure 1 This is a flowchart illustrating a pin naming verification method according to an embodiment of this application. The method includes:

[0043] S101: Preset and store information for several parts.

[0044] In some embodiments, the preset component information may be the component's electrical specifications, including the component's input pins and corresponding output pins, as well as the component's logic output form (e.g., non-inverting logic output, inverting logic output).

[0045] S102: Confirm whether the information of all components in the circuit to be verified has been preset and stored.

[0046] When it is confirmed that there is information about a component in the circuit to be verified that has not been preset or stored, the information about that component is preset and stored according to the component list, and then S103 is executed.

[0047] Once it is confirmed that the components in the circuit to be verified have been stored, S104 is executed.

[0048] S103: Obtain information about the components in the circuit to be verified from the parts list, preset and store it, and then execute S104.

[0049] S104: Run the circuit to be verified and generate a component pin report, then execute S105.

[0050] In some embodiments, after the circuit to be verified is run by the program, a component pin report is generated. The component pin report includes the part number, location, pins, and pin names of the components in the circuit to be verified.

[0051] S105: Compare the component pin reports with the stored component information to confirm whether the component pin names in the circuit to be verified are correct.

[0052] If the component pin report differs from the stored component information, it is confirmed that the component pin name in the circuit to be verified is incorrect, and then S106 is executed.

[0053] If the component pin report matches the stored component information, it is confirmed that the component pin naming in the circuit to be verified is correct, and then S107 is executed.

[0054] S106: Issue a prompt to indicate that the circuit needs to be modified.

[0055] S107: Verification complete.

[0056] Please see Figure 2 This is an architecture diagram of a pin naming verification system 1 according to an embodiment of this application. Verification system 1 is used to execute a pin naming verification method. Verification system 1 includes a storage module 10, a first operation module 20, a second operation module 30, and a detection module 40.

[0057] The storage module 10 is used to preset and store information about several parts, and the stored part information can be used as a verification standard.

[0058] The first running module 20 can be a basic design toolkit, which contains a program to run the circuit to be verified. By running the circuit to be verified, a component pin report is generated, which is the information of the components in the circuit to be verified.

[0059] The second running module 30 can be OrCAD, which can generate a parts list including information on various parts. In some embodiments, when the storage module 10 lacks part information for the circuit to be verified, the part information can be obtained from the second running module 30 and preset and stored.

[0060] The detection module 40 includes a preset program for comparing the component pin report generated in the first running module 20 with the component information stored in the storage module 10, thereby detecting whether the naming of the component pins in the circuit to be verified is correct.

[0061] Please see Figure 3 This is a schematic diagram of the structure of the verification system 1 according to an embodiment of this application. In one embodiment, the verification system 1 includes a memory 50 and at least one processor 60. Those skilled in the art should understand that... Figure 3 The structure of the verification system 1 shown does not constitute a limitation of the embodiments of this application. The verification system 1 may also include more or fewer other hardware or software than shown, or different component arrangements.

[0062] In some embodiments, the verification system 1 includes a terminal capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions. Its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), programmable gate arrays (PGAs), digital processors, and embedded devices. In some embodiments, the memory 50 is used to store program code and various data. The memory 50 may include read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0063] In some embodiments, the at least one processor 60 may include an integrated circuit, such as a single-packaged integrated circuit or multiple integrated circuits with the same or different functions in their packages, including combinations of microprocessors, digital processing chips, graphics processors, and various control chips. The at least one processor 60 is the control unit of the verification system 1, executing various functions and processing data of the verification system 1 by running or executing programs or modules stored in the memory 50 and calling data stored in the memory 50, such as the operation of the first running module 20.

[0064] The integrated unit implemented as a software functional module described above can be stored in a computer-readable storage medium. This software functional module, stored in a storage medium, includes several instructions to cause a computer device (which may be a personal computer, terminal, or network device, etc.) or processor to execute portions of the methods described in the various embodiments of this application.

[0065] The memory 50 stores program code, and the at least one processor 60 can call the program code stored in the memory 50 to execute related functions. In one embodiment of this application, the memory 50 stores multiple instructions, which are executed by the at least one processor 60 to implement a pin naming verification method. Specifically, the specific implementation method of the at least one processor 60 for the above instructions can be found in [reference needed]. Figure 1 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0066] Please see Figure 4 This is a schematic diagram of the structure of the first component S1 in this embodiment. This embodiment uses the first component S1 as an example to illustrate the operation of the pin naming verification method.

[0067] In this embodiment, the first component S1 can be a Dual N-MOS component with part number DMN601DWK-7. The logic output mode of the first component S1 preset and stored in the storage module 10 is reverse logic output.

[0068] In this embodiment, the first component S1 includes a first pin A and a second pin B. The first pin A is an input port, and the second pin B is the corresponding output port of the first pin A. The first pin A is named CPLD_CPU_RST, and since the name does not contain the suffix "N", the signal of the first pin A is a high-level signal. The second pin B is named CPU1_RST_N, and since the name contains the suffix "N", the signal of the second pin B is a low-level signal. Therefore, it can be concluded that the logic output mode of the first component S1 is an inverted logic output.

[0069] Furthermore, the running result of the first component S1 is consistent with the component information stored in the storage module 10. By verifying the pin naming method, it can be concluded that the first pin A and the second pin B of the first component S1 are correctly named.

[0070] Please see Figure 5 This is a schematic diagram of the structure of the second component S2 in this embodiment. This embodiment uses the second component S2 as an example to illustrate the operation of the pin naming verification method.

[0071] In this embodiment, the second component S2 can be a GTL transceiver component with part number GTL2014PW. The logic output mode of the second component S2 preset and stored in the storage module 10 is the same-direction logic output.

[0072] In this embodiment, the second component S2 includes a third pin C and a fourth pin D. The third pin C is an input port, and the fourth pin D is the corresponding output port of the third pin C. The third pin C is named CPLD_CPU_PROCHOT, and since the name does not contain the suffix "N", the signal of the third pin C is a high-level signal. The fourth pin D is named LVC1_PROCHOT_R_N, and since the name contains the suffix "N", the signal of the fourth pin D is a low-level signal. Therefore, it can be concluded that the logic output mode of the second component S2 is an inverted logic output.

[0073] Furthermore, the operating result of the second component S2 is inconsistent with the component information stored in the storage module 10. By verifying the pin naming method, it can be concluded that the third pin C and the fourth pin D in the second component S2 are correctly named.

[0074] The program code and data used in the pin naming verification method proposed above can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above-described embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), or a random access memory (RAM).

[0075] The pin naming verification method proposed in this application involves pre-setting and storing component information in a storage module 10, and combining this with the operation of a first operating module 20 (i.e., a second operating module 30). A detection module 40 then determines whether the component's pin naming conforms to the preset information. Specifically, the first operating module 20 runs the circuit to be verified, generating a component pin report. The detection module 40 then compares this report with the preset component specifications to determine if the pin naming is correct. Simultaneously, the second operating module 30 generates a component list to supplement the required component information for verification. This improves the efficiency and accuracy of pin naming verification.

[0076] Those skilled in the art should recognize that the above embodiments are only used to illustrate this application and are not intended to limit this application. Any appropriate changes and variations made to the above embodiments within the essential spirit and scope of this application should fall within the scope of protection claimed in this application.

Claims

1. A method for verifying pin naming, characterized in that, The method includes: Stores information about several parts; Run the circuit to be verified and generate a component pin report; the component pin report includes the pins of the component and their names; when the pins of the component are named with a preset letter as a suffix, the signal transmitted by the pin is a first signal; when the pins of the component are not named with a preset letter as a suffix, the signal transmitted by the pin is a second signal. Based on the logic output method of the component and the signals of the pins, confirm whether the pin names are correct; when the signal transmitted by the input pin of the component is the same as the signal transmitted by the output pin, the logic output method of the component is to perform in-direction logic output; when the signal transmitted by the input pin of the component is different from the signal transmitted by the output pin, the logic output method of the component is to perform in-direction logic output. Compare the component pin reports with the stored information of the components to confirm whether the component pin names in the circuit to be verified are correct; If the comparison shows that the reported component pins are different from the stored information of the components, it is confirmed that the component pin names in the circuit to be verified are incorrect. If the comparison shows that the component pin report is the same as the information of the stored components, then the component pin naming in the circuit to be verified is confirmed to be correct.

2. The pin naming verification method as described in claim 1, characterized in that, The method further includes, before running the circuit to be verified, detecting the components in the circuit to be verified, and confirming whether there is any component information in the circuit to be verified that has not been preset and stored. When it is confirmed that there is information about a component in the circuit to be verified that has not been preset or stored, the information about the component that has not been preset or stored is preset and stored according to the component list. Once it is confirmed that all components in the circuit to be verified have been stored, the circuit to be verified is run.

3. The pin naming verification method as described in claim 1, characterized in that, The method further includes the following: when the logic output mode of the stored component is the same as the logic output mode of the component in the circuit to be verified, then the pin naming of the component in the circuit to be verified is correct. If the logic output mode of the stored component is different from the logic output mode of the component in the circuit to be verified, then the pin naming of the component in the circuit to be verified is incorrect.

4. The pin naming verification method as described in claim 1, characterized in that, The method further includes issuing a prompt when it is determined that the pin names of the components in the circuit to be verified are incorrect, prompting that the circuit to be verified needs to be modified.

5. A pin naming verification system, characterized in that, The pin naming verification system is used to implement the pin naming verification method as described in any one of claims 1 to 4; The pin naming verification system includes: A storage module is used to preset and store information about several parts; A first running module is used to run the circuit to be verified and generate a component pin report. The component pin report includes the pins of the component and their names. When the pins of the component are named with a preset letter as a suffix, the signal transmitted by the pin is a first signal. When the pins of the component are not named with a preset letter as a suffix, the signal transmitted by the pin is a second signal. A verification module is used to verify whether the pin names are correct based on the logic output mode of the component and the pin signals. When the signal transmitted by the input pin of the component is the same as the signal transmitted by the output pin, the logic output mode of the component is a same-direction logic output. When the signal transmitted by the input pin of the component is different from the signal transmitted by the output pin, the logic output mode of the component is a reverse logic output. The component pin report generated in the first running module is compared with the information of the plurality of components stored in the storage module.

6. The pin naming verification system as described in claim 5, characterized in that, The pin naming verification system also includes a second operation module; the second operation module is used to generate a parts list, which includes information on various parts.

7. The pin naming verification system as described in claim 6, characterized in that, When the storage module lacks component information in the circuit to be verified, the storage module obtains the missing component information from the second operating module and presets and stores it.

8. A computer-readable storage medium storing at least one computer instruction thereon, characterized in that, The computer instructions are loaded by the processor and executed using the pin naming verification method as described in any one of claims 1 to 4.

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