High-precision low-temperature drift reference circuit and application thereof

Abstract

The application discloses a kind of high-precision low-temperature drift reference circuit and application, it is related to reference voltage circuit technical field, the circuit includes first-order reference circuit and second-order compensation circuit, the second-order compensation circuit is connected with the first-order reference circuit, the second-order compensation circuit is used to linearly superimposed target voltage under low-temperature condition and high-temperature condition;The second-order compensation circuit includes the PNP tube Q3, the operational amplifier OP2, multiple polysilicon resistors, multiple NMOS tubes and multiple PMOS tubes with connection relationship;Solve the characteristics that reference voltage temperature drift of traditional first-order reference circuit output is not low enough, and the second-order compensation circuit that can generate linear target voltage is superimposed voltage that changes linearly when low temperature and high temperature condition, so as to realize in wide temperature range make the high-precision, low-temperature drift characteristics that reference voltage of overall circuit output has.

Description

Technical Field

[0001] This invention relates to the field of reference voltage circuit technology, and more specifically, to a high-precision, low-temperature drift reference circuit and its application. Background Technology

[0002] In high-performance integrated circuit systems, such as high-sensitivity current sensor chips, the junction temperature inside the chip varies greatly during operation. Therefore, in order to ensure that the reference voltage required inside has sufficiently good low temperature drift characteristics without affecting the chip's sensitivity performance, the provided reference voltage needs to have high accuracy and low temperature drift characteristics. Generally speaking, the source of the reference voltage is to achieve the above characteristics by connecting a reference circuit. However, traditional first-order temperature-compensated reference circuits mainly utilize the negative temperature characteristic of the transistor's emitter-junction voltage and the positive temperature characteristic of the difference between the emitter-junction voltages of two transistors. By processing the voltages with these two temperature characteristics, a zero temperature coefficient is achieved at a certain temperature. However, for other operating temperatures, such as -40℃ and 150℃, the reference voltage still exhibits voltage variation. Designing the temperature drift parameter to be less than 10ppm / °C is very difficult and costly. Summary of the Invention

[0003] The purpose of this invention is to provide a high-precision low-temperature drift reference circuit and its application to solve the problems existing in the above-mentioned background art.

[0004] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0005] In a first aspect, embodiments of this application provide a high-precision low-temperature drift reference circuit, including a first-order reference circuit and a second-order compensation circuit. The second-order compensation circuit is connected to the first-order reference circuit and is used to linearly superimpose the target voltage under low-temperature and high-temperature conditions.

[0006] The second-order compensation circuit includes a PNP transistor Q3 with interconnected components, an operational amplifier OP2, multiple polysilicon resistors, multiple NMOS transistors, and multiple PMOS transistors.

[0007] The beneficial effects of this invention are: due to the low voltage characteristic of the reference voltage output by the first-order reference circuit under low and high temperature conditions, the second-order compensation circuit, which can generate a linear target voltage, superimposes a voltage that changes linearly under low and high temperature conditions, thereby achieving high precision and low temperature drift characteristics of the reference voltage output by the overall circuit over a wide temperature range, ultimately meeting the power supply requirements of the system chip.

[0008] Based on the above technical solution, the present invention can be further improved as follows.

[0009] Furthermore, the above applies to the second-order compensation circuit:

[0010] The non-inverting input of operational amplifier OP2 is connected to a first-order reference circuit. The output of operational amplifier OP2 is connected sequentially to the gates of NMOS transistors MP2, MP5, and MP6. The inverting input of operational amplifier OP2 is connected to the drain of PMOS transistor MP2 and one end of polysilicon resistor R4, with the other end of polysilicon resistor R4 grounded. The drain of PMOS transistor MP5 is connected to the gates of NMOS transistors MN4, MN5, and MN5, and the drain of PMOS transistor MP6 is connected to the gates of NMOS transistors MN6, MN7, and MN7.

[0011] Furthermore, the above applies to the second-order compensation circuit:

[0012] The gates of PMOS transistors MP3, MP4, and MP7 are all connected to a first-order reference circuit. The drain of PMOS transistor MP3 is connected to the drains of NMOS transistors MN1, MN2, and MN6, respectively. The drain of PMOS transistor MP4 is connected to the gates of NMOS transistors MN3, MN3, and MN4, respectively. The drain of PMOS transistor MP7 is connected to the gates of NMOS transistors MN8, MN9, and MN9, respectively. The source of NMOS transistor MN1 is connected to the emitter of PNP transistor Q3. The base and collector of PNP transistor Q3 are both grounded. One end of polysilicon resistor R5 is connected to the first-order reference circuit, and the other end of polysilicon resistor R5 is connected to the emitter of PNP transistor Q3.

[0013] Furthermore, the above applies to the second-order compensation circuit:

[0014] The sources of PMOS transistors MP2, MP3, MP5, MP6, and MP7 are all connected to the power supply VDD terminal.

[0015] The sources of NMOS transistors MN2, MN3, MN4, MN5, MN6, MN7, MN8, and MN9 are all grounded.

[0016] Furthermore, the aforementioned first-order reference circuit includes a PMOS transistor MP1, a PNP transistor Q1, a PNP transistor Q2, polysilicon resistors R1, R2, and R3, a chopper operational amplifier OP1, and a notch filter NF1, wherein:

[0017] The base and collector of PNP transistor Q1 and the base and collector of PNP transistor Q2 are both grounded. The emitter of PNP transistor Q1 is connected to one end of polysilicon resistor R1 to form node VGN. The emitter of PNP transistor Q2 is connected to one end of polysilicon resistor R3. The other end of polysilicon resistor R3 is connected to one end of polysilicon resistor R2 to form node VGP. The other ends of polysilicon resistor R2 and polysilicon resistor R1 are both connected to the drain of PMOS transistor MP1 to form node VBG.

[0018] Furthermore, the non-inverting input terminal and the inverting input terminal of the chopper operational amplifier OP1 are connected to the node VGP terminal and the node VGN terminal, respectively. The clock input terminal of the chopper operational amplifier OP1 is connected to the externally input fch signal. The output terminal of the chopper operational amplifier OP1 is connected to the input terminal of the notch filter NF1. The clock input terminal of the notch filter NF1 is connected to the externally input fs signal. The output terminal of the notch filter NF1 is connected to the gate of the PMOS transistor MP1. The source of the PMOS transistor MP1 is connected to the power supply VDD terminal.

[0019] Furthermore, the VBG terminal of the above-mentioned node is connected to the non-inverting input terminal of the operational amplifier OP2 in the second-order compensation circuit, the VGP terminal of the node is connected to one end of the polysilicon resistor R5 in the second-order compensation circuit, and the gate of PMOS transistor MP1 is connected to the gate of PMOS transistor MP3, the gate of PMOS transistor MP4 and the gate of PMOS transistor MP7 in the second-order compensation circuit, respectively.

[0020] Furthermore, the reference voltage output by the aforementioned reference circuit is output through the node VBG terminal, and the voltage value output by the node VBG terminal is expressed by the first formula, which is:

[0021] V BG =( (kT / q)·ln(n)) / R3·(R2+R3)+V BE2 +I2·R2;

[0022] In the formula, V BG This represents the voltage output at node VBG, where k is a constant, T is the temperature, q is the calculated parameter, and V is the voltage value. BE2 R2 represents the emitter voltage of PNP transistor Q2, R3 represents the resistance of polysilicon resistor R2, n represents the area ratio of PNP transistor Q2 to PNP transistor Q1, I2 represents the current through polysilicon resistor R5, and I2·R2 represents the target voltage.

[0023] Furthermore, the aforementioned NMOS transistors MN2, MN3, MN4, MN5, MN6, MN7, MN8, and MN9 are each connected in parallel with multiple compensation circuits;

[0024] For each compensation circuit, the compensation circuit includes a compensation NMOS transistor and a switch, the drain of the compensation NMOS transistor is connected to the switch, and the source of the compensation NMOS transistor is grounded.

[0025] The beneficial effect of adopting the above-mentioned further scheme is that by connecting multiple switches in parallel at various NMOS current mirror positions and connecting the current branches of NMOS of different sizes in series, the ratio of the corresponding current mirror can be adjusted, thereby adjusting the temperature characteristics of the compensation current.

[0026] Secondly, embodiments of this application provide the application of a high-precision low-temperature drift reference circuit, as described in any of the first aspects, in system-on-a-chip power supply.

[0027] Compared with the prior art, the present invention has at least the following beneficial effects:

[0028] In this application, due to the insufficient temperature drift of the reference voltage output by the traditional first-order reference circuit, a second-order compensation circuit that can generate a linear target voltage is used to superimpose a voltage that varies linearly under low and high temperature conditions. This achieves high accuracy and low temperature drift characteristics of the overall circuit output reference voltage over a wide temperature range, ultimately meeting the power supply requirements of the system chip.

[0029] In this application, multiple switches are connected in parallel at various NMOS current mirror locations to connect the current branches of NMOS of different sizes in series, thereby adjusting the ratio of the corresponding current mirror and thus regulating the temperature characteristics of the compensation current. This makes the reference circuit in this solution more widely applicable to meet the needs of use under different temperature conditions. Attached Figure Description

[0030] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0031] Figure 1 This is a circuit schematic diagram of the reference circuit in an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram showing the connection between the reference circuit and the compensation circuit in an embodiment of the present invention;

[0033] Figure 3 This is a graph showing the voltage output by the first-order reference circuit in an embodiment of the present invention, the target voltage, and the relationship between the reference voltage and temperature. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0036] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0037] In the description of the embodiments of the present invention, "multiple" means at least two.

[0038] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0039] Example 1: This example provides a high-precision low-temperature drift reference circuit, including a first-order reference circuit and a second-order compensation circuit. The second-order compensation circuit is connected to the first-order reference circuit and is used to linearly superimpose the target voltage under low-temperature and high-temperature conditions.

[0040] In this application, the first-order reference circuit and the second-order compensation circuit are interconnected and together form the reference circuit. Based on the traditional first-order reference circuit, a novel second-order temperature compensation circuit (second-order compensation circuit) is introduced, which enables the output voltage of the first-order reference circuit to be linearly superimposed with a small voltage (target voltage) under low temperature and high temperature conditions, thereby achieving extremely low temperature drift.

[0041] The second-order compensation circuit includes a PNP transistor Q3 with interconnected components, an operational amplifier OP2, multiple polysilicon resistors, multiple NMOS transistors, and multiple PMOS transistors.

[0042] Optionally, the above applies to a second-order compensation circuit:

[0043] Specifically, see the connection diagram of the second-order compensation circuit. Figure 1 , Figure 1 The second-order temperature compensation circuit in this application is the same as the second-order compensation circuit in the present application. In this circuit, the non-inverting input of the operational amplifier OP2 is connected to the first-order reference circuit. The output of the operational amplifier OP2 is connected to the gates of NMOS transistors MP2, MP5, and MP6 in sequence. The inverting input of the operational amplifier OP2 is connected to the drain of the PMOS transistor MP2 and one end of the polysilicon resistor R4, and the other end of the polysilicon resistor R4 is grounded. The drain of the PMOS transistor MP5 is connected to the gates of NMOS transistors MN4, MN5, and MN5, and the drain of the PMOS transistor MP6 is connected to the gates of NMOS transistors MN6, MN7, and MN7.

[0044] Specifically, see the connection diagram of the second-order compensation circuit. Figure 1 In this circuit, the gates of PMOS transistors MP3, MP4, and MP7 are all connected to a first-order reference circuit. The drain of PMOS transistor MP3 is connected to the drains of NMOS transistors MN1, MN2, and MN6, respectively. The drain of PMOS transistor MP4 is connected to the gates of NMOS transistors MN3, MN3, and MN4, respectively. The drain of PMOS transistor MP7 is connected to the gates of NMOS transistors MN8, MN9, and MN9, respectively. The source of NMOS transistor MN1 is connected to the emitter of PNP transistor Q3. The base and collector of PNP transistor Q3 are both grounded. One end of polysilicon resistor R5 is connected to the first-order reference circuit, and the other end of polysilicon resistor R5 is connected to the emitter of PNP transistor Q3.

[0045] Specifically, see the connection diagram of the second-order compensation circuit. Figure 1 Among them, the sources of PMOS transistors MP2, MP3, MP5, MP6, and MP7 are all connected to the power supply VDD terminal; the sources of NMOS transistors MN2, MN3, MN4, MN5, MN6, MN7, MN8, and MN9 are all grounded.

[0046] Optionally, the above first-order reference circuit includes PMOS transistor MP1, PNP transistors Q1 and Q2, polysilicon resistors R1, R2, and R3, chopper operational amplifier OP1, and notch filter NF1. See the connection diagram of the first-order reference circuit. Figure 1 , Figure 1 The first-order temperature compensation reference circuit is the first-order reference circuit in this application.

[0047] In this configuration, the base and collector of PNP transistor Q1 and the base and collector of PNP transistor Q2 are both grounded. The emitter of PNP transistor Q1 is connected to one end of polysilicon resistor R1 to form node VGN. The emitter of PNP transistor Q2 is connected to one end of polysilicon resistor R3. The other end of polysilicon resistor R3 is connected to one end of polysilicon resistor R2 to form node VGP. The other ends of polysilicon resistor R2 and polysilicon resistor R1 are both connected to the drain of PMOS transistor MP1 to form node VBG.

[0048] Specifically, the non-inverting input terminal and the inverting input terminal of the chopper operational amplifier OP1 are connected to the node VGP terminal and the node VGN terminal, respectively. The clock input terminal of the chopper operational amplifier OP1 is connected to the externally input fch signal. The output terminal of the chopper operational amplifier OP1 is connected to the input terminal of the notch filter NF1. The clock input terminal of the notch filter NF1 is connected to the externally input fs signal. The output terminal of the notch filter NF1 is connected to the gate of the PMOS transistor MP1. The source of the PMOS transistor MP1 is connected to the power supply VDD terminal.

[0049] In this circuit, the VBG terminal of node VBG is connected to the non-inverting input terminal of operational amplifier OP2 in the second-order compensation circuit, the VGP terminal of node VGP is connected to one end of polysilicon resistor R5 in the second-order compensation circuit, and the gate of PMOS transistor MP1 is connected to the gates of PMOS transistor MP3, PMOS transistor MP4 and PMOS transistor MP7 in the second-order compensation circuit, respectively.

[0050] Optionally, in the absence of a second-order compensation circuit, the reference circuit output from the first-order reference circuit is output through node VBG, and the output voltage value can be expressed by the second formula, which is:

[0051] V BG =I1·(R2+R3)+V BE2 ;

[0052] In the formula, I1 = (V BE1 -V BE2 ) / R3, V BE1 -V BE2 = (kT / q)·ln(n), therefore, after transformation, the second formula can be expressed as: VBG =I1·(R2+R3)+V BE2 .

[0053] Specifically, due to the clamping effect of the chopper operational amplifier OP1, the voltage at node VGP and the voltage at node VGN are nearly equal, such as Figure 1 As shown, the current I1 flowing through the polysilicon resistor R3 can therefore be obtained, i.e., I1 = (V BE1 -V BE2 ) / R3 .

[0054] Optionally, the chopper operational amplifier OP1 introduced above achieves the function of eliminating offset voltage within one cycle by periodically switching the two input terminals and having a corresponding polarity switching circuit at the output terminal to ensure correct feedback polarity. This reduces the voltage error between the VGP and VGN nodes, preventing the output reference voltage from being affected. Then, it is filtered by the notch filter NF1 to suppress noise jitter at the output of the chopper operational amplifier, further achieving low-noise performance for the output reference voltage.

[0055] In this context, the polysilicon resistors R1 and R2 have equal resistance values. If the voltage at node VGP and node VGN are equal, then the current flowing through polysilicon resistors R1 and R2 is equal, meaning the current flowing through PNP transistors Q1 and Q2 is equal. Therefore, the voltage (V...) BE1 -V BE2 The value of ) can be represented as: V BE1 -V BE2 = (kT / q)·ln(n).

[0056] Specifically, n represents the ratio of the area of ​​PNP transistor Q2 to the area of ​​PNP transistor Q1, due to the voltage (V BE1 -V BE2 It exhibits a positive temperature characteristic, V BE2 Exhibiting negative temperature characteristics, the reference voltage after first-order temperature compensation can be obtained by designing the ratio n, the resistance value of polysilicon resistor R2, and the resistance value of polysilicon resistor R3. Experiments show that when only the first-order reference circuit exists, the reference voltage output at node VBG can exhibit zero temperature characteristics near 25°C. However, it will still change with temperature under low and high temperature conditions, and the absolute value of the reference voltage is less than that under the 25°C operating condition. Therefore, a second-order compensation circuit is introduced, as described below.

[0057] Optionally, the reference voltage output by the above reference circuit is output through the node VBG terminal, and the voltage value output by the node VBG terminal is expressed by the first formula, which is:

[0058] V BG=( (kT / q)·ln(n)) / R3·(R2+R3)+V BE2 +I2·R2;

[0059] In the formula, V BG This represents the voltage output at node VBG, where k is a constant, T is the temperature, q is the calculated parameter, and V is the voltage value. BE2 R2 represents the emitter voltage of PNP transistor Q2, R3 represents the resistance of polysilicon resistor R2, n represents the area ratio of PNP transistor Q2 to PNP transistor Q1, I2 represents the current through polysilicon resistor R5, and I2·R2 represents the target voltage.

[0060] Among them, the additional term compared with the first formula and the second formula is I2·R2, that is, I2·R2 is the target voltage of linear superposition; specifically, I2 represents the current through the polysilicon resistor R5, which is also the compensation current used in the second-order compensation circuit.

[0061] In practical implementation, the width-to-length ratios of PMOS transistors MP3, MP4, and MP7 are kept consistent, each being half the length of PMOS transistor MP1, and their gate terminals are connected to PMOS transistor MP1. If the current flowing through PMOS transistors MP3, MP4, and MP7 is Ip, then the current flowing through PMOS transistor MP1 is 2Ip. Since the currents flowing through PNP transistors Q1 and Q2 are equal, the current flowing through them is also Ip. Based on the working principle of the first-order reference circuit, the expression for the Ip current is approximately (V... BE1 -V BE2 R3 has a positive temperature characteristic. In actual use, PNP transistor Q3 is made the same as PNP transistor Q1. If the emitter voltage of PNP transistor Q3 is approximately equal to the voltages at nodes VGP and VGN, then the current flowing through PNP transistor Q3 is equal to that of PNP transistor Q1, i.e., I3 = Ip. Therefore, for the current flowing through NMOS transistor MN1, we have I3 - I2 = Ip - I4, i.e., I2 = I4. The current characteristic of I4 is also the compensation current characteristic in the second-order compensation circuit.

[0062] Specifically, considering the voltage clamping effect of operational amplifier OP2, the voltage at its inverting input terminal is the voltage at node VBG. Therefore, the current flowing through PMOS transistor MP2 is Ib = V. BG / R4, since the voltage at node VBG is the reference voltage, Ib can be approximated as a current that does not change with temperature relative to Ip. The width-to-length ratio of PMOS transistors MP5 and MP6 is the same as that of PMOS transistor MP2, and the gate terminals of PMOS transistors MP5 and MP6 are connected to PMOS transistor MP2. Therefore, the current flowing through PMOS transistors MP5 and MP6 is also Ib.

[0063] Among them, NMOS transistors MN2 and MN3 form a current mirror with a current ratio of K1, i.e., (W / L)2 / (W / L)3=K1; NMOS transistors MN4 and MN5 form a current mirror with a current ratio of K2, i.e., (W / L)4 / (W / L)5=K2; therefore, the current flowing through NMOS transistor MN3 is Ip-K2Ib, but when K2Ib is greater than Ip, the current flowing through MN3 is 0. Therefore, the expression for the current flowing through NMOS transistor MN2 can be: I5= K1(Ip-K2Ib), Ip-K2Ib≥0 / I5= 0, Ip-K2Ib<0.

[0064] Specifically, since Ip exhibits a positive temperature characteristic, I5 = 0 at low temperatures. When the temperature is sufficiently high, such that Ip - K2Ib ≥ 0, I5 begins to increase with increasing temperature. NMOS transistors MN6 and MN7 also form a current mirror with a current ratio of K3, i.e., (W / L)6 / (W / L)7 = K3. Similarly, NMOS transistors MN8 and MN9 form a current mirror with a current ratio of K4, i.e., (W / L)8 / (W / L)9 = K4. See [link to relevant documentation]. Figure 1 Therefore, the current flowing through NMOS transistor MN8 is Ib-K4Ip. However, when K4Ip is greater than Ib, the current flowing through MN8 is 0. So the expression for the current flowing through NMOS transistor MN6 is: I6= K3(Ib-K4Ip), Ib-K4Ip≥0 / I5= 0, Ib-K4Ip<0. Since Ip has a positive temperature characteristic, under high temperature conditions, I6=0. When the temperature is low enough that Ib-K4Ip≥0, I6 begins to increase as the temperature decreases.

[0065] Specifically, a comparison of the first and second formulas above shows that the reference voltage output by the reference circuit in this application is the sum of the voltage output by the first-order reference circuit and the target voltage obtained by multiplying I2 and the polysilicon resistor R2 in the second-order compensation circuit; specifically, as shown... Figure 3 As shown, in Figure 3 In the diagram, the first image on the left shows the relationship between the voltage output of the first-order reference circuit and the temperature, while the second image on the left shows the relationship between the target voltage compensated by the second-order compensation circuit and the temperature. Therefore, by superimposing the voltages in the first and second images on the left, we can obtain the voltage-temperature relationship diagram shown in the third image on the left. It can be seen that the first-order reference circuit has a high voltage under intermediate temperature conditions and a low voltage under low and high temperature conditions. The compensation voltage has a linear change under low and high temperature conditions and a voltage of 0 under intermediate temperature conditions. By superimposing the two, high accuracy of the reference voltage and low temperature drift characteristics are achieved over a wide temperature range.

[0066] Optionally, the above-mentioned NMOS transistors MN2, MN3, MN4, MN5, MN6, MN7, MN8 and MN9 are each connected in parallel with multiple compensation circuits;

[0067] For each compensation circuit, the compensation circuit includes a compensation NMOS transistor and a switch, the drain of the compensation NMOS transistor is connected to the switch, and the source of the compensation NMOS transistor is grounded.

[0068] Since I4 = I5 + I6, the temperature characteristic of the compensation current in the second-order compensation circuit is as follows: at lower temperatures, the current gradually decreases to 0 with increasing temperature; at intermediate temperatures, the current remains 0; and at higher temperatures, the current gradually increases from 0 with increasing temperature. The magnitude of the current change with temperature, and the inflection point when the current switches to 0 at low and high temperatures, can be adjusted by designing K1, K2, K3, and K4. Preferably, the adjustment of K1, K2, K3, and K4 can be achieved through a modification scheme of the compensation circuit, such as... Figure 2 As shown, the temperature characteristics of the compensation current are adjusted by connecting multiple switches in parallel at various NMOS current mirror locations and connecting current branches of NMOS with different sizes in series to adjust the ratio of the current mirrors; specifically, as... Figure 1 and Figure 2 As shown, with Figure 1 and Figure 2 Using I4, I5, and I6 as reference points in the two diagrams, it is clear that two identical compensation circuits are connected in parallel in each of the NMOS transistors MN2, MN3, MN4, MN5, MN6, MN7, MN8, and MN9. The on / off state of the corresponding compensation circuit is controlled by each switch, thereby achieving the purpose of adjusting K1, K2, K3, and K4.

[0069] Example 2: This application provides the application of a high-precision low-temperature drift reference circuit as described in any of Examples 1 in the power supply of a system chip.

[0070] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high precision low temperature drift reference circuit, characterized by, It includes a first-order reference circuit and a second-order compensation circuit, wherein the second-order compensation circuit is connected to the first-order reference circuit, and the second-order compensation circuit is used to linearly superimpose the target voltage under low temperature conditions and high temperature conditions; The second-order compensation circuit includes a PNP transistor Q3, an operational amplifier OP2, multiple polysilicon resistors, multiple NMOS transistors, and multiple PMOS transistors connected in a specific order; in the second-order compensation circuit: The non-inverting input of operational amplifier OP2 is connected to the reference voltage output node VBG of the first-order reference circuit. The output of operational amplifier OP2 is sequentially connected to the gates of NMOS transistors MP2, MP5, and MP6. The inverting input of operational amplifier OP2 is connected to the drain of PMOS transistor MP2 and one end of polysilicon resistor R4, with the other end of polysilicon resistor R4 grounded. The drain of PMOS transistor MP5 is connected to the gates of NMOS transistors MN4, MN5, and MN5, and the drain of PMOS transistor MP6 is connected to the gates of NMOS transistors MN6, MN7, and MN8. In the second-order compensation circuit: The gates of PMOS transistors MP3, MP4, and MP7 are all connected to a first-order reference circuit to obtain a positive temperature characteristic current. The drain of PMOS transistor MP3 is connected to the drains of NMOS transistors MN1, MN2, and MN6, respectively. The drain of PMOS transistor MP4 is connected to the gates of NMOS transistors MN3, MN3, MN4, and MN2, respectively. The drain of PMOS transistor MP7 is connected to the gates of NMOS transistors MN8, MN9, and MN9, respectively. The source of NMOS transistor MN1 is connected to the emitter of PNP transistor Q3. The base and collector of PNP transistor Q3 are both grounded. One end of polysilicon resistor R5 is connected to the first-order reference circuit, and the other end of polysilicon resistor R5 is connected to the emitter of PNP transistor Q3. In the second-order compensation circuit: The sources of PMOS transistors MP2, MP3, MP5, MP6, and MP7 are all connected to the power supply VDD terminal. The sources of NMOS transistors MN2, MN3, MN4, MN5, MN6, MN7, MN8, and MN9 are all grounded.

2. The high-precision low-temperature drift reference circuit according to claim 1, characterized in that, The first-order reference circuit includes PMOS transistor MP1, PNP transistor Q1, PNP transistor Q2, polysilicon resistors R1, R2, and R3, chopper operational amplifier OP1, and notch filter NF1, wherein: The base and collector of the PNP transistor Q1 and the base and collector of the PNP transistor Q2 are both grounded. The emitter of the PNP transistor Q1 is connected to one end of the polysilicon resistor R1 to form the node VGN terminal. The emitter of the PNP transistor Q2 is connected to one end of the polysilicon resistor R3. The other end of the polysilicon resistor R3 is connected to one end of the polysilicon resistor R2 to form the node VGP terminal. The other ends of the polysilicon resistor R2 and the other ends of the polysilicon resistor R1 are both connected to the drain of the PMOS transistor MP1 to form the node VBG terminal.

3. The high-precision low-temperature drift reference circuit according to claim 2, characterized in that, The non-inverting input and inverting input of the chopper operational amplifier OP1 are connected to the node VGP and node VGN, respectively. The clock input of the chopper operational amplifier OP1 is connected to the externally input fch signal. The output of the chopper operational amplifier OP1 is connected to the input of the notch filter NF1. The clock input of the notch filter NF1 is connected to the externally input fs signal. The output of the notch filter NF1 is connected to the gate of the PMOS transistor MP1. The source of the PMOS transistor MP1 is connected to the power supply VDD.

4. The high precision low temperature drift reference circuit of claim 3, wherein, The node VBG terminal is connected to the non-inverting input terminal of the operational amplifier OP2 in the second-order compensation circuit, the node VGP terminal is connected to one end of the polysilicon resistor R5 in the second-order compensation circuit, and the gate of the PMOS transistor MP1 is connected to the gate of the PMOS transistor MP3, the gate of the PMOS transistor MP4 and the gate of the PMOS transistor MP7 in the second-order compensation circuit, respectively.

5. The high-precision low-temperature drift reference circuit according to claim 3, characterized in that, The reference voltage output by the reference circuit is output through the node VBG terminal. The voltage value output by the node VBG terminal is expressed by a first formula, which is: V BG = ((kT / q) - ln(n)) / R3 - (R2+R3) + V BE2 + I2 - R2; In the formula, V BG This represents the voltage output at node VBG, where k is a constant, T is the temperature, q is the calculated parameter, and V is the voltage value. BE2 R2 represents the emitter voltage of PNP transistor Q2, R3 represents the resistance of polysilicon resistor R2, n represents the area ratio of PNP transistor Q2 to PNP transistor Q1, I2 represents the current through polysilicon resistor R5, and I2·R2 represents the target voltage.

6. The high precision low temperature drift reference circuit of claim 1, wherein, The NMOS transistors MN2, MN3, MN4, MN5, MN6, MN7, MN8 and MN9 are each connected in parallel with multiple compensation circuits; For each of the compensation circuits, the compensation circuit includes a compensation NMOS transistor and a switch, the drain of the compensation NMOS transistor is connected to the switch, and the source of the compensation NMOS transistor is grounded.

7. The application of a high-precision low-temperature drift reference circuit as described in any one of claims 1-6 in system-on-a-chip power supply.

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