Slave control address allocation system and slave control address allocation method

Abstract

The present disclosure discloses a slave control address allocation system and a slave control address allocation method, which are applied to a distributed battery management system. The system includes: a master control; n slave controls, each slave control is connected to the master control via a system bus; the n slave controls are connected to each other via a DI port and a DO port, and the DO port of the nth slave control is connected to the DI port of the master control, where n is an integer greater than 1; wherein each of the n slave controls is configured to, in response to matching an acquired first signal with a preset signal, configure first address information corresponding to the first slave control, and send the first address information to the master control, and process the first signal to output a second signal, and send the second signal to a second slave control, so that the second slave control performs slave control address configuration based on the second signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of battery management, and in particular to a slave control address allocation method and system, electronic equipment, and medium. Background Art

[0002] During the use of a battery management system, the slave address assignment step is particularly important to ensure stable communication between the master and slave units. However, in related art, slave address assignment is performed using DIP switches, which is not only complex but also prone to erroneous modification due to human error, thus reducing the accuracy of slave address assignment. Summary of the Invention

[0003] The present disclosure provides a slave address allocation method and a slave address allocation system, an electronic device, a storage medium, and a computer program product.

[0004] According to one aspect of the present disclosure, a slave control address allocation system is provided, which is applied to a distributed battery management system, including: a master control; n slave controls, each slave control is connected to the master control via a system bus; the n slave controls are connected to each other via a DI port and a DO port, and the DO port of the nth slave control is connected to the DI port of the master control, where n is an integer greater than 1; wherein each of the n slave controls is configured to configure first address information corresponding to the first slave control in response to matching an acquired first signal with a preset signal, and send the first address information to the master control, and process the first signal to output a second signal, and send the second signal to the second slave control, so that the second slave control performs slave control address configuration based on the second signal.

[0005] According to an embodiment of the present disclosure, each slave control includes a first addressing circuit and a second addressing circuit; the first addressing circuit is configured to process the first signal in response to the acquired first signal matching the preset signal to obtain a third signal, and use the third signal to configure the first address information corresponding to the first slave control; the second addressing circuit is configured to generate a second signal based on a fourth signal obtained after the first addressing circuit uses the third signal for processing.

[0006] According to an embodiment of the present disclosure, the first addressing circuit includes: a Zener diode and a first chip capacitor; one end of the Zener diode and one end of the first chip capacitor are respectively connected between the DI port and the first end of the first chip resistor, and the other end of the Zener diode and the other end of the first chip capacitor are respectively connected to the ground; one end of the second chip capacitor, one end of the second chip resistor and the base of the first NPN transistor are respectively connected to the second end of the first chip resistor, and the other end of the second chip capacitor, the other end of the second chip resistor and the emitter of the first NPN transistor are respectively connected to the ground; the collector of the first NPN transistor is connected to one end of the third chip resistor and the DI microcontroller, and one end of the third chip resistor is connected to the power supply.

[0007] According to an embodiment of the present disclosure, the second addressing circuit includes: a DO microcontroller; one end of the fourth chip resistor is connected to the output end of the DO microcontroller, the other end of the fourth chip resistor is respectively connected to one end of the fifth chip resistor, one end of the second chip capacitor and the base of the second NPN transistor, the other end of the second chip capacitor and the emitter of the second NPN transistor are respectively connected to ground; the collector of the second NPN transistor is connected to one end of the sixth chip resistor and one end of the seventh chip resistor, the other end of the fifth chip resistor and the other end of the sixth chip resistor are respectively connected to the power supply; the other end of the seventh chip resistor is connected to the gate of the N-channel MOS tube and one end of the fourth chip capacitor, the source of the N-channel MOS tube and the other end of the fourth chip capacitor are grounded; the drain of the N-channel MOS tube is connected to one end of the eighth chip resistor and the DO port, and the other end of the eighth chip resistor is connected to the power supply.

[0008] According to an embodiment of the present disclosure, the preset signal is a low-level signal, the second signal is a low-level signal, the third signal is a high-level signal, and the fourth signal is a low-level signal.

[0009] According to another aspect of the present disclosure, a slave control address allocation method is provided, which is applied to a distributed battery management system. The method includes: in response to an acquired first signal matching a preset signal, configuring first address information corresponding to a first slave control, and sending the first address information to a master control; and processing the first signal to output a second signal, and sending the second signal to a second slave control, so that the second slave control performs slave control address configuration based on the second signal.

[0010] According to an embodiment of the present disclosure, the preset signal is a low-level signal, and the second signal is a low-level signal.

[0011] According to an embodiment of the present disclosure, the method further includes: in response to the acquired first signal not matching the preset signal, generating prompt information, the prompt information being used to prompt that the slave address configuration for the first slave has failed.

[0012] According to another aspect of the present disclosure, an electronic device is provided, comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors are enabled to execute the method described above.

[0013] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which executable instructions are stored. When the instructions are executed by a processor, the processor is caused to implement the method described above.

[0014] According to another aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements the method described above when executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0016] Figure 1 is a schematic diagram of a slave control address allocation system according to an embodiment of the present disclosure;

[0017] Figure 2 is a schematic diagram of a first addressing circuit according to an embodiment of the present disclosure;

[0018] Figure 3 is a schematic diagram of a second addressing circuit according to an embodiment of the present disclosure;

[0019] Figure 4 is a flow chart of a slave control address allocation method according to an embodiment of the present disclosure;

[0020] Figure 5 4 is a block diagram of an electronic device suitable for implementing a slave control address allocation method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The following will be combined with the embodiments of the present disclosure and the drawings in the embodiments to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0022] It should be noted that the sequence numbers of the operations in the following method are only used to indicate the operation for the purpose of description and should not be regarded as indicating the order in which the operations should be performed. Unless explicitly stated, the method does not need to be performed in the order shown.

[0023] Figure 1 Schematic diagram of a slave control address allocation system according to an embodiment of the present disclosure.

[0024] An embodiment of the present disclosure provides a slave control address allocation system applicable to a distributed battery management system.

[0025] like Figure 1 As shown, the slave address allocation system includes a master and n slaves, where n is an integer greater than 1. Each slave is connected to the master via a system bus, and the n slaves are connected to each other via DI ports and DO ports, with the DO port of the nth slave (i.e., slave n) being connected to the DI port of the master.

[0026] In the disclosed embodiment, each of the n slaves is configured to, in response to a match between an acquired first signal and a preset signal, configure first address information corresponding to the first slave and send the first address information to the master, and process the first signal to output a second signal, and send the second signal to a second slave so that the second slave performs slave address configuration based on the second signal. The second slave is the next slave of the first slave.

[0027] In an embodiment of the present disclosure, the preset signal is, for example, a low-level signal. After the first slave controller obtains the first signal, the first signal and the preset signal may be matched. If the first signal matches the preset signal, that is, the first signal is a low-level signal, the first address information corresponding to the first slave controller may be configured, and the first address information may be sent to the master controller via the system bus. If the acquired first signal does not match the preset signal, for example, the first signal is a high-level signal and is inconsistent with the preset signal, a prompt message may be generated, which may be used to prompt that the slave controller address configuration for the first slave controller has failed. At this point, the first slave controller may not be addressed, and may wait for the previous slave controller to be successfully addressed.

[0028] In an embodiment of the present disclosure, after processing the first signal, such as a low-level signal, the second signal output by the first slave is, for example, a low-level signal. In this way, the second slave can configure the slave address based on the second signal, and after the second address information corresponding to the second slave is configured, the second address information can be sent to the master via the system bus. In addition, the second slave can also process the second signal to output another second signal, and send the other second signal to another second slave, so that the other second slave performs the slave address configuration based on the other second signal. The other second slave is the next slave of the second slave, and the other second signal is, for example, a low-level signal. Similarly, using the above method, a "hand-in-hand" transmission addressing method can be used to transmit signals between n slaves to achieve addressing of each slave. After the master monitors that the addressing of the nth slave (i.e., slave n) is completed, the slave addressing process ends.

[0029] According to the embodiments of the present disclosure, compared with the solution of manual dialing in the related art, the technical solution of the present disclosure can automatically realize the addressing of all slave controls, thereby helping to avoid human errors in the slave control address allocation process, and further helping to improve the accuracy of slave control address allocation.

[0030] It should be noted that the aforementioned first slave controller can be, for example, any one of n slave controllers. When the first slave controller is the first of the n slave controllers (e.g., slave controller 1), since the DI port of the first slave controller is floating, the first slave controller does not receive any input signal. Therefore, the first signal to the first slave controller can be considered a low-level signal. In this way, the first slave controller can be address-configured based on the first signal.

[0031] According to an embodiment of the present disclosure, each slave controller includes a first addressing circuit and a second addressing circuit. The first addressing circuit is configured to, in response to a match between an acquired first signal and a preset signal, process the first signal to obtain a third signal, and use the third signal to configure first address information corresponding to the first slave controller. The second addressing circuit is configured to generate a second signal based on a fourth signal obtained by processing the third signal by the first addressing circuit. In the embodiment of the present disclosure, the third signal is, for example, a high-level signal, and the fourth signal is, for example, a low-level signal.

[0032] Figure 2 is a schematic diagram of a first addressing circuit according to an embodiment of the present disclosure, Figure 3 Schematic diagram of the second addressing circuit of the embodiment of the present disclosure. Figure 1 、 Figure 2 、 Figure 3 The structures of the first address allocation circuit and the second address allocation circuit and the slave control address allocation principle are illustrated.

[0033] like Figure 2As shown, the first addressing circuit includes, for example: a voltage regulator diode D2 and a first chip capacitor C4, one end of the voltage regulator diode D2 and one end of the first chip capacitor C4 are respectively connected between the DI port and the first end of the first chip resistor R16, and the other end of the voltage regulator diode D2 and the other end of the first chip capacitor C4 are respectively connected to ground; one end of the second chip capacitor C5, one end of the second chip resistor R19, and the base of the first NPN transistor Q3 are respectively connected to the second end of the first chip resistor R16, and the other end of the second chip capacitor C5, the other end of the second chip resistor R19, and the emitter of the first NPN transistor Q3 are respectively connected to ground; the collector of the first NPN transistor Q3 is connected to one end of the third chip resistor R13 and the DI microcontroller (DI MCU), and one end of the third chip resistor R13 is connected to the power supply.

[0034] See also Figure 3 The second addressing circuit includes, for example: a DO microcontroller (DO MCU), one end of the fourth chip resistor R17 is connected to the output terminal of the DO microcontroller, the other end of the fourth chip resistor R17 is respectively connected to one end of the fifth chip resistor R15, one end of the second chip capacitor C7, and the base of the second NPN transistor Q4, the other end of the second chip capacitor C7 and the emitter of the second NPN transistor Q4 are respectively connected to ground; the collector of the second NPN transistor Q4 is connected to one end of the sixth chip resistor R14 and one end of the seventh chip resistor R18, the other end of the fifth chip resistor R15 and the other end of the sixth chip resistor R14 are respectively connected to the power supply; the other end of the seventh chip resistor R18 is connected to the gate of the N-channel MOS transistor Q2 and one end of the fourth chip capacitor C6, the source of the N-channel MOS transistor Q2 and the other end of the fourth chip capacitor C6 are connected to ground; the drain of the N-channel MOS transistor Q2 is connected to one end of the eighth chip resistor R12 and the DO port, and the other end of the eighth chip resistor R12 is connected to the power supply.

[0035] Please refer to Figure 1 、 Figure 2 and Figure 3 Since the first slave controller (i.e., slave 1) is not connected to the DO port and is not receiving any input signals, the first signal to slave 1 can be considered a low-level signal. When the first addressing circuit processes a signal, the first NPN transistor Q3 is disconnected. At this point, the DI microcontroller (DI MCU) of slave 1 receives a high-level signal (i.e., the third signal). Slave 1 can then begin configuring its address information and send it to the master controller via the system bus.

[0036] In addition, the DO microcontroller (DO MCU) of slave 1 outputs a low-level signal (i.e., the fourth signal), turning off the second NPN transistor Q4 and turning on the N-channel MOS transistor Q2, causing the DO port to output a low-level signal (i.e., the second signal). Thus, after slave 1 sends the second signal to slave 2, slave 2 can continue configuring the slave address based on the second signal.

[0037] Similarly, using the above method, each of the n slaves in the slave address allocation system can automatically achieve address configuration. The slave addressing process ends when the master monitors the nth slave (i.e., slave n) and completes its addressing. In the disclosed embodiment, since each slave is assigned an address using a "hand-in-hand" transfer method, this separates the communication circuit between each slave and the master, ensuring that the two do not affect each other. This results in more reliable communication and a more accurate addressing process.

[0038] Furthermore, if the signal input to the DI port of the next slave controller is high during the previous slave controller's addressing process, the first NPN transistor Q3 in the next slave controller's first addressing circuit will turn on, and the DI microcontroller (DIMCU) of the next slave controller will input a low signal. Consequently, the next slave controller will not begin addressing. Only after the previous slave controller's addressing is successful will the next slave controller automatically perform addressing based on the first signal that matches the preset signal. For example, if the signal input to the DI port of slave controller 2 is high during the addressing process of slave controller 1, the first NPN transistor Q3 in the first addressing circuit of slave controller 2 will turn on, and the DI microcontroller (DI MCU) of slave controller 2 will input a low signal. Consequently, slave controller 2 will not begin addressing. Only after slave controller 1's addressing is successful will slave controller 2 automatically perform addressing based on the first signal that matches the preset signal.

[0039] Figure 4 4 is a flowchart of a slave control address allocation method according to an embodiment of the present disclosure.

[0040] like Figure 4 As shown, the slave address allocation method can be applied to a distributed battery management system, and the method includes operations S410 to S420.

[0041] In operation S410 , in response to the acquired first signal matching the preset signal, first address information corresponding to the first slave is configured and the first address information is sent to the master.

[0042] In operation S420 , the first signal is processed to output a second signal, and the second signal is sent to the second slave, so that the second slave performs slave address configuration based on the second signal.

[0043] According to an embodiment of the present disclosure, the above-mentioned preset signal may be, for example, a low-level signal. After the first slave controller obtains the first signal, the first signal and the preset signal may be matched. If the first signal matches the preset signal, that is, the first signal is a low-level signal, the first address information corresponding to the first slave controller may be configured, and the first address information may be sent to the master controller via the system bus. If the acquired first signal does not match the preset signal, for example, the first signal is a high-level signal and is inconsistent with the preset signal, a prompt message may be generated, which may be used to prompt that the slave controller address configuration for the first slave controller has failed. At this point, the first slave controller may not be addressed, and wait for the previous slave controller to be successfully addressed.

[0044] Based on the operating principle of the above-mentioned slave address allocation system, it can be seen that after processing the first signal, the second signal obtained can be, for example, a low-level signal. In other words, the second signal received by the second slave matches the preset signal. In this way, the second slave can configure the slave address based on the second signal, and after the second address information corresponding to the second slave is configured, the second address information can be sent to the master via the system bus. In addition, the second slave can also process the second signal to output another second signal, and send the other second signal to another second slave, so that the other second slave performs slave address configuration based on the other second signal. The second slave is the next slave of the first slave, the other second slave is the next slave of the second slave, and the other second signal is, for example, a low-level signal.

[0045] Similarly, using the above method, a "hand-in-hand" addressing method can be used to transmit signals between n slaves to achieve the addressing of each slave. The slave addressing process ends when the master monitors the addressing of the nth slave (i.e., slave n).

[0046] According to the embodiments of the present disclosure, based on the above-described method, all slave controllers can be automatically assigned addresses, thereby helping to avoid human errors in the slave address assignment process and thereby improving the accuracy of slave address assignment. In addition, because each slave controller is assigned an address using a "hand-in-hand" transfer method, this is separate from the communication circuit between each slave controller and the master controller, and the two do not affect each other, thereby making communication more reliable and the addressing process more accurate.

[0047] Figure 5 A block diagram of an electronic device suitable for implementing a slave control address allocation method according to an embodiment of the present disclosure is schematically shown.

[0048] like Figure 5As shown, the electronic device 500 according to an embodiment of the present disclosure includes a processor 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage unit 508 into a random access memory (RAM) 503. The processor 501 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 501 may also include onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to the embodiment of the present disclosure.

[0049] Various programs and data required for the operation of the electronic device 500 are stored in the RAM 503. The processor 501, ROM 502, and RAM 503 are connected to each other via a bus 504. The processor 501 executes the various operations of the method flow according to the embodiment of the present disclosure by executing the programs in the ROM 502 and / or RAM 503. It should be noted that the programs may also be stored in one or more memories other than the ROM 502 and RAM 503. The processor 501 may also execute the various operations of the method flow according to the embodiment of the present disclosure by executing the programs stored in the one or more memories.

[0050] According to an embodiment of the present disclosure, electronic device 500 may further include an input / output (I / O) interface 505, which is also connected to bus 504. Electronic device 500 may also include one or more of the following components connected to I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including devices such as a cathode ray tube (CRT), liquid crystal display (LCD), and speakers; a storage section 508 including a hard disk; and a communication section 509 including a network interface card such as a LAN card or modem. Communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to I / O interface 505 as needed. Removable media 511, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in drive 510 as needed, so that computer programs read from the removable media can be installed into storage section 508 as needed.

[0051] The present disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not be incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, and when executed, implements the method according to the embodiments of the present disclosure.

[0052] According to an embodiment of the present disclosure, a computer-readable storage medium may be a non-volatile computer-readable storage medium, and may include, for example, but not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present disclosure, a computer-readable storage medium may include the ROM 502 and / or RAM 503 described above, and / or one or more memories other than ROM 502 and RAM 503.

[0053] The embodiments of the present disclosure also include a computer program product, which includes a computer program containing program code for executing the method shown in the flowchart. When the computer program product is run in a computer system, the program code is used to enable the computer system to implement the slave control address allocation method provided by the embodiments of the present disclosure.

[0054] The computer program executes the above functions defined in the system / device of the embodiment of the present disclosure when the computer program is executed by the processor 501. According to the embodiment of the present disclosure, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0055] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal on a network medium, downloaded and installed via the communication portion 509, and / or installed from a removable medium 511. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0056] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 509, and / or installed from a removable medium 511. When the computer program is executed by the processor 501, the above-described functions defined in the system of the embodiment of the present disclosure are performed. According to the embodiment of the present disclosure, the systems, devices, means, modules, units, etc. described above can be implemented by computer program modules.

[0057] According to an embodiment of the present disclosure, the program code for executing the computer program provided by the embodiment of the present disclosure can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0058] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0059] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or couplings fall within the scope of the present disclosure.

[0060] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A slave control addressing system, applied to a distributed battery management system, comprising: Master control; n slave controls, each connected to the master control via a system bus; the n slave controls are sequentially connected in series via a DI port and a DO port, with the DI port of the first slave control being left floating so that a first signal for the first slave control is a low-level signal, and the DO port of the nth slave control is connected to the DI port of the master control, where n is an integer greater than 1; Among them, each first slave control of the n slave controls is configured to configure first address information corresponding to the first slave control in response to the acquired first signal being a low-level signal, and send the first address information to the master control, and process the first signal to output a second signal, and send the second signal to the second slave control, so that the second slave control performs slave control address configuration based on the second signal, the second slave control is the next slave control of the first slave control, and the second signal is a low-level signal.

2. The system according to claim 1, wherein: Each slave controller includes a first addressing circuit and a second addressing circuit; The first address allocation circuit is configured to, in response to the acquired first signal being a low-level signal, process the first signal to obtain a third signal, and use the third signal to configure first address information corresponding to the first slave control; The second addressing circuit is configured to generate the second signal according to a fourth signal obtained by processing the third signal by the first addressing circuit.

3. The system according to claim 2, wherein: The first addressing circuit includes: Voltage regulator and first chip capacitor; One end of the voltage regulator tube and one end of the first chip capacitor are respectively connected between the DI port and the first end of the first chip resistor, and the other end of the voltage regulator tube and the other end of the first chip capacitor are respectively connected to the ground; one end of the second chip capacitor, one end of the second chip resistor and the base of the first NPN transistor are respectively connected to the second end of the first chip resistor, and the other end of the second chip capacitor, the other end of the second chip resistor and the emitter of the first NPN transistor are respectively connected to the ground; the collector of the first NPN transistor is connected to one end of the third chip resistor and the DI microcontroller, and one end of the third chip resistor is connected to the power supply.

4. The system according to claim 2 or 3, wherein: The second addressing circuit includes: DO single-chip computer, one end of the fourth chip resistor is connected to the output terminal of the DO single-chip computer, the other end of the fourth chip resistor is respectively connected to one end of the fifth chip resistor, one end of the second chip capacitor, and the base of the second NPN transistor, and the other end of the second chip capacitor and the emitter of the second NPN transistor are respectively connected to ground; The collector of the second NPN transistor is connected to one end of the sixth chip resistor and one end of the seventh chip resistor, and the other end of the fifth chip resistor and the other end of the sixth chip resistor are respectively connected to a power supply; The other end of the seventh chip resistor is connected to the gate of the N-channel MOS tube and one end of the fourth chip capacitor, and the source of the N-channel MOS tube and the other end of the fourth chip capacitor are grounded; the drain of the N-channel MOS tube is connected to one end of the eighth chip resistor and the DO port, and the other end of the eighth chip resistor is connected to the power supply.

5. The system according to claim 4, wherein: The third signal is a high-level signal, and the fourth signal is a low-level signal.

6. A slave control addressing method, applicable to the slave control addressing system according to any one of claims 1 to 5, the method comprising: In response to the acquired first signal being a low-level signal, configuring first address information corresponding to the first slave controller, and sending the first address information to the master controller; as well as The first signal is processed to output a second signal, and the second signal is sent to a second slave control so that the second slave control performs slave control address configuration based on the second signal, wherein the second slave control is the next slave control of the first slave control, and the second signal is a low-level signal.

7. The method according to claim 6, further comprising: In response to the acquired first signal not being a low-level signal, prompt information is generated, where the prompt information is used to prompt that the slave address configuration for the first slave controller fails.

8. An electronic device comprising: one or more processors; a memory for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors are enabled to execute the method according to any one of claims 6 to 7.

9. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to perform the method according to any one of claims 6 to 7.

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