Five-port chip, chip system and data interaction method

Abstract

The application provides a five-port chip, comprising: a clock module, configured to form a synchronous clock according to an external clock input by a main clock port; a data input module, connected to an output end of the clock module, configured to receive configuration differential data input by a main data positive port and a main data negative port under control of the synchronous clock and convert the configuration differential data into configuration information and store the configuration information; a main module, connected to an output end of the data input module, configured to read the configuration information, perform chip configuration, and generate data to be transmitted under control of a system clock; and a data output module, connected to the output end of the clock module and the output end of the main module, configured to convert the data to be transmitted into differential data to be transmitted, and output the differential data to be transmitted through the main data positive port and the main data negative port in a set frame format based on the synchronous clock. The five-port chip provided by the application solves the problem of poor anti-interference capability of an existing image sensor chip in a data transmission process.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a five-port chip, chip system, and data interaction method. Background Technology

[0002] Image sensors are widely used in digital cameras, mobile phones, medical devices, automobiles and other applications to capture and identify optical image information of people or scenes and convert the optical image information into electrical signals.

[0003] Traditional image sensor chips have poor anti-interference capabilities because both clock and data are transmitted from one end. Therefore, how to improve the anti-interference capability during data transmission is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a five-port chip, a chip system and a data interaction method, which solves the problem of poor anti-interference capability of existing image sensor chips during data transmission.

[0005] To achieve the above and other related objectives, the present invention provides a five-port chip, powered by a main power port and a main ground port, and for data interaction via a main clock port, a main data positive port, and a main data negative port; the five-port chip includes:

[0006] A clock module is used to generate a synchronous clock based on an external clock input from the main clock port;

[0007] The data input module is connected to the output of the clock module and is used to receive the configuration differential data input from the main data positive port and the main data negative port under the control of the synchronization clock and convert it into configuration information for storage.

[0008] The main module is connected to the output of the data input module and is used to read the configuration information and configure the chip, and to generate the data to be transmitted under the control of the system clock.

[0009] The data output module is connected to the output of the clock module and the output of the main module. It is used to convert the data to be transmitted into differential data to be transmitted, and to output the differential data to be transmitted differentially through the main data positive port and the main data negative port in a set frame format based on the synchronous clock.

[0010] Optionally, the clock module is further configured to multiply the synchronous clock to generate a multiplied clock, and the data output module outputs the differential data to be transmitted under the control of the multiplied clock.

[0011] Optionally, the clock module is implemented using an adjustable frequency multiplier phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state.

[0012] Optionally, the main module is also connected to the output of the clock module to form the system clock based on the synchronization clock.

[0013] Optionally, the five-port chip includes an image sensor chip, and the data to be transmitted includes image data in the form of digital signals.

[0014] The present invention also provides a chip system, the chip system comprising:

[0015] The main chip adopts a five-port chip as described in any of the above items;

[0016] The slave chip has a slave clock port, a slave data positive port, and a slave data negative port, and the slave clock port, the slave data positive port, and the slave data negative port are correspondingly connected to the master clock port, the master data positive port, and the master data negative port for data interaction. It is used to provide the external clock and the configuration information to the master chip, and to receive the differential data to be transmitted output by the master chip.

[0017] Optionally, the slave chip includes:

[0018] A clock generation module is used to generate the external clock and output it through the clock port.

[0019] The data generation module is used to generate the configuration information and convert it into configuration differential data for differential output through the positive data port and the negative data port.

[0020] The data processing module is used to receive the differential data to be transmitted through the positive data port and the negative data port and convert it into the data to be transmitted.

[0021] Optionally, when the main chip includes an image sensor chip, the slave chip includes a processor chip.

[0022] This invention also provides a data interaction method for a chip system, the chip system including a master chip and a slave chip, wherein the master clock port, master data positive port, and master data negative port of the master chip are correspondingly connected to the slave clock port, slave data positive port, and slave data negative port of the slave chip for data interaction; the data interaction method includes:

[0023] The main chip receives the external clock sent by the slave chip through the main clock port and forms a synchronous clock;

[0024] Under the control of the synchronization clock, the master chip receives the configuration differential data sent by the slave chip through the master data positive port and the master data negative port, and converts the configuration differential data into configuration information;

[0025] The main chip is configured according to the configuration information;

[0026] The master chip converts the data to be transmitted into differential data to be transmitted, and outputs the differential data to be transmitted differentially to the slave chip through the master data positive port and the master data negative port under the set frame format based on the synchronization clock.

[0027] The slave chip receives the differential data to be transmitted through the slave data positive port and the slave data negative port and converts it into the data to be transmitted.

[0028] Optionally, the data interaction method further includes: after the main chip performs the chip configuration, it generates a frequency multiplier clock based on the synchronous clock, and outputs the differential data to be transmitted under the control of the frequency multiplier clock.

[0029] Optionally, the main chip generates the frequency-doubled clock based on an adjustable frequency-doubled phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state.

[0030] Optionally, after the chip sends the external clock, it sends the configuration information after a set time.

[0031] Optionally, after the master chip receives the frame start field sent by the slave chip, the master chip switches from receive mode to send mode, and at this time, the slave chip switches from send mode to receive mode; after the slave chip receives the frame end field sent by the master chip, the slave chip switches from receive mode to send mode, and at this time, the master chip switches from send mode to receive mode.

[0032] Optionally, the frame format setting includes several row fields, and each row field has the same format, including {start of row field, clock synchronization field, data field, clock synchronization field, end of row field}.

[0033] Optionally, the data field includes n bits; the frame start field includes 10n bits; the frame end field includes 10n bits; the line start field includes 3n bits; the line end field includes 3n bits; and the clock synchronization field includes 6n bits, where n is an integer greater than 1.

[0034] Optionally, the frame start field includes 100 bits, which are 5 sets of cyclic {11111111110000000000}; the frame end field includes 100 bits, which are 10 sets of cyclic {1111100000}; the line start field includes 30 bits, which are 3 sets of cyclic {0000000000}; the line end field includes 30 bits, which are 3 sets of cyclic {1111111111}; and the clock synchronization field includes 60 bits, which are 6 sets of cyclic {1010101010}.

[0035] As described above, the five-port chip, chip system and data interaction method of the present invention use a five-port chip to quantize the pixel signal and output it differentially at both ends using a master-slave handshake mechanism, thereby improving the anti-interference capability during data transmission and achieving stable data transmission frame rate through a small number of ports (five ports). Attached Figure Description

[0036] Figure 1 The diagram shown is a schematic of the five-port chip of this invention.

[0037] Figure 2 The diagram shown is a schematic of the chip system of the present invention.

[0038] Figure 3 The flowchart shown is a data interaction method of the present invention.

[0039] Component designation explanation

[0040] 100 Five-Port Chip / Main Chip

[0041] 101 Clock Module

[0042] 102 Data Input Module

[0043] 103 Main Module

[0044] 104 Data Output Module

[0045] 200 from chips

[0046] 201 Clock Generation Module

[0047] 202 Data Generation Module

[0048] 203 Data Processing Module Detailed Implementation

[0049] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] Please see Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0051] Example 1

[0052] like Figure 1 As shown, this embodiment provides a five-port chip 100, which is powered by the main power port VDD1 and the main ground port GND1, and performs data interaction through the main clock port SCL1, the main data positive port SDA1+ and the main data negative port SDA1-. The five-port chip 100 includes: a clock module 101, a data input module 102, a main module 103 and a data output module 104.

[0053] The clock module 101 is used to generate a synchronization clock SYN_CLK based on the external clock EXT_CLK input to the master clock port SCL1. Furthermore, the clock module 101 is also used to multiply the synchronization clock SYN_CLK to generate a multiplied clock MUL_CLK.

[0054] Specifically, the clock module 101 is implemented using an adjustable frequency multiplier phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state to maintain a constant frequency by keeping the phase difference constant, thereby obtaining a stable clock signal.

[0055] In practical applications, the frequency of the synchronization clock SYN_CLK is the same as the frequency of the external clock EXT_CLK, and the frequency of the frequency multiplier clock MUL_CLK is m times the frequency of the synchronization clock SYN_CLK, where m is a positive number greater than 1.

[0056] In one example, the initial frequency multiplication value of the phase-locked loop (PLL) circuit can be assumed to be 1. At this initial state, the PLL circuit multiplies the external clock EXT_CLK by 1 to generate the synchronization clock SYN_CLK. Alternatively, after chip configuration, the frequency multiplication value of the PLL circuit is configured to m. At this point, the PLL circuit multiplies the synchronization clock SYN_CLK by m to generate the multiplied clock MUL_CLK. The clock module can be implemented using any PLL circuit capable of frequency adjustment available in the prior art.

[0057] The data input module 102 is connected to the output terminal of the clock module 101 and is used to receive the configuration differential data input from the main data positive port SDA1+ and the main data negative port SDA1- under the control of the synchronization clock SYN_CLK and convert it into configuration information for storage.

[0058] Specifically, the data input module 102 includes a differential-to-single-ended circuit and a storage circuit. The differential-to-single-ended circuit receives the configuration differential data under the control of the synchronization clock SYN_CLK and converts it into configuration information. The storage circuit is connected to the output of the differential-to-single-ended circuit and stores the configuration information. Additionally, the data input module may also include a control register bank, which is used to implement data input.

[0059] The main module 103 is connected to the output of the data input module 102, and is used to read the configuration information and configure the chip, as well as generate the data to be transmitted under the control of the system clock SYS_CLK. Furthermore, the main module 103 is also connected to the output of the clock module 101 to generate the system clock SYS_CLK based on the synchronization clock SYN_CLK. In practical applications, the frequency of the system clock SYS_CLK and the frequency of the synchronization clock SYN_CLK can be the same. Of course, they can also be different, generating the required frequency of the system clock SYS_CLK based on the synchronization clock SYN_CLK according to actual needs.

[0060] Specifically, the main module 103 includes a clock / control unit and a data unit. The clock / control unit is connected to the output of the clock module 101 and the output of the data input module 102, and is used to generate the system clock SYS_CLK based on the synchronization clock SYN_CLK, and to read the configuration information and perform chip configuration, so as to generate a control signal based on the system clock SYS_CLK after the chip configuration is completed. The data unit is connected to the output of the clock / control unit and is used to generate the data to be transmitted based on the control signal. In another example, the system clock SYS_CLK can be generated based on the clock module 11, and the main module 13 can directly receive the system clock SYS_CLK to generate image data, etc. Of course, the main module 13 can also adopt other conventional modules of the prior art.

[0061] More specifically, when the five-port chip 100 includes an image sensor chip, the data unit includes: a pixel circuit and a quantization circuit; the pixel circuit is connected to the output of the clock / control unit and is used to perform photoelectric conversion according to the control signal to generate a pixel signal; the quantization circuit is connected to the output of the pixel circuit and is used to quantize the pixel signal and generate the data to be transmitted; wherein, the pixel signal is image data in analog signal form, and the data to be transmitted is image data in digital signal form.

[0062] In practical applications, the pixel circuit corresponds to a number of pixels arranged in rows and columns. Each pixel includes at least a photodiode, a transmission transistor, a reset transistor, a source follower transistor, and a selection transistor. The anode of the photodiode is grounded, and its cathode is connected to the first terminal of the transmission transistor. The control terminal of the transmission transistor receives a transmission control signal, and its second terminal is connected to a floating diffused active region. The control terminal of the reset transistor receives a reset control signal, its first terminal receives a power supply voltage, and its second terminal is connected to the floating diffused active region. The gate terminal of the source follower transistor is connected to the floating diffused active region, its drain terminal receives a power supply voltage, and its source terminal is connected to the first terminal of the selection transistor. The control terminal of the selection transistor receives a selection control signal, and its second terminal generates a pixel signal.

[0063] The quantization circuit includes a comparator and a counter. The comparator compares the pixel signal and the ramp signal, while the counter starts counting. When the ramp signal is greater than the pixel signal, the output of the comparator flips, and the counter stops counting. The counting result at this time is the digital code value of the quantized pixel signal.

[0064] The data output module 104 is connected to the output terminal of the clock module 101 and the output terminal of the main module 103. It is used to convert the data to be transmitted into differential data, and based on the synchronization clock SYN_CLK, differentially output the differential data to be transmitted through the main data positive port SDA1+ and the main data negative port SDA1- in a set frame format. Further, the data output module 104 outputs the differential data to be transmitted under the control of the frequency multiplication clock MUL_CLK.

[0065] Specifically, the data output module 104 includes a single-ended to differential circuit and an output circuit; the single-ended to differential circuit is used to convert the data to be transmitted into differential data to be transmitted; the output circuit is connected to the single-ended to differential circuit and is used to output the differential data to be transmitted in a set frame format at the frequency multiplication clock MUL_CLK.

[0066] Correspondingly, such as Figure 2 As shown, this embodiment also provides a chip system, which includes a master chip 100 and a slave chip 200; wherein, the master chip 100 adopts a five-port chip as described above; the slave chip 200 has a slave clock port SCL2, a slave positive data port SDA2+, and a slave negative data port SDA2-, and the slave clock port SCL2, the slave positive data port SDA2+, and the slave negative data port SDA2- are correspondingly connected to the master clock port SCL1, the master positive data port SDA1+, and the master negative data port SDA1- for data interaction, used to provide the master chip 100 with the external clock EXT_CLK and the configuration information, and to receive the differential data to be transmitted output by the master chip 100.

[0067] Specifically, the slave chip 200 includes a clock generation module 201, a data generation module 202, and a data processing module 203. The clock generation module 201 generates the external clock EXT_CLK and outputs it through the slave clock port SCL2. The data generation module 202 generates the configuration information and converts it into configuration differential data for differential output through the slave data positive port SDA2+ and the slave data negative port SDA2-. The data processing module 203 receives the differential data to be transmitted through the slave data positive port SDA2+ and the slave data negative port SDA2- and converts it into the data to be transmitted. In practical applications, the master chip 100 includes an image sensor chip, and the slave chip 200 includes a processor chip. The clock generation module can use existing clock generation modules, such as those based on a phase-locked loop circuit.

[0068] More specifically, the data generation module 202 includes: a configuration information generation circuit and a single-ended to differential circuit; the configuration information generation circuit is used to generate the configuration information; the single-ended to differential circuit is connected to the output terminal of the configuration information generation circuit, and is used to convert the configuration information into the configuration differential data, and output it differentially through the positive data port SDA2+ and the negative data port SDA2-.

[0069] The data processing module 203 includes: a differential-to-single-ended circuit and a data processing circuit; the differential-to-single-ended circuit receives the differential data to be transmitted through the positive data port SDA2+ and the negative data port SDA2- and converts it into the data to be transmitted; the data processing circuit is connected to the output of the differential-to-single-ended circuit and is used to perform subsequent data processing on the data to be transmitted to generate an image.

[0070] Example 2

[0071] like Figure 3 As shown, this embodiment provides a data interaction method for a chip system, the data interaction method including: steps 1), 2), 3), 4), and 5); wherein, the chip system includes a master chip 100 and a slave chip 200, the master clock port SCL1, master data positive port SDA1+, and master data negative port SDA1- of the master chip 100 are correspondingly connected to the slave clock port SCL2, slave data positive port SDA2+, and slave data negative port SDA2- of the slave chip 200 for data interaction. In practical applications, the chip system can be the chip system described in Embodiment 1.

[0072] Step 1) The main chip 100 receives the external clock EXT_CLK sent by the slave chip 200 through the main clock port SCL1 and forms a synchronization clock SYN_CLK.

[0073] Step 2) Under the control of the synchronization clock SYN_CLK, the master chip 100 receives the configuration differential data sent by the slave chip 200 through the master data positive port SDA1+ and the master data negative port SDA1-, and converts the configuration differential data into configuration information.

[0074] Step 3) The main chip 100 performs chip configuration according to the configuration information. Further, the data interaction method also includes: after the main chip performs the chip configuration, it generates a frequency multiplier clock MUL_CLK based on the synchronization clock SYN_CLK.

[0075] Specifically, after the slave chip 200 sends the external clock EXT_CLK, it sends the configuration information after a set time. During this set time, the master chip 100 receives the external clock EXT_CLK and generates the synchronization clock SYN_CLK based on it. By setting the external clock and configuration information to be sent in a time-sharing manner, the waiting time is prioritized, which is beneficial for smooth and stable subsequent operations.

[0076] Specifically, the main chip 100 generates the synchronous clock SYN_CLK and the frequency-multiplying clock MUL_CLK based on an adjustable frequency-multiplying phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state.

[0077] In practical applications, the frequency of the synchronization clock SYN_CLK is the same as the frequency of the external clock EXT_CLK, and the frequency of the frequency multiplier clock MUL_CLK is m times the frequency of the synchronization clock SYN_CLK, where m is a positive number greater than 1.

[0078] In one example, it can be assumed that the initial multiplication value of the phase-locked loop circuit is 1 in the initial state. At this time, the phase-locked loop circuit multiplies the external clock EXT_CLK by 1 to generate the synchronization clock SYN_CLK. In addition, after the chip configuration is completed, the multiplication value of the phase-locked loop circuit is configured to m. At this time, the phase-locked loop circuit multiplies the synchronization clock SYN_CLK by m to generate the multiplied clock MUL_CLK.

[0079] Step 4) The master chip 100 converts the data to be transmitted into differential data, and outputs the differential data to be transmitted differentially to the slave chip 200 through the master data positive port SDA1+ and the master data negative port SDA1- under the set frame format based on the synchronization clock SYN_CLK. Further, the master chip 100 outputs the differential data to be transmitted under the control of the frequency multiplication clock MUL_CLK.

[0080] In practical applications, when the master chip 100 and the slave chip 200 interact with each other, after the master chip 100 receives the start-of-frame field sent by the slave chip 200, the master chip 100 switches from receiving mode to sending mode, and at this time, the slave chip 200 switches from sending mode to receiving mode; after the slave chip 200 receives the end-of-frame field sent by the master chip 100, the slave chip 200 switches from receiving mode to sending mode, and at this time, the master chip 100 switches from sending mode to receiving mode.

[0081] Specifically, the frame format setting includes several row fields, each with the same format, including {start of row field, clock synchronization field, data field, clock synchronization field, end of row field}. More specifically, the data field includes n bits, the start of frame field includes 10n bits, the end of frame field includes 10n bits; the start of row field includes 3n bits, the end of row field includes 3n bits, and the clock synchronization field includes 6n bits, where n is an integer greater than 1.

[0082] In this example, n = 10. The frame start field includes 100 bits, which are 5 sets of cyclic {11111111110000000000}; the frame end field includes 100 bits, which are 10 sets of cyclic {1111100000}; the line start field includes 30 bits, which are 3 sets of cyclic {0000000000}; the line end field includes 30 bits, which are 3 sets of cyclic {1111111111}; and the clock synchronization field includes 60 bits, which are 6 sets of cyclic {1010101010}.

[0083] Step 5) The slave chip 200 receives the differential data to be transmitted through the slave data positive port SDA2+ and the slave data negative port SDA2- and converts it into the data to be transmitted so as to facilitate subsequent image processing.

[0084] In summary, the five-port chip, chip system, and data interaction method of this invention utilize a master-slave handshake mechanism to quantize pixel signals and output them differentially at both ends, thereby improving the anti-interference capability during data transmission and achieving stable data transmission frame rate through a small number of ports (five ports). Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0085] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A five-port chip, characterized in that, Power is supplied through the main power port and the main ground port, and data is exchanged through the main clock port, the main data positive port and the main data negative port. The five-port chip includes: A clock module is used to generate a synchronous clock based on an external clock input from the main clock port; The data input module is connected to the output of the clock module and is used to receive the configuration differential data input from the main data positive port and the main data negative port under the control of the synchronization clock and convert it into configuration information for storage. The main module is connected to the output of the data input module and is used to read the configuration information and configure the chip, and to generate the data to be transmitted under the control of the system clock. The data output module is connected to the output of the clock module and the output of the main module. It is used to convert the data to be transmitted into differential data to be transmitted, and output the differential data to be transmitted differentially through the main data positive port and the main data negative port in a set frame format based on the synchronous clock. By reusing the main data positive port and the main data negative port for data input and output, data transmission can be completed through five ports.

2. The five-port chip according to claim 1, characterized in that, The clock module is also used to multiply the synchronous clock to generate a multiplied clock, and the data output module outputs the differential data to be transmitted under the control of the multiplied clock.

3. The five-port chip according to claim 2, characterized in that, The clock module is implemented using an adjustable frequency multiplier phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state.

4. The five-port chip according to claim 1, characterized in that, The main module is also connected to the output of the clock module to form the system clock based on the synchronization clock.

5. The five-port chip according to claim 1, characterized in that, The five-port chip includes an image sensor chip, and the data to be transmitted includes image data in digital signal form.

6. A chip system, characterized in that, The chip system includes: The main chip is a five-port chip as described in any one of claims 1-5; The slave chip has a slave clock port, a slave data positive port, and a slave data negative port, and the slave clock port, the slave data positive port, and the slave data negative port are correspondingly connected to the master clock port, the master data positive port, and the master data negative port for data interaction, used to provide the external clock and the configuration information to the master chip. Receive the differential data to be transmitted output by the main chip.

7. The chip system according to claim 6, characterized in that, The slave chip includes: A clock generation module is used to generate the external clock and output it through the clock port. The data generation module is used to generate the configuration information and convert it into configuration differential data for differential output through the positive data port and the negative data port. The data processing module is used to receive the differential data to be transmitted through the positive data port and the negative data port and convert it into the data to be transmitted.

8. The chip system according to claim 6, characterized in that, When the main chip includes an image sensor chip, the slave chip includes a processor chip.

9. A data interaction method for a chip system, characterized in that, The chip system includes a master chip and a slave chip. The master clock port, master data positive port, and master data negative port of the master chip are connected to the slave clock port, slave data positive port, and slave data negative port of the slave chip respectively to perform data interaction. The data interaction method includes: The main chip receives the external clock sent by the slave chip through the main clock port and forms a synchronous clock; Under the control of the synchronization clock, the master chip receives the configuration differential data sent by the slave chip through the master data positive port and the master data negative port, and converts the configuration differential data into configuration information; The main chip is configured according to the configuration information; The master chip converts the data to be transmitted into differential data to be transmitted, and outputs the differential data to be transmitted differentially to the slave chip through the master data positive port and the master data negative port under the set frame format based on the synchronization clock. The slave chip receives the differential data to be transmitted through the slave data positive port and the slave data negative port and converts it into the data to be transmitted. The main chip performs data input and output by reusing the main data positive port and the main data negative port, thereby enabling data transmission through five ports.

10. The data interaction method for a chip system according to claim 9, characterized in that, The data interaction method further includes: after the main chip performs the chip configuration, it generates a frequency multiplier clock based on the synchronous clock, and outputs the differential data to be transmitted under the control of the frequency multiplier clock.

11. The data interaction method for a chip system according to claim 10, characterized in that, The main chip generates the frequency-doubled clock based on an adjustable frequency-doubled phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state.

12. The data interaction method for a chip system according to claim 9, characterized in that, After the chip sends the external clock, it sends the configuration information after a set time.

13. The data interaction method for a chip system according to claim 9, characterized in that, After the master chip receives the start-of-frame field sent by the slave chip, the master chip switches from receive mode to send mode, and at this time, the slave chip switches from send mode to receive mode; after the slave chip receives the end-of-frame field sent by the master chip, the slave chip switches from receive mode to send mode, and at this time, the master chip switches from send mode to receive mode.

14. The data interaction method for a chip system according to claim 13, characterized in that, The frame format setting includes several row fields, and each row field has the same format, including {start of row field, clock synchronization field, data field, clock synchronization field, end of row field}.

15. The data interaction method for a chip system according to claim 14, characterized in that, The data field includes n bits; the frame start field includes 10n bits; the frame end field includes 10n bits; the line start field includes 3n bits; the line end field includes 3n bits; and the clock synchronization field includes 6n bits, where n is an integer greater than 1.

16. The data interaction method for a chip system according to claim 15, characterized in that, The frame start field comprises 100 bits, consisting of 5 cyclic groups of {11111111110000000000}; the frame end field comprises 100 bits, consisting of 10 cyclic groups of {1111100000}; the line start field comprises 30 bits, consisting of 3 cyclic groups of {0000000000}; the line end field comprises 30 bits, consisting of 3 cyclic groups of {1111111111}; and the clock synchronization field comprises 60 bits, consisting of 6 cyclic groups of {1010101010}.

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