Low input voltage negative output ultra-low noise linear regulator

Abstract

A low-input-voltage, negative-output, ultra-low-noise linear regulator, relating to integrated circuit technology, comprises a reference circuit, an error amplifier, and a drive circuit. The output of the drive circuit is connected to the gate of a power transistor. The drive circuit has a positive input and a negative input, and the output of the error amplifier is connected to the negative input of the drive circuit. This invention significantly reduces the output noise of the linear regulator. Furthermore, the linear regulator generates a negative output, providing a negative voltage source for the load. The high-gain drive circuit suppresses input voltage noise, extending the input voltage range.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuits, in particular to linear voltage regulators. Background Art

[0002] Ultra-low-noise linear regulators with low input voltage and negative output are important components in power management systems. They are mainly used in noise-sensitive systems, including receivers in the RF field, high-precision ADCs and DACs, and medical equipment.

[0003] Ultra-low noise is an extremely important performance parameter. Lower noise means a cleaner power supply voltage for the load chip. In RF applications, receiver chips include circuits such as low-noise amplifiers (LNAs), mixer circuits, and phase-locked loops (PLLs). The LNA, in particular, has extremely stringent requirements for power supply noise parameters. Excessive power supply noise for the LNA will increase the receiver's noise factor, causing the ADC circuit within the receiver chip to incorrectly identify the input voltage, ultimately leading to malfunction. Therefore, ultra-low-noise linear regulators are crucial for providing a very clean power supply voltage for chips such as receivers.

[0004] In order to realize low-noise linear regulator, common technical solutions are:

[0005] (1) Use RC filtering to reduce the noise generated by the reference circuit.

[0006] (2) Use low-noise amplifier circuit structure to reduce the noise of the amplifier circuit.

[0007] However, the disadvantages are: the simulation models provided by most wafer fabs do not include the thermal noise model of the MOS tube, but only the flicker noise model of the MOS tube. This results in the noise parameters of the chip being tested after the wafer is returned, and the actual test results are larger than the simulation results; the input voltage of the low-noise amplifier circuit structure is at least 2.5V, which cannot achieve the low input voltage characteristics.

[0008] Figure 1 This is a conventional linear voltage regulator with a positive output voltage. In the circuit, the noise-generating circuits are the reference circuit and the error amplifier circuit. To eliminate the noise generated by the reference circuit, the most common technique is to use a first-order RC filter with resistors R12 and C12. To reduce the noise generated by the error amplifier, a low-noise amplifier structure is used. Finally, output capacitor Cout12 is used to reduce output noise.

[0009] Both positive- and negative-output linear regulators generally employ the three aforementioned technical solutions. However, most simulation models do not include a thermal noise model for the MOS transistor, only a flicker noise model. This, coupled with limitations in the low-noise amplifier structure, results in measured noise parameters that are slightly higher than the simulated results, typically around 20 μVrms.

[0010] Figure 2 yes Figure 1 This circuit structure uses four stacked MOS tubes, which requires the input voltage to be at least 2.5V and cannot achieve low input voltage. Summary of the Invention

[0011] The technical problem to be solved by the present invention is to propose a linear voltage regulator with low noise, low input voltage and negative output, in order to solve the problem that the linear voltage regulator has high noise and cannot achieve low input voltage.

[0012] The technical solution adopted by the present invention to solve the technical problem is a low-input voltage negative-output ultra-low-noise linear regulator, which includes a reference circuit, an error amplifier and a drive circuit, wherein the output end of the drive circuit is connected to the gate of the power tube, and is characterized in that the drive circuit has a positive input end and a negative input end, and the output end of the error amplifier is connected to the negative input end of the drive circuit.

[0013] The driving circuit includes:

[0014] The eleventh PMOS transistor (PMOS11) has a source connected to the ground, and a gate and a drain connected to the voltage input terminal (VIN) through a twelfth resistor (R12);

[0015] The twelfth PMOS transistor (PMOS12) has a source connected to the ground, a gate connected to the gate of the eleventh PMOS transistor (PMOS11), and a drain connected to the voltage input terminal (VIN) via a thirteenth resistor (R13);

[0016] A thirteenth PMOS transistor (PMOS13) has a source connected to the ground, a twelfth capacitor (C12) is provided between the drain and the gate, and the gate is connected to the drain of the twelfth PMOS transistor (PMOS12);

[0017] The source of the fourteenth PMOS transistor (PMOS14) is grounded, and the gate serves as the third bias voltage input point net3;

[0018] A fifteenth PMOS transistor (PMOS15) has a source connected to the drain of the fourteenth PMOS transistor (PMOS14) and a gate connected to the drain of the twelfth PMOS transistor (PMOS12);

[0019] An eighteenth PMOS transistor (PMOS18), whose source is grounded and whose gate is connected to the fifth bias voltage input point net5;

[0020] The sixteenth PMOS transistor (PMOS16) has a source connected to the drain of the eighteenth PMOS transistor (PMOS18), a gate connected to the negative input terminal of the drive circuit, and a drain connected to the drain of the eleventh PMOS transistor (PMOS11);

[0021] The seventeenth PMOS transistor (PMOS17) has a source connected to the drain of the eighteenth PMOS transistor (PMOS18), a gate connected to the positive input terminal of the drive circuit, and a drain connected to the drain of the twelfth PMOS transistor (PMOS12);

[0022] The drain and gate of the eleventh NMOS transistor (NMOS11) are connected to the drain of the fifteenth PMOS transistor (PMOS15), the source is connected to the voltage input terminal (VIN), and the drain serves as the output terminal of the driving circuit;

[0023] The gate of the twenty-first NMOS transistor (NMOS21) is connected to the positive input terminal of the driving circuit, and the drain is grounded through the twenty-first resistor (R21);

[0024] A twenty-second NMOS transistor (NMOS22), having a gate connected to the negative input terminal of the driving circuit and a drain connected to ground via a twenty-second resistor (R22);

[0025] A twenty-sixth NMOS transistor (NMOS26), having a gate connected to the fourth bias voltage input terminal net4, a drain connected to the source of the twenty-first NMOS transistor (NMOS21) and the source of the twenty-second NMOS transistor (NMOS22), and a source connected to the voltage input terminal (VIN);

[0026] The gate and drain of the twenty-third NMOS transistor (NMOS23) are connected to the drain of the twenty-first NMOS transistor (NMOS21), and the source is connected to the voltage input terminal (VIN);

[0027] A twenty-fourth NMOS transistor (NMOS24) has a gate connected to the gate of the twenty-third NMOS transistor (NMOS23), a drain connected to the drain of the eleventh PMOS transistor (PMOS11), and a source connected to the voltage input terminal (VIN);

[0028] The drain of the twenty-fifth NMOS transistor (NMOS25) is connected to the drain of the twelfth PMOS transistor (PMOS12), and the source is connected to the voltage input terminal (VIN);

[0029] The twenty-seventh NMOS transistor (NMOS27) has a gate and a drain connected to the drain of the twenty-second NMOS transistor (NMOS22), a source connected to the voltage input terminal (VIN), and a gate connected to the gate of the twenty-fifth NMOS transistor (NMOS25).

[0030] The error amplifier comprises:

[0031] The first PMOS transistor (PMOS1) has a source connected to the ground and a gate connected to the drain;

[0032] The second PMOS transistor (PMOS2) has a source connected to the ground and a gate connected to the gate of the first PMOS transistor (PMOS1);

[0033] The fifth NMOS transistor (NMOS5) has a drain connected to the drain of the first PMOS transistor (PMOS1) and a gate connected to the negative input terminal of the error amplifier;

[0034] The third PMOS transistor (PMOS3) has its source connected to the ground and its gate connected to the drain;

[0035] a sixth NMOS transistor (NMOS6), having a drain connected to the drain of the third PMOS transistor (PMOS3), and a gate connected to the positive input terminal of the error amplifier;

[0036] a seventh NMOS transistor (NMOS7), having a drain connected to the source of the fifth NMOS transistor (NMOS5) and the source of the sixth NMOS transistor (NMOS6), a gate connected to the first bias voltage input point net1, and a source connected to the voltage input terminal (VIN);

[0037] The drain of the third NMOS transistor (NMOS3) is connected to the drain of the fourth PMOS transistor (PMOS4), and the source is connected to the voltage input terminal (VIN);

[0038] The fourth NMOS transistor (NMOS4) has a drain and a gate connected to the drain of the second PMOS transistor (PMOS2), a source connected to the voltage input terminal (VIN), and a gate connected to the gate of the third NMOS transistor (NMOS3);

[0039] The fifth PMOS transistor (PMOS5) has a source connected to the ground, a gate connected to the drain of the fourth PMOS transistor (PMOS4), and a gate connected to the ground via a series resistor and a capacitor;

[0040] The second NMOS transistor (NMOS2) has its gate and drain connected to the drain of the fifth PMOS transistor (PMOS5), and its source grounded;

[0041] The sixth PMOS transistor (PMOS6) has a source connected to the ground, a gate connected to the second bias voltage input point net2, and a drain serving as the output end of the error amplifier;

[0042] The first NMOS transistor (NMOS1) has a drain connected to the output end of the error amplifier, a source connected to the voltage input end (VIN), and a gate connected to the gate of the second NMOS transistor (NMOS2).

[0043] The present invention significantly reduces the output noise of the linear voltage stabilizer. At the same time, the linear voltage stabilizer generates a negative phase output to provide a negative phase voltage source for the load. The high-gain drive circuit suppresses the noise of the input voltage and expands the input voltage range. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a structural diagram of a linear regulator in the prior art.

[0045] Figure 2 It is a structural diagram of a low noise amplifier in the prior art.

[0046] Figure 3 1 is a structural diagram of a linear voltage regulator of the present invention.

[0047] Figure 4 is a circuit diagram of the error amplifier of the present invention.

[0048] Figure 5 It is a bias current circuit diagram of the present invention.

[0049] Figure 6 is a circuit diagram of a driving circuit of the present invention.

[0050] Figure 7 It is a screenshot of the noise parameter simulation result of the linear regulator of the present invention.

[0051] Figure 8 This is a graph showing actual testing of the linear voltage regulator after tape-out.

[0052] Figure 9 It is a structural diagram of an improved embodiment. Specific implementation plan

[0053] Based on the existing linear regulator architecture, the present invention reduces output noise by forming an active filter circuit with a driver (voltage follower) circuit Buffer, a power transistor NMOS, and an output capacitor Cout11. At the same time, the linear regulator has a low input voltage negative output and a drive current capability of -500mA. The feedback capacitor C of the error amplifier circuit AFB To reduce the noise of the error amplifier; the voltage follower circuit Buffer enables the present invention to have high gain, thereby improving the power supply rejection ratio of the linear regulator and suppressing the noise of the input voltage; in the selected wafer process, the MOS device has a low threshold characteristic to achieve the characteristic of low input voltage.

[0054] The present invention solves the disadvantage of inaccurate noise simulation results of common technologies and realizes the feature of low input voltage.

[0055] See also Figures 3 to 9 .

[0056] A low-input-voltage, negative-output, ultra-low-noise linear regulator comprises a reference circuit, an error amplifier, and a drive circuit, wherein the output of the drive circuit is connected to the gate of the power tube. The drive circuit has a positive input terminal and a negative input terminal, and the output of the error amplifier is connected to the negative input terminal of the drive circuit.

[0057] The driving circuit includes:

[0058] The eleventh PMOS transistor (PMOS11) has a source connected to the ground, and a gate and a drain connected to the voltage input terminal (VIN) through a twelfth resistor (R12);

[0059] The twelfth PMOS transistor (PMOS12) has a source connected to the ground, a gate connected to the gate of the eleventh PMOS transistor (PMOS11), and a drain connected to the voltage input terminal (VIN) via a thirteenth resistor (R13);

[0060] A thirteenth PMOS transistor (PMOS13) has a source connected to the ground, a twelfth capacitor (C12) is provided between the drain and the gate, and the gate is connected to the drain of the twelfth PMOS transistor (PMOS12);

[0061] The source of the fourteenth PMOS transistor (PMOS14) is grounded, and the gate serves as the third bias voltage input point net3;

[0062] A fifteenth PMOS transistor (PMOS15) has a source connected to the drain of the fourteenth PMOS transistor (PMOS14) and a gate connected to the drain of the twelfth PMOS transistor (PMOS12);

[0063] An eighteenth PMOS transistor (PMOS18), whose source is grounded and whose gate is connected to the fifth bias voltage input point net5;

[0064] The sixteenth PMOS transistor (PMOS16) has a source connected to the drain of the eighteenth PMOS transistor (PMOS18), a gate connected to the negative input terminal of the drive circuit, and a drain connected to the drain of the eleventh PMOS transistor (PMOS11);

[0065] The seventeenth PMOS transistor (PMOS17) has a source connected to the drain of the eighteenth PMOS transistor (PMOS18), a gate connected to the positive input terminal of the drive circuit, and a drain connected to the drain of the twelfth PMOS transistor (PMOS12);

[0066] The drain and gate of the eleventh NMOS transistor (NMOS11) are connected to the drain of the fifteenth PMOS transistor (PMOS15), the source is connected to the voltage input terminal (VIN), and the drain serves as the output terminal of the driving circuit;

[0067] The gate of the twenty-first NMOS transistor (NMOS21) is connected to the positive input terminal of the driving circuit, and the drain is grounded through the twenty-first resistor (R21);

[0068] A twenty-second NMOS transistor (NMOS22), having a gate connected to the negative input terminal of the driving circuit and a drain connected to ground via a twenty-second resistor (R22);

[0069] A twenty-sixth NMOS transistor (NMOS26), having a gate connected to the fourth bias voltage input terminal net4, a drain connected to the source of the twenty-first NMOS transistor (NMOS21) and the source of the twenty-second NMOS transistor (NMOS22), and a source connected to the voltage input terminal (VIN);

[0070] The gate and drain of the twenty-third NMOS transistor (NMOS23) are connected to the drain of the twenty-first NMOS transistor (NMOS21), and the source is connected to the voltage input terminal (VIN);

[0071] A twenty-fourth NMOS transistor (NMOS24) has a gate connected to the gate of the twenty-third NMOS transistor (NMOS23), a drain connected to the drain of the eleventh PMOS transistor (PMOS11), and a source connected to the voltage input terminal (VIN);

[0072] The drain of the twenty-fifth NMOS transistor (NMOS25) is connected to the drain of the twelfth PMOS transistor (PMOS12), and the source is connected to the voltage input terminal (VIN);

[0073] The twenty-seventh NMOS transistor (NMOS27) has a gate and a drain connected to the drain of the twenty-second NMOS transistor (NMOS22), a source connected to the voltage input terminal (VIN), and a gate connected to the gate of the twenty-fifth NMOS transistor (NMOS25).

[0074] The error amplifier comprises:

[0075] The first PMOS transistor (PMOS1) has a source connected to the ground and a gate connected to the drain;

[0076] The second PMOS transistor (PMOS2) has a source connected to the ground and a gate connected to the gate of the first PMOS transistor (PMOS1);

[0077] The fifth NMOS transistor (NMOS5) has a drain connected to the drain of the first PMOS transistor (PMOS1) and a gate connected to the negative input terminal of the error amplifier;

[0078] The third PMOS transistor (PMOS3) has its source connected to the ground and its gate connected to the drain;

[0079] a sixth NMOS transistor (NMOS6), having a drain connected to the drain of the third PMOS transistor (PMOS3), and a gate connected to the positive input terminal of the error amplifier;

[0080] a seventh NMOS transistor (NMOS7), having a drain connected to the source of the fifth NMOS transistor (NMOS5) and the source of the sixth NMOS transistor (NMOS6), a gate connected to the first bias voltage input point net1, and a source connected to the voltage input terminal (VIN);

[0081] The drain of the third NMOS transistor (NMOS3) is connected to the drain of the fourth PMOS transistor (PMOS4), and the source is connected to the voltage input terminal (VIN);

[0082] The fourth NMOS transistor (NMOS4) has a drain and a gate connected to the drain of the second PMOS transistor (PMOS2), a source connected to the voltage input terminal (VIN), and a gate connected to the gate of the third NMOS transistor (NMOS3);

[0083] The fifth PMOS transistor (PMOS5) has a source connected to the ground, a gate connected to the drain of the fourth PMOS transistor (PMOS4), and a gate connected to the ground via a series resistor and a capacitor;

[0084] The second NMOS transistor (NMOS2) has its gate and drain connected to the drain of the fifth PMOS transistor (PMOS5), and its source grounded;

[0085] The sixth PMOS transistor (PMOS6) has a source connected to the ground, a gate connected to the second bias voltage input point net2, and a drain serving as the output end of the error amplifier;

[0086] The first NMOS transistor (NMOS1) has a drain connected to the output end of the error amplifier, a source connected to the voltage input end (VIN), and a gate connected to the gate of the second NMOS transistor (NMOS2).

[0087] Figure 3 In the figure, the circuit inside the dotted line is the circuit inside the chip, and the peripheral devices outside the dotted line are external to the chip. GND is the ground line and the high level; VIN is the input voltage and the low level. The reference voltage generates -1.2V. R11 and C11 filter the noise in the reference voltage to generate a clean reference voltage as the positive input of the error amplifier AMP. The output voltage value of the linear regulator, that is, the voltage value of the VA port, is achieved by using the series feedback resistors R1 and R2 outside the chip. The feedback capacitor C AFB =10nF to reduce the noise of VA port, while the capacitor C A=1uF not only provides loop stability for the error amplifier AMP circuit but also reduces noise. The driver circuit buffer, power transistor NMOS, and output capacitor Cout11 = 2.2uF form an active filter circuit that reduces noise at the VA port, ultimately achieving low noise at the linear regulator output Vout. Vout also features a negative output characteristic.

[0088] Figure 4 This is the circuit structure of the error amplifier AMP. To achieve a low input voltage of -1.8V to -5.5V, a fully symmetrical current conversion circuit structure is used. The input pair NMOS transistors have low threshold characteristics. To achieve low noise characteristics, the area of ​​the input pair NMOS5 and NMOS6 is increased.

[0089] Figure 5 The structure of the bias current circuit is shown. This part of the circuit provides the bias voltages for each of net1 to net5. As an improved embodiment, the bias current circuit can be set inside the chip as part of the present invention, such as Figure 9 shown.

[0090] Figure 6 This is the circuit structure of the driver circuit buffer. Traditional driver circuits are limited by low input voltages, and common solutions employ low-gain structures such as followers or inverters. The major drawback of these structures is low gain and poor input voltage noise suppression. In this case, the driver circuit buffer utilizes a rail-to-rail circuit structure. The input transistors PMOS16 and PMOS17, and NMOS21 and NMOS22 are all low-threshold devices with a threshold voltage of approximately 0.2V. Unlike traditional rail-to-rail error amplifiers, the input transistors PMOS16 and PMOS17, and NMOS21 and NMOS22 operate in saturation over the entire input voltage (Vout) range of -1.2V to -3.3V (Vin = Vout - 0.5V). This achieves a gain of 2x, resulting in high gain and noise suppression on the input voltage Vin.

[0091] Figure 7 This is the noise simulation value. At room temperature, the noise is 5.62uVrms.

[0092] Figure 8 The test value after the chip is taped out is about 2uVrms.

[0093] It can be seen that the characteristics of the present invention include:

[0094] (1) Generate a reference voltage of -1.2V using a reference voltage circuit;

[0095] (2) Use the error amplifier circuit AMP, resistor R1, and resistor R2 to generate the output voltage value of the linear regulator; use the feedback capacitor C AFB and output capacitor C A To reduce the noise of VA port;

[0096] (3) The voltage follower circuit Buffer and the power tube NMOS generate negative phase output;

[0097] (4) The voltage follower circuit Buffer, power tube NMOS, and output capacitor Cout11 form an active filter circuit that can effectively reduce the noise at the output end Vout of the linear regulator;

[0098] (5) Design a voltage follower circuit buffer, using low-threshold NMOS and low-threshold PMOS as input transistors, and a rail-rail architecture so that it still has high gain in the input voltage range of -1.8V to -5.5V, thereby improving the power supply rejection ratio of the linear regulator and suppressing the noise of the input voltage.

Claims

1. A low input voltage negative output ultra-low noise linear regulator, comprising a reference circuit, an error amplifier and a drive circuit, wherein the output terminal of the drive circuit is connected to the gate of the power tube, characterized in that: The driving circuit has a positive input terminal and a negative input terminal, the output terminal of the error amplifier is connected to the negative input terminal of the driving circuit, and the driving circuit includes: The eleventh PMOS transistor (PMOS11) has a source connected to the ground, and a gate and a drain connected to the voltage input terminal (VIN) through a twelfth resistor (R12); The twelfth PMOS transistor (PMOS12) has a source connected to the ground, a gate connected to the gate of the eleventh PMOS transistor (PMOS11), and a drain connected to the voltage input terminal (VIN) via a thirteenth resistor (R13); A thirteenth PMOS transistor (PMOS13) has a source connected to the ground, a twelfth capacitor (C12) is provided between the drain and the gate, and the gate is connected to the drain of the twelfth PMOS transistor (PMOS12); The source of the fourteenth PMOS transistor (PMOS14) is grounded, and the gate serves as a third bias voltage input point; A fifteenth PMOS transistor (PMOS15) has a source connected to the drain of the fourteenth PMOS transistor (PMOS14) and a gate connected to the drain of the twelfth PMOS transistor (PMOS12); An eighteenth PMOS transistor (PMOS18), whose source is grounded and whose gate is connected to the fifth bias voltage input point; The sixteenth PMOS transistor (PMOS16) has a source connected to the drain of the eighteenth PMOS transistor (PMOS18), a gate connected to the negative input terminal of the drive circuit, and a drain connected to the drain of the eleventh PMOS transistor (PMOS11); The seventeenth PMOS transistor (PMOS17) has a source connected to the drain of the eighteenth PMOS transistor (PMOS18), a gate connected to the positive input terminal of the drive circuit, and a drain connected to the drain of the twelfth PMOS transistor (PMOS12); The drain and gate of the eleventh NMOS transistor (NMOS11) are connected to the drain of the fifteenth PMOS transistor (PMOS15), the source is connected to the voltage input terminal (VIN), and the drain serves as the output terminal of the driving circuit; The gate of the twenty-first NMOS transistor (NMOS21) is connected to the positive input terminal of the driving circuit, and the drain is grounded through the twenty-first resistor (R21); A twenty-second NMOS transistor (NMOS22), having a gate connected to the negative input terminal of the driving circuit and a drain connected to ground via a twenty-second resistor (R22); a twenty-sixth NMOS transistor (NMOS26), having a gate connected to the fourth bias voltage input terminal, a drain connected to the source of the twenty-first NMOS transistor (NMOS21) and the source of the twenty-second NMOS transistor (NMOS22), and a source connected to the voltage input terminal (VIN); The gate and drain of the twenty-third NMOS transistor (NMOS23) are connected to the drain of the twenty-first NMOS transistor (NMOS21), and the source is connected to the voltage input terminal (VIN); A twenty-fourth NMOS transistor (NMOS24) has a gate connected to the gate of the twenty-third NMOS transistor (NMOS23), a drain connected to the drain of the eleventh PMOS transistor (PMOS11), and a source connected to the voltage input terminal (VIN); The drain of the twenty-fifth NMOS transistor (NMOS25) is connected to the drain of the twelfth PMOS transistor (PMOS12), and the source is connected to the voltage input terminal (VIN); The twenty-seventh NMOS transistor (NMOS27) has a gate and a drain connected to the drain of the twenty-second NMOS transistor (NMOS22), a source connected to the voltage input terminal (VIN), and a gate connected to the gate of the twenty-fifth NMOS transistor (NMOS25).

2. The low input voltage negative output ultra-low noise linear regulator according to claim 1, characterized in that: The error amplifier comprises: The first PMOS transistor (PMOS1) has a source connected to the ground and a gate connected to the drain; The second PMOS transistor (PMOS2) has a source connected to the ground and a gate connected to the gate of the first PMOS transistor (PMOS1); The fifth NMOS transistor (NMOS5) has a drain connected to the drain of the first PMOS transistor (PMOS1) and a gate connected to the negative input terminal of the error amplifier; The third PMOS transistor (PMOS3) has its source connected to the ground and its gate connected to the drain; a sixth NMOS transistor (NMOS6), having a drain connected to the drain of the third PMOS transistor (PMOS3), and a gate connected to the positive input terminal of the error amplifier; a seventh NMOS transistor (NMOS7), having a drain connected to the source of the fifth NMOS transistor (NMOS5) and the source of the sixth NMOS transistor (NMOS6), a gate connected to the first bias voltage input point, and a source connected to the voltage input terminal (VIN); The drain of the third NMOS transistor (NMOS3) is connected to the drain of the fourth PMOS transistor (PMOS4), and the source is connected to the voltage input terminal (VIN); The fourth NMOS transistor (NMOS4) has a drain and a gate connected to the drain of the second PMOS transistor (PMOS2), a source connected to the voltage input terminal (VIN), and a gate connected to the gate of the third NMOS transistor (NMOS3); The fifth PMOS transistor (PMOS5) has a source connected to the ground, a gate connected to the drain of the fourth PMOS transistor (PMOS4), and a gate connected to the ground via a series resistor and a capacitor; The gate and drain of the second NMOS transistor (NMOS2) are connected to the drain of the fifth PMOS transistor (PMOS5), and the source is connected to the voltage input terminal (VIN); The sixth PMOS transistor (PMOS6) has a source connected to the ground, a gate connected to the second bias voltage input point, and a drain serving as an output terminal of the error amplifier; The first NMOS transistor (NMOS1) has a drain connected to the output end of the error amplifier, a source connected to the voltage input end (VIN), and a gate connected to the gate of the second NMOS transistor (NMOS2).

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