A low cost fast transient response linear regulator circuit

Abstract

The present application relates to the technical field of voltage stabilizing circuit, in particular to a low-cost fast transient response linear voltage stabilizer circuit, comprising an LDO main loop module and a transient response enhancement feedback circuit, the transient response enhancement feedback circuit is coupled between the error amplifier output end and the power tube gate end, a fast feedback path is constructed through two groups of coupling capacitors, directly acting on the power tube gate, and cooperating with the clamping unit to accelerate the node voltage change. The present application cancels the complex modules such as comparator and band gap reference in the traditional scheme, without relying on large off-chip capacitors, the voltage overshoot and undershoot during load jump can be effectively suppressed, the circuit structure is simple, the static power consumption is low, the layout area is small, the manufacturing cost is low, and the system reliability and integration are high.

Description

Technical Field

[0001] This invention relates to the field of voltage regulator circuit technology, and specifically to a low-cost, fast transient response linear voltage regulator circuit. Background Technology

[0002] During system operation, fluctuations in power supply voltage or a sudden change in load from light to full load can cause changes in output voltage. The negative feedback loop adjusts to restore the regulated voltage; this process is called the transient response process. When the load current changes from light to heavy, the current provided by the power transistor is less than the load current under heavy load. The LDO loop cannot react promptly, and the load capacitor discharges to maintain the load demand, causing the output voltage to drop (Vdl). Subsequently, the LDO negative feedback loop adjusts the gate voltage of the power transistor, lowering it. The power transistor then provides current to maintain the load current value, restoring the output voltage to normal. When the load current changes from heavy to light, the current provided by the power transistor is greater than the load current under light load. The LDO loop cannot react promptly, and the excess load current flows into the load capacitor, charging it. The accumulation of charge on the capacitor causes the output voltage to rise (Vrise).

[0003] Traditional wide-input-range linear regulators rely on large off-chip capacitors to enhance load transient response. Their internal circuitry includes an error amplifier, bandgap reference circuit, bias current source circuit, compensation capacitor, power transistor, and feedback resistor. With decreasing chip size and increased integration, designing wide-input-range, fast-transient-response linear regulators to replace these traditional off-chip capacitors has become a pressing issue.

[0004] Existing widely used transient response enhancement schemes employ comparator structures, such as... Figure 5 As shown, a comparator is used as the core to collect the difference between the feedback voltage and the reference voltage. The output signal, after being buffered and driven by a circuit, directly controls the gate of the power transistor, thereby accelerating the response speed. However, this type of solution has many shortcomings. In addition to a high-precision comparator, it also requires auxiliary modules such as a bandgap reference source, a stable bias circuit, and a startup circuit, which significantly increases the overall power consumption of the circuit, as well as the layout area and manufacturing cost. Furthermore, the threshold voltage of the inverter in this solution is difficult to control stably. When the load current is stable, the fixed voltage output by the comparator can easily cause the subsequent inverter to flip incorrectly, limiting the adjustment range of the power transistor gate voltage and thus limiting the load-carrying capacity of the LDO. The complex circuit structure also reduces the overall reliability of the system. The startup circuit may experience startup abnormalities at different temperatures, the bandgap reference output voltage is easily affected by temperature and power supply fluctuations, and the signal coordination between modules also places extremely high demands on design accuracy. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a low-cost, fast transient response linear regulator circuit.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A low-cost, fast transient response linear regulator circuit includes an LDO main loop module. The LDO main loop module includes an error amplifier, a power transistor MP, and a feedback voltage divider unit. The feedback voltage divider unit collects the output voltage, generates a feedback voltage, and inputs it to the error amplifier. The output of the error amplifier controls the gate of the power transistor MP to achieve voltage regulation. It also includes a transient response enhancement feedback circuit, which is coupled between the output terminal of the error amplifier and the gate terminal of the power transistor MP. The transient response enhancement feedback circuit includes a first high-voltage isolation transistor MP7, a pull-up transistor MP6, a pull-down high-voltage transistor MN6, a first coupling capacitor C1, a second coupling capacitor C2, and gate clamping units MP3, MP4, and MP5. The gate of the first high-voltage isolation transistor MP7 is coupled to the output of the error amplifier. The drain of the first high-voltage isolation transistor MP7 is connected to the intermediate node N2. The intermediate node N2 is coupled to the gate of the pull-up transistor MP6 through the first coupling capacitor C1. The intermediate node N2 is also coupled to the gate of the pull-down high-voltage transistor MN6 through the second coupling capacitor C2. The drain of the pull-down high-voltage transistor MN6 is coupled to the gate of the power transistor MP. The gate clamping units MP3, MP4, and MP5 are coupled between the gate of the first high-voltage isolation transistor MP7 and the power supply terminal. They are used to clamp the gate voltage of the first high-voltage isolation transistor MP7 in steady state and accelerate the rate of change of the gate voltage of the first high-voltage isolation transistor MP7 when the load current switches.

[0007] Furthermore, the first high-voltage isolation transistor MP7, the pull-down high-voltage transistor MN6, and the power transistor MP are all high-voltage withstand devices, while the input pair transistors, load transistors, and pull-up transistor MP6 inside the error amplifier are all low-voltage devices. The circuit is also equipped with a bias voltage terminal Vb2 to provide a stable bias voltage for each high-voltage isolation transistor to achieve high-voltage isolation.

[0008] Furthermore, the first coupling capacitor C1 is used to couple the voltage change of the intermediate node N2 to the gate of the pull-up transistor MP6 to adjust the pull-up strength of the pull-up transistor MP6 to the intermediate node N2, and the second coupling capacitor C2 is used to couple the voltage change of the intermediate node N2 to the gate of the pull-down high voltage transistor MN6 to control the pull-down action of the pull-down high voltage transistor MN6 to the gate of the power transistor MP.

[0009] Furthermore, the gate clamping units MP3, MP4, and MP5 are composed of three PMOS transistors connected in series. The source and drain of the three PMOS transistors are connected in series between the power supply terminal and the gate of the first high-voltage isolation transistor MP7, and the gates are connected to the reference voltage terminal to form a steady-state clamping path.

[0010] Furthermore, the error amplifier is a differential amplifier structure, including PMOS differential input pairs MP1 and MP2 and NMOS current mirror loads MN1, MN2 and MN3. One end of the differential input pairs is connected to a reference voltage, and the other end is connected to the feedback voltage output by the feedback voltage divider unit.

[0011] Furthermore, the feedback voltage divider unit includes a first feedback resistor Rf1 and a second feedback resistor Rf2 connected in series. The upper end of the first feedback resistor Rf1 is connected to the output voltage terminal, and the lower end is connected to the upper end of the second feedback resistor Rf2. The lower end of the second feedback resistor Rf2 is grounded, and the connection node of the two resistors outputs the feedback voltage to the input terminal of the error amplifier.

[0012] Preferably, the circuit also includes a startup circuit module, which includes a startup branch, a bias resistor R1, and an enable switch MN1. The startup branch is turned on when powered on and generates a bias voltage, driving the error amplifier to enter the working state. The enable switch MN1 is controlled by the output voltage feedback and turns off the startup branch after the circuit enters a steady state.

[0013] Furthermore, the startup branch includes a startup current source and a startup transistor MN4. The gate of the startup transistor MN4 is grounded through a bias resistor R1. When powered on, the startup current source charges the bias resistor R1 to generate a startup voltage, which turns on the startup transistor MN4 and provides bias to the error amplifier. The enable switch MN1 is an NMOS transistor, and its gate is connected to the output voltage feedback signal processed by the inverter INV1. In steady state, the output voltage enables the switch MN1 to conduct, pulling down the gate of the startup transistor MN4 to ground potential to turn off the startup branch.

[0014] The present invention has at least the following beneficial effects: This invention eliminates complex modules such as comparators and bandgap references in traditional comparator-type transient response enhancement circuits, greatly simplifying the overall circuit structure, effectively reducing the static power consumption of the circuit, while also reducing the layout area, lowering chip manufacturing costs, reducing reliability issues caused by multi-module collaboration, and significantly improving system stability.

[0015] This invention constructs a fast feedback path through two sets of coupling capacitors, which can directly transmit the load change signal to the gate of the power transistor without going through the LDO main negative feedback loop. The response speed is significantly improved, and the output voltage overshoot and undershoot during load jumps can be effectively suppressed. Moreover, the entire circuit can achieve excellent transient response performance without relying on large external capacitors, with higher integration and wider applicability.

[0016] This invention is equipped with a gate clamping unit, which can clamp the gate voltage of the internal high-voltage tube during steady-state operation, ensuring the stability of the circuit's steady-state operation and avoiding the problem of malfunctions that limit the load capacity. At the same time, it can accelerate the voltage change rate of the high-voltage tube gate during rapid load switching, further enhancing the transient response capability. This solves the problems of unstable inverter threshold and limited load capacity in traditional solutions. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of the linear voltage regulator circuit described in this invention; Figure 2 This is a schematic diagram of the startup circuit in this invention; Figure 3 This is a waveform diagram of the load transient response of an LDO without the addition of a transient response enhancement circuit; Figure 4 This is a waveform diagram of the LDO load transient response after incorporating the transient response enhancement circuit of this invention; Figure 5 This is a schematic diagram of an existing comparator-type transient response enhancement circuit. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present invention, the technical solution of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0019] Figures 1 to 4 A low-cost, fast transient response linear regulator circuit is presented, comprising two main parts: an LDO main loop and a transient response enhancement feedback circuit. MN4, MN5, MN6, MP7, and MP are high-voltage isolation devices capable of withstanding high input voltages. MP1, MP2, MP3, MP4, MP5, MP6, MN1, MN2, and MN3 are low-voltage devices used for signal amplification and logic control. Vb2 is the bias voltage terminal, providing a stable bias voltage to each high-voltage isolation tube, achieving isolation between high and low voltage regions, and ensuring that the low-voltage devices operate within a safe voltage range.

[0020] The error amplifier in the LDO main loop consists of a differential input pair of MP1 and MP2, and a current mirror load of MN1, MN2, and MN3. The gate of MP1 is connected to the feedback voltage Vfb, and the gate of MP2 is connected to the reference voltage Vref. The differential pair amplifies the difference between the feedback voltage and the reference voltage, and the control signal is output from the drain of MP2, which is the output terminal of the error amplifier. The power transistor MP is a high-voltage PMOS transistor, with its source connected to the input power supply VDD and its drain connected to the output voltage Vout. The feedback voltage divider unit consists of a first feedback resistor Rf1 and a second feedback resistor Rf2 connected in series. The upper end of Rf1 is connected to Vout, and the lower end is connected to the upper end of Rf2. The lower end of Rf2 is grounded. The connection point of the two resistors outputs the feedback voltage Vfb to the gate of MP1, forming a complete negative feedback voltage regulation loop.

[0021] In the transient response enhancement feedback circuit, the gate of the first high-voltage isolation transistor, MP7, is coupled to the output of the error amplifier. The source of MP7 is connected to the high-voltage power supply side, and its drain is connected to the intermediate node N2. The pull-up transistor MP6 is a low-voltage PMOS transistor, with its source connected to the power supply and its drain connected to the intermediate node N2. The intermediate node N2 is connected to the gate of MP6 through the first coupling capacitor C1. At the same time, the intermediate node N2 is also connected to the gate of the pull-down high-voltage transistor MN6 through the second coupling capacitor C2. The drain of MN6 is connected to the gate of the power transistor MP, and its source is grounded. The gate clamping unit consists of three PMOS transistors, MP3, MP4, and MP5, connected in series. Their sources and drains are connected in series between the power supply terminal and the gate of MP7. The gates are all connected to the reference voltage terminal. In steady state, they clamp the gate voltage of MP7, limiting its voltage fluctuation range.

[0022] When the LDO's load current switches from light load to heavy load, the output voltage Vout decreases, and the feedback voltage Vfb decreases accordingly. This decrease is transmitted through the negative feedback network to the negative input terminal of the error amplifier, i.e., the gate of MP1, causing a decrease in the gate voltage of MP1. Consequently, the output voltage of the error amplifier decreases, which in turn lowers the gate voltage of MP7. MP7's conduction capability increases, and the current flowing through the drain of MP7 increases rapidly, pulling up the voltage at the intermediate node N2. The voltage increase at N2 is transmitted to the gate of MP6 through the coupling effect of capacitor C1, causing the gate voltage of MP6 to increase synchronously. MP6 is a PMOS transistor, and its conduction capability weakens after the gate voltage increases, thus weakening the pull-up effect on node N2. This further pushes up the voltage at node N2, forming positive feedback to accelerate the response. Simultaneously, the voltage rise at node N2 is coupled to the gate of MN6 through capacitor C2, causing the gate voltage of MN6 to rise. This rapidly increases the conduction capability of MN6, creating a pull-down effect that discharges the gate capacitor of power transistor MP, causing the gate voltage of MP to drop rapidly. MP's conduction capability is then quickly enhanced, and the output current increases rapidly to match the heavy load requirements, effectively suppressing the undershoot of the output voltage. During this process, the clamping unit composed of MP3 to MP5 can accelerate the drop in the gate voltage of MP7, further shortening the response time and enhancing the transient response effect.

[0023] When the LDO's load current switches from heavy load to light load, the output voltage Vout rises, and the feedback voltage Vfb rises accordingly. This causes the gate voltage of MP1 to rise, and the output voltage of the error amplifier to rise, which in turn causes the gate voltage of MP7 to rise. MP7's conduction capability weakens, and the current flowing through MP7's drain terminal decreases rapidly, resulting in a drop in the voltage at intermediate node N2. This voltage drop at N2 is coupled to the gate of MP6 through capacitor C1, causing a synchronous decrease in MP6's gate voltage. This enhances MP6's conduction capability and strengthens its pull-up effect on node N2, further driving down the voltage at node N2. Simultaneously, the voltage drop at node N2 is coupled to the gate of MN6 through capacitor C2, causing a drop in MN6's gate voltage. MN6 quickly turns off, ceasing its pull-down effect on the gate of power transistor MP. The power transistor's gate voltage rises rapidly under the main loop regulation, and its conduction capability decreases rapidly, matching the light load requirements and effectively suppressing the overshoot of the output voltage. By cooperating with C1 and C2, the transient enhancement circuit can bypass the main error amplifier loop and directly and quickly adjust the gate of the power transistor, thus greatly improving the transient response speed of the LDO.

[0024] During steady-state operation, the error amplifier outputs a stable voltage, MP7 operates in a constant on state, the voltage at node N2 remains stable, there is no coupling current between C1 and C2, and both MP6 and MN6 maintain a stable operating state without causing additional interference to the gate of the power transistor. At the same time, the clamping unit composed of MP3 to MP5 clamps the gate voltage of MP7 within a reasonable range, ensuring the stability of steady-state operation and preventing malfunctions that could limit the load-carrying capacity.

[0025] Reference Figure 3 As shown, this circuit also includes a startup circuit, where MP1, MP4, MP7, and MP8 are high-voltage isolated devices, and MP2, MP3, MP5, MP6, MN1, MN2, MN3, MN4, MN5, and MN6 are low-voltage devices. During the LDO power-up process, the startup current source branch on the left is the first to conduct, generating a bias current that flows through the branch containing MN2. This generates a voltage across resistor R1, providing the bias voltage required to turn on the gate of MN4, causing MN4 to conduct. The error amplifier circuit is then biased and begins to operate, providing a bias voltage to the gate of the power transistor. The LDO gradually establishes a stable output voltage Vref. After the output voltage Vref is established, it is fed back to the power supply terminal of inverter INV1, and the enable signal VEN turns high. The enable signal controls the gate of MN1 to rise to the Vref voltage, MN1 turns on, pulls the gate of MN4 down to a low potential, turns off MN4, and the start-up circuit stops working to avoid consuming extra power consumption, while not affecting the normal steady-state operation of the main loop.

[0026] Reference Figure 4 and Figure 5 Comparing the test waveforms, the linear regulator without the transient response enhancement circuit exhibits a downshoot voltage of 0.76V when the load switches from light to heavy, and an overshoot voltage of 0.667V when the load switches from heavy to light. With the transient response enhancement circuit of this invention, the downshoot voltage drops to 0.335V when the load switches from light to heavy, and the overshoot voltage drops to 0.289V. This demonstrates that the transient response enhancement circuit significantly suppresses overshoot voltage, resulting in a substantial improvement in transient response performance and effectively preventing output voltage spikes from damaging downstream driver chips.

[0027] The terms "upper," "lower," "outer," "inner," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish relative positional relationships and are not necessarily qualitative. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0028] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-cost, fast transient response linear regulator circuit, comprising an LDO main loop module, wherein the LDO main loop module includes an error amplifier, a power transistor MP, and a feedback voltage divider unit, the feedback voltage divider unit acquiring the output voltage to generate a feedback voltage and inputting it into the error amplifier, and the output of the error amplifier controlling the gate of the power transistor MP to achieve voltage regulation; characterized in that: It also includes a transient response enhancement feedback circuit, which is coupled between the output terminal of the error amplifier and the gate terminal of the power transistor MP. The transient response enhancement feedback circuit includes a first high-voltage isolation transistor MP7, a pull-up transistor MP6, a pull-down high-voltage transistor MN6, a first coupling capacitor C1, a second coupling capacitor C2, and gate clamping units MP3, MP4, and MP5. The gate of the first high-voltage isolation transistor MP7 is coupled to the output of the error amplifier. The drain of the first high-voltage isolation transistor MP7 is connected to the intermediate node N2. The intermediate node N2 is coupled to the gate of the pull-up transistor MP6 through the first coupling capacitor C1. The intermediate node N2 is also coupled to the gate of the pull-down high-voltage transistor MN6 through the second coupling capacitor C2. The drain of the pull-down high-voltage transistor MN6 is coupled to the gate of the power transistor MP. The gate clamping units MP3, MP4, and MP5 are coupled between the gate of the first high-voltage isolation transistor MP7 and the power supply terminal. They are used to clamp the gate voltage of the first high-voltage isolation transistor MP7 in steady state and accelerate the rate of change of the gate voltage of the first high-voltage isolation transistor MP7 when the load current switches.

2. The low-cost, fast transient response linear regulator circuit as described in claim 1, characterized in that: The first high-voltage isolation transistor MP7, the pull-down high-voltage transistor MN6, and the power transistor MP are all high-voltage withstand devices. The input pair transistors, load transistors, and pull-up transistor MP6 inside the error amplifier are all low-voltage devices. The circuit is also equipped with a bias voltage terminal Vb2 to provide a stable bias voltage for each high-voltage isolation transistor to achieve high-voltage isolation.

3. The low-cost, fast transient response linear regulator circuit as described in claim 1, characterized in that: The first coupling capacitor C1 is used to couple the voltage change of the intermediate node N2 to the gate of the pull-up transistor MP6, so as to adjust the pull-up strength of the pull-up transistor MP6 to the intermediate node N2. The second coupling capacitor C2 is used to couple the voltage change of the intermediate node N2 to the gate of the pull-down high voltage transistor MN6, so as to control the pull-down action of the pull-down high voltage transistor MN6 to the gate of the power transistor MP.

4. The low-cost, fast transient response linear regulator circuit as described in claim 1, characterized in that: The gate clamping units MP3, MP4, and MP5 consist of three PMOS transistors connected in series. The source and drain of the three PMOS transistors are connected in series between the power supply terminal and the gate of the first high-voltage isolation transistor MP7. The gates are connected to the reference voltage terminal to form a steady-state clamping path.

5. The low-cost, fast transient response linear regulator circuit as described in claim 1, characterized in that: The error amplifier is a differential amplifier structure, including PMOS differential input pairs MP1 and MP2 and NMOS current mirror loads MN1, MN2 and MN3. One end of the differential input pair is connected to a reference voltage, and the other end is connected to the feedback voltage output by the feedback voltage divider unit.

6. The low-cost, fast transient response linear regulator circuit as described in claim 1, characterized in that: The feedback voltage divider unit includes a first feedback resistor Rf1 and a second feedback resistor Rf2 connected in series. The upper end of the first feedback resistor Rf1 is connected to the output voltage terminal, and the lower end is connected to the upper end of the second feedback resistor Rf2. The lower end of the second feedback resistor Rf2 is grounded. The connection node of the two resistors outputs the feedback voltage to the input terminal of the error amplifier.

7. The low-cost, fast transient response linear regulator circuit as described in claim 1, characterized in that: It also includes a startup circuit module, which includes a startup branch, a bias resistor R1 and an enable switch MN1. The startup branch is turned on when powered on and generates a bias voltage, driving the error amplifier to enter the working state. The enable switch MN1 is controlled by the output voltage feedback and turns off the startup branch after the circuit enters the steady state.

8. The low-cost, fast transient response linear regulator circuit as described in claim 7, characterized in that: The startup branch includes a startup current source and a startup transistor MN4. The gate of the startup transistor MN4 is grounded through a bias resistor R1. When powered on, the startup current source charges the bias resistor R1 to generate a startup voltage, which turns on the startup transistor MN4 and provides bias to the error amplifier. The enable switch MN1 is an NMOS transistor, and its gate is connected to the output voltage feedback signal processed by the inverter INV1. In steady state, the output voltage enables the switch MN1 to conduct, pulling the gate of the startup transistor MN4 down to ground potential to turn off the startup branch.

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