Low-dropout linear voltage regulator and enable control circuit therefor

Abstract

This disclosure provides an enable control circuit for a low-dropout linear regulator, comprising a voltage conversion circuit and a hysteresis comparator circuit. The voltage conversion circuit generates an internal enable signal based on an external enable signal and a power supply voltage. When the voltage value of the external enable signal is lower than the power supply voltage, the voltage value of the internal enable signal follows the change of the external enable signal. When the voltage value of the external enable signal is equal to or higher than the power supply voltage, the voltage value of the internal enable signal is equal to the power supply voltage, such that the quiescent current of the hysteresis comparator circuit is zero. The hysteresis comparator circuit is powered by the power supply voltage. The hysteresis comparator circuit generates an enable control signal based on the internal enable signal. When the voltage value of the internal enable signal rises to a first threshold, the enable control signal flips to a first level. When the voltage value of the internal enable signal falls to a second threshold, the enable control signal flips to a second level. The power supply voltage is higher than the first threshold. The first threshold is higher than the second threshold.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to an enable control circuit for a low-dropout linear regulator and a low-dropout linear regulator. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in integrated circuits to provide the power supply voltage required within the circuit. In some applications, low quiescent current is desirable in LDOs to reduce the power consumption of the integrated circuit. Summary of the Invention

[0003] The embodiments described herein provide an enable control circuit for a low-dropout linear regulator, and the low-dropout linear regulator itself.

[0004] According to a first aspect of this disclosure, an enable control circuit for a low-dropout linear regulator is provided. The enable control circuit includes a voltage conversion circuit and a hysteresis comparator circuit. The voltage conversion circuit is configured to generate an internal enable signal based on an external enable signal from an enable signal terminal and a power supply voltage from a power supply voltage terminal. When the voltage value of the external enable signal is lower than the power supply voltage, the voltage value of the internal enable signal follows the change of the external enable signal. When the voltage value of the external enable signal is equal to or higher than the power supply voltage, the voltage value of the internal enable signal is equal to the power supply voltage, such that the quiescent current of the hysteresis comparator circuit is zero. The hysteresis comparator circuit is powered by the power supply voltage. The hysteresis comparator circuit is configured to generate an enable control signal based on the internal enable signal. When the voltage value of the internal enable signal rises to a first threshold, the enable control signal flips from a second level to a first level. When the voltage value of the internal enable signal falls to a second threshold, the enable control signal flips from the first level to a second level. The power supply voltage is higher than the first threshold. The first threshold is higher than the second threshold. The enable control signal is used to enable the low-dropout linear regulator.

[0005] In some embodiments of this disclosure, the voltage conversion circuit includes a first transistor, a first resistor, and an internal load circuit. The control electrode of the first transistor is coupled to a first terminal of the first resistor and a power supply voltage terminal. The first electrode of the first transistor is coupled to a second terminal of the first resistor, the internal load circuit, and a hysteresis comparator circuit. The second electrode of the first transistor is coupled to an enable signal terminal. An internal enable signal is provided to the hysteresis comparator circuit from the first electrode of the first transistor.

[0006] In some embodiments of this disclosure, the resistance value of the first resistor is greater than ten times the on-resistance value of the first transistor in the switching on region.

[0007] In some embodiments of this disclosure, the resistance value of the first resistor is greater than one hundred times the on-resistance value of the first transistor in the switching on region.

[0008] In some embodiments of this disclosure, the resistance value of the first resistor is less than one-tenth of the on-resistance value of the first transistor in the saturation conduction region.

[0009] In some embodiments of this disclosure, the resistance value of the first resistor is less than one percent of the on-resistance value of the first transistor in the saturation conduction region.

[0010] In some embodiments of this disclosure, the internal load circuit includes a first current source. A first terminal of the first current source is coupled to a first electrode of a first transistor. A second terminal of the first current source is coupled to a second voltage terminal. The first current output by the first current source is less than one-tenth of the current flowing through the first resistor.

[0011] In some embodiments of this disclosure, the internal load circuit includes an internal load resistor. A first terminal of the internal load resistor is coupled to a first terminal of a first transistor. A second terminal of the internal load resistor is coupled to a second voltage terminal. The resistance value of the internal load resistor is greater than ten times the resistance value of the first resistor.

[0012] In some embodiments of this disclosure, the resistance value of the internal load resistor is greater than one hundred times the resistance value of the first resistor.

[0013] In some embodiments of this disclosure, the hysteresis comparator circuit includes: a second transistor to a ninth transistor. The control electrode of the second transistor is provided with an internal enable signal. The first electrode of the second transistor is coupled to a power supply voltage terminal. The second electrode of the second transistor is coupled to the first electrodes of the third transistor and the fourth transistor. The control electrode of the third transistor is coupled to the control electrode of the second transistor. The second electrode of the third transistor is coupled to the control electrodes of the fourth transistor, the fifth transistor, the seventh transistor, the eighth transistor, and the ninth transistor. The second electrode of the fourth transistor is coupled to a second voltage terminal. The control electrode of the fifth transistor is coupled to the control electrode of the second transistor. The first electrode of the fifth transistor is coupled to the second electrodes of the sixth transistor and the seventh transistor. The control electrode of the sixth transistor is coupled to the control electrode of the second transistor. The first electrode of the sixth transistor is coupled to a second voltage terminal. The second electrode of the seventh transistor is coupled to a power supply voltage terminal. The first electrode of the eighth transistor is coupled to a power supply voltage terminal. The second electrode of the eighth transistor is coupled to the second electrode of the ninth transistor and the output terminal of the hysteresis comparator circuit. The first electrode of the ninth transistor is coupled to the second voltage terminal.

[0014] In some embodiments of this disclosure, the second through fourth transistors and the eighth transistor are P-type transistors. The fifth through seventh transistors and the ninth transistor are N-type transistors. The second voltage terminal is grounded.

[0015] In some embodiments of this disclosure, the low-dropout linear regulator includes an enable control circuit, a bandgap reference circuit, and an error amplifier. When the enable control signal is at a second level, the bandgap reference circuit and the error amplifier are deactivated. When the enable control signal is at a first level, the bandgap reference circuit and the error amplifier are enabled.

[0016] According to a second aspect of this disclosure, a low-dropout linear regulator is provided. The low-dropout linear regulator includes an enable control circuit as described in the first aspect of this disclosure, a secondary regulator, a bandgap reference circuit, an error amplifier, a power regulator, a first feedback resistor, and a second feedback resistor. The secondary regulator is configured to convert an input voltage from an input voltage terminal into a supply voltage. The bandgap reference circuit is configured to generate a bandgap reference voltage based on the input voltage. The non-inverting input of the error amplifier is coupled to a first terminal of the first feedback resistor and a first terminal of the second feedback resistor. The inverting input of the error amplifier is coupled to the output of the bandgap reference circuit. The output of the error amplifier is coupled to the control terminal of the power regulator. The first terminal of the power regulator is coupled to the input voltage terminal. The second terminal of the power regulator is coupled to a second terminal of the first feedback resistor and the output voltage terminal. The second terminal of the second feedback resistor is coupled to a second voltage terminal. The output of the enable control circuit is coupled to the enable terminal of the bandgap reference circuit and the error amplifier. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0018] Figure 1 This is an exemplary circuit diagram of a low-dropout linear regulator;

[0019] Figure 2 This is an exemplary circuit diagram of a low-dropout linear regulator according to an embodiment of the present disclosure;

[0020] Figure 3 yes Figure 2 An exemplary circuit diagram of the enable control circuit in the example;

[0021] Figure 4 yes Figure 3 An exemplary circuit diagram of the hysteresis comparator circuit in the example;

[0022] Figure 5 It is used for Figure 3 Timing diagram of some signals of the enable control circuit;

[0023] Figure 6 It is used for Figure 3 A diagram showing the relationship between some signals in the enable control circuit;

[0024] Figure 7 This is a schematic block diagram of an enable control circuit according to an embodiment of the present disclosure;

[0025] Figure 8 yes Figure 7 An exemplary circuit diagram of the enable control circuit in the diagram; and

[0026] Figure 9 It is used for Figure 7 The timing diagram of some signals of the enable control circuit.

[0027] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0030] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0031] Figure 1 An exemplary circuit diagram of a low-dropout linear regulator (LDO) 100 is shown. The LDO converts an input voltage Vin into an output voltage Vout. The LDO includes a bandgap reference circuit BGR, an error amplifier EA, a power regulation transistor Mp, a first feedback resistor Rf1, and a second feedback resistor Rf2. The first feedback resistor Rf1 and the second feedback resistor Rf2 form a resistive feedback network. The resistive feedback network samples the LDO's output voltage Vout to obtain a feedback voltage Vfb. The error amplifier EA compares the feedback voltage Vfb with the bandgap reference voltage Vref generated by the bandgap reference circuit BGR. The difference between the two is amplified by the error amplifier EA and then used to control the current of the power regulation transistor Mp, thereby controlling the stability of the output voltage Vout. Figure 1 The power regulation transistor Mp in the diagram is a MOS transistor.

[0032] In practical applications, many LDOs have a high input voltage Vin. Although the drain-source voltage of a conventional high-voltage MOS transistor can withstand high voltage, its gate-source voltage can generally only withstand up to 5.5V. Therefore, in high-voltage products, it is usually necessary to convert the high-voltage input voltage Vin to a voltage below 5.5V for use.

[0033] Figure 2 An exemplary circuit diagram of a low-dropout linear regulator 200 according to an embodiment of the present disclosure is shown. Figure 1 On this basis, Figure 2 The LDO 200 shown adds a secondary regulator 210 to convert the high-voltage input voltage Vin into a low-voltage supply voltage Vcc. Furthermore, the LDO 200 adds an enable control circuit 220. The enable control circuit 220 is coupled to the enable signal terminal Ven. The output of the enable control circuit is coupled to the enable terminals of the bandgap reference circuit BRG and the error amplifier EA. When a low-level external enable signal Ven is input to the enable signal terminal Ven, the enable control circuit 220 outputs a low-level enable control signal Vo to control the bandgap reference circuit BRG and the error amplifier EA to stop operating, thereby controlling the LDO to enter standby mode and simultaneously turning off the power regulation transistor Mp. In this way, when the LDO does not need to provide an output voltage Vout, the overall power consumption of the LDO can be reduced. For example, when the LDO is outputting normally, the current flowing through the input voltage terminal Vin is 100uA, while when the LDO enters standby mode, the current flowing through the input voltage terminal Vin is 1uA.

[0034] Figure 3 Show Figure 2An exemplary circuit diagram of the enable control circuit 320 is shown in the example. The enable control circuit 320 includes: a first transistor M1, a first current source I1, and a hysteresis comparator circuit 321. The control electrode of the first transistor M1 is coupled to the power supply voltage terminal Vcc. The first electrode of the first transistor M1 is coupled to the first current source I1 and the hysteresis comparator circuit 321. The second electrode of the first transistor M1 is coupled to the enable signal terminal Ven. An internal enable signal Ven2 is provided from the first electrode of the first transistor M1 to the hysteresis comparator circuit 321.

[0035] The hysteresis comparator circuit 321 is configured to generate an enable control signal Vo based on the internal enable signal Ven2. Specifically, when the voltage value of the internal enable signal Ven2 rises to a first threshold VIH, the enable control signal Vo flips from a second level to a first level. When the voltage value of the internal enable signal Ven2 falls to a second threshold VIL, the enable control signal Vo flips from the first level to a second level. The power supply voltage Vcc is higher than the first threshold VIH. The first threshold VIH is higher than the second threshold VIL. Figure 3 In this context, Ivcc represents the static current inside the hysteresis comparator circuit 321.

[0036] Figure 4 Show Figure 3 An exemplary circuit diagram of the hysteresis comparator circuit 421 in the example is provided. The hysteresis comparator circuit 421 may include: second transistors M2 through M9. The control electrode of the second transistor M2 is provided with an internal enable signal Ven2. The first electrode of the second transistor M2 is coupled to the power supply voltage terminal Vcc. The second electrode of the second transistor M2 is coupled to the first electrodes of the third transistor M3 and the fourth transistor M4. The control electrode of the third transistor M3 is coupled to the control electrode of the second transistor M2. The second electrode of the third transistor M3 is coupled to the control electrodes of the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9. The second electrode of the fourth transistor M4 is coupled to a second voltage terminal V2. The control electrode of the fifth transistor M5 is coupled to the control electrode of the second transistor M2. The first electrode of the fifth transistor M5 is coupled to the second electrode of the sixth transistor M6 and the first electrode of the seventh transistor M7. The control electrode of the sixth transistor M6 is coupled to the control electrode of the second transistor M2. The first electrode of the sixth transistor M6 is coupled to the second voltage terminal V2. The second terminal of the seventh transistor M7 is coupled to the power supply voltage terminal Vcc. The first terminal of the eighth transistor M8 is coupled to the power supply voltage terminal Vcc. The second terminal of the eighth transistor M8 is coupled to the second terminal of the ninth transistor M9 and the output terminal of the hysteresis comparator circuit 421. The first terminal of the ninth transistor M9 is coupled to the second voltage terminal V2.

[0037] exist Figure 4In the example, transistors M2 through M4 and M8 are P-type transistors. Transistors M5 through M7 and M9 are N-type transistors. The second voltage terminal V2 is grounded.

[0038] Figure 5 Showing the use of Figure 3 The timing diagram of some signals of the enable control circuit. From Figure 5 As can be seen, when the voltage of the external enable signal Ven rises from 0V, the first transistor M1 is in the switching conduction region. Therefore, the voltage of the internal enable signal Ven2 is equal to the voltage of the external enable signal Ven, i.e., Ven2 = Ven. When the internal enable signal Ven2 reaches the first threshold VIH, the enable control signal Vo flips from low to high. After the external enable signal Ven continues to rise until Ven2 = Vcc - Vth, the first transistor M1 gradually enters the saturation conduction region, and the voltage of the internal enable signal Ven2 is clamped to Vcc - Vth by the power supply voltage Vcc. Here, Vth is the threshold voltage of the first transistor M1. Even when the external enable signal Ven continues to rise, the voltage of the internal enable signal Ven2 remains at Vcc - Vth.

[0039] Figure 6 The diagram shows the relationship between the internal enable signal Ven2 and the quiescent current Ivcc of the hysteresis comparator circuit. When the voltage of the internal enable signal Ven2 reaches the first threshold VIH, the quiescent current Ivcc of the hysteresis comparator circuit reaches its maximum value. As the voltage of the internal enable signal Ven2 continues to increase, the quiescent current Ivcc of the hysteresis comparator circuit gradually decreases. When the voltage of the internal enable signal Ven2 reaches the power supply voltage Vcc, the quiescent current Ivcc of the hysteresis comparator circuit decreases to zero. Figure 6 As can be seen from this, when the voltage of the internal enable signal Ven2 is equal to Vcc-Vth, the static current Ivcc of the hysteresis comparator circuit is greater than zero.

[0040] To reduce the quiescent current Ivcc of the hysteresis comparator circuit, embodiments of this disclosure propose... Figure 7 The enable control circuit 720 shown may include a voltage conversion circuit 722 and a hysteresis comparator circuit 721.

[0041] A voltage conversion circuit 722 can be coupled to an enable signal terminal Ven, a power supply voltage terminal Vcc, and a hysteresis comparator circuit 721. The voltage conversion circuit 722 can be configured to generate an internal enable signal Ven2 based on an external enable signal Ven from the enable signal terminal Ven and a power supply voltage Vcc from the power supply voltage terminal Vcc, and provide the internal enable signal Ven2 to the hysteresis comparator circuit 721. Specifically, when the voltage value of the external enable signal Ven is lower than the power supply voltage Vcc, the voltage value of the internal enable signal Ven2 follows the change of the external enable signal Ven. When the voltage value of the external enable signal Ven is equal to or higher than the power supply voltage Vcc, the voltage value of the internal enable signal Ven2 is equal to the power supply voltage Vcc, such that the quiescent current of the hysteresis comparator circuit 721 is zero.

[0042] The voltage conversion circuit 722 is coupled to and powered by the power supply voltage Vcc from the power supply voltage terminal Vcc. The hysteresis comparator circuit 721 is configured to generate an enable control signal Vo based on an internal enable signal Ven2. Specifically, when the voltage value of the internal enable signal Ven2 rises to a first threshold VIH, the enable control signal Vo flips from a second level to a first level. When the voltage value of the internal enable signal Ven2 falls to a second threshold VIL, the enable control signal Vo flips from the first level to a second level. The power supply voltage Vcc is higher than the first threshold VIH. The first threshold VIH is higher than the second threshold VIL. The enable control signal Vo is used to enable the low-dropout linear regulator. In some embodiments of this disclosure, the first level is high and the second level is low. In some embodiments of this disclosure, the hysteresis comparator circuit 721 includes a Schmitt trigger.

[0043] Figure 8 Show Figure 7 An exemplary circuit diagram of the enable control circuit 822 is provided. The voltage conversion circuit 822 may include: a first transistor M1, a first resistor R1, and an internal load circuit 8221. The control electrode of the first transistor M1 is coupled to the first terminal of the first resistor R1 and the power supply voltage terminal Vcc. The first electrode of the first transistor M1 is coupled to the second terminal of the first resistor R1, the internal load circuit 8221, and the hysteresis comparator circuit 821. The second electrode of the first transistor M1 is coupled to the enable signal terminal Ven. An internal enable signal Ven2 is provided from the first electrode of the first transistor M1 to the hysteresis comparator circuit 821.

[0044] In some embodiments of this disclosure, the resistance value of the first resistor R1 is greater than ten times the on-resistance value of the first transistor M1 in the switch-on region. Further, the resistance value of the first resistor R1 may be greater than one hundred times the on-resistance value of the first transistor M1 in the switch-on region. It can be considered that the resistance value of the first resistor R1 is much greater than the on-resistance value of the first transistor M1 in the switch-on region.

[0045] In some embodiments of this disclosure, the resistance value of the first resistor R1 is less than one-tenth of the on-resistance value of the first transistor M1 in the saturation conduction region. Further, the resistance value of the first resistor R1 is less than one-hundredth of the on-resistance value of the first transistor M1 in the saturation conduction region. It can be considered that the resistance value of the first resistor R1 is much smaller than the on-resistance value of the first transistor M1 in the saturation conduction region.

[0046] exist Figure 8 In the example, the internal load circuit 8221 may include: a first current source I1. The first terminal of the first current source I1 is coupled to the first electrode of the first transistor M1. The second terminal of the first current source I1 is coupled to the second voltage terminal V2. The first current output by the first current source I1 is less than the current value I flowing through the first resistor R1. R1 One-tenth of that. Furthermore, the first current output by the first current source I1 is less than the current value I flowing through the first resistor R1. R1 One percent. It can be assumed that the first current output by the first current source I1 is much smaller than the current value I flowing through the first resistor R1. R1 .

[0047] In some alternative embodiments of this disclosure, Figure 8 The first current source I1 can be replaced by an internal load resistor. The first terminal of the internal load resistor is coupled to the first terminal of the first transistor M1. The second terminal of the internal load resistor is coupled to the second voltage terminal V2. The resistance value of the internal load resistor is more than ten times the resistance value of the first resistor R1. Further, the resistance value of the internal load resistor can be more than one hundred times the resistance value of the first resistor R1. It can be considered that the resistance value of the internal load resistor is much larger than the resistance value of the first resistor R1, thus the current flowing through the internal load resistor is much smaller than the current value I flowing through the first resistor R1. R1 .

[0048] Figure 9 Showing the use of Figure 7 The timing diagram of some signals of the enable control circuit. From Figure 9 As can be seen, when the voltage of the external enable signal Ven rises from 0V, the first transistor is in the switching conduction region. The current I flowing through the first resistor R1... R1It equals the first current I1 from the first current source I1 and the current I flowing through the first transistor M1. M1 The sum. Because the first current I1 from the first current source I1 is compared to the current I flowing through the first resistor R1. R1 Negligible, therefore

[0049] Ven2=Ven+(Vcc-Ven) / (R1+Ron)×Ron (1),

[0050] Where Ron represents the on-resistance of the first transistor M1, R1 represents the resistance of the first resistor R1, Ven2 represents the voltage of the internal enable signal Ven2, Ven represents the voltage of the external enable signal Ven, and Vcc represents the voltage of the power supply voltage Vcc.

[0051] As described above, the resistance value of the first resistor R1 can be much larger than the on-resistance value of the first transistor M1 in the switching conduction region, thus equation (1) can be equivalent to Ven2 = Ven. As the voltage of the external enable signal Ven rises, the voltage of the internal enable signal Ven2 also rises. When the voltage of the internal enable signal Ven2 rises to Vcc - Vth (Vth represents the threshold voltage of the first transistor M1), the first transistor M1 gradually enters the saturation conduction region, and the impedance gradually increases until the on-resistance value Ron of the first transistor M1 is much larger than the resistance value R1 of the first resistor R1, at which point equation (1) can be equivalent to Ven2 = Vcc. When Ven2 = Vcc, the gate-source voltage of the first transistor M1 is equal to 0V, and the first transistor M1 is in the cutoff region. Reference Figure 9 As can be seen, Ven2 is ultimately approximately equal to Vcc. (Reference) Figure 6 As can be seen, there is no quiescent current in the hysteresis comparator circuit 721 under this condition, so the power consumption of the LDO is lower.

[0052] exist Figure 8 In the example, the second voltage terminal V2 is grounded. The first transistor M1 is an NMOS transistor. Those skilled in the art will understand that, based on the above inventive concept... Figure 8 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 8 The examples shown have different settings.

[0053] In summary, the enable control circuit for a low-dropout linear regulator according to embodiments of this disclosure enables the maximum voltage value of the internal enable signal to reach the power supply voltage, thereby reducing the quiescent current of the hysteresis comparator circuit in the enable control circuit to zero, thus reducing the power consumption of the low-dropout linear regulator. The low-dropout linear regulator according to embodiments of this disclosure can enter a standby state under the control of an external enable signal to further reduce power consumption.

[0054] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0055] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0056] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. An enable control circuit for a low-dropout linear regulator, comprising: Voltage conversion circuit and hysteresis comparator circuit, The voltage conversion circuit is configured to generate an internal enable signal based on an external enable signal from an enable signal terminal and a power supply voltage from a power supply voltage terminal; wherein, when the voltage value of the external enable signal is lower than the power supply voltage, the voltage value of the internal enable signal follows the change of the external enable signal; and when the voltage value of the external enable signal is equal to or higher than the power supply voltage, the voltage value of the internal enable signal is equal to the power supply voltage such that the quiescent current of the hysteresis comparator circuit is zero. The hysteresis comparator circuit is powered by the power supply voltage and is configured to: generate an enable control signal based on the internal enable signal; wherein, when the voltage value of the internal enable signal rises to a first threshold, the enable control signal flips from a second level to a first level; and when the voltage value of the internal enable signal drops to a second threshold, the enable control signal flips from the first level to the second level. Wherein, the power supply voltage is higher than the first threshold, the first threshold is higher than the second threshold, and the enable control signal is used to enable the low dropout linear regulator; The voltage conversion circuit includes: a first transistor, a first resistor, and an internal load circuit. Wherein, the control electrode of the first transistor is coupled to the first terminal of the first resistor and the power supply voltage terminal, the first electrode of the first transistor is coupled to the second terminal of the first resistor, the internal load circuit and the hysteresis comparator circuit, the second electrode of the first transistor is coupled to the enable signal terminal, and the internal enable signal is provided from the first electrode of the first transistor to the hysteresis comparator circuit.

2. The enable control circuit according to claim 1, wherein, The resistance value of the first resistor is more than ten times the on-resistance value of the first transistor in the switching conduction region.

3. The enable control circuit according to claim 1 or 2, wherein, The resistance value of the first resistor is less than one-tenth of the on-resistance value of the first transistor in the saturation conduction region.

4. The enable control circuit according to claim 1 or 2, wherein, The internal load circuit includes: a first current source, Wherein, the first terminal of the first current source is coupled to the first electrode of the first transistor, the second terminal of the first current source is coupled to the second voltage terminal, and the first current output by the first current source is less than one-tenth of the current value flowing through the first resistor.

5. The enable control circuit according to claim 1 or 2, wherein, The internal load circuit includes: an internal load resistor. Wherein, the first end of the internal load resistor is coupled to the first terminal of the first transistor, the second end of the internal load resistor is coupled to the second voltage terminal, and the resistance value of the internal load resistor is more than ten times the resistance value of the first resistor.

6. The enable control circuit according to claim 1, wherein, The hysteresis comparator circuit includes: a second transistor to a ninth transistor. The control electrode of the second transistor is provided with the internal enable signal, the first electrode of the second transistor is coupled to the power supply voltage terminal, and the second electrode of the second transistor is coupled to the first electrode of the third transistor and the first electrode of the fourth transistor. The control electrode of the third transistor is coupled to the control electrode of the second transistor, and the second electrode of the third transistor is coupled to the control electrode of the fourth transistor, the second electrode of the fifth transistor, the control electrode of the seventh transistor, the control electrode of the eighth transistor, and the control electrode of the ninth transistor. The second terminal of the fourth transistor is coupled to the second voltage terminal; The control electrode of the fifth transistor is coupled to the control electrode of the second transistor, and the first electrode of the fifth transistor is coupled to the second electrode of the sixth transistor and the first electrode of the seventh transistor; The control electrode of the sixth transistor is coupled to the control electrode of the second transistor, and the first electrode of the sixth transistor is coupled to the second voltage terminal; The second terminal of the seventh transistor is coupled to the power supply voltage terminal; The first terminal of the eighth transistor is coupled to the power supply voltage terminal, and the second terminal of the eighth transistor is coupled to the second terminal of the ninth transistor and the output terminal of the hysteresis comparator circuit. The first terminal of the ninth transistor is coupled to the second voltage terminal.

7. The enable control circuit according to claim 6, wherein, The second to the fourth and eighth transistors are P-type transistors, the fifth to the seventh and the ninth transistors are N-type transistors, and the second voltage terminal is grounded.

8. The enable control circuit according to claim 1, wherein, The low-dropout linear regulator includes: an enable control circuit, a bandgap reference circuit, and an error amplifier. Specifically, when the enable control signal is at the second level, the bandgap reference circuit and the error amplifier stop working; when the enable control signal is at the first level, the bandgap reference circuit and the error amplifier are enabled.

9. A low-dropout linear regulator, comprising an enable control circuit according to any one of claims 1 to 8, a secondary regulator, a bandgap reference circuit, an error amplifier, a power adjustment transistor, a first feedback resistor, and a second feedback resistor. in, The secondary regulator is configured to convert the input voltage from the input voltage terminal into the power supply voltage; The bandgap reference circuit is configured to generate a bandgap reference voltage based on the input voltage; The non-inverting input of the error amplifier is coupled to the first terminal of the first feedback resistor and the first terminal of the second feedback resistor; the inverting input of the error amplifier is coupled to the output terminal of the bandgap reference circuit; and the output terminal of the error amplifier is coupled to the control electrode of the power adjustment transistor. The first terminal of the power regulating transistor is coupled to the input voltage terminal, and the second terminal of the power regulating transistor is coupled to the second terminal of the first feedback resistor and the output voltage terminal; The second terminal of the second feedback resistor is coupled to the second voltage terminal; The output of the enable control circuit is coupled to the enable terminal of the bandgap reference circuit and the error amplifier.

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