Zero-pole load-following compensation low-dropout linear regulator and circuit thereof

Abstract

The application belongs to the field of electronic devices, and discloses a low-dropout linear voltage regulator with zero-pole load following compensation and a circuit thereof, which comprises a low-dropout linear voltage regulator circuit, a current sampling circuit and a resistance-capacitance network circuit connected with each other; the current sampling circuit is connected with a power supply end of the low-dropout linear voltage regulator circuit and an output end of an error amplifier of the low-dropout linear voltage regulator circuit; and the resistance-capacitance network circuit is connected with a negative input end of the error amplifier of the low-dropout linear voltage regulator circuit, an output end of the low-dropout linear voltage regulator circuit and connection lines of two feedback resistors of the low-dropout linear voltage regulator circuit. The compensation position is adapted to the load, and the adjustment degree is high. Even if other additional zero-pole points exist near the main pole of the error amplifier to accelerate the phase drop of the circuit, the phase starting point of the load following compensation is near 0°, so that the compatible phase or gain attenuation range is larger, and the stability of the system is ensured.

Description

Technical Field

[0001] This invention belongs to the field of electronic devices and relates to a low dropout linear regulator with zero-pole load following compensation and its circuit. Background Technology

[0002] Low-dropout regulators (LDOs) are an important component of power management circuits, offering advantages such as high power supply rejection ratio and low noise compared to other types of power supply circuits. An LDO circuit internally includes a reference voltage source, an error amplifier, a P-channel MOSFET, and two feedback resistors. Externally, it includes a load capacitor and a load resistor. The LDO circuit relies on a feedback loop to regulate the current of the P-channel MOSFET, thereby controlling the output voltage to stabilize near the reference voltage source.

[0003] When the load on an LDO circuit increases from light to heavy, the load resistance decreases, causing pole shifts. This results in a gain above 0dB at the secondary dominant pole of the LDO loop (typically the dominant pole of the error amplifier). If the parasitic resistance of the load capacitor is zero, the phase across the bandwidth approaches -180°, leading to poor or unstable system stability. If the parasitic resistance of the load capacitor is not zero, phase compensation can be achieved near the secondary dominant pole of the LDO loop using appropriate values ​​of the parasitic resistance and the load capacitance, bringing the phase across the bandwidth back to around -90° and improving system stability. However, in practical applications, LDO circuits often have other complex zeros and poles near the secondary dominant pole of the LDO loop. These zeros and poles typically accelerate the decrease in gain and phase, making the LDO circuit highly susceptible to instability. In such cases, the compensation effect of the parasitic resistance of the load capacitor is insignificant or even impossible. Furthermore, the load capacitance value affects the dominant pole frequency, the parasitic resistance is greatly influenced by the load capacitor manufacturing process, and the zero point is simultaneously affected by both the parasitic resistance and the load capacitance value, making adjustment highly limited. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a zero-pole load-following compensated low-dropout linear regulator and its circuit.

[0005] To achieve the above objectives, the present invention employs the following technical solution:

[0006] In a first aspect, the present invention provides a zero-pole load-following compensated low-dropout linear regulator circuit, comprising a low-dropout linear regulator circuit and a current sampling circuit and a resistor-capacitor (RC) network circuit interconnected thereto; the current sampling circuit is connected to the power supply terminal of the low-dropout linear regulator circuit and the output terminal of the error amplifier of the low-dropout linear regulator circuit; the RC network circuit is connected to the positive input terminal of the error amplifier of the low-dropout linear regulator circuit, the output terminal of the low-dropout linear regulator circuit, and the connection line of the two feedback resistors of the low-dropout linear regulator circuit; the current sampling circuit is used to adjust the frequency and gain of the zeros and poles of the RC network circuit, and to adjust the voltage change amplitude of the positive input terminal of the error amplifier of the low-dropout linear regulator circuit through the RC network circuit; the RC network circuit is used to generate zero-pole pairs unaffected by load changes.

[0007] Optionally, the current sampling circuit includes a sampling P-channel MOSFET M2 and a source negative feedback resistor R1; the source of the sampling P-channel MOSFET M2 is connected to the power supply terminal of the low dropout linear regulator circuit through the source negative feedback resistor R1, the gate of the sampling P-channel MOSFET M2 is connected to the output terminal of the error amplifier of the low dropout linear regulator circuit, and the drain of the sampling P-channel MOSFET M2 is connected to the RC network circuit.

[0008] Optionally, the RC network circuit includes a first resistor R2, a second resistor R3, a first capacitor C1, and a second capacitor C2; one end of the first resistor R2 is grounded, and the other end is connected to one end of the second capacitor C2 and the drain of the sampling P-channel MOSFET M2; the other end of the second capacitor C2 is connected to the positive input terminal of the error amplifier of the low dropout linear regulator circuit, one end of the first capacitor C1, and one end of the second resistor R3; the other end of the first capacitor C1 is connected to the output terminal of the low dropout linear regulator circuit, and the other end of the second resistor R3 is connected to the connection line of the two feedback resistors of the low dropout linear regulator circuit.

[0009] Optionally, the capacitance values ​​of both the first capacitor C1 and the second capacitor C2 are less than 10pF.

[0010] Optionally, the low-dropout linear regulator circuit includes a reference voltage source VREF, an error amplifier, a P-channel MOSFET M1, and a first feedback resistor R. FB1 Second feedback resistor R FB2 Load capacitor C L The power supply terminal and output terminal; the drain and output terminal of the P-channel MOSFET M1 and the first feedback resistor R FB1 One end of the P-channel MOSFET M1 is connected to the power supply terminal, and the gate of the P-channel MOSFET M1 is connected to the output terminal of the error amplifier; the first feedback resistor R FB1 The other end is connected to the first feedback resistor R FB1Grounding, first feedback resistor R FB1 With the second feedback resistor R FB2 The connecting wire between them is connected to the positive input terminal of the error amplifier; the reference voltage source V REF The output terminal is connected to the negative input terminal of the error amplifier; the load capacitor C L One end is grounded, and the other end is connected to the output terminal.

[0011] Optionally, the sampling P-channel MOS transistor M2 and the P-channel MOS transistor M1 have the same gate-source voltage and gate length.

[0012] Optionally, the load capacitor C L The capacitance is greater than 1μF.

[0013] In a second aspect, the present invention provides a zero-pole load follower compensated low-dropout linear regulator, wherein the zero-pole load follower compensated low-dropout linear regulator is packaged using the aforementioned zero-pole load follower compensated low-dropout linear regulator circuit.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] This invention relates to a zero-pole load-following compensated low-dropout linear regulator circuit. By adding an interconnected current sampling circuit and an RC network circuit to the existing low-dropout linear regulator circuit, and adjusting the RC network circuit, zero-pole pairs are introduced near the system's cross-bandwidth. This reduces the rate of gain and phase drop with frequency. Furthermore, since the zero-pole pair positions are unaffected by load changes, system stability is improved under different load conditions. Moreover, the combination of the RC network and the current sampling circuit avoids the influence of large load capacitance on the rate of current change, further optimizing the system response speed under different operating conditions. Ultimately, the compensation position adapts to the load, offering high degree of adjustment freedom. In practical circuits, even if additional zero-pole acceleration circuits exist near the dominant pole of the error amplifier, the load-following compensation phase starting point is located near 0°, resulting in a wider compatible phase or gain attenuation range and ensuring system stability. Attached Figure Description

[0016] Figure 1 This is a circuit topology diagram for a low-dropout linear regulator.

[0017] Figure 2 The loop ideal Bode plot for a low dropout linear regulator circuit without considering the parasitic resistance of the load capacitor.

[0018] Figure 3 The ideal Bode plot of the loop considering the parasitic resistance of the load capacitor for a low dropout linear regulator circuit.

[0019] Figure 4 This is a circuit topology diagram of a zero-pole load-following compensated low-dropout linear regulator according to an embodiment of the present invention.

[0020] Figure 5 This is the ideal loop Bode plot of the zero-pole load-following compensated low-dropout linear regulator circuit under light load in an embodiment of the present invention.

[0021] Figure 6 This is the loop ideal Bode plot of the zero-pole load-following compensated low-dropout linear regulator circuit under heavy load in an embodiment of the present invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] The present invention will now be described in further detail with reference to the accompanying drawings:

[0025] See Figure 1 A conventional low-dropout linear regulator contains an internal reference voltage source V. REF Error amplifier, P-channel MOSFET M1, first feedback resistor R FB1 With the second feedback resistor R FB2 The LDO has an external load capacitor C. L With load resistance R L wait.

[0026] Inside the low-dropout linear regulator: the drain of the P-channel MOSFET M1 is connected to the output terminal of the low-dropout linear regulator, and the output voltage is V. OUTThe source of the P-channel MOSFET M1 is connected to the power supply terminal, and the gate is connected to the output terminal V of the error amplifier. E First feedback resistor R FB1 With the second feedback resistor R FB2 Connected in series between the output terminal and ground, the voltage V between them is... FB Used as the positive input of the error amplifier; reference voltage source V REF The output serves as the negative input of the error amplifier. External to the low-dropout linear regulator, the load capacitor C... L With load capacitance and parasitic resistance R ESR After being connected in series with the load resistor R L It is connected in parallel between the output and ground.

[0027] The low-dropout linear regulator controls the output voltage V by adjusting the current of the P-channel MOSFET M1 through a feedback loop. OUT Stabilized at the reference voltage source V REF Nearby. If the load resistance R L If the voltage decreases, the output voltage V OUT The decrease led to V FB The voltage drops due to the reference voltage source V. REF Since the error amplifier output remains unchanged, the output current of the P-channel MOSFET M1 decreases, causing the output voltage V to drop. OUT Rebound to the reference voltage source V REF Similarly, the load resistance R L Increase the output voltage V OUT As the voltage increases, the current of the P-channel MOSFET M1 controlled by the loop decreases, causing the output voltage V to rise. OUT The voltage drops to the reference voltage source V REF .

[0028] The zero-pole distribution of a low-dropout linear regulator loop determines its response characteristics to load changes. Assume A... EA For the low-frequency gain of the error amplifier, P EA G is the dominant pole of the error amplifier (secondary dominant pole of the LDO loop). M1 Given the transconductance of the P-channel MOSFET M1, the open-loop gain H1(s) is:

[0029]

[0030] Typically, the load capacitor C L Above 1 μF, the dominant pole frequency P0 = 1 / (R) L +R ESR C L Secondary principal pole frequency P EA It is at least 100 times greater than P0. Load capacitance and parasitic resistance R ESR The system is given a zero point Z0 = 1 / RESR C L .

[0031] See Figure 2 and 3 When the load on the low-dropout linear regulator increases from light to heavy, the load resistance R... L The change from large to small causes the pole P0 to move to P0', resulting in P EA The gain is above 0dB. At this point, if the parasitic resistance R of the load capacitance... ESR If the phase at the bandwidth is zero, the phase is close to -180°, resulting in poor or unstable system stability. If the load capacitance parasitic resistance R... ESR If it is not zero, then a suitable load capacitance parasitic resistance R can be used. ESR The resistance value and the load capacitance C L The capacitance value in P EA Phase compensation is implemented nearby to bring the phase back to around -90° at the crossing bandwidth, thereby improving system stability.

[0032] However, in real systems, P EA There may be other complex zeros and poles nearby, and these types of zeros and poles usually accelerate the decrease in gain and phase, making the system very prone to instability. In this case, the parasitic resistance R of the load capacitance will increase. ESR The compensation effect is not obvious, or even impossible. Furthermore, the load capacitance C... L The value of R will affect the dominant pole frequency, load capacitance, and parasitic resistance. ESR Load capacitor C L The process has a significant impact, and the zero point is simultaneously affected by the parasitic resistance R of the load capacitance. ESR With load capacitance C L The influence of this makes regulation quite limited.

[0033] Based on the above, see Figure 4 In one embodiment of the present invention, a zero-pole load-following compensated low-dropout linear regulator circuit is provided, which allows the compensation zero point to follow the change of the dominant pole during load changes, thereby improving system stability. Specifically, the zero-pole load-following compensated low-dropout linear regulator circuit includes a low-dropout linear regulator circuit and interconnected current sampling circuit and RC network circuit.

[0034] The current sampling circuit is connected to the power supply terminal of the low-dropout linear regulator circuit and the output terminal of the error amplifier of the low-dropout linear regulator circuit; the RC network circuit is connected to the negative input terminal of the error amplifier of the low-dropout linear regulator circuit, the output terminal of the low-dropout linear regulator circuit, and the connection lines of the two feedback resistors of the low-dropout linear regulator circuit.

[0035] The current sampling circuit is used to adjust the frequency and gain of the zeros and poles of the RC network circuit, and to adjust the voltage variation amplitude of the positive input terminal of the error amplifier of the low dropout linear regulator circuit through the RC network circuit, thereby improving the stability and response speed of the regulator; the RC network circuit is used to generate zero-pole pairs that are not affected by load changes, thereby reducing the rate at which the gain of the system decreases with frequency near the cross-bandwidth, and thus compensating for the system phase margin, thereby improving the system stability.

[0036] Specifically, the zero-pole load-following compensated low-dropout linear regulator circuit of this invention no longer considers the parasitic resistance R of the load capacitance, based on the structure of the traditional low-dropout linear regulator circuit. ESR Add a current sampling circuit, and connect the first feedback resistor R to the positive input of the error amplifier. FB1 With the second feedback resistor R FB2 intermediate node V A An RC network is inserted between the two to form a feedforward circuit. Finally, the feedforward circuit signal is superimposed with the original loop signal to form a controllable zero.

[0037] This invention presents a zero-pole load-following compensation low-dropout linear regulator circuit. By incorporating an interconnected current sampling circuit and an RC network circuit into an existing low-dropout linear regulator circuit, the current sampling circuit adjusts the RC network circuit to generate zero-pole pairs near the system's cross-bandwidth, unaffected by load changes. This reduces the rate of gain and phase drop with frequency near the cross-bandwidth, improving system stability under different load conditions. Furthermore, combining the RC network with the current sampling circuit avoids the influence of large load capacitance on the current change rate of the P-channel MOSFET M1, further optimizing the system response speed under different operating conditions. Ultimately, the compensation position adaptively changes with the load, offering high adjustment freedom. In practical circuits, even if additional zero-pole acceleration circuits exist near the dominant pole of the error amplifier, the load-following compensation phase starting point is located near 0°, resulting in a wider compatible phase or gain attenuation range and ensuring system stability.

[0038] In one possible implementation, the current sampling circuit includes a sampling P-channel MOSFET M2 and a source negative feedback resistor R1; the source of the sampling P-channel MOSFET M2 is connected to the power supply terminal of the low dropout linear regulator circuit through the source negative feedback resistor R1, the gate of the sampling P-channel MOSFET M2 is connected to the output terminal of the error amplifier of the low dropout linear regulator circuit, and the drain of the sampling P-channel MOSFET M2 is connected to the RC network circuit.

[0039] In one possible implementation, the RC network circuit includes a first resistor R2, a second resistor R3, a first capacitor C1, and a second capacitor C2; one end of the first resistor R2 is grounded, and the other end is connected to one end of the second capacitor C2 and the drain of the sampling P-channel MOSFET M2; the other end of the second capacitor C2 is connected to the negative input terminal of the error amplifier of the low dropout linear regulator circuit, one end of the first capacitor C1, and one end of the second resistor R3; the other end of the first capacitor C1 is connected to the output terminal of the low dropout linear regulator circuit, and the other end of the second resistor R3 is connected to the connection line of the two feedback resistors of the low dropout linear regulator circuit.

[0040] Optionally, the capacitance values ​​of both the first capacitor C1 and the second capacitor C2 are less than 10pF, and can be less than 0.1pF. EA The nearby low-frequency band is open-circuited, at which point V FB ≈V A The loop gain is the same as that of a traditional low-dropout linear regulator circuit.

[0041] In one possible implementation, the low-dropout linear regulator circuit includes a reference voltage source VREF, an error amplifier, a P-channel MOSFET M1, and a first feedback resistor R. FB1 Second feedback resistor R FB2 Load capacitor C L The power supply terminal and output terminal; the drain and output terminal of the P-channel MOSFET M1 and the first feedback resistor R FB1 One end of the P-channel MOSFET M1 is connected to the power supply terminal, and the gate of the P-channel MOSFET M1 is connected to the output terminal of the error amplifier; the first feedback resistor R FB1 The other end is connected to the first feedback resistor R FB1 Grounding, first feedback resistor R FB1 With the second feedback resistor R FB2 The connecting wire between them is connected to the positive input terminal of the error amplifier; the reference voltage source V REF The output terminal is connected to the negative input terminal of the error amplifier; the load capacitor C L One end is grounded, and the other end is connected to the output terminal.

[0042] In one possible implementation, the sampling P-channel MOS transistor M2 and the P-channel MOS transistor M1 have the same gate-source voltage and gate length.

[0043] Specifically, based on the above design, the current ratio of the sampling P-channel MOSFET M2 and the gate width ratio of the P-channel MOSFET M1 are made the same. This allows the sampling P-channel MOSFET M2 to replicate the current change of the P-channel MOSFET M1 under a small bias current, reducing circuit power consumption. Furthermore, this design is applied to different load capacitors C. LUnder these conditions, a strong voltage signal can be fed back to the positive input terminal of the error amplifier, thereby improving the circuit response speed.

[0044] In one possible implementation, the load capacitor C L The capacitance is greater than 1μF.

[0045] At a frequency close to 0.1*P EA At that time, the load capacitance C L Approximate short circuit, let G M2 To sample the overall transconductance of the P-channel MOSFET M2 and R1, then V E To V FB The gain H2(s) can be approximated as follows:

[0046]

[0047] See Figure 5 and 6 Ideally, under light load, the loop crossing bandwidth is low, and the first and second terms of H2(s) intersect in the Bode plot to first form a coincident double zero point Z0. 2 Then, a pole P1 is formed. Under heavy load, the loop crossing bandwidth increases, and the first and second terms of H2(s) intersect in the Bode plot to form a zero Z1. Due to the influence of the zero, the phase of H2(s) can be compensated back to 0° under different loads. In the Bode plot, it is equivalent to a zero that can follow the movement of the dominant pole, which provides better compensation for loop stability under a large load range.

[0048] Compared to the traditional method that relies on load capacitance and parasitic resistance R ESR The compensation method of this invention, in the zero-pole load-following compensation low-dropout linear regulator circuit, determines the starting point of the zero-point compensation frequency by the second resistor R2, the first capacitor C1, and the second capacitor C2. The compensation position adaptively changes with the load, offering high adjustment freedom. Furthermore, the small capacitance values ​​of the first capacitor C1 and the second capacitor C2 facilitate integration into a chip. In practical circuits, even in P... EA There are other additional zero-pole acceleration circuits nearby that reduce phase, but because the phase starting point of the load follower compensation is near 0°, the range of phase or gain attenuation that can be accommodated is also greater.

[0049] In another embodiment of the present invention, a zero-pole load follower compensated low-dropout linear regulator is provided. Specifically, the zero-pole load follower compensated low-dropout linear regulator is obtained by packaging the above-mentioned zero-pole load follower compensated low-dropout linear regulator circuit.

[0050] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A zero-pole load-following compensated low-dropout linear regulator circuit, characterized in that, This includes a low-dropout linear regulator circuit and interconnected current sampling circuits and RC network circuits; The current sampling circuit is connected to the power supply terminal of the low-dropout linear regulator circuit and the output terminal of the error amplifier of the low-dropout linear regulator circuit; the RC network circuit is connected to the positive input terminal of the error amplifier of the low-dropout linear regulator circuit, the output terminal of the low-dropout linear regulator circuit, and the connection lines of the two feedback resistors of the low-dropout linear regulator circuit. The current sampling circuit is used to adjust the frequency and gain of the zeros and poles of the RC network circuit, and to adjust the voltage variation at the positive input terminal of the error amplifier of the low dropout linear regulator circuit through the RC network circuit; the RC network circuit is used to generate zero-pole pairs that are unaffected by load changes. The current sampling circuit includes a sampling P-channel MOSFET M2 and a source negative feedback resistor R1; The source of the sampling P-channel MOSFET M2 is connected to the power supply terminal of the low dropout linear regulator circuit through the source negative feedback resistor R1. The gate of the sampling P-channel MOSFET M2 is connected to the output terminal of the error amplifier of the low dropout linear regulator circuit. The drain of the sampling P-channel MOSFET M2 is connected to the RC network circuit. The resistor-capacitor network circuit includes a first resistor R2, a second resistor R3, a first capacitor C1, and a second capacitor C2; One end of the first resistor R2 is grounded, and the other end is connected to one end of the second capacitor C2 and the drain of the sampling P-channel MOSFET M2; the other end of the second capacitor C2 is connected to the positive input terminal of the error amplifier of the low dropout linear regulator circuit, one end of the first capacitor C1, and one end of the second resistor R3; the other end of the first capacitor C1 is connected to the output terminal of the low dropout linear regulator circuit, and the other end of the second resistor R3 is connected to the connection line of the two feedback resistors of the low dropout linear regulator circuit.

2. The zero-pole load-following compensated low-dropout linear regulator circuit according to claim 1, characterized in that, The capacitance values ​​of the first capacitor C1 and the second capacitor C2 are both less than 10pF.

3. The zero-pole load-following compensated low-dropout linear regulator circuit according to claim 1, characterized in that, The low-dropout linear regulator circuit includes a reference voltage source VREF, an error amplifier, a P-channel MOSFET M1, and a first feedback resistor R. FB1 Second feedback resistor R FB2 Load capacitor C L Power supply terminal and output terminal; The drain and output terminals of the P-channel MOSFET M1 and the first feedback resistor R FB1 One end of the P-channel MOSFET M1 is connected to the power supply terminal, and the gate of the P-channel MOSFET M1 is connected to the output terminal of the error amplifier; the first feedback resistor R FB1 The other end is connected to the second feedback resistor R FB2 Grounding, first feedback resistor R FB1 With the second feedback resistor R FB2 The connecting wire between them is connected to the positive input terminal of the error amplifier; the reference voltage source V REF The output terminal is connected to the negative input terminal of the error amplifier; the load capacitor C L One end is grounded, and the other end is connected to the output terminal.

4. The zero-pole load-following compensated low-dropout linear regulator circuit according to claim 3, characterized in that, The sampling P-channel MOS transistor M2 and P-channel MOS transistor M1 have the same gate-source voltage and gate length.

5. The zero-pole load-following compensated low-dropout linear regulator circuit according to claim 3, characterized in that, The load capacitor C L The capacitance is greater than 1μF.

6. A zero-pole load-following compensated low-dropout linear regulator, characterized in that, The zero-pole load-following compensated low-dropout linear regulator is packaged using the zero-pole load-following compensated low-dropout linear regulator circuit described in any one of claims 1 to 5.

Images