Power supply circuit, power supply method and power management chip

Abstract

Embodiments of this disclosure provide a power supply circuit, a power supply method, and a power management chip, including: a source follower circuit, a low-dropout linear regulator circuit, and a switching circuit. The source follower circuit includes at least a plurality of transistors connected in series. The switching circuit is configured to turn off when a first control signal is received, and the source follower circuit outputs a first voltage signal to power the power management chip. When a second control signal is received, the switching circuit turns on, controls at least one transistor of the source follower circuit to turn off, and the source follower circuit outputs a second voltage signal. The power supply circuit then switches to the low-dropout linear regulator circuit to power the power management chip. The second voltage signal is less than the first voltage signal, so that when the low-dropout linear regulator circuit is on, the voltage signal output by the source follower circuit is less than the voltage signal output by the low-dropout linear regulator, and the power management chip is powered through the low-dropout linear regulator circuit.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology and related technical fields, specifically to a power supply circuit, power supply method, and power management chip suitable for a power management chip. Background Technology

[0002] In power management chips, a source-following power supply circuit is required as part of the overall chip power supply. Before the low dropout regulator (LDO) starts up, the power management chip is powered by the source-following power supply circuit. After the low dropout regulator starts up, the power management chip is powered by the voltage output by the low dropout regulator.

[0003] Traditional source-follower (SFL) power supply circuits typically use a Zener diode and an NMOS transistor to generate the SFL output. However, this method generally results in a fixed operating voltage, dependent on the Zener diode's performance. To ensure the LDO provides power to the power management chip after startup, the circuit only switches to the LDO when its output voltage is higher than the SFL's output voltage. When the power management chip requires a lower operating voltage, a series NMOS transistor is used instead of the Zener diode, making the SFL's output voltage lower than the LDO's. However, due to the significant voltage drift caused by the NMOS transistor's process angle and temperature during SFL-based output, the SFL output voltage can sometimes exceed the LDO's output voltage, failing to meet the requirement of the LDO providing power after startup.

[0004] Therefore, based on the problems existing in the prior art, a source follower power supply circuit is proposed to ensure that the source follower output voltage is lower than the LDO output voltage at all temperatures and process angles, thus guaranteeing that the chip is powered by the LDO output voltage. Summary of the Invention

[0005] The embodiments described herein provide a power supply circuit, power supply method, and power management chip for a power management chip, addressing the problems existing in the prior art.

[0006] According to a first aspect of this disclosure, a power supply circuit for a power management chip is provided, comprising: a source follower circuit, a low dropout linear regulator circuit, and a switching circuit, wherein the source follower circuit comprises at least a plurality of transistors connected in series.

[0007] The switching circuit is configured such that when a first control signal is received, the switching circuit turns off, the source follower circuit outputs a first voltage signal, and the source follower circuit supplies power to the power management chip; when a second control signal is received, the switching circuit turns on, the switching circuit controls at least one transistor of the source follower circuit to turn off, the source follower circuit outputs a second voltage signal, and the power supply circuit switches to the low dropout linear regulator circuit to supply power to the power management chip.

[0008] The second voltage signal is smaller than the first voltage signal.

[0009] In some embodiments of this disclosure, a delay circuit is also included;

[0010] The delay circuit is configured to output the received second control signal to the switching circuit after a target delay time when the low-dropout linear regulator circuit receives the second control signal, so that the switching circuit turns on after the target delay time.

[0011] In some embodiments of this disclosure, the first terminal of the delay circuit is electrically connected to the control terminal of the low-dropout linear regulator circuit, and the second terminal of the delay circuit is electrically connected to the control terminal of the switching circuit.

[0012] In some embodiments of this disclosure, the source follower circuit includes at least a first transistor, a second transistor, a resistor, and an output power transistor;

[0013] The first end of the resistor and the first end of the output power transistor are electrically connected to the input voltage node, respectively. The second end of the first resistor is electrically connected to the control terminal of the output power transistor, the first end of the first transistor, and the control terminal of the first transistor, respectively. The second end of the output power transistor is electrically connected to the output voltage node. The second end of the first transistor is electrically connected to the first end of the second transistor, the control terminal of the second transistor, and the first end of the switching circuit, respectively. The second end of the second transistor is electrically connected to the ground node.

[0014] In some embodiments of this disclosure, the switching circuit includes a third transistor, the control terminal of the third transistor being electrically connected to the second terminal of the delay circuit, the first terminal of the third transistor being electrically connected to the first terminal of the second transistor, and the second terminal of the third transistor being electrically connected to the ground node.

[0015] In some embodiments of this disclosure, the output power transistor is a PMOS transistor, and the first transistor, the second transistor, and the third transistor are NMOS transistors.

[0016] In some embodiments of this disclosure, the number of series transistors included in the source follower circuit is related to the operating voltage of the power management chip.

[0017] According to a second aspect of this disclosure, a power supply method for a power management chip is provided, applied to the power supply circuit of any one of the first aspects, the power supply method comprising:

[0018] When the switching circuit receives the first control signal, the switching circuit is turned off, the source follower circuit outputs the first voltage signal, and the source follower circuit supplies power to the power management chip.

[0019] When the switching circuit receives the second control signal, the switching circuit is turned on, the switching circuit controls at least one transistor of the source follower circuit to be turned off, the source follower circuit outputs the second voltage signal, and the power supply circuit switches to the low dropout linear regulator circuit to supply power to the power management chip.

[0020] The second voltage signal is smaller than the first voltage signal.

[0021] In some embodiments of this disclosure, before the switching circuit turns on when it receives a second control signal, controls at least one transistor of the source follower circuit to turn off, the source follower circuit outputs a second voltage signal, and the power supply circuit switches to the low-dropout linear regulator circuit to supply power to the power management chip, the method further includes:

[0022] The delay circuit receives the second control signal output by the drive circuit of the low dropout linear regulator circuit, and outputs the received second control signal to the switching circuit after the target delay time.

[0023] According to a third aspect of this disclosure, a power management chip is provided, including a power supply circuit as described in any of the first aspects, or powering the power supply circuit using a power supply method as described in any of the second aspects.

[0024] The power supply circuit, power supply method, and power management chip provided in this disclosure embodiment utilize a switching circuit within the power supply circuit. When the switching circuit receives a first control signal, it turns off, and the source follower circuit outputs a first voltage signal. When the switching circuit receives a second control signal, it turns on, controlling at least one transistor in the source follower circuit to turn off. The low-dropout linear regulator circuit then provides the operating voltage to the power management chip. Because the switching circuit short-circuits the second transistor in the source follower circuit when the low-dropout linear regulator circuit is on, the second voltage signal output by the source follower circuit is less than the first voltage signal. This means the second voltage signal output by the source follower circuit is less than the operating voltage of the power management chip output by the low-dropout linear regulator circuit. This achieves the following: when the low-dropout linear regulator circuit is off, the operating voltage is provided to the power management chip through the source follower circuit; when the low-dropout linear regulator circuit is on, the operating voltage is provided to the power management chip through the low-dropout linear regulator circuit. Furthermore, by adjusting the width-to-length ratio of the second transistor channel in the source-follower circuit, the voltage signal output by the source-follower circuit is less than the voltage signal output by the low-dropout linear regulator when the low-dropout linear regulator is turned on. This avoids significant changes in the voltage signal output by the source-follower circuit due to NMOS transistor process corners and temperature drift, which could cause the voltage signal output by the source-follower circuit to be higher than the voltage signal output by the low-dropout linear regulator, thus failing to meet the requirement that the low-dropout linear regulator should supply power to the power management chip after the low-dropout linear regulator is turned on. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0026] Figure 1 This is a schematic diagram of the power supply circuit structure of a power management chip provided in an embodiment of this disclosure;

[0027] Figure 2 This is a schematic diagram of the power supply circuit structure of another power management chip provided in this embodiment of the present disclosure;

[0028] Figure 3 This is a schematic flowchart of a power supply method for a power management chip provided in an embodiment of this disclosure. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0031] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled intermediate terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0032] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0033] Based on the problems existing in the prior art, this disclosure provides a power supply circuit for a power management chip, such as... Figure 1As shown, the power supply circuit of the power management chip includes a source follower circuit 10, a low-dropout linear regulator circuit 20, and a switching circuit 30. The source follower circuit 10 includes at least a plurality of transistors connected in series. The switching circuit 30 is configured to turn off when a first control signal is received, and the source follower circuit 10 outputs a first voltage signal to power the power management chip 100. When a second control signal is received, the switching circuit 30 turns on, controls at least one transistor of the source follower circuit 10 to turn off, and the source follower circuit 10 outputs a second voltage signal. The power supply circuit then switches to the low-dropout linear regulator circuit 20 to power the power management chip 100. The second voltage signal is less than the first voltage signal.

[0034] Low dropout regulators (LDOs) offer advantages such as circuit simplicity, low power consumption, low output noise, and high power supply rejection ratio, making them an important component of power management chips and widely used in various electronic devices. Power-stage LDO driver circuits provide stable output voltage and sufficient current to subsequent circuits (BUCK circuits or BUCK_BOOST), thus their widespread application in power management chips.

[0035] To ensure that the power supply circuit can provide a stable operating voltage for the power management chip, when the low dropout linear regulator circuit 20 is in the off state, that is, when the low dropout linear regulator circuit 20 does not output a voltage signal, the operating voltage is output through the source follower circuit 10 to power the power management chip 100. When the low dropout linear regulator circuit 20 is in the on state, the power management chip 100 is powered through the low dropout linear regulator circuit 20.

[0036] Combination Figure 1 The outputs of the source follower circuit 10 and the low dropout linear regulator circuit 20 are electrically connected to the output voltage node VINT, that is, the output voltage node VINT is electrically connected to the input voltage node of the power management chip 100, and the power management chip 100 is powered through the output voltage node VINT.

[0037] It should be noted that in the above embodiments, the first control signal and the second control signal are control signals output by the drive circuit of the low-dropout linear regulator circuit. The drive circuit of the low-dropout linear regulator circuit outputs the control signal to the control terminal of the low-dropout linear regulator circuit. When the drive circuit of the low-dropout linear regulator circuit outputs the first control signal to the control terminal of the low-dropout linear regulator circuit, the low-dropout linear regulator circuit is in the off state under the action of the first control signal. When the drive circuit of the low-dropout linear regulator circuit outputs the second control signal to the control terminal of the low-dropout linear regulator circuit, the low-dropout linear regulator circuit is turned on under the action of the second control signal.

[0038] The switching circuit is electrically connected to the control terminal of the low-dropout linear regulator circuit and receives the control signal output by the drive circuit of the low-dropout linear regulator circuit. When the switching circuit receives the first control signal, the switching circuit is turned off, and when the switching circuit receives the second control signal, the switching circuit is turned on.

[0039] In specific implementation methods, such as Figure 2 As shown, the source follower circuit 10 includes at least a first transistor MN1, a second transistor MN2, a resistor R1, and an output power transistor MH; the first end of the resistor R1 and the first end of the output power transistor MH are electrically connected to the input voltage node HV, respectively; the second end of the first resistor R1 is electrically connected to the control terminal of the output power transistor MH, the first end of the first transistor MN1, and the control terminal of the first transistor MN1, respectively; the second end of the output power transistor MH is electrically connected to the output voltage node VINT; the second end of the first transistor MN1 is electrically connected to the first end of the second transistor MN2, the control terminal of the second transistor MN2, and the first end of the switching circuit 30, respectively; and the second end of the second transistor MN2 is electrically connected to the ground node GND.

[0040] The switching circuit 30 includes a third transistor MS. The control terminal of the third transistor MS is electrically connected to the second terminal of the delay circuit 40. The first terminal of the third transistor MS is electrically connected to the first terminal of the second transistor MN2. The second terminal of the third transistor MS is electrically connected to the ground node GND.

[0041] In the above embodiment, the output power transistor MH is a PMOS transistor, and the first transistor MN1, the second transistor MN2 and the third transistor MS are NMOS transistors.

[0042] Specifically, by setting a switching circuit 30 in the power supply circuit, when the switching circuit 30 receives the first control signal, the switching circuit 30 is turned off under the action of the first control signal. At this time, the source follower circuit 10 outputs a first voltage signal. The first voltage signal output by the source follower circuit 10 is related to the gate-source voltage of the series-connected transistor and the gate-source voltage of the output power transistor of the source follower circuit. Figure 2 When the source follower circuit 10 includes a first transistor MN1, a second transistor MN2, and an output power transistor MH connected in series, the first voltage signal output by the source follower circuit 10 satisfies VGS. MN1 +VGS MN2 -VGS MH The first voltage signal output by the source circuit 10 is also the operating voltage of the power management chip, where VGS MN1 VGS is the gate-to-source voltage of the first transistor MN1. MN2 VGS is the gate-to-source voltage of the second transistor MN2. MHThis refers to the voltage between the gate and source of the output power transistor MH; when the switching circuit 30 receives the second control signal, the switching circuit 30 is turned on under the action of the second control signal, and the switching circuit 30 controls the source to turn off at least one transistor of the circuit 10, combined with... Figure 2 The exemplary switching circuit 30 controls the second transistor MN2 included in the source follower circuit 10 to turn off. At this time, the second voltage signal output by the source follower circuit 10 satisfies: VGS MN1 -VGS MH When the low-dropout linear regulator circuit 20 is turned on under the action of the second control signal, it provides the operating voltage to the power management chip. Since the switching circuit 30 short-circuits the second transistor MN2 in the source follower circuit 10 when the low-dropout linear regulator circuit 20 is turned on, the second voltage signal output by the source follower circuit 10 is less than the first voltage signal. That is, the second voltage signal output by the source follower circuit 10 is less than the operating voltage of the power management chip output by the low-dropout linear regulator circuit 20. This achieves the following: when the low-dropout linear regulator circuit 20 is in the off state, it provides the operating voltage to the power management chip through the source follower circuit 10; when the low-dropout linear regulator circuit 20 is in the on state, it provides the operating voltage to the power management chip through the low-dropout linear regulator circuit 20. Furthermore, by adjusting the width-to-length ratio of the channel of the second transistor MN2 in the source follower circuit 10, the voltage signal output by the source follower circuit 10 is less than the voltage signal output by the low dropout linear regulator circuit 20 when the low dropout linear regulator circuit 20 is turned on. This avoids significant changes in the voltage signal output by the source follower circuit due to NMOS transistor process angle and temperature drift, which would cause the voltage signal output by the source follower circuit to be higher than the voltage signal output by the low dropout linear regulator circuit, thus failing to meet the requirement that the low dropout linear regulator circuit supplies power to the power management chip after the low dropout linear regulator circuit is turned on.

[0043] In a specific implementation, by adjusting the dimensions of the second transistor MN2 (e.g., the gate width and length of the second transistor, i.e., the width-to-length ratio of the channel of the second transistor), the output voltage of the source follower circuit 10 before the switching circuit 30 is turned on can be made close to the output voltage of the low dropout linear regulator circuit 20. After the switching circuit 30 is turned on, the output voltage of the source follower circuit 10 is lower than the output voltage of the low dropout linear regulator circuit 20 at all temperatures and process angles, and at this time the source follower voltage output voltage is a reasonable value, i.e. the source follower circuit output voltage will not be too low.

[0044] In a specific implementation, the number of series transistors included in the source follower circuit 10 is related to the operating voltage of the power management chip.

[0045] Taking the above embodiment as an example, in this embodiment, the source-following circuit 10 includes a first transistor MN1 and a second transistor MN2 connected in series, that is, the second transistor MN2 is a transistor that is short-circuited when the switching circuit 30 is turned on. In a specific embodiment, the number of first transistors MN1 included in the source-following circuit 10 is related to the operating voltage required by the power management chip. For example, if the operating voltage of the power management chip is X1, the voltage between the gate and source of the first transistor MN1 is VGS. MN1 The gate-to-source voltage of the second transistor MN2 is VGS. MN2 The gate-to-source voltage of the output power transistor is VGS. MH Then the number N of the first transistors connected in series satisfies:

[0046]

[0047] As one possible implementation, the power supply circuit of the power management chip may optionally include a delay circuit 40, such as... Figure 2 As shown, the first terminal of the delay circuit 40 is electrically connected to the control terminal of the low-dropout linear regulator circuit 20, and the second terminal of the delay circuit 40 is electrically connected to the control terminal of the switching circuit 30. The delay circuit 40 is configured to output the received second control signal to the switching circuit 30 after a target delay time when the low-dropout linear regulator circuit 20 receives the second control signal, so that the switching circuit 30 turns on after the target delay time.

[0048] When the low-dropout linear regulator 20 receives the first control signal, it is in a turned-off state under the action of the first control signal. The delay circuit 40, which is electrically connected to the control terminal of the low-dropout linear regulator 20, directly sends the received first control signal to the switching circuit 30, causing the switching circuit 30 to turn off under the action of the first control signal. When the low-dropout linear regulator 20 receives the second control signal, it is turned on under the action of the second control signal. The delay circuit 40, which is electrically connected to the control terminal of the low-dropout linear regulator 20, outputs the received second control signal to the switching circuit 30 after a target delay time, so that the switching circuit 30 turns on after the target delay time. The target delay time is the time between the start of the low-dropout linear regulator 20 turning on and the output of the stable voltage signal by the low-dropout linear regulator 20.

[0049] By configuring the power supply circuit of the power management chip to include a delay circuit 40, the power management chip can be switched to the low dropout linear regulator circuit 20 to supply power when the low dropout linear regulator circuit 20 outputs a stable voltage signal.

[0050] In specific implementation methods, combined with Figure 2 The power supply circuit of the power management chip also includes a delay circuit 40. When the drive circuit of the low-dropout linear regulator 20 outputs a low-level signal, the low-dropout linear regulator 20 is in a turned-off state and does not output a voltage signal. The delay circuit 40, which is electrically connected to the control terminal of the low-dropout linear regulator 20, receives the low-level signal output by the drive circuit and outputs a first control signal (e.g., a low-level signal) corresponding to the low-level signal to the switching circuit 30. At this time, the switching circuit 30 is in a turned-off state under the action of the first control signal, so that when the low-dropout linear regulator 20 is in a turned-off state, the switching circuit 30 is also in a turned-off state. When the low-dropout linear regulator 20 is in a turned-off state, the delay circuit 40 is in a turned-off state. When the drive circuit of circuit 20 outputs a high-level signal, the low-dropout linear regulator circuit 20 is turned on and outputs a voltage signal. The delay circuit 40, which is electrically connected to the control terminal of the low-dropout linear regulator circuit 20, receives the high-level signal output by the drive circuit and outputs the received second control signal (e.g., a high-level signal) to the switching circuit 30 after a target delay time. At this time, the switching circuit 30 is turned on under the action of the second control signal. The target delay time is the time between the start of the low-dropout linear regulator circuit turning on and the output of a stable voltage signal by the low-dropout linear regulator circuit, so that the switching circuit turns on when the low-dropout linear regulator circuit outputs a stable voltage signal.

[0051] For example, when the drive circuit of the low-dropout linear regulator 20 outputs a low-level signal, the low-dropout linear regulator 20 is in a turned-off state and does not output a voltage signal. The delay circuit 40, electrically connected to the control terminal of the low-dropout linear regulator 20, receives the low-level signal output by the drive circuit and outputs a first control signal (e.g., a low-level signal) corresponding to the low-level signal to the third transistor MS. At this time, the third transistor MS is in a turned-off state under the action of the first control signal. The first transistor MN1 and the second transistor MN2 are connected in series. The first voltage signal output by the source follower circuit 10 is VGS. MN1 +VGS MN2 -VGS MH The source-following circuit 10 supplies power to the power management chip. When the drive circuit of the low-dropout linear regulator 20 outputs a high-level signal, the low-dropout linear regulator 20 is turned on and outputs a voltage signal. The delay circuit 40, which is electrically connected to the control terminal of the low-dropout linear regulator 20, receives the high-level signal output by the drive circuit and outputs a second control signal (e.g., a high-level signal) corresponding to the high-level signal to the third transistor MS after the target delay time. At this time, the third transistor MS is turned on under the action of the second control signal, and the turned-on third transistor MS short-circuits the second transistor MN2. At this time, the second voltage signal output by the source-following circuit 10 is: VGS. MN1 -VGS MHSince the second voltage signal output by the source follower circuit 10 is less than the first voltage signal (that is, the operating voltage of the power management chip, that is, the voltage signal output by the low dropout linear regulator circuit 20), the voltage signal output by the low dropout linear regulator circuit 20 supplies power to the power management chip.

[0052] The power supply circuit of the power management chip provided in this embodiment includes a switching circuit. When the switching circuit receives a first control signal, it turns off, and the source follower circuit outputs a first voltage signal. When the switching circuit receives a second control signal, it turns on, controlling at least one transistor in the source follower circuit to turn off. The low-dropout linear regulator circuit then provides the operating voltage to the power management chip. Because the switching circuit short-circuits the second transistor in the source follower circuit when the low-dropout linear regulator circuit is on, the second voltage signal output by the source follower circuit is less than the first voltage signal. This means the second voltage signal output by the source follower circuit is less than the operating voltage of the power management chip output by the low-dropout linear regulator circuit. This achieves the following: when the low-dropout linear regulator circuit is off, the operating voltage is provided to the power management chip through the source follower circuit; when the low-dropout linear regulator circuit is on, the operating voltage is provided to the power management chip through the low-dropout linear regulator circuit. Furthermore, by adjusting the width-to-length ratio of the second transistor channel in the source-follower circuit, the voltage signal output by the source-follower circuit is less than the voltage signal output by the low-dropout linear regulator when the low-dropout linear regulator is turned on. This avoids significant changes in the voltage signal output by the source-follower circuit due to NMOS transistor process corners and temperature drift, which could cause the voltage signal output by the source-follower circuit to be higher than the voltage signal output by the low-dropout linear regulator, thus failing to meet the requirement that the low-dropout linear regulator should supply power to the power management chip after the low-dropout linear regulator is turned on.

[0053] Based on the above embodiments, this disclosure also provides a power supply method for a power management chip, which is applied to the power supply circuit described in any of the above embodiments, such as... Figure 3 As shown, the power supply methods include:

[0054] S110. When the switching circuit receives the first control signal, the switching circuit turns off, the source follower circuit outputs the first voltage signal, and the source follower circuit supplies power to the power management chip.

[0055] S120. When the switching circuit receives the second control signal, the switching circuit is turned on, and the switching circuit controls at least one transistor of the source follower circuit to turn off. The source follower circuit outputs the second voltage signal, and the power supply circuit switches to the low dropout linear regulator circuit to supply power to the power management chip.

[0056] The second voltage signal is smaller than the first voltage signal.

[0057] In a specific implementation, the delay circuit receives the second control signal output by the drive circuit of the low-dropout linear regulator circuit, and outputs the received second control signal to the switching circuit after the target delay time.

[0058] Specifically, when the switching circuit 30 receives the first control signal, the switching circuit 30 is turned off under the action of the first control signal. At this time, the source follower circuit 10 outputs a first voltage signal. The first voltage signal output by the source follower circuit 10 is related to the gate-source voltage of the series-connected transistor and the gate-source voltage of the output power transistor of the source follower circuit. Figure 2 When the source follower circuit 10 includes a first transistor MN1, a second transistor MN2, and an output power transistor MH connected in series, the first voltage signal output by the source follower circuit 10 satisfies VGS. MN1 +VGS MN2 -VGS MH The first voltage signal output by the source circuit 10 is also the operating voltage of the power management chip, where VGS MN1 VGS is the gate-to-source voltage of the first transistor MN1. MN2 VGS is the gate-to-source voltage of the second transistor MN2. MH This refers to the voltage between the gate and source of the output power transistor MH; when the switching circuit 30 receives the second control signal, the switching circuit 30 is turned on under the action of the second control signal, and the switching circuit 30 controls the source to turn off at least one transistor of the circuit 10, combined with... Figure 2 The exemplary switching circuit 30 controls the second transistor MN2 included in the source follower circuit 10 to turn off. At this time, the second voltage signal output by the source follower circuit 10 satisfies: VGS MN1 -VGS MHWhen the low-dropout linear regulator circuit 20 is turned on under the action of the second control signal, it provides the operating voltage to the power management chip. Since the switching circuit 30 short-circuits the second transistor MN2 in the source follower circuit 10 when the low-dropout linear regulator circuit 20 is turned on, the second voltage signal output by the source follower circuit 10 is less than the first voltage signal. That is, the second voltage signal output by the source follower circuit 10 is less than the operating voltage of the power management chip output by the low-dropout linear regulator circuit 20. This achieves the following: when the low-dropout linear regulator circuit 20 is in the off state, it provides the operating voltage to the power management chip through the source follower circuit 10; when the low-dropout linear regulator circuit 20 is in the on state, it provides the operating voltage to the power management chip through the low-dropout linear regulator circuit 20. Furthermore, by adjusting the width-to-length ratio of the channel of the second transistor MN2 in the source follower circuit 10, the voltage signal output by the source follower circuit 10 is less than the voltage signal output by the low dropout linear regulator circuit 20 when the low dropout linear regulator circuit 20 is turned on. This avoids significant changes in the voltage signal output by the source follower circuit due to NMOS transistor process angle and temperature drift, which would cause the voltage signal output by the source follower circuit to be higher than the voltage signal output by the low dropout linear regulator circuit, thus failing to meet the requirement that the low dropout linear regulator circuit supplies power to the power management chip after the low dropout linear regulator circuit is turned on.

[0059] Based on the above embodiments, this disclosure also provides a power management chip, including the power supply circuit described in any of the above embodiments, or using the power supply method described in any of the above embodiments to supply power to the power supply circuit, which has the beneficial effects described in any of the above embodiments. This disclosure will not provide specific examples of these effects.

[0060] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0061] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A power supply circuit for a power management chip, characterized in that, include: The circuit comprises a source follower circuit, a low-dropout linear regulator circuit, and a switching circuit. The source follower circuit includes at least a first transistor, a second transistor, a resistor, and an output power transistor. The first terminal of the resistor and the first terminal of the output power transistor are electrically connected to the input voltage node, respectively. The second terminal of the resistor is electrically connected to the control terminal of the output power transistor, the first terminal of the first transistor, and the control terminal of the first transistor. The second terminal of the output power transistor is electrically connected to the output voltage node. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the control terminal of the second transistor, and the first terminal of the switching circuit, respectively. The second terminal of the second transistor is electrically connected to the ground node. The switching circuit is configured such that when a first control signal is received, the switching circuit turns off, the source follower circuit outputs a first voltage signal, and the source follower circuit supplies power to the power management chip; when a second control signal is received, the switching circuit turns on, the switching circuit controls at least one transistor of the source follower circuit to turn off, the source follower circuit outputs a second voltage signal, and the power supply circuit switches to the low dropout linear regulator circuit to supply power to the power management chip. The second voltage signal is smaller than the first voltage signal.

2. The power supply circuit according to claim 1, characterized in that, It also includes delay circuits; The delay circuit is configured to output the received second control signal to the switching circuit after a target delay time when the low-dropout linear regulator circuit receives the second control signal, so that the switching circuit turns on after the target delay time.

3. The power supply circuit according to claim 2, characterized in that, The first terminal of the delay circuit is electrically connected to the control terminal of the low-dropout linear regulator circuit, and the second terminal of the delay circuit is electrically connected to the control terminal of the switching circuit.

4. The power supply circuit according to claim 3, characterized in that, The switching circuit includes a third transistor, the control terminal of which is electrically connected to the second terminal of the delay circuit, the first terminal of which is electrically connected to the first terminal of the second transistor, and the second terminal of which is electrically connected to the ground node.

5. The power supply circuit according to claim 4, characterized in that, The output power transistor is a PMOS transistor, and the first transistor, the second transistor, and the third transistor are NMOS transistors.

6. The power supply circuit according to claim 1, characterized in that, The number of series transistors included in the source follower circuit is related to the operating voltage of the power management chip.

7. A power supply method for a power management chip, characterized in that, The power supply method, applied to the power supply circuit according to any one of claims 1-6, comprises: When the switching circuit receives the first control signal, the switching circuit is turned off, the source follower circuit outputs the first voltage signal, and the source follower circuit supplies power to the power management chip. When the switching circuit receives the second control signal, the switching circuit is turned on, the switching circuit controls at least one transistor of the source follower circuit to be turned off, the source follower circuit outputs the second voltage signal, and the power supply circuit switches to the low dropout linear regulator circuit to supply power to the power management chip. The second voltage signal is smaller than the first voltage signal.

8. The power supply method according to claim 7, characterized in that, When the switching circuit receives the second control signal, the switching circuit is turned on, the switching circuit controls at least one transistor of the source follower circuit to turn off, the source follower circuit outputs a second voltage signal, and before the power supply circuit switches to the low-dropout linear regulator circuit to supply power to the power management chip, the method further includes: The delay circuit receives the second control signal output by the drive circuit of the low dropout linear regulator circuit, and outputs the received second control signal to the switching circuit after the target delay time.

9. A power management chip, characterized in that, The power supply circuit includes any one of claims 1-6, or the power supply method described in any one of claims 7-8 is used to power the power supply circuit.

Images