A high-voltage, output capacitorless, low noise linear voltage regulator

Abstract

This invention relates to a high-voltage, capacitor-free, low-noise linear regulator. It comprises a high-voltage switching voltage follower, a self-zeroing error amplifier, and voltage divider resistors. The high-voltage switching voltage follower significantly enhances the system's transient response to load changes and improves power supply rejection in the mid-frequency range. The self-zeroing error amplifier, together with the high-voltage switching voltage follower, forms a global slow loop. The self-zeroing error amplifier employs a ping-pong self-zeroing method, effectively reducing low-frequency flicker noise and offset while ensuring continuous operation in the time domain. This invention introduces a settling phase between the self-zeroing and amplification phases of the ping-pong module, significantly reducing output glitches caused by amplifier settling time. This invention operates stably without an external output capacitor, supports a wide input and output voltage range, and possesses excellent characteristics such as low noise, high power supply rejection, and fast response, making it suitable for various demanding high-voltage power supply applications.

Description

Technical Field

[0001] This invention belongs to the field of linear regulator (LDO) technology, specifically relating to a high-voltage, capacitor-free, low-noise linear regulator. Background Technology

[0002] Linear regulators (LDOs) are widely used in portable electronics, wireless communication modules, and high-precision sensors due to their low noise, high accuracy, and fast response. High-voltage LDOs are specifically designed for applications with high input voltages (typically tens of volts or higher), aiming to provide a stable, low-noise low-voltage power supply. With technological advancements, the importance of high-voltage LDOs has expanded beyond industrial automation to include automotive electronics, battery management systems (BMS), and other fields with stringent power quality requirements.

[0003] In LDO design, transient response capability and noise performance are two crucial performance indicators.

[0004] Firstly, numerous attempts have been made in existing technologies to improve transient response. For example, adaptive transient current distribution technology and high-gain positive feedback loops are used to address the challenges posed by rapid load changes. In addition, the flipped-voltage-follower (FVF) structure has been proposed and applied in LDOs as an effective means to achieve faster transient response.

[0005] Secondly, noise is another core metric for evaluating LDO performance. Low-noise LDOs are primarily used to power signal processing systems that are highly sensitive to noise, such as radio frequency (RF) mixers and modulators, high-speed, high-resolution data converters (ADCs and DACs), and high-precision sensors. To reduce flicker noise in the LDO's internal error amplifier, existing techniques typically incorporate a BJT preamplifier stage before the conventional operational amplifier (EA) to improve the LDO's overall noise performance. Additionally, introducing chopper technology within the operational amplifier also helps reduce output noise. However, chopper technology inevitably introduces chopping-induced ripple, which requires additional complex circuit design to suppress in practical applications.

[0006] In addition, traditional high-voltage low-noise LDOs often rely on large off-chip output capacitors to maintain loop stability, which severely restricts the trend of power management chips towards high integration and miniaturization.

[0007] In summary, designing an LDO that can operate stably over a wide input and output voltage range, while also being capacitorless, having a fast transient response, and effectively suppressing low-frequency noise without introducing severe ripple interference, is a technical challenge that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0008] The purpose of this invention is to provide a low-noise linear regulator (LDO) with a wide input-output range and no output capacitor.

[0009] This invention proposes a high-voltage capacitorless, low-noise linear regulator, comprising: a high-voltage switching voltage follower, a self-adjusting zero-error amplifier, and a voltage divider resistor; wherein:

[0010] A high-voltage flip-flop voltage follower is used to step down the input voltage and convert it to an output voltage, receiving the output V from a self-zeroing error amplifier. EA External output voltage V OUT It consists of six ordinary MOSFETs, six high-voltage MOSFETs, and one high-voltage power transistor circuit. Specifically: the drain of the first ordinary MOSFET is connected to the source of the second high-voltage MOSFET; the drain of the seventh ordinary MOSFET is connected to the source of the eighth high-voltage MOSFET; and the drain of the twelfth ordinary MOSFET is connected to the source of the eleventh ordinary MOSFET. The gate voltages of the first, second, and eleventh ordinary MOSFETs are all fixed bias voltages, forming three common-source, common-gate structures. The drain of the fourth ordinary MOSFET is connected to the source of the third high-voltage MOSFET; the gate of the fifth ordinary MOSFET is connected to its drain, and simultaneously connected to the drain of the sixth high-voltage MOSFET, and the gates of the third and fourth high-voltage MOSFETs, forming a current mirror structure. The source of the sixth high-voltage MOSFET is connected to the external output voltage V. OUT The source of the high-voltage power transistor is connected to its gate, and its gate is connected to the output V of the self-zeroing error amplifier. EA Connected; External input power supply V INSimultaneously, it is connected to the source of the first ordinary MOSFET, the source of the seventh ordinary MOSFET, and the drain of the high-voltage power transistor, respectively; the source of the ninth high-voltage MOSFET is connected to the drain of the eighth high-voltage MOSFET, the drain of the tenth high-voltage MOSFET, and the gate of the high-voltage power transistor, respectively; the gate of the ninth high-voltage MOSFET is simultaneously connected to the source of the second high-voltage MOSFET and the drain of the third high-voltage MOSFET; the drain of the ninth high-voltage MOSFET is connected to the drain of the eleventh ordinary MOSFET and the gate of the tenth high-voltage MOSFET, respectively; the sources of the fourth ordinary MOSFET, the fifth ordinary MOSFET, the tenth high-voltage MOSFET, and the twelfth ordinary MOSFET are all grounded;

[0011] The voltage divider resistor is composed of a first resistor and a second resistor connected in series, with one end connected to the external output voltage V of the high-voltage flip-flop voltage follower. OUT The other end connects to the input of the self-zeroing error amplifier, and the output of the self-zeroing error amplifier is connected to a high-voltage flip-flop voltage follower. The high-voltage flip-flop voltage follower, the self-zeroing error amplifier, and the voltage divider resistor together form a relatively slow feedback loop, which converts the external output voltage V... OUT Keep consistent with the external reference voltage VBG;

[0012] The voltage divider resistor accepts the external output voltage V of the high-voltage switching voltage follower. OUT After voltage division by resistors, the feedback voltage V FB The signal is sent to the self-zeroing error amplifier; the self-zeroing error amplifier receives the feedback voltage V. FB With external reference voltage V BG Output error signal V EA To high voltage flip voltage follower.

[0013] In this invention, the LDO has no external output capacitor;

[0014] The high-voltage flip-over voltage follower contains a fast feedback loop to accelerate the system's transient response to load changes and improve the power supply rejection ratio (PSR) in the mid-frequency range.

[0015] The self-zeroing error amplifier adopts the ping-pong auto-zeroing method, which reduces the low-frequency noise of the linear regulator while ensuring the continuous operation of the linear regulator in the time domain.

[0016] The Ping-pong auto-zeroing method employs a setup phase during switching to suppress glitches caused by amplifier setup time.

[0017] In this invention, the high-voltage switching voltage follower further includes a super source follower; wherein, the seventh ordinary MOSFET, the eighth high-voltage MOSFET, the ninth high-voltage MOSFET, the tenth high-voltage MOSFET, the eleventh ordinary MOSFET, and the twelfth ordinary MOSFET together constitute the super source follower; the super source follower is used to drive the high-voltage power transistor (M... N The larger gate capacitance allows for stronger drive capability and lower output impedance with less current, thereby increasing the bandwidth of the high-voltage flip voltage follower.

[0018] In this invention, the self-zeroing error amplifier is a two-stage operational amplifier; wherein the first stage circuit has the characteristics of low-voltage input and low-voltage output, and the second stage circuit has the characteristics of low-voltage input and high-voltage output, and is used to drive the high-voltage flip-flop voltage follower to generate a wide range of output voltages.

[0019] In this invention, the ping-pong self-zeroing method includes a self-zeroing stage and an amplification stage, with a setup phase inserted between the self-zeroing stage and the amplification stage. Before ping-pong switching, the module in the self-zeroing stage first enters the setup stage, and after the output stabilizes, it enters the amplification stage, thereby significantly attenuating the glitches generated during direct switching.

[0020] The setup phase includes an auxiliary amplifier structure specifically designed to simulate the input and output of the high-voltage flip voltage follower. The input of this simulation structure is the output of the first-stage circuit of the high-voltage flip voltage follower. During the setup phase, the input of the first-stage circuit of the self-zeroing error amplifier, in addition to the voltage reference V, is... BG In addition, it also includes the analog output of the auxiliary amplifier or the actual external output voltage V of the circuit, which is selected by the system via a switch. OUT The output of the first stage circuit of the self-zeroing error amplifier is pre-stabilized at the desired position of the amplification stage to be entered, thereby effectively suppressing the glitches caused by the amplifier settling time.

[0021] In this invention, all high-voltage MOSFETs are double-diffused metal-oxide-semiconductor (DMOS) devices; the second, third, sixth, eighth, and ninth high-voltage MOSFETs are respectively connected to clamping circuits, and the gates and drains of the MOSFETs inside the clamping circuits are interconnected to avoid potential breakdown risks caused by high voltage.

[0022] In this invention, the LDO can support an input voltage range of 3.7V to 65V and an output voltage range of 2.1V to 50V.

[0023] The beneficial effects of this invention are as follows: Unlike existing LDOs, the high-voltage capacitorless low-noise LDO proposed in this invention utilizes a fast feedback loop built inside a high-voltage switching voltage follower, accelerating the system's transient response to load changes and improving the power supply rejection ratio (PSR) in the mid-frequency range; by utilizing the ping-pong auto-zeroing technology of the self-zeroing error amplifier, the system's low-frequency noise is reduced while ensuring continuous operation in the time domain. Specifically:

[0024] (1) Regarding high-voltage reversing voltage follower

[0025] The high-voltage flip-flop voltage follower consists of a power transistor (M) N It consists of a cascode structure and a super source follower (SSF); wherein, the seventh to twelfth power transistors (M7, M8, M9, M10, M11, M12) together form the super source follower; the super source follower is used to drive the power transistors (M10, M11, M12). N The larger gate capacitance allows for stronger drive capability and lower output impedance with less current, thereby increasing the bandwidth of the high-voltage flip voltage follower.

[0026] (2) Regarding the self-zeroing error amplifier

[0027] The self-zeroing error amplifier of the present invention is a two-stage operational amplifier; wherein the first stage circuit (A1) has the characteristics of low-voltage input and low-voltage output, and the second stage circuit (A2) has the characteristics of low-voltage input and high-voltage output, and is used to drive the high-voltage flip-flop voltage follower to generate a wide range of output voltages.

[0028] The working timing of the ping-pong self-zeroing technology of the present invention includes a self-zeroing stage and an amplification stage. The setup phase is inserted between the self-zeroing stage and the amplification stage. Before ping-pong switching, the module in the self-zeroing stage first enters the setup stage. After the output stabilizes, it enters the amplification stage, thereby significantly attenuating the glitches generated during direct switching.

[0029] The setup phase includes an auxiliary amplifier structure specifically designed to simulate the input and output of the high-voltage flip voltage follower. The input of this simulation structure is the output of the first-stage circuit (A1) of the high-voltage flip voltage follower. During the setup phase, the input of the first-stage circuit (A1) of the self-zeroing error amplifier, in addition to the voltage reference V, is... BG In addition, it also includes the analog output of the auxiliary amplifier or the actual external output voltage V of the circuit, which is selected by the system via a switch. OUTTherefore, the output of the first stage circuit (A1) of the self-zeroing error amplifier will be pre-stabilized at the desired position of the amplification stage to be entered, thereby effectively suppressing the glitches caused by the amplifier settling time.

[0030] (3) Regarding high-voltage MOSFETs

[0031] To accommodate a wide range of input and output voltages, the high-voltage MOSFETs used in the circuit to withstand high voltages are all double-diffused metal-oxide-semiconductor (DMOS) devices; and a clamping circuit (with the gate and drain of the internal MOSFETs interconnected) is connected in the circuit to avoid potential breakdown risks caused by high voltages.

[0032] In summary, this invention designs a high-voltage, capacitor-free, low-noise linear regulator (LDO) with a wide input-output range. It achieves a fast dynamic response through a high-voltage switching voltage follower and low low-frequency noise through a self-zeroing error amplifier. It exhibits key performance indicators such as a wide input-output voltage range, good response speed, and low noise. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the high-voltage capacitorless low-noise LDO structure of the present invention.

[0034] Figure 2 The diagram illustrates the high-voltage reversing voltage follower of the present invention.

[0035] Figure 3 This is a timing diagram of the self-zeroing technology in table tennis.

[0036] Figure 4 This is a schematic diagram of the auxiliary amplifier in a self-adjusting zero-error amplifier.

[0037] Figure 5 shows the simulation results of the transient response of the LDO.

[0038] Figure 6 shows the noise simulation results of the LDO.

[0039] Figure 7 shows the simulation results of power supply rejection (PSR) of LDO.

[0040] In the diagram, the following are the labels: 100 is a high-voltage flip-flop voltage follower (FVF), 110 is a self-adjusting zero error amplifier (EA), and 120 is a voltage divider resistor; M1, M4, M5, M7, M11, and M12 are the first, fourth, fifth, seventh, eleventh, and twelfth ordinary MOSFETs, respectively; M2, M3, M6, M8, M9, and M10 are the second, third, sixth, eighth, ninth, and tenth high-voltage MOSFETs, respectively. Detailed Implementation

[0041] The present invention will be further described below with reference to the embodiments and accompanying drawings.

[0042] Example 1:

[0043] This invention proposes a high-voltage capacitorless, low-noise LDO, such as... Figure 1 As shown and Figure 2 As shown, it includes: a high-voltage flip-flop voltage follower (FVF) 100, a self-zeroing error amplifier (EA) 110, and a voltage divider resistor 120; wherein:

[0044] The high-voltage flip-flop voltage follower 100 is used to step down the input voltage and convert it to an output voltage. It consists of six general-purpose MOSFETs, six high-voltage MOSFETs, and one high-voltage power transistor M. N The circuit connection consists of receiving the output V of the self-zeroing error amplifier 110. EA External output voltage V OUT In this configuration, the drain of the first MOSFET M1 is connected to the source of the second MOSFET M2, the drain of the seventh MOSFET M7 is connected to the source of the eighth MOSFET M8, and the drain of the twelfth MOSFET M12 is connected to the source of the eleventh MOSFET M11. The gate voltages of these MOSFETs are all fixed bias voltages, forming three sets of common-source, common-gate structures. The drain of the fourth MOSFET M4 is connected to the source of the third MOSFET M3, and the gate and drain of the fifth MOSFET M5 are connected, and simultaneously connected to the drain of the sixth MOSFET M6, and the gates of the third MOSFET M3 and the fourth MOSFET M4, forming a current mirror structure. The source of the sixth MOSFET M6 is connected to the external output voltage V. OUT High-voltage power transistor M N The source is connected to the gate, and the gate is connected to the output V of the self-zeroing error amplifier 110. EA Connected; External input power supply V IN Simultaneously, it is connected to the source of the first MOSFET M1, the source of the seventh MOSFET M7, and the high-voltage power transistor M... NThe drain of the ninth MOSFET M9 is connected to the drain of the eighth MOSFET M8, and is also connected to the drain of the tenth MOSFET M10 and the high-voltage power transistor M10. N The gate of the ninth MOSFET M9 is connected to the source of the second MOSFET M2 and the drain of the third MOSFET M3. The drain of the ninth MOSFET M9 is connected to the drain of the eleventh MOSFET M11 and the gate of the tenth MOSFET M10. The source of the fourth MOSFET M4, the source of the fifth MOSFET M5, the source of the tenth MOSFET M10, and the source of the twelfth MOSFET M12 are all grounded.

[0045] The voltage divider resistor 120 consists of two series resistors R1 and R2, and receives the external output voltage V from the high-voltage switching voltage follower 100. OUT The feedback voltage V is then divided by resistors. FB The signal is sent to the self-adjusting zero-error amplifier 110;

[0046] The self-zeroing error amplifier 110 receives feedback voltage V. FB With external reference voltage V BG Output error signal V EA To the high voltage flip-over voltage follower 100.

[0047] In this invention, the LDO is characterized by having no external output capacitor;

[0048] Table 1 Performance Indicators of the Designed High-Voltage Capacitorless Low-Noise LDO

[0049]

[0050] The entire workflow of a high-voltage capacitorless low-noise LDO is as follows:

[0051] The high-voltage switching voltage follower 100 is used to step down the input voltage and convert it into an output voltage. The voltage divider resistor 120 consists of two series resistors R1 and R2. It receives the external output voltage VOUT of the high-voltage switching voltage follower 100 and sends the feedback voltage VFB to the self-zeroing error amplifier 110 after voltage division by the resistors. The self-zeroing error amplifier 110 receives the feedback voltage VFB and the external reference voltage VBG and outputs the error signal VEA to the high-voltage switching voltage follower 100. Together, they form a global feedback loop to adjust the external output voltage VOUT of the LDO to be consistent with the external reference voltage VBG.

[0052] The simulation results of the transient response of the LDO are as follows: Figure 5 As shown, when the load current jumps from 0mA to 50mA, the output voltage only fluctuates by a maximum of about 14.3mV and recovers to stability within 1.7us.

[0053] System noise simulation, such as Figure 6 As shown, after enabling the ping-pong self-zeroing technology, the integrated noise in the 10Hz to 100kHz frequency band decreased from 102.89 μVRMS to 31.95 μVRMS. The noise power spectral density at 100Hz is 0.16 μV / √Hz, indicating that the low-frequency flicker noise is well suppressed.

[0054] Figure 7 The simulation results of the power supply rejection (PSR) of the LDO under full load are presented. In the mid-frequency range, the fast loop inside the high-voltage switching voltage follower significantly improves the PSR, reaching -66.7dB at 100kHz and -48.5dB at 1MHz.

Claims

1. A high-voltage capacitorless, low-noise linear regulator, characterized in that, include: A high-voltage flip-flop voltage follower, a self-adjusting zero-error amplifier, and voltage divider resistors; wherein: A high-voltage flip-flop voltage follower is used to step down the input voltage and convert it to an output voltage, receiving the output V from a self-zeroing error amplifier. EA External output voltage V OUT It consists of six ordinary MOSFETs, six high-voltage MOSFETs, and one high-voltage power transistor circuit. Specifically: the drain of the first ordinary MOSFET is connected to the source of the second high-voltage MOSFET; the drain of the seventh ordinary MOSFET is connected to the source of the eighth high-voltage MOSFET; and the drain of the twelfth ordinary MOSFET is connected to the source of the eleventh ordinary MOSFET. The gate voltages of the first, second, and eleventh ordinary MOSFETs are all fixed bias voltages, forming three common-source, common-gate structures. The drain of the fourth ordinary MOSFET is connected to the source of the third high-voltage MOSFET; the gate of the fifth ordinary MOSFET is connected to its drain, and simultaneously connected to the drain of the sixth high-voltage MOSFET, and the gates of the third and fourth high-voltage MOSFETs, forming a current mirror structure. The source of the sixth high-voltage MOSFET is connected to the external output voltage V. OUT The source of the high-voltage power transistor is connected to its gate, and its gate is connected to the output V of the self-zeroing error amplifier. EA Connected; External input power supply V IN Simultaneously, it is connected to the source of the first ordinary MOSFET, the source of the seventh ordinary MOSFET, and the drain of the high-voltage power transistor, respectively; the source of the ninth high-voltage MOSFET is connected to the drain of the eighth high-voltage MOSFET, the drain of the tenth high-voltage MOSFET, and the gate of the high-voltage power transistor, respectively; the gate of the ninth high-voltage MOSFET is simultaneously connected to the source of the second high-voltage MOSFET and the drain of the third high-voltage MOSFET; the drain of the ninth high-voltage MOSFET is connected to the drain of the eleventh ordinary MOSFET and the gate of the tenth high-voltage MOSFET, respectively; the sources of the fourth ordinary MOSFET, the fifth ordinary MOSFET, the tenth high-voltage MOSFET, and the twelfth ordinary MOSFET are all grounded; The voltage divider resistor is composed of a first resistor and a second resistor connected in series, with one end connected to the external output voltage V of the high-voltage flip-flop voltage follower. OUT The other end connects to the input of the self-zeroing error amplifier, and the output of the self-zeroing error amplifier is connected to a high-voltage flip-flop voltage follower. The high-voltage flip-flop voltage follower, the self-zeroing error amplifier, and the voltage divider resistor together form a relatively slow feedback loop, which converts the external output voltage V... OUT Keep consistent with the external reference voltage VBG; The voltage divider resistor accepts the external output voltage V of the high-voltage switching voltage follower. OUT After voltage division by resistors, the feedback voltage V FB The signal is sent to the self-zeroing error amplifier; the self-zeroing error amplifier receives the feedback voltage V. FB With external reference voltage V BG Output error signal V EA To high voltage flip voltage follower.

2. The high-voltage capacitorless low-noise linear regulator according to claim 1, characterized in that... The LDO has no external output capacitor. The high-voltage flip-over voltage follower contains a fast feedback loop to accelerate the system's transient response to load changes and improve the power supply rejection ratio (PSR) in the mid-frequency range. The self-zeroing error amplifier adopts the ping-pong self-zeroing method, which reduces the low-frequency noise of the linear regulator while ensuring the continuous operation of the linear regulator in the time domain. The ping-pong self-zeroing method employs a setup phase during switching to suppress glitches caused by amplifier setup time.

3. The high-voltage capacitorless low-noise linear regulator according to claim 1, characterized in that, The high-voltage switching voltage follower also includes a super source follower; wherein, the seventh ordinary MOSFET, the eighth high-voltage MOSFET, the ninth high-voltage MOSFET, the tenth high-voltage MOSFET, the eleventh ordinary MOSFET, and the twelfth ordinary MOSFET together form the super source follower; the super source follower is used to drive the high-voltage power transistor (M N The larger gate capacitance allows for stronger drive capability and lower output impedance with less current, thereby increasing the bandwidth of the high-voltage flip voltage follower.

4. The high-voltage capacitorless low-noise linear regulator according to claim 1, characterized in that, The self-adjusting zero-error amplifier is a two-stage operational amplifier; the first stage circuit has the characteristics of low-voltage input and low-voltage output, and the second stage circuit has the characteristics of low-voltage input and high-voltage output, which is used to drive the high-voltage flip-flop voltage follower to generate a wide range of output voltages.

5. The high-voltage capacitorless low-noise linear regulator according to claim 2, characterized in that, The ping-pong self-zeroing method includes a self-zeroing stage and an amplification stage, with a setup stage inserted between the self-zeroing stage and the amplification stage. Before ping-pong switching, the module in the self-zeroing stage first enters the setup stage, and after the output stabilizes, it enters the amplification stage, thereby significantly attenuating the glitches generated during direct switching. The setup phase includes an auxiliary amplifier structure specifically designed to simulate the input and output of the high-voltage flip voltage follower. The input of this simulation structure is the output of the first-stage circuit of the high-voltage flip voltage follower. During the setup phase, the input of the first-stage circuit of the self-zeroing error amplifier, in addition to the voltage reference V, is... BG In addition, it also includes the analog output of the auxiliary amplifier or the actual external output voltage V of the circuit, which is selected by the system via a switch. OUT The output of the first stage circuit of the self-zeroing error amplifier is pre-stabilized at the desired position of the amplification stage to be entered, thereby effectively suppressing the glitches caused by the amplifier settling time.

6. The high-voltage capacitorless low-noise linear regulator according to claim 1, characterized in that, All the high-voltage MOSFETs are double-diffused metal-oxide-semiconductor devices; the second, third, sixth, eighth and ninth high-voltage MOSFETs are respectively connected to clamping circuits, and the gate and drain of the MOSFETs inside the clamping circuits are connected to each other to avoid potential breakdown risks caused by high voltage.

7. A high-voltage capacitorless, low-noise linear regulator according to claim 1, characterized in that: The LDO supports an input voltage range of 3.7V to 65V and an output voltage range of 2.1V to 50V.

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