Method for manufacturing a heterojunction solar cell and heterojunction solar cell

Abstract

This invention provides a method for manufacturing a heterojunction solar cell and the heterojunction solar cell itself. The cell includes an N-type monocrystalline silicon wafer. On the front side of the wafer, a first intrinsic amorphous silicon layer, an N-type amorphous silicon / microcrystalline silicon layer, a first transparent conductive film, and a first electrode are sequentially formed. On the back side of the wafer, a second intrinsic amorphous silicon layer, a P-type amorphous silicon / microcrystalline silicon layer, a second transparent conductive film, and a second electrode are sequentially formed. The N-type amorphous silicon / microcrystalline silicon layer is formed before the P-type amorphous silicon / microcrystalline silicon layer, and both are formed using N-type PECVD and P-type PECVD processes, respectively. Before the P-type PECVD process, a plasma etching process is performed on the back side of the wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon. The etching gas used in the plasma etching process includes hydrogen, an inert gas, or a mixture of both. This invention avoids the adverse effects of pre-doped elements being deposited around the opposite side and improves the parallel resistance and conversion efficiency of the cell.

Description

Technical Field

[0001] This invention relates to the field of solar energy manufacturing, and particularly to a method for manufacturing heterojunction solar cells and heterojunction solar cells. Background Technology

[0002] Thin-film / crystalline silicon heterojunction solar cells (hereinafter referred to as heterojunction solar cells, also known as HIT, HJT, or SHJ solar cells) belong to the third generation of high-efficiency solar cell technology. They combine the advantages of first-generation crystalline silicon and second-generation silicon thin film, and have the characteristics of high conversion efficiency and low temperature coefficient. They will gradually replace PERC (Passivated Emitter and Rear Cell) cells and become the mainstream of solar cells.

[0003] The photoelectric conversion efficiency of heterojunction solar cells has now reached over 26%. Amorphous silicon layers are formed on both the front and back surfaces of a heterojunction solar cell. These amorphous silicon layers specifically include a front i-type amorphous silicon layer (referred to as "front i"), a back i-type amorphous silicon layer (referred to as "back i"), a front n-type amorphous silicon layer (referred to as "front n"), and a back p-type amorphous silicon / microcrystalline silicon layer (referred to as "back p"). One existing process for forming the amorphous silicon layer of a heterojunction solar cell is front i → front n → back i → back p. This process is simple and involves fewer wafer flipping operations. However, the doping elements in the front n step can easily contaminate the pyramidal textured surface of the back side due to the winding plating, leading to a decrease in the parallel resistance of the cell and a drop in conversion efficiency.

[0004] To avoid the influence of the doped elements in the amorphous silicon deposition process, some equipment manufacturers have changed the traditional and simple process flow from positive i → positive n → back i → back p to back i → positive i → positive n → back p. However, this process flow requires the silicon wafer to be flipped multiple times, and the silicon wafer will come into contact with the automated equipment multiple times, which will increase the manufacturing cost of the cavity and the automated equipment. At the same time, the contact between the n-type doped elements deposited on the back of the silicon wafer and the subsequent p-type doped elements will have an adverse effect on the parallel resistance and conversion efficiency of the battery.

[0005] Therefore, how to provide a method for manufacturing heterojunction solar cells and heterojunction solar cells in order to avoid the adverse effects of the pre-doped elements being deposited around the other side, and to improve the parallel resistance and conversion efficiency of the cells, has become a technical problem that urgently needs to be solved in the industry. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention proposes a method for fabricating heterojunction solar cells, comprising the following steps:

[0007] S01. Texturing and cleaning of N-type monocrystalline silicon wafers using a texturing and cleaning process;

[0008] S02. A first intrinsic amorphous silicon layer and an N-type amorphous silicon / microcrystalline silicon layer are formed sequentially on the top-facing side of an N-type monocrystalline silicon wafer using a first intrinsic PECVD process and an N-type PECVD process.

[0009] S03. Flip the N-type monocrystalline silicon wafer so that its back side faces up;

[0010] S04. Perform a plasma etching process on the back side of a silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon, wherein the etching gas in the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and an inert gas, wherein the inert gas includes argon and helium.

[0011] S05. A second intrinsic amorphous silicon layer and a P-type amorphous silicon / microcrystalline silicon layer are formed on the back side of the silicon wafer by means of a second intrinsic PECVD process and a P-type PECVD process, respectively.

[0012] S06. A first transparent conductive film and a second transparent conductive film are formed on the N-type amorphous silicon / microcrystalline silicon layer and the P-type amorphous silicon / microcrystalline silicon layer, respectively; and

[0013] S07. A first electrode and a second electrode are formed on the first transparent conductive film and the second transparent conductive film, respectively.

[0014] In one embodiment, in step S04, the etching time of the plasma etching process ranges from 5 to 50 seconds, the etching power ranges from 100 to 2000 W, the etching frequency ranges from 350 kHz to 81.56 MHz, and the etching pressure ranges from 0.1 to 100 mbar.

[0015] In one embodiment, steps S04 and S05 are both performed in the reaction chamber of a PECVD device under vacuum.

[0016] In one embodiment, step S04 is performed in a preheating chamber under vacuum, and step S05 is performed in the reaction chamber of the PECVD equipment under vacuum.

[0017] The present invention also provides a method for preparing a heterojunction solar cell, comprising the following steps:

[0018] S11. Texturing and cleaning of N-type monocrystalline silicon wafers using a texturing and cleaning process;

[0019] S12. A first intrinsic amorphous silicon layer is formed on the upward-facing back side of an N-type monocrystalline silicon wafer using a first intrinsic PECVD process;

[0020] S13. Flip the N-type monocrystalline silicon wafer so that the front side is facing up;

[0021] S14. A second intrinsic amorphous silicon layer and an N-type amorphous silicon / microcrystalline silicon layer are formed on the front side of the silicon wafer by the second intrinsic PECVD process and the N-type PECVD process, respectively.

[0022] S15. Flip the N-type monocrystalline silicon wafer so that its back side faces up;

[0023] S16. Perform a plasma etching process on the back side of a silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon, wherein the etching gas in the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and an inert gas, wherein the inert gas includes argon and helium.

[0024] S17. A P-type amorphous silicon / microcrystalline silicon layer is formed on the first intrinsic amorphous silicon layer on the back side of a silicon wafer by a P-type PECVD process.

[0025] S18. A first transparent conductive film and a second transparent conductive film are formed on the N-type amorphous silicon / microcrystalline silicon layer and the P-type amorphous silicon / microcrystalline silicon layer, respectively; and

[0026] S19. A first electrode and a second electrode are formed on the first transparent conductive film and the second transparent conductive film, respectively.

[0027] In one embodiment, in step S16, the etching time of the plasma etching process ranges from 5 to 50 seconds, the etching power ranges from 100 to 2000 W, the etching frequency ranges from 350 kHz to 81.56 MHz, and the etching pressure ranges from 0.1 to 100 mbar.

[0028] In one embodiment, steps S16 and S17 are both performed in the reaction chamber of a PECVD device under vacuum.

[0029] In one embodiment, step S16 is performed in a preheating chamber under vacuum, and step S17 is performed in the reaction chamber of the PECVD equipment under vacuum.

[0030] The present invention also provides a heterojunction solar cell, comprising an N-type monocrystalline silicon wafer. A first intrinsic amorphous silicon layer, an N-type amorphous silicon / microcrystalline silicon layer, a first transparent conductive film, and a first electrode are sequentially formed on the front side of the N-type monocrystalline silicon wafer. A second intrinsic amorphous silicon layer, a P-type amorphous silicon / microcrystalline silicon layer, a second transparent conductive film, and a second electrode are sequentially formed on the back side of the N-type monocrystalline silicon wafer. The N-type amorphous silicon / microcrystalline silicon layer is formed before the P-type amorphous silicon / microcrystalline silicon layer, and both are formed by N-type PECVD and P-type PECVD processes, respectively. Before the P-type PECVD process, a plasma etching process is performed on the back side of the silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon. The etching gas in the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and an inert gas, wherein the inert gas includes argon and helium.

[0031] In one embodiment, the plasma etching process has an etching time range of 5-50s, an etching power range of 100-2000w, an etching frequency range of 350kHz-81.56MHZ, and an etching pressure range of 0.1-100mbar.

[0032] Compared to existing technologies where an N-type amorphous silicon / microcrystalline silicon layer is directly deposited around the back of a monocrystalline silicon wafer, resulting in a higher parallel resistance and lower efficiency, the heterojunction solar cell of this invention comprises an N-type monocrystalline silicon wafer. On the front side of the N-type monocrystalline silicon wafer, a first intrinsic amorphous silicon layer, an N-type amorphous silicon / microcrystalline silicon layer, a first transparent conductive film, and a first electrode are sequentially formed. On the back side of the N-type monocrystalline silicon wafer, a second intrinsic amorphous silicon layer, a P-type amorphous silicon / microcrystalline silicon layer, and a second transparent conductive film are sequentially formed. The invention includes a conductive film and a second electrode, wherein the N-type amorphous silicon / microcrystalline silicon layer is formed before the P-type amorphous silicon / microcrystalline silicon layer, and both are formed by N-type PECVD and P-type PECVD processes, respectively. Before the P-type PECVD process, a plasma etching process is performed on the back side of the silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon. The etching gas for the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and inert gases, and the inert gas includes argon and helium. This invention performs a plasma etching process using hydrogen and / or an inert gas as the etching gas to remove the pre-doped elements deposited thereon before the deposition of post-doped elements. Therefore, it avoids the adverse effects of pre-doped elements being deposited on the other side, and improves the parallel resistance and conversion efficiency of the battery. Attached Figure Description

[0033] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0034] Figure 1 This is a schematic flowchart of the first embodiment of the method for manufacturing heterojunction solar cells according to the present invention.

[0035] Figure 2 This is a schematic diagram of the composition and structure of a heterojunction solar cell embodiment of the present invention.

[0036] Figure 3 To complete Figure 1 A schematic diagram of the battery structure after step S120 in the first embodiment of the method for manufacturing heterojunction solar cells.

[0037] Figure 4 To complete Figure 1 A schematic diagram of the battery composition structure after step S140 in the first embodiment of the method for manufacturing heterojunction solar cells.

[0038] Figure 5 This is a schematic flowchart of a second embodiment of the method for manufacturing heterojunction solar cells according to the present invention.

[0039] Figure 6 To complete Figure 5 A schematic diagram of the battery composition structure after step S540 in the second embodiment of the method for manufacturing heterojunction solar cells.

[0040] Figure 7 To complete Figure 5 A schematic diagram of the battery composition structure after step S560 in the second embodiment of the method for manufacturing heterojunction solar cells. Detailed Implementation Plan

[0041] The present invention will now be described in detail with reference to the accompanying drawings and embodiments to provide a clearer understanding of its objectives, features, and advantages. It should be understood that the aspects described below with reference to the accompanying drawings and embodiments are merely exemplary and should not be construed as limiting the scope of protection of the present invention in any way. Unless the context explicitly indicates otherwise, the singular forms “a” and “described” include plural referents. It should be noted that, in this document, relational terms such as “first” and “second” are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0042] See Figure 1This is a schematic flowchart of the first embodiment of the method for manufacturing heterojunction solar cells according to the present invention. See also... Figure 2 It shows through Figure 1 The manufacturing method shown illustrates the composition and structure of a heterojunction solar cell. For example... Figure 2 As shown, the heterojunction solar cell 2 includes an N-type monocrystalline silicon wafer 20 having a first surface (front) S1 and a second surface (back) S2, where the front surface S1 is typically the sunlight incident surface. The heterojunction solar cell 2 also includes a first intrinsic amorphous silicon layer 21, an N-type amorphous silicon / microcrystalline silicon layer 22, a first transparent conductive film 23, and a first electrode 24 sequentially stacked on the front surface S1, and a second intrinsic amorphous silicon layer 25, a P-type amorphous silicon / microcrystalline silicon layer 26, a second transparent conductive film 27, and a second electrode 28 sequentially stacked on the back surface S2. The first intrinsic amorphous silicon layer 21 can also be referred to as the front intrinsic amorphous silicon layer 21, and the second intrinsic amorphous silicon layer 25 can also be referred to as the back intrinsic amorphous silicon layer 25.

[0043] The resistivity of N-type single-crystal silicon wafers 20 can be 0.5-3Ω·cm, the thickness can be 100-180 micrometers (μm), and the size can be 125mm×125mm, 156mm×156mm, 166mm×166mm or 210mm×210mm, etc., which are currently commonly used or will be common sizes in the future.

[0044] The thickness of both the first intrinsic amorphous silicon layer 21 and the second intrinsic amorphous silicon layer 25 can range from 4 to 10 nanometers (nm). The thickness of both the N-type amorphous silicon / microcrystalline silicon layer 22 and the P-type amorphous silicon / microcrystalline silicon layer 26 can range from 4 to 30 nanometers. The amorphous silicon / microcrystalline silicon layer in the N-type amorphous silicon / microcrystalline silicon layer 22 and the P-type amorphous silicon / microcrystalline silicon layer 26 can be entirely amorphous silicon, entirely microcrystalline silicon, or a hybrid layer of amorphous silicon and microcrystalline silicon. That is, the N-type amorphous silicon / microcrystalline silicon layer 22 can include N-type amorphous silicon layers, N-type microcrystalline silicon layers, and N-type amorphous silicon / microcrystalline silicon hybrid layers; the P-type amorphous silicon / microcrystalline silicon layer 26 can include P-type amorphous silicon layers, P-type microcrystalline silicon layers, and P-type amorphous silicon / microcrystalline silicon hybrid layers.

[0045] The N-type amorphous silicon / microcrystalline silicon layer 22 is formed before the P-type amorphous silicon / microcrystalline silicon layer 26, and both are formed by N-type PECVD and P-type PECVD processes respectively (see below). Before the P-type PECVD process, a plasma etching process is performed on the back side of the silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon. The etching gas for the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and inert gases, and the inert gas includes argon and helium. The etching time range of the plasma etching process is 5-50s, the etching power range is 100-2000W, the etching frequency range is 350kHz-81.56MHz, and the etching pressure range is 0.1-100mbar.

[0046] Both the first transparent conductive film 23 and the second transparent conductive film 27 can be indium tin oxide (ITO), ZnO-based TCO, IWO, or ITIO transparent conductive films, which can be formed on the N-type amorphous silicon / microcrystalline silicon layer 22 and the P-type amorphous silicon / microcrystalline silicon layer 26 respectively by sputtering. The thickness of both the first transparent conductive film 23 and the second transparent conductive film 27 can be in the range of 70-110 nanometers.

[0047] The first electrode 24 and the second electrode 28 can be formed by silver paste screen printing and sintering commonly used in the industry, or they can be electroplated electrodes commonly used in the industry. The specific thicknesses and characteristics of the other components of the heterojunction solar cell 2 are known to those skilled in the art and will not be described in detail here.

[0048] See also Figure 1 See also Figure 2 The method 10 for manufacturing heterojunction solar cells first performs step S100, which involves texturing and cleaning the N-type monocrystalline silicon wafer 20 using a texturing and cleaning process. In this embodiment, step S100 uses an alkaline etching solution (e.g., a mixture of sodium hydroxide solution, potassium hydroxide solution, isopropanol, and Na2SiO3) to remove the damaged layer and form a pyramid-shaped textured surface on the N-type monocrystalline silicon wafer 20.

[0049] Method 10 continues with step S110, forming a first intrinsic amorphous silicon layer 21 on the facing side S1 of the N-type monocrystalline silicon wafer 20 using a first intrinsic PECVD process. In this embodiment, the first intrinsic PECVD process uses silane or a mixture of silane and hydrogen as the process gas, and the thickness of the first intrinsic amorphous silicon layer 21 can be 4-10 nanometers.

[0050] Method 10 continues to step S120, forming an N-type amorphous silicon / microcrystalline silicon layer 22 on the first intrinsic amorphous silicon layer 21 using an N-type PECVD process. In this embodiment, the thickness of the N-type amorphous silicon / microcrystalline silicon layer 22 is 4-30 nanometers, and the process gas for the N-type PECVD process includes silane, hydrogen, and phosphine, or other gases suitable for N-type doping.

[0051] See Figure 3 This is a schematic diagram of the battery structure after step S120 in the first embodiment of the method for manufacturing heterojunction solar cells according to the present invention. In addition to forming an N-type amorphous silicon / microcrystalline silicon layer 22 on the first intrinsic amorphous silicon layer 21 on the front side S1, step S120 also forms a wound-deposited N-type amorphous silicon / microcrystalline silicon layer 220 on the back side S2 of the N-type monocrystalline silicon wafer 20.

[0052] It should be noted that step S110 also involves depositing a first intrinsic amorphous silicon layer on the back side S2 of the N-type monocrystalline silicon wafer 20, but this has virtually no adverse effect on battery performance and conversion efficiency, so it will not be described in this invention.

[0053] See also Figure 1 See also Figure 2 Method 10 continues with step S130, flipping the N-type monocrystalline silicon wafer 20 so that its back side S2 faces upward. Various silicon wafer flipping devices commonly used in the industry can be used to flip the silicon wafer in step S130.

[0054] Method 10 continues to step S140, performing a plasma etching process on the back side S2 of the silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer 220 deposited thereon. The etching gas for the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and inert gases, wherein the inert gas includes argon and helium. In step S140, the etching time ranges from 5 to 50 seconds, the etching power ranges from 100 to 2000 W, the etching frequency ranges from 350 kHz to 81.56 MHz, and the etching pressure ranges from 0.1 to 100 mbar. Those skilled in the art can select the etching gas and etching parameters from the above parameter ranges according to specific circumstances, for example, choosing a mixture of hydrogen and argon as the etching gas and 13.56 MHz or 40.68 MHz as the etching frequency.

[0055] See Figure 4 This is a schematic diagram of the cell composition structure after step S140 in the first embodiment of the method for manufacturing heterojunction solar cells according to the present invention. Figure 4 As shown, Figure 3The N-type amorphous silicon / microcrystalline silicon layer 220 located on the back side S2 of the silicon wafer shown has been removed, thereby eliminating the adverse effects of the N-type amorphous silicon / microcrystalline silicon layer 220 on the parallel resistance and conversion efficiency of the heterojunction solar cell.

[0056] Method 10 continues to step S150, forming a second intrinsic amorphous silicon layer 25 on the back side S2 of the silicon wafer using a second intrinsic PECVD process. The second intrinsic PECVD process in step S150 can be exactly the same as the first intrinsic PECVD process in step S110, or it can be adjusted according to specific circumstances. In this embodiment, the second intrinsic PECVD process uses silane or a mixture of silane and hydrogen as the process gas, and the thickness of the second intrinsic amorphous silicon layer 25 can range from 4 to 10 nanometers.

[0057] Method 10 continues to step S160, forming a P-type amorphous silicon / microcrystalline silicon layer 26 on the second intrinsic amorphous silicon layer 25 using a P-type PECVD process. In this embodiment, the thickness of the P-type amorphous silicon / microcrystalline silicon layer 22 in step S160 is 4-30 nanometers, and the process gas for the P-type PECVD process includes silane, hydrogen, and borane, or other gases suitable for P-type doping.

[0058] Steps S140, S150, and S160 can all be performed in the PECVD equipment reaction chamber under vacuum, and all three steps can be performed in the same PECVD equipment reaction chamber. Alternatively, the three steps can be performed in different PECVD equipment reaction chambers; for example, steps S140 and S150 can be performed in the same PECVD equipment reaction chamber, while step S160 can be performed in a different PECVD equipment reaction chamber; or, steps S150 and S160 can be performed in the same PECVD equipment reaction chamber, while step S140 can be performed in a different PECVD equipment reaction chamber.

[0059] Steps S140, S150, and S160 can also be performed in different types of chambers. For example, step S140 can be performed in a preheating chamber under vacuum, which is equipped with a corresponding plasma generation module. Meanwhile, steps S150 and S160 can be performed in the same PECVD equipment reaction chamber under vacuum, or steps S150 and S160 can be performed in different PECVD equipment reaction chambers under vacuum.

[0060] See also Figure 1 See also Figure 2Method 10 continues to step S170, where a first transparent conductive film 23 and a second transparent conductive film 27 are formed on the N-type amorphous silicon / microcrystalline silicon layer 22 and the P-type amorphous silicon / microcrystalline silicon layer 26, respectively. In step S170, the first transparent conductive film 23 and the second transparent conductive film 27 are formed on the N-type amorphous silicon / microcrystalline silicon layer 22 and the P-type amorphous silicon / microcrystalline silicon layer 26 by reactive plasma deposition or physical vapor deposition. Both the first transparent conductive film 23 and the second transparent conductive film 27 can be indium tin oxide (ITO), ZnO-based, IWO, or ITIO transparent conductive films, which can be deposited by sputtering. The thickness of both the first transparent conductive film 23 and the second transparent conductive film 27 can be in the range of 70-110 nm.

[0061] Method 10 continues to step S180, forming a first electrode 24 and a second electrode 28 on the first transparent conductive film 23 and the second transparent conductive film 27, respectively. The first electrode 24 and the second electrode 28 in step S180 can be formed by screen printing, specifically by screen printing and sintering of silver paste commonly used in the industry, or by electroplating commonly used in the industry.

[0062] See Figure 5 This is a schematic flowchart of a second embodiment of the method for manufacturing heterojunction solar cells according to the present invention. Figure 5 The heterojunction solar cell formed by the manufacturing method shown also has the same composition and structure as... Figure 2 As shown, the specific structure of the heterojunction solar cell 2 is as described above. Figure 5 The second embodiment of the method shown is similar to Figure 1 In the first embodiment of the method shown, many steps are the same or similar. For the sake of simplicity, the similar or identical process steps will not be described in detail below. Please refer to the corresponding descriptions and records above for details.

[0063] See Figure 5 See also Figure 2 The method 50 for manufacturing heterojunction solar cells first performs step S500, which involves texturing and cleaning the N-type monocrystalline silicon wafer 20 using a texturing and cleaning process. In this embodiment, step S500 involves using an alkaline etching solution (e.g., a mixture of sodium hydroxide solution, potassium hydroxide solution, isopropanol, and Na2SiO3) to remove the damaged layer and form a pyramid-shaped textured surface on the monocrystalline silicon wafer.

[0064] Method 50 continues with step S510, forming a first intrinsic amorphous silicon layer 25 (or back intrinsic amorphous silicon layer 25) on the upward-facing back side S2 of the N-type monocrystalline silicon wafer using a first intrinsic PECVD process. In this embodiment, the first intrinsic PECVD process uses silane or a mixture of silane and hydrogen as the process gas, and the thickness of the first intrinsic amorphous silicon layer 25 can be 4-10 nanometers.

[0065] Method 50 continues with step S520, flipping the N-type monocrystalline silicon wafer 20 so that its front side S1 faces upward. Step S520 can be performed using a commonly used silicon wafer flipping device.

[0066] Method 50 continues to step S530, forming a second intrinsic amorphous silicon layer 21 (or front intrinsic amorphous silicon layer 21) on the front side S1 of the silicon wafer using a second intrinsic PECVD process. In this embodiment, the second intrinsic PECVD process uses silane or a mixture of silane and hydrogen as the process gas, and the thickness of the second intrinsic amorphous silicon layer can be 4-10 nanometers.

[0067] Method 50 continues to step S540, forming an N-type amorphous silicon / microcrystalline silicon layer 22 on the second intrinsic amorphous silicon layer 21 using an N-type PECVD process. In this embodiment, the thickness of the N-type amorphous silicon layer 22 is 4-30 nanometers, and the process gas for the N-type PECVD process includes silane, hydrogen, and phosphine, or other gases suitable for N-type doping.

[0068] See Figure 6 This is a schematic diagram of the cell composition structure after step S540 in the second embodiment of the method for manufacturing heterojunction solar cells of the present invention. In addition to forming an N-type amorphous silicon / microcrystalline silicon layer 22 on the second intrinsic amorphous silicon layer 21 on the front side S1, step S540 also forms a wound-deposited N-type amorphous silicon / microcrystalline silicon layer 220 on the first intrinsic amorphous silicon layer 25 on the back side S2 of the N-type silicon wafer.

[0069] Method 50 continues with step S550, flipping the N-type monocrystalline silicon wafer 20 so that its back side S2 faces upward. Step S550 can be performed by flipping the silicon wafer using a commonly used silicon wafer flipping device in the industry.

[0070] Method 50 continues to step S560, performing a plasma etching process on the back side S2 of the silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer 220 deposited thereon. The etching gas for the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and inert gases, wherein the inert gas includes argon and helium. In step S560, the etching time of the plasma etching process ranges from 5 to 50 seconds, the etching power ranges from 100 to 2000 W, the etching frequency ranges from 350 kHz to 81.56 MHz, and the etching pressure ranges from 0.1 to 100 mbar.

[0071] See Figure 7 This is a schematic diagram of the cell composition structure after step S560 in the second embodiment of the method for manufacturing heterojunction solar cells according to the present invention. Figure 7 As shown, Figure 6 The N-type amorphous silicon / microcrystalline silicon layer 220 located on the back side S2 of the silicon wafer shown has been removed, thereby eliminating the adverse effects of the N-type amorphous silicon / microcrystalline silicon layer 220 on the parallel resistance and conversion efficiency of the heterojunction solar cell.

[0072] Method 50 continues to step S570, forming a P-type amorphous silicon / microcrystalline silicon layer 26 on the first intrinsic amorphous silicon layer 25 on the back side S2 of the silicon wafer by a P-type PECVD process.

[0073] Both steps S560 and S570 can be performed in the reaction chamber of the PECVD equipment under vacuum. That is, the two steps can be performed in the same PECVD equipment reaction chamber or in different PECVD equipment reaction chambers.

[0074] Steps S560 and S570 can also be performed in different types of chambers. For example, step S560 can be performed in a preheating chamber under vacuum, which is equipped with a corresponding plasma generation module; meanwhile, step S570 can be performed in the reaction chamber of a PECVD device under vacuum.

[0075] Method 50 continues to step S580, where a first transparent conductive film 23 and a second transparent conductive film 27 are formed on the N-type amorphous silicon / microcrystalline silicon layer 22 and the P-type amorphous silicon / microcrystalline silicon layer 26, respectively. In step S580, the first transparent conductive film 23 and the second transparent conductive film 27 are formed on the N-type amorphous silicon / microcrystalline silicon layer 22 and the P-type amorphous silicon / microcrystalline silicon layer 26 by reactive plasma deposition or physical vapor deposition. Both the first transparent conductive film 23 and the second transparent conductive film 27 can be indium tin oxide (ITO), ZnO-based, IWO, or ITIO transparent conductive films, which can be deposited on the N-type amorphous silicon / microcrystalline silicon layer and the P-type amorphous silicon / microcrystalline silicon layer by sputtering.

[0076] Method 50 continues to step S590, forming a first electrode 24 and a second electrode 28 on the first transparent conductive film 23 and the second transparent conductive film 27, respectively. The first electrode 24 and the second electrode 28 in step S590 can be formed by screen printing, specifically by screen printing and sintering of silver paste commonly used in the industry, or by electroplating commonly used in the industry.

[0077] The heterojunction solar cell of the present invention includes an N-type monocrystalline silicon wafer. A first intrinsic amorphous silicon layer, an N-type amorphous silicon / microcrystalline silicon layer, a first transparent conductive film, and a first electrode are sequentially formed on the front side of the N-type monocrystalline silicon wafer. A second intrinsic amorphous silicon layer, a P-type amorphous silicon / microcrystalline silicon layer, a second transparent conductive film, and a second electrode are sequentially formed on the back side of the N-type monocrystalline silicon wafer. The N-type amorphous silicon / microcrystalline silicon layer is formed before the P-type amorphous silicon / microcrystalline silicon layer, and both are formed by N-type PECVD and P-type PECVD processes, respectively. Before the P-type PECVD process, a plasma etching process is performed on the back side of the silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon. The etching gas in the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and an inert gas. The inert gas includes argon and helium. The present invention performs a plasma etching process using hydrogen and / or inert gas as etching gas before depositing the post-doped element to remove the pre-doped element layer that has been deposited around it. This avoids the adverse effects of the pre-doped element being deposited around to the other side, and can improve the parallel resistance and conversion efficiency of the battery, with an improvement in conversion efficiency of at least 0.3%.

[0078] The above embodiments are provided for those skilled in the art to implement or use the present invention. Those skilled in the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the protection scope of the present invention is not limited to the above embodiments, but should be the maximum scope that conforms to the innovative features mentioned in the claims.

Claims

1. A method for fabricating a heterojunction solar cell, comprising the following steps: S01. Texturing and cleaning of N-type monocrystalline silicon wafers using a texturing and cleaning process; S02. A first intrinsic amorphous silicon layer and an N-type amorphous silicon / microcrystalline silicon layer are formed sequentially on the top-facing side of an N-type monocrystalline silicon wafer using a first intrinsic PECVD process and an N-type PECVD process. S03. Flip the N-type monocrystalline silicon wafer so that its back side faces up; S04. Perform a plasma etching process on the back side of a silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon, wherein the etching gas in the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and an inert gas, wherein the inert gas includes argon and helium. S05. A second intrinsic amorphous silicon layer and a P-type amorphous silicon / microcrystalline silicon layer are formed on the back side of the silicon wafer by means of a second intrinsic PECVD process and a P-type PECVD process, respectively. S06. A first transparent conductive film and a second transparent conductive film are formed on the N-type amorphous silicon / microcrystalline silicon layer and the P-type amorphous silicon / microcrystalline silicon layer, respectively; as well as S07. A first electrode and a second electrode are formed on the first transparent conductive film and the second transparent conductive film, respectively.

2. The method for preparing heterojunction solar cells according to claim 1, characterized in that, In step S04, the etching time of the plasma etching process ranges from 5 to 50 seconds, the etching power ranges from 100 to 2000 W, the etching frequency ranges from 350 kHz to 81.56 MHz, and the etching pressure ranges from 0.1 to 100 mbar.

3. The method for preparing a heterojunction solar cell according to claim 1, characterized in that, Steps S04 and S05 are both performed in the reaction chamber of the PECVD equipment under vacuum.

4. The method for preparing a heterojunction solar cell according to claim 1, characterized in that, Step S04 is carried out in a preheating chamber under vacuum, and step S05 is carried out in the reaction chamber of the PECVD equipment under vacuum.

5. A method for fabricating a heterojunction solar cell, comprising the following steps: S11. Texturing and cleaning of N-type monocrystalline silicon wafers using a texturing and cleaning process; S12. A first intrinsic amorphous silicon layer is formed on the upward-facing back side of an N-type monocrystalline silicon wafer using a first intrinsic PECVD process; S13. Flip the N-type monocrystalline silicon wafer so that the front side is facing up; S14. A second intrinsic amorphous silicon layer and an N-type amorphous silicon / microcrystalline silicon layer are formed on the front side of the silicon wafer by the second intrinsic PECVD process and the N-type PECVD process, respectively. S15. Flip the N-type monocrystalline silicon wafer so that its back side faces up; S16. Perform a plasma etching process on the back side of a silicon wafer to remove the N-type amorphous silicon / microcrystalline silicon layer deposited thereon, wherein the etching gas in the plasma etching process includes hydrogen, an inert gas, or a mixture of hydrogen and an inert gas, wherein the inert gas includes argon and helium. S17. A P-type amorphous silicon / microcrystalline silicon layer is formed on the first intrinsic amorphous silicon layer on the back side of a silicon wafer by a P-type PECVD process. S18. A first transparent conductive film and a second transparent conductive film are formed on the N-type amorphous silicon / microcrystalline silicon layer and the P-type amorphous silicon / microcrystalline silicon layer, respectively; and S19. A first electrode and a second electrode are formed on the first transparent conductive film and the second transparent conductive film, respectively.

6. The method for preparing a heterojunction solar cell according to claim 5, characterized in that, In step S16, the etching time of the plasma etching process ranges from 5 to 50 seconds, the etching power ranges from 100 to 2000 W, the etching frequency ranges from 350 kHz to 81.56 MHz, and the etching pressure ranges from 0.1 to 100 mbar.

7. The method for preparing a heterojunction solar cell according to claim 5, characterized in that, Steps S16 and S17 are both performed in the reaction chamber of the PECVD equipment under vacuum.

8. The method for preparing a heterojunction solar cell according to claim 5, characterized in that, Step S16 is performed in a preheating chamber under vacuum, and step S17 is performed in the reaction chamber of the PECVD equipment under vacuum.

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