Method and apparatus for determining a bit punchthrough condition

Abstract

Embodiments of the present application provide a method and device for determining a bit breakdown condition, the method comprising: determining a plurality of first breakdown conditions; performing breakdown on corresponding first bits according to each first breakdown condition respectively to obtain a first breakdown result of each first breakdown condition, different first breakdown conditions corresponding to different first bits; and determining a second breakdown condition from the plurality of first breakdown conditions according to the first breakdown result. Embodiments of the present application can perform breakdown experiments through the plurality of first breakdown conditions to determine the second breakdown condition. Since the second breakdown condition is selected through the breakdown result of the breakdown experiment, the second breakdown condition can have a better breakdown effect.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method and apparatus for determining bit breakdown conditions. Background Technology

[0002] In the field of semiconductor technology, memory arrays are used to store data. A memory array consists of multiple bits, each of which stores one bit of data. Memory arrays can be divided into primary arrays and redundant arrays. Bits in the redundant array (called redundant bits) are used to replace faulty bits (called faulty bits) in the primary array. After replacing the faulty bits, the data that needs to be stored in the faulty bits is actually stored in the corresponding redundant bits.

[0003] In the prior art, before the above replacement process is performed, the oxide layer between the gate and drain of the redundant bits needs to be broken down to form a path. This breakdown process is carried out according to breakdown conditions, which may include, but are not limited to, breakdown duration and breakdown voltage. When the breakdown duration and / or breakdown voltage is too small, breakdown failure may occur.

[0004] It can be seen that the breakdown conditions used in the above breakdown process affect the breakdown effect, so how to select the breakdown conditions for redundant bits is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a method and apparatus for determining bit breakdown conditions, so as to determine the breakdown conditions of redundant bits.

[0006] In a first aspect, embodiments of this application provide a method for determining bit breakdown conditions, the method comprising:

[0007] Determine multiple first breakdown conditions;

[0008] According to each first breakdown condition, the corresponding first bit is broken down to obtain the first breakdown result of each first breakdown condition. Different first breakdown conditions correspond to different first bits.

[0009] A second breakdown condition is determined from the plurality of first breakdown conditions based on the first breakdown result.

[0010] Optionally, the first breakdown result is used to indicate whether the plurality of first bits of the first breakdown condition have been broken down, and the step of determining the second breakdown condition from the plurality of first breakdown conditions based on the first breakdown result includes:

[0011] The breakdown success rate of the first breakdown condition is determined based on the first breakdown result;

[0012] The second breakdown condition is determined from the first breakdown condition, which states that the breakdown success rate is greater than or equal to a preset success rate threshold.

[0013] Optionally, determining the second breakdown condition from the first breakdown condition where the breakdown success rate is greater than or equal to a preset success rate threshold includes:

[0014] The first breakdown condition, in which the breakdown success rate is greater than or equal to a preset success rate threshold, is used as the third breakdown condition.

[0015] The third breakdown condition that meets the preset conditions is determined as the second breakdown condition. The preset conditions are conditions for at least one parameter: false breakdown rate, current difference, breakdown time included in the first breakdown condition, and breakdown voltage included in the first breakdown condition. The current difference is the difference in current magnitude between non-broken bits and broken bits.

[0016] Optionally, the conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to a preset false breakdown rate, or the false breakdown rate is arranged in ascending order and is in the first M positions;

[0017] The conditions for the current difference include at least one of the following: the current difference is greater than or equal to a preset current difference, or the current difference is ranked in descending order and is among the top N.

[0018] The conditions for the breakdown duration include at least one of the following: the breakdown duration is less than or equal to a preset duration, or the breakdown duration is arranged in ascending order and is in the first L positions;

[0019] The conditions for the breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to a preset voltage, or the breakdown voltage is arranged in ascending order and is in the first K positions.

[0020] Optionally, the method further includes:

[0021] If the first breakdown condition where the breakdown success rate is greater than or equal to the preset success rate threshold does not exist, then the breakdown duration and / or the breakdown voltage included in the first breakdown condition are increased, and the process proceeds to the step of breaking down the corresponding first bit according to each first breakdown condition to obtain the first breakdown result of each first breakdown condition.

[0022] Optionally, increasing the breakdown time and / or breakdown voltage of the first breakdown condition includes:

[0023] Increase the breakdown duration in the first target breakdown condition, wherein the first target breakdown condition is one or more first breakdown conditions with the largest breakdown duration;

[0024] And / or, increase the breakdown voltage in the second target breakdown condition, where the second target breakdown condition is one or more first breakdown conditions with the largest breakdown voltage.

[0025] Optionally, before determining the third breakdown condition that satisfies the preset conditions as the second breakdown condition, the method further includes:

[0026] For the third breakdown condition, determine the second bit to be broken down and the third bit other than the second bit;

[0027] The second bit is broken down according to the third breakdown condition to obtain the second breakdown result;

[0028] The false breakdown rate for the third bit is determined based on the second breakdown result.

[0029] Optionally, the second breakdown result is used to indicate whether the third bit has been broken down, and the step of determining the false breakdown rate for the third bit based on the second breakdown result includes:

[0030] Determine the total number of the second bit and the third bit;

[0031] The false breakdown rate is determined based on the ratio of the number of third bits that have been broken down to the total number.

[0032] Optionally, it also includes:

[0033] If the third breakdown condition corresponding to the false breakdown rate does not exist, then the breakdown time and / or breakdown voltage included in the third breakdown condition are reduced, and the process proceeds to the step of breaking down the second bit according to the third breakdown condition to obtain the second breakdown result.

[0034] Optionally, reducing the breakdown time and / or breakdown voltage included in the third breakdown condition includes:

[0035] Reduce the breakdown time in the third target breakdown condition, wherein the third target breakdown condition is one or more third breakdown conditions with the minimum breakdown time;

[0036] And / or, reduce the breakdown voltage in the fourth target breakdown condition, which is one or more third breakdown conditions that minimize the breakdown voltage.

[0037] Optionally, the third bit is set at a position adjacent to the second bit.

[0038] Optionally, the first breakdown condition corresponds to multiple first bits, and the multiple first bits corresponding to the same first breakdown condition are located in at least two non-adjacent regions of the redundant array.

[0039] The third breakdown condition corresponds to multiple second bits, and the multiple second bits corresponding to the same third breakdown condition are located in at least two non-adjacent regions of the redundant array.

[0040] Optionally, multiple first bits corresponding to the same first breakdown condition are located in two centrally symmetrical, non-adjacent regions of the redundant array;

[0041] The second bits corresponding to the same third breakdown condition are located in two centrally symmetrical, non-adjacent regions of the redundant array.

[0042] Optionally, before determining the third breakdown condition that satisfies the preset conditions as the second breakdown condition, the method further includes:

[0043] For the third breakdown condition, a first current passing through the broken-down bit and a second current passing through the non-broken-down bit are determined. The broken-down bit includes at least one of the following: the broken-down first bit and the broken-down second bit. The non-broken-down bit includes at least one of the following: the non-broken third bit.

[0044] The current difference is determined based on the first current and the second current.

[0045] Secondly, embodiments of this application provide a device for determining bit breakdown conditions, the device comprising:

[0046] The first breakdown condition determination module is used to determine multiple first breakdown conditions;

[0047] The first bit breakdown module is used to break down the corresponding first bit according to each first breakdown condition to obtain the first breakdown result of each first breakdown condition. Different first breakdown conditions correspond to different first bits.

[0048] The second breakdown condition determination module is used to determine a second breakdown condition from the plurality of first breakdown conditions based on the first breakdown result.

[0049] Optionally, the first breakdown result is used to indicate whether the multiple first bits of the first breakdown condition have been broken down, and the second breakdown condition determination module is further used to:

[0050] The breakdown success rate of the first breakdown condition is determined based on the first breakdown result;

[0051] The second breakdown condition is determined from the first breakdown condition, which states that the breakdown success rate is greater than or equal to a preset success rate threshold.

[0052] Optionally, the second breakdown condition determination module is further configured to:

[0053] In the process of determining the second breakdown condition from the first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold, the first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold is used as the third breakdown condition.

[0054] The third breakdown condition that meets the preset conditions is determined as the second breakdown condition. The preset conditions are conditions for at least one parameter: false breakdown rate, current difference, breakdown time included in the first breakdown condition, and breakdown voltage included in the first breakdown condition. The current difference is the difference in current magnitude between non-broken bits and broken bits.

[0055] Optionally, the conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to a preset false breakdown rate, or the false breakdown rate is arranged in ascending order and is in the first M positions;

[0056] The conditions for the current difference include at least one of the following: the current difference is greater than or equal to a preset current difference, or the current difference is ranked in descending order and is among the top N.

[0057] The conditions for the breakdown duration include at least one of the following: the breakdown duration is less than or equal to a preset duration, or the breakdown duration is arranged in ascending order and is in the first L positions;

[0058] The conditions for the breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to a preset voltage, or the breakdown voltage is arranged in ascending order and is in the first K positions.

[0059] Optionally, the device further includes:

[0060] The first breakdown condition adjustment module is used to increase the breakdown duration and / or the breakdown voltage included in the first breakdown condition if the first breakdown condition, in which the breakdown success rate is greater than or equal to a preset success rate threshold, does not exist, and then enter the first bit breakdown module.

[0061] Optionally, the first breakdown condition adjustment module is used to:

[0062] In the process of increasing the breakdown duration and / or breakdown voltage included in the first breakdown condition, the breakdown duration in the first target breakdown condition is increased, and the first target breakdown condition is one or more first breakdown conditions with the largest breakdown duration.

[0063] And / or, in the process of increasing the breakdown duration and / or the breakdown voltage included in the first breakdown condition, the breakdown voltage in the second target breakdown condition is increased, wherein the second target breakdown condition is one or more of the first breakdown conditions with the largest breakdown voltage.

[0064] Optionally, the device further includes:

[0065] The bit determination module is used to determine the second bit to be broken down and a third bit other than the second bit for the third breakdown condition before determining the third breakdown condition that meets the preset condition as the second breakdown condition.

[0066] The second bit breakdown module is used to break down the second bit according to the third breakdown condition to obtain the second breakdown result;

[0067] The false breakdown rate determination module is used to determine the false breakdown rate for the third bit based on the second breakdown result.

[0068] Optionally, the second breakdown result is used to indicate whether the third bit has been broken down, and the false breakdown rate determination module is further used to:

[0069] In determining the false breakdown rate for the third bit based on the second breakdown result, the total number of the second bit and the third bit is determined;

[0070] The false breakdown rate is determined based on the ratio of the number of third bits that have been broken down to the total number.

[0071] Optionally, the device further includes:

[0072] The second breakdown condition adjustment module is used to reduce the breakdown time and / or breakdown voltage included in the third breakdown condition if the third breakdown condition corresponding to the false breakdown rate does not exist, and then enter the second bit breakdown module.

[0073] Optionally, the second breakdown condition adjustment module is further configured to:

[0074] In the process of reducing the breakdown duration and / or breakdown voltage included in the third breakdown condition, the breakdown duration in the third target breakdown condition is reduced, wherein the third target breakdown condition is one or more third breakdown conditions with the minimum breakdown duration.

[0075] And / or, in the process of reducing the breakdown duration and / or breakdown voltage included in the third breakdown condition, the breakdown voltage in the fourth target breakdown condition is reduced, the fourth target breakdown condition being one or more of the third breakdown conditions with the minimum breakdown voltage.

[0076] Optionally, the third bit is set at a position adjacent to the second bit.

[0077] Optionally, the first breakdown condition corresponds to multiple first bits, and the multiple first bits corresponding to the same first breakdown condition are located in at least two non-adjacent regions of the redundant array.

[0078] The third breakdown condition corresponds to multiple second bits, and the multiple second bits corresponding to the same third breakdown condition are located in at least two non-adjacent regions of the redundant array.

[0079] Optionally, multiple first bits corresponding to the same first breakdown condition are located in two centrally symmetrical, non-adjacent regions of the redundant array;

[0080] The second bits corresponding to the same third breakdown condition are located in two centrally symmetrical, non-adjacent regions of the redundant array.

[0081] Optionally, the device further includes:

[0082] A current determination module is used to determine, before determining the third breakdown condition that meets the preset conditions as the second breakdown condition, a first current passing through a already broken bit and a second current passing through a non-broken bit for the third breakdown condition. The already broken bit includes at least one of the following: the first bit that has been broken down and the second bit that has been broken down. The non-broken bit includes at least one of the following: the third bit that has not been broken down.

[0083] A current difference determination module is used to determine the current difference based on the first current and the second current.

[0084] Thirdly, embodiments of this application provide an electronic device, including: at least one processor and a memory;

[0085] The memory stores computer-executed instructions;

[0086] The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to implement the method described in the first aspect.

[0087] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computing device, cause the computing device to implement the method described in the first aspect.

[0088] Fifthly, embodiments of this application provide a computer program for performing the method described in the first aspect.

[0089] The method and apparatus for determining bit breakdown conditions provided in this application can determine multiple first breakdown conditions; based on each first breakdown condition, the corresponding first bit is broken down to obtain a first breakdown result for each first breakdown condition, with different first breakdown conditions corresponding to different first bit bits; and a second breakdown condition is determined from the multiple first breakdown conditions based on the first breakdown results. This application embodiment can determine the second breakdown condition by conducting a breakdown experiment using multiple first breakdown conditions. Since the second breakdown condition is selected based on the breakdown results of the breakdown experiment, it can ensure that the second breakdown condition has a good breakdown effect in actual practice. Attached Figure Description

[0090] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with those of this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0091] Figure 1 This is a schematic diagram of a redundant array structure provided in an embodiment of this application;

[0092] Figure 2 This is a flowchart illustrating the steps of a method for determining bit breakdown conditions provided in an embodiment of this application.

[0093] Figure 3 This is a schematic diagram of a breakdown result detection circuit provided in an embodiment of this application;

[0094] Figure 4 This is a schematic diagram illustrating the impact of an abnormal region on the breakdown result, provided in an embodiment of this application.

[0095] Figure 5 This is a schematic diagram of the distribution of the first element in a redundant array provided in an embodiment of this application;

[0096] Figure 6 This is a schematic diagram of current distribution provided in an embodiment of this application;

[0097] Figure 7 This is a detailed flowchart illustrating the process of determining a second breakdown condition according to an embodiment of this application;

[0098] Figure 8 This is a schematic diagram of a device for determining bit breakdown conditions provided in an embodiment of this application;

[0099] Figure 9 This is a structural block diagram of an electronic device provided in an embodiment of this application.

[0100] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the embodiments of this application in any way, but rather to illustrate the concepts of the embodiments of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0101] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0102] In this embodiment, multiple first breakdown conditions are pre-selected, and breakdown experiments are performed on bits using these first breakdown conditions to select a suitable second breakdown condition. Since the second breakdown condition is selected based on the breakdown results of the breakdown experiment, it can be ensured that the second breakdown condition has a good breakdown effect in actual operation.

[0103] The bits mentioned above in the embodiments of this application can be redundant bits in a redundant array. The redundant array can include M rows and N columns of redundant bits, where M and N are values ​​greater than or equal to 1. Figure 1 This is a schematic diagram of a redundant array structure provided in an embodiment of this application. (Refer to...) Figure 1 As shown, the redundant array includes 10 rows and 10 columns of redundant bits, which is 10 × 10 = 100 redundant bits. One redundant bit is used to store one bit of data. Figure 1 The redundant array shown can store 100 bits of data. Each redundant bit can be used to repair bits in a main array, meaning... Figure 1 The redundant array shown can replace 100 bits in 100 main arrays.

[0104] Figure 2 This is a flowchart illustrating the steps of a method for determining bit breakdown conditions provided in an embodiment of this application. Please refer to... Figure 2 The above methods include:

[0105] S101: Determine multiple first breakdown conditions.

[0106] Each first breakdown condition can be a combination of one or more breakdown conditions of different dimensions. The first breakdown condition may include, but is not limited to, breakdown duration and breakdown voltage. Breakdown duration and breakdown voltage are two-dimensional breakdown conditions.

[0107] The breakdown duration is used to indicate the length of time the breakdown lasts, for example, 0.5ms, 1ms, 5ms, 10ms, and 30ms. Redundant bits can only be broken down when the breakdown duration reaches a certain length.

[0108] The breakdown voltage indicates the voltage required to break down redundant bits. For example, a default voltage V is set, so the breakdown voltage can include: 0.8V, 0.85V, 0.9V, 0.95V, and V. Redundant bits can only be broken down when the breakdown voltage reaches a certain level.

[0109] To achieve accurate breakdown, it is typically necessary to include all dimensions of breakdown conditions affecting the breakdown effect in the first breakdown condition. When all dimensions of breakdown conditions include the breakdown duration and breakdown voltage mentioned above, multiple values ​​of the breakdown duration and breakdown voltage can be arbitrarily combined to obtain multiple first breakdown conditions. Each first breakdown condition includes one value of the breakdown duration and one value of the breakdown voltage. For example, combining breakdown durations of 0.5ms, 1ms, 5ms, 10ms, and 30ms, and values ​​of 0.8V, 0.85V, 0.9V, 0.95V, and V, yields the 25 first breakdown conditions shown in the table below.

[0110]

[0111] S102: According to each first breakdown condition, the corresponding first bit is broken down to obtain the first breakdown result of each first breakdown condition. Different first breakdown conditions correspond to different first bits.

[0112] Each first breakdown condition can correspond to one or more first bits, where the first bit is any redundant bit. Accordingly, the first breakdown result is the breakdown result of breaking down the first bit through the first breakdown condition, and the first breakdown result is used to indicate whether the first bit has been broken down.

[0113] The aforementioned first breakdown result can be obtained through a circuit detection. Figure 3 This is a schematic diagram of a breakdown result detection circuit provided in an embodiment of this application. (Refer to...) Figure 3 As shown, for each first element, after it is broken down according to the first breakdown condition, the voltage divider of the first element can be measured and input into the comparator to output the first breakdown result corresponding to the first element. The first breakdown result can be stored in the latch.

[0114] The comparator outputs the first breakdown result according to the following principle: when the voltage division of the first element's resistor is greater than the reference voltage, the comparator outputs a first value as the first breakdown result, indicating that the first element has broken down. Conversely, when the voltage division of the first element's resistor is less than or equal to the reference voltage, the comparator outputs a second value as the first breakdown result, indicating that the first element has not broken down. For example, the first value can be 1, and the second value can be 0.

[0115] It should be noted that in practical applications, each first bit is connected to a comparator, and each comparator connected to the first bit is connected to a latch. Thus, the latch can store the first breakdown results of multiple first bits. Therefore, after breaking down the first bit through multiple first breakdown conditions, the first breakdown results of each first bit can be obtained from the latch.

[0116] To ensure that each first breakdown condition corresponds to a unique first breakdown result, meaning that each first breakdown result is determined by a single first breakdown condition, this embodiment assigns different first bit elements to different first breakdown conditions. Thus, the breakdown result of each first bit element is only affected by the corresponding first breakdown condition, which helps to accurately analyze the impact of each first breakdown condition on breakdown, thereby ensuring the accuracy of the final selected breakdown condition.

[0117] Optionally, when assigning one or more first bits to each first breakdown condition, the redundant bits in the redundant array can be divided into N equal parts, each part including one or more redundant bits, so that each redundant bit in each part can be assigned to a first breakdown condition. Thus, N needs to be greater than or equal to the number of first breakdown conditions. For example, when the number of first breakdown conditions is 25, N can be 25. (See reference...) Figure 4 As shown, Figure 4 The first and second redundant bits of the first row, and the first and second redundant bits of the second row, constitute the first bit of a first breakdown condition D11. Additionally, Figure 4 The first and second redundant bits in the second row, and the first and second redundant bits in the third row, constitute the first bit of another first breakdown condition D12. And so on. Figure 4 Four adjacent redundant bits of the same pattern can be used as the first bit corresponding to the first breakdown condition.

[0118] from Figure 4 As can be seen, the first element corresponding to the same first breakdown condition is set adjacently, but this setting method may cause the first breakdown result to be affected by position, resulting in lower accuracy. For example, refer to Figure 4As shown, an anomalous region exists in the redundant array, encompassing the top left nine bits of the array. In this scenario, the first bit of the following first breakdown conditions is affected by their position, resulting in a non-breakdown outcome: all first bits B11, B12, B21, and B22 of first breakdown condition D11; some first bits B31 and B32 of first breakdown condition D12; some first bits B13 and B23 of first breakdown condition D13; and some first bit B33 of first breakdown condition D14. The first breakdown outcome corresponding to the remaining first bits outside the anomalous region is only affected by the first breakdown condition.

[0119] The results above show that the accuracy of the first breakdown results affected by location, ranked from highest to lowest, is as follows: the first breakdown result under first breakdown condition D11, the first breakdown results under first breakdown conditions D12 and D13, and the first breakdown result under first breakdown condition D14. This results in the lowest accuracy for the first breakdown result under first breakdown condition D11, higher accuracy for the first breakdown results under first breakdown conditions D12 and D13, and the highest accuracy for the first breakdown result under first breakdown condition D14.

[0120] To address the issue of low accuracy in the first breakdown result due to the aforementioned positional influence, embodiments of this application may consider distributing multiple first bits corresponding to the same first breakdown condition in non-adjacent regions. This, by distributing the first bits corresponding to the same first breakdown condition in different locations as much as possible, helps reduce the problem of low accuracy in the first breakdown result caused by positional influence, thereby improving the accuracy of the first breakdown result.

[0121] Optionally, multiple first bits corresponding to the same first breakdown condition are located in two centrosymmetric, non-adjacent regions of the redundant array. For example, Figure 5 This is a schematic diagram illustrating the distribution of the first element in a redundant array according to an embodiment of this application. Referring to Figure 5, the first element of D11 includes B11, B22, B33, B44, B55, B66, B77, B88, B99, and B00, wherein the regions containing B11, B22, B33, B44, and B55 are symmetrical about the center of symmetry with the regions containing B66, B77, B88, B99, and B00. Similarly, the first element of D12 includes B01, B92, B83, B74, B65, B56, B47, B38, B29, and B00, wherein the regions containing B11, B22, B33, B44, and B55 are symmetrical about the center of symmetry with the regions containing B66, B77, B88, B99, and B10. Of course, it can also be arranged according to... Figure 5 The first element of the remaining region symmetrical about the center of symmetry is assigned to the remaining first breakdown conditions. Figure 5The first element of all centrally symmetric elements is not shown in the text.

[0122] S103: Determine the second breakdown condition from multiple first breakdown conditions based on the first breakdown result.

[0123] The second breakdown condition can be either the first breakdown condition that achieves successful breakdown, or the first breakdown condition with a higher success rate. Successful breakdown means that the first breakdown result is that the breakdown has been achieved. The breakdown success rate is determined by the proportion of the first element that achieves successful breakdown. For example, if a certain first breakdown condition corresponds to 10 first elements, and the first breakdown result of 9 of the first elements is that the breakdown has been achieved, then the breakdown success rate of this first breakdown condition can be 0.9.

[0124] When determining the second breakdown condition based on the first breakdown success rate, the second breakdown condition can be selected from the first breakdown conditions whose breakdown success rate is greater than or equal to a preset success rate threshold. This ensures that the selected second breakdown condition has a higher breakdown success rate, which helps improve the success rate of repairing invalid bits from redundant bits.

[0125] The embodiments of this application can provide two strategies for selecting the second breakdown condition, so as to select the second breakdown condition from the first breakdown condition whose breakdown success rate is greater than or equal to a preset success rate threshold.

[0126] In the first strategy of selecting the second breakdown condition, the first breakdown condition with a breakdown success rate greater than or equal to a preset success rate threshold is determined as the second breakdown condition.

[0127] In the second strategy for selecting the second breakdown condition, the first breakdown condition with a breakdown success rate greater than or equal to a preset success rate threshold is used as the third breakdown condition, so that the third breakdown condition that satisfies the preset condition is determined as the second breakdown condition.

[0128] The preset conditions here are conditions for at least one parameter: false breakdown rate, current difference, breakdown duration included in the first breakdown condition, and breakdown voltage included in the first breakdown condition.

[0129] The false breakdown rate represents the proportion of bits that are falsely broken down. Falsely broken-down bits are those that are broken down due to the impact of adjacent bit breakdowns. For example, redundant bits in a redundant array can be divided into bits that need to be broken down and bits that do not need to be broken down. After breaking down the bits, the number N1 of the bits that did not need to be broken down can be counted, and N1 can then be used to determine the false breakdown rate. The false breakdown rate can be the ratio of N1 to the total number of bits that did not need to be broken down, or the ratio of N1 to the total number of all bits.

[0130] Understandably, a lower false breakdown rate is better. Therefore, we can select the second breakdown condition from the third breakdown condition, which has a lower false breakdown rate. This ensures that the selected second breakdown condition has a lower false breakdown rate for redundant bits, thus helping to prevent unnecessary redundant bits from being broken down and improving breakdown accuracy.

[0131] Specifically, the conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to a preset false breakdown rate, or it is ranked in the top M positions in ascending order of the false breakdown rate. In other words, the third breakdown condition, where the false breakdown rate is less than or equal to the preset false breakdown rate and / or it is ranked in the top M positions in ascending order of the false breakdown rate, can be determined as the second breakdown condition.

[0132] The aforementioned current difference represents the difference in current magnitude between non-broken bits and broken bits. The current in broken bits is typically greater than that in non-broken bits. A larger current difference indicates a more thorough breakdown of the redundant bits under the second breakdown condition, resulting in better breakdown performance and improved conductivity of the broken-down redundant bits. Therefore, the second breakdown condition can be selected from the third breakdown conditions with a larger current difference. This ensures that the selected second breakdown condition achieves a more thorough breakdown of the redundant bits and better conductivity.

[0133] Specifically, the conditions for current difference include at least one of the following: the current difference is greater than or equal to a preset current difference, or it is among the top N current differences in descending order. In other words, the third breakdown condition, which is that the current difference is greater than or equal to a preset current difference and / or it is among the top N current differences in descending order, can be determined as the second breakdown condition.

[0134] Regarding the aforementioned breakdown time, a second breakdown condition can be selected from the third breakdown condition, which has a shorter breakdown time. This ensures that the selected second breakdown condition requires a shorter time to break down redundant bits, thus helping to shorten the breakdown time and repair time, and saving time.

[0135] Specifically, the conditions for breakdown duration include at least one of the following: the breakdown duration is less than or equal to a preset duration, or it is ranked in the top L positions in ascending order of breakdown duration. In other words, the third breakdown condition, which is that the breakdown duration is less than or equal to the preset duration and / or it is ranked in the top L positions in ascending order of breakdown duration, can be determined as the second breakdown condition.

[0136] For the aforementioned breakdown voltage, a second breakdown condition can be selected from the third breakdown condition with a lower breakdown voltage. This ensures that the selected second breakdown condition requires a lower voltage to break down the redundant bits, thus helping to save energy.

[0137] Specifically, the conditions for breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to a preset voltage, or it is among the top K breakdown voltages in ascending order. In other words, the third breakdown condition, which is a breakdown voltage less than or equal to a preset voltage and / or among the top K breakdown voltages in ascending order, can be determined as the second breakdown condition.

[0138] It should be noted that M, N, L and K are all integers greater than 1, and M, N, L and K can be the same or different.

[0139] In practical applications, one or more of the above-mentioned false breakdown rate, current difference, breakdown voltage, and breakdown time can be combined to select the second breakdown condition from the third breakdown conditions. For example, the third breakdown condition where the current difference is greater than or equal to a preset current difference and the false breakdown rate is less than or equal to a preset false breakdown rate can be determined as the second breakdown condition to ensure that the false breakdown rate of the second breakdown condition is small and the breakdown is more complete. Alternatively, the third breakdown condition that is among the top M in ascending order of false breakdown rate and whose breakdown time is less than or equal to a preset time can also be determined as the second breakdown condition to ensure that the false breakdown rate of the second breakdown condition is small and the breakdown time required is short.

[0140] Of course, the third breakdown condition that simultaneously meets the following conditions can be determined as the second breakdown condition: the false breakdown rate is less than or equal to the preset false breakdown rate, the current difference is greater than or equal to the preset current difference, the breakdown time is less than or equal to the preset time, and the breakdown voltage is less than or equal to the preset voltage.

[0141] In an optional embodiment, after determining the breakdown success rate, the false breakdown rate can also be determined through a breakdown experiment on the second bit. That is, after determining the third breakdown condition, and before determining the third breakdown condition that meets the preset conditions as the second breakdown condition, a breakdown experiment on the second bit is required to determine the false breakdown rate. This approach decouples the first bit used to determine the breakdown success rate from the second bit used to determine the false breakdown rate, helping to improve the accuracy of both the breakdown success rate and the false breakdown rate.

[0142] The second bit is different from the first bit. The second bit can be located in the same redundant array or a different redundant array as the first bit.

[0143] Specifically, first, the third bit (other than the second bit) to be broken down is determined based on the third breakdown condition; then, the second bit is broken down according to the third breakdown condition to obtain the second breakdown result; finally, the false breakdown rate for the third bit is determined based on the second breakdown result.

[0144] In this context, the second bit can be understood as the bit that needs to be broken down, and the third bit can be understood as the bit that does not need to be broken down. The goal is to determine whether the third bit is broken down during the process of breaking down the second bit. This allows us to statistically analyze the percentage of the third bit that is broken down, thus determining the false breakdown rate.

[0145] To better detect whether the third bit will be broken down, it can be positioned adjacent to the second bit. This close proximity means the third bit has the greatest impact during a breakdown of the second bit, allowing for better detection of whether the third bit is affected by the breakdown of the second bit. If it is indeed broken down, this improves the accuracy of the false breakdown rate.

[0146] The aforementioned second breakdown result is used to indicate whether the second bit and the third bit have been broken down. Therefore, the aforementioned false breakdown rate can be the ratio of the number of broken third bits to the total number of bits, and the total number of bits can be the sum of the second and third bits.

[0147] The embodiments of this application can represent the false breakdown rate by the ratio of the number of broken third bits to the total number of bits. This false breakdown rate takes into account not only the number of third bits but also the number of second bits. Compared to using the ratio of the number of broken third bits to the total number of third bits as the false breakdown rate, the accuracy is higher.

[0148] Optionally, there may be multiple second bits, distributed in the same way as the first bit. Multiple second bits corresponding to the same third breakdown condition can be located in at least two non-adjacent regions of the redundant array. This minimizes the influence of location on the second breakdown result of the third breakdown condition, helping to improve the accuracy of the second breakdown result and the accuracy of the false breakdown rate, and thus improving the accuracy of selecting the second breakdown condition based on the false breakdown rate.

[0149] Furthermore, similar to the distribution of the first bit, multiple second bits corresponding to the same third breakdown condition are located in two centrally symmetric, non-adjacent regions of the redundant array.

[0150] In another example of the embodiments of this application, before determining the third breakdown condition that satisfies the preset conditions as the second breakdown condition, it is also necessary to determine the current difference. Specifically, for the third breakdown condition, a first current passing through the broken-down bits and a second current passing through the non-broken-down bits are determined. The broken-down bits include at least one of the following: a broken-down first bit and a broken-down second bit. The non-broken-down bits include at least one of the following: a non-broken-down third bit. Then, the current difference is determined based on the first current and the second current.

[0151] Since there are usually multiple non-breakdown bits and broken-down bits, the current difference can be calculated through the following steps: First, determine the statistical value of the first current, including but not limited to: average value, maximum value, minimum value, etc.; then, determine the statistical value of the second current, including but not limited to: average value, maximum value, minimum value, etc.; finally, subtract the statistical value of the second current from the statistical value of the first current to obtain the current difference.

[0152] The embodiments of this application can combine the breakdown results of the first, second, and third bits to determine the current difference. Since this current difference is determined through two breakdown experiments, it helps improve the accuracy of the current difference. Furthermore, it helps improve the accuracy of selecting the second breakdown condition based on the current difference.

[0153] Figure 6 This is a schematic diagram of current distribution provided in an embodiment of this application. (Refer to...) Figure 6 As shown, the current distribution includes the following two parts: the current distribution passing through the non-broken bits and the current distribution passing through the broken bits.

[0154] Reference Figure 6 As shown, for the current distribution passing through the non-breakdown bits, the horizontal axis represents current, with units of microamperes (μA). The vertical axis represents the number of non-breakdown bits, with units of individual bits. From... Figure 6 As can be seen from this, the number of non-breakdown bits with current S1 is N1.

[0155] Reference Figure 6 As shown, for the current distribution passing through the broken-down bits, the horizontal axis represents the current, and the vertical axis represents the number of broken-down bits. From... Figure 6 As can be seen from this, the number of broken-down bits with current S2 is N2.

[0156] from Figure 6 As can be seen, the difference between the maximum current passing through the non-breakdown bit and the minimum current passing through the breakdown bit can be defined as the current difference. This ensures that the current difference is the minimum difference between the current passing through the breakdown bit and the current passing through the non-breakdown bit. This minimum difference can more accurately represent the degree of difference between the first and second currents, helping to improve the accuracy of determining the second breakdown condition based on the current difference.

[0157] Figure 7 This is a detailed flowchart illustrating the process for determining a second breakdown condition, as provided in an embodiment of this application. (Refer to...) Figure 7 As shown, the process of determining the second breakdown condition may include the following steps S1 to S12:

[0158] S1: Determine multiple first breakdown conditions to proceed to S2.

[0159] S2: According to each first breakdown condition, the corresponding first bit is broken down to obtain the first breakdown result of each first breakdown condition. The first breakdown result is used to indicate whether each first bit has been broken down, so as to proceed to S3.

[0160] S3: Determine the success rate of the first breakdown condition based on the first breakdown result, and proceed to S4.

[0161] S4: The first breakdown condition with a breakdown success rate greater than or equal to the preset success rate threshold is determined as the third breakdown condition, so as to proceed to S5.

[0162] S5: Determine if the third breakdown condition exists. If it exists, proceed to S6. If it does not exist, proceed to S7.

[0163] S6: Select a third breakdown condition with a shorter breakdown time and / or a shorter breakdown voltage to proceed to S8.

[0164] S7: Increase the breakdown duration and / or breakdown voltage in the first breakdown condition, and proceed to S2.

[0165] Understandably, increasing the breakdown duration and / or breakdown voltage in the first breakdown condition is equivalent to adjusting the first breakdown condition, thereby increasing the probability of the first element breaking down under the adjusted first breakdown condition, until a first breakdown condition exists with a breakdown success rate greater than or equal to a preset success rate threshold. This ensures the successful determination of the second breakdown condition.

[0166] In the first enhancement method, the breakdown duration and / or breakdown voltage in all first breakdown conditions can be increased.

[0167] In the second enhancement method, some of the first breakdown conditions can be adjusted. Specifically, the breakdown duration in the first target breakdown condition is increased, where the first target breakdown condition is one or more first breakdown conditions with the largest breakdown duration; and / or, the breakdown voltage in the second target breakdown condition is increased, where the second target breakdown condition is one or more first breakdown conditions with the largest breakdown voltage.

[0168] It can be seen that the second method only increases the breakdown time and / or the breakdown voltage. Since a smaller breakdown time may require a larger increase to break down the first element, this part of the breakdown time can be left unincreased. Only the larger breakdown time can be increased to achieve the breakdown time of the first element more quickly, saving time.

[0169] Similarly, since a smaller breakdown voltage may require a larger increase to break down the first element, it is possible to not increase this part of the breakdown voltage, but only increase the larger breakdown voltage to reach the breakdown voltage of the first element more quickly, thus saving time.

[0170] S8: The second bit is broken down by the third breakdown condition to obtain the second breakdown result. The second breakdown result is used to indicate whether the third bit has been broken down, so as to proceed to S9.

[0171] S9: Determine the false breakdown rate based on the ratio between the number of third bits that have been broken down and the total number of bits, where the total number of bits is the sum of the number of second bits and the total number of third bits, and proceed to S10.

[0172] S10: Determine if a third breakdown condition with a false breakdown rate less than a preset false breakdown rate exists. If it exists, proceed to S11; otherwise, proceed to S12. This ensures that the false breakdown rate of the finally selected second breakdown condition is within a controllable range.

[0173] S11: Based on the third breakdown condition of a shorter breakdown time and / or a shorter breakdown voltage and a lower false breakdown rate, statistically analyze the current difference to proceed to S13.

[0174] This step can be referred to in the detailed explanation of the statistical current difference mentioned above, and will not be repeated here.

[0175] S12: Reduce the breakdown duration and / or breakdown voltage in the third breakdown condition to proceed to S8.

[0176] Specifically, reducing the breakdown time and / or breakdown voltage in the third breakdown condition means adjusting the third breakdown condition to reduce the false breakdown rate until a third breakdown condition exists with a false breakdown rate lower than a preset success rate threshold. This ensures the successful determination of the second breakdown condition.

[0177] In the first reduction method, the breakdown duration and / or breakdown voltage in all first breakdown conditions can be reduced.

[0178] In the second reduction method, some of the third breakdown conditions can be adjusted. Specifically, the breakdown duration in the third target breakdown condition can be reduced, where the third target breakdown condition is one or more third breakdown conditions with the shortest breakdown duration; and / or, the breakdown voltage in the fourth target breakdown condition can be reduced, where the fourth target breakdown condition is one or more third breakdown conditions with the shortest breakdown voltage.

[0179] It can be seen that the second reduction method only reduces a small portion of the breakdown time and / or a small portion of the breakdown voltage. Since a larger breakdown time may require a larger reduction to make the false breakdown rate less than the preset false breakdown rate, this portion of the breakdown time can be left unreduced. Instead, only a small portion of the breakdown time can be reduced to make the false breakdown rate less than the preset false breakdown rate more quickly, saving time.

[0180] Similarly, since a larger breakdown voltage requires a larger reduction to make the false breakdown rate less than the preset false breakdown rate, it is possible not to reduce this part of the breakdown voltage, but only to reduce a smaller breakdown voltage, so as to make the false breakdown rate less than the preset false breakdown rate more quickly and save time.

[0181] S13: The third breakdown condition, which has a shorter breakdown time and / or a shorter breakdown voltage, a lower false breakdown rate, and a larger current difference, is determined as the second breakdown condition.

[0182] Corresponding to the above method embodiments, Figure 8 This is a schematic diagram of a device for determining bit breakdown conditions provided in an embodiment of this application. Please refer to... Figure 8 The aforementioned bit breakdown condition determining device 200 includes:

[0183] The first breakdown condition determination module 201 is used to determine multiple first breakdown conditions.

[0184] The first bit breakdown module 202 is used to break down the corresponding first bit according to each first breakdown condition to obtain the first breakdown result of each first breakdown condition. Different first breakdown conditions correspond to different first bits.

[0185] The second breakdown condition determination module 203 is used to determine a second breakdown condition from the plurality of first breakdown conditions based on the first breakdown result.

[0186] Optionally, the first breakdown result is used to indicate whether the multiple first bits of the first breakdown condition have been broken down, and the second breakdown condition determination module is further used to:

[0187] The breakdown success rate of the first breakdown condition is determined based on the first breakdown result.

[0188] The second breakdown condition is determined from the first breakdown condition, which states that the breakdown success rate is greater than or equal to a preset success rate threshold.

[0189] Optionally, the second breakdown condition determination module is further configured to:

[0190] In the process of determining the second breakdown condition from the first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold, the first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold is used as the third breakdown condition.

[0191] The third breakdown condition that meets the preset conditions is determined as the second breakdown condition. The preset conditions are conditions for at least one parameter: false breakdown rate, current difference, breakdown time included in the first breakdown condition, and breakdown voltage included in the first breakdown condition. The current difference is the difference in current magnitude between non-broken bits and broken bits.

[0192] Optionally, the conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to a preset false breakdown rate, or the false breakdown rate is ranked in ascending order and is among the top M.

[0193] The conditions for the current difference include at least one of the following: the current difference is greater than or equal to a preset current difference, or the current difference is ranked in descending order and is among the top N.

[0194] The conditions for the breakdown duration include at least one of the following: the breakdown duration is less than or equal to a preset duration, or the breakdown duration is arranged in ascending order and is in the first L positions.

[0195] The conditions for the breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to a preset voltage, or the breakdown voltage is arranged in ascending order and is in the first K positions.

[0196] Optionally, the device further includes:

[0197] The first breakdown condition adjustment module is used to increase the breakdown duration and / or the breakdown voltage included in the first breakdown condition if the first breakdown condition, in which the breakdown success rate is greater than or equal to a preset success rate threshold, does not exist, and then enter the first bit breakdown module.

[0198] Optionally, the first breakdown condition adjustment module is used to:

[0199] In the process of increasing the breakdown duration and / or breakdown voltage included in the first breakdown condition, the breakdown duration in the first target breakdown condition is increased, and the first target breakdown condition is one or more first breakdown conditions with the largest breakdown duration.

[0200] And / or, in the process of increasing the breakdown duration and / or the breakdown voltage included in the first breakdown condition, the breakdown voltage in the second target breakdown condition is increased, wherein the second target breakdown condition is one or more of the first breakdown conditions with the largest breakdown voltage.

[0201] Optionally, the device further includes:

[0202] The bit determination module is used to determine the second bit to be broken down and a third bit other than the second bit for the third breakdown condition before determining the third breakdown condition that meets the preset conditions as the second breakdown condition.

[0203] The second bit breakdown module is used to break down the second bit according to the third breakdown condition to obtain the second breakdown result.

[0204] The false breakdown rate determination module is used to determine the false breakdown rate for the third bit based on the second breakdown result.

[0205] Optionally, the second breakdown result is used to indicate whether the third bit has been broken down, and the false breakdown rate determination module is further used to:

[0206] In determining the false breakdown rate for the third bit based on the second breakdown result, the total number of the second bit and the third bit is determined.

[0207] The false breakdown rate is determined based on the ratio of the number of third bits that have been broken down to the total number.

[0208] Optionally, the device further includes:

[0209] The second breakdown condition adjustment module is used to reduce the breakdown time and / or breakdown voltage included in the third breakdown condition if the third breakdown condition corresponding to the false breakdown rate does not exist, and then enter the second bit breakdown module.

[0210] Optionally, the second breakdown condition adjustment module is further configured to:

[0211] In the process of reducing the breakdown duration and / or breakdown voltage included in the third breakdown condition, the breakdown duration in the third target breakdown condition is reduced, wherein the third target breakdown condition is one or more third breakdown conditions with the minimum breakdown duration.

[0212] And / or, in the process of reducing the breakdown duration and / or breakdown voltage included in the third breakdown condition, the breakdown voltage in the fourth target breakdown condition is reduced, the fourth target breakdown condition being one or more of the third breakdown conditions with the minimum breakdown voltage.

[0213] Optionally, the third bit is set at a position adjacent to the second bit.

[0214] Optionally, the first breakdown condition corresponds to multiple first bits, and the multiple first bits corresponding to the same first breakdown condition are located in at least two non-adjacent regions of the redundant array.

[0215] The third breakdown condition corresponds to multiple second bits, and the multiple second bits corresponding to the same third breakdown condition are located in at least two non-adjacent regions of the redundant array.

[0216] Optionally, multiple first bits corresponding to the same first breakdown condition are located in two centrally symmetrical, non-adjacent regions of the redundant array.

[0217] The second bits corresponding to the same third breakdown condition are located in two centrally symmetrical, non-adjacent regions of the redundant array.

[0218] Optionally, the device further includes:

[0219] The current determination module is used to determine, before determining the third breakdown condition that meets the preset conditions as the second breakdown condition, a first current passing through a already broken bit and a second current passing through a non-broken bit for the third breakdown condition. The already broken bit includes at least one of the following: the first bit that has been broken down and the second bit that has been broken down. The non-broken bit includes at least one of the following: the third bit that has not been broken down.

[0220] A current difference determination module is used to determine the current difference based on the first current and the second current.

[0221] The above-described apparatus embodiment is an embodiment corresponding to the foregoing method embodiment, and has the same technical effects as the method embodiment. A detailed description of this apparatus embodiment can be found in the detailed description of the foregoing method embodiment, and will not be repeated here.

[0222] Figure 9 This is a structural block diagram of an electronic device provided in an embodiment of this application. The electronic device 600 includes a memory 602 and at least one processor 601.

[0223] Among them, memory 602 stores computer-executed instructions.

[0224] At least one processor 601 executes computer execution instructions stored in memory 602, causing electronic device 601 to perform the aforementioned functions. Figure 2 The method in the middle.

[0225] In addition, the electronic device may also include a receiver 603 and a transmitter 604, wherein the receiver 603 is used to receive information from other devices or equipment and forward it to the processor 601, and the transmitter 604 is used to send information to other devices or equipment.

[0226] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0227] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0228] The above are merely preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural or procedural transformations made using the description and drawings of the present application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present application.

Claims

1. A method for determining a bit breakdown condition, characterized in that, include: Determine multiple first breakdown conditions; According to each first breakdown condition, the corresponding first bit is broken down to obtain the first breakdown result of each first breakdown condition. Different first breakdown conditions correspond to different first bits. A second breakdown condition is determined from the plurality of first breakdown conditions based on the first breakdown result; Wherein, the first breakdown result is used to indicate whether the plurality of first bits of the first breakdown condition have been broken down, and the step of determining the second breakdown condition from the plurality of first breakdown conditions based on the first breakdown result includes: The breakdown success rate of the first breakdown condition is determined based on the first breakdown result; The second breakdown condition is determined from the first breakdown condition in which the breakdown success rate is greater than or equal to a preset success rate threshold; Determining the second breakdown condition from the first breakdown condition where the breakdown success rate is greater than or equal to a preset success rate threshold includes: The first breakdown condition, in which the breakdown success rate is greater than or equal to a preset success rate threshold, is used as the third breakdown condition. The third breakdown condition that meets the preset conditions is determined as the second breakdown condition. The preset conditions are conditions for at least one parameter: false breakdown rate, current difference, breakdown time included in the first breakdown condition, and breakdown voltage included in the first breakdown condition. The current difference is the difference in current magnitude between non-broken bits and broken bits.

2. The method according to claim 1, characterized in that, The conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to a preset false breakdown rate, or the false breakdown rate is arranged in ascending order and is in the first M positions; The conditions for the current difference include at least one of the following: the current difference is greater than or equal to a preset current difference, or the current difference is ranked in descending order and is among the top N. The conditions for the breakdown duration include at least one of the following: the breakdown duration is less than or equal to a preset duration, or the breakdown duration is arranged in ascending order and is in the first L positions; The conditions for the breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to a preset voltage, or the breakdown voltage is arranged in ascending order and is in the first K positions.

3. The method according to claim 1, characterized in that, The method further includes: If the first breakdown condition where the breakdown success rate is greater than or equal to the preset success rate threshold does not exist, then the breakdown duration and / or the breakdown voltage included in the first breakdown condition are increased, and the process proceeds to the step of breaking down the corresponding first bit according to each first breakdown condition to obtain the first breakdown result of each first breakdown condition.

4. The method according to claim 3, characterized in that, The increase in the first breakdown condition includes the breakdown duration and / or the breakdown voltage, including: Increase the breakdown duration in the first target breakdown condition, wherein the first target breakdown condition is one or more first breakdown conditions with the largest breakdown duration; And / or, increase the breakdown voltage in the second target breakdown condition, where the second target breakdown condition is one or more first breakdown conditions with the largest breakdown voltage.

5. The method according to claim 1 or 2, characterized in that, Before determining the third breakdown condition that meets the preset conditions as the second breakdown condition, the method further includes: For the third breakdown condition, determine the second bit to be broken down and the third bit other than the second bit; The second bit is broken down according to the third breakdown condition to obtain the second breakdown result; The false breakdown rate for the third bit is determined based on the second breakdown result.

6. The method according to claim 5, characterized in that, The second breakdown result is used to indicate whether the third bit has been broken down. Determining the false breakdown rate for the third bit based on the second breakdown result includes: Determine the total number of the second bit and the third bit; The false breakdown rate is determined based on the ratio of the number of third bits that have been broken down to the total number.

7. The method according to claim 5, characterized in that, Also includes: If the third breakdown condition corresponding to the false breakdown rate does not exist, then the breakdown time and / or breakdown voltage included in the third breakdown condition are reduced, and the process proceeds to the step of breaking down the second bit according to the third breakdown condition to obtain the second breakdown result.

8. The method according to claim 7, characterized in that, The reduction of the third breakdown condition includes the breakdown duration and / or breakdown voltage, including: Reduce the breakdown time in the third target breakdown condition, wherein the third target breakdown condition is one or more third breakdown conditions with the minimum breakdown time; And / or, reduce the breakdown voltage in the fourth target breakdown condition, which is one or more third breakdown conditions that minimize the breakdown voltage.

9. The method according to claim 5, characterized in that, The third bit is set at a position adjacent to the second bit.

10. The method according to claim 6, characterized in that, The first breakdown condition corresponds to multiple first bits, and the multiple first bits corresponding to the same first breakdown condition are located in at least two non-adjacent regions of the redundant array. The third breakdown condition corresponds to multiple second bits, and the multiple second bits corresponding to the same third breakdown condition are located in at least two non-adjacent regions of the redundant array.

11. The method according to claim 10, characterized in that, Multiple first bits corresponding to the same first breakdown condition are located in two centrally symmetrical, non-adjacent regions of the redundant array; The second bits corresponding to the same third breakdown condition are located in two centrally symmetrical, non-adjacent regions of the redundant array.

12. The method according to claim 5, characterized in that, Before determining the third breakdown condition that meets the preset conditions as the second breakdown condition, the method further includes: For the third breakdown condition, a first current passing through the broken-down bit and a second current passing through the non-broken-down bit are determined. The broken-down bit includes at least one of the following: the broken-down first bit and the broken-down second bit. The non-broken-down bit includes at least one of the following: the non-broken third bit. The current difference is determined based on the first current and the second current.

13. A device for determining bit breakdown conditions, characterized in that, include: The first breakdown condition determination module is used to determine multiple first breakdown conditions; The first bit breakdown module is used to break down the corresponding first bit according to each first breakdown condition to obtain the first breakdown result of each first breakdown condition. Different first breakdown conditions correspond to different first bits. The second breakdown condition determination module is used to determine a second breakdown condition from the plurality of first breakdown conditions based on the first breakdown result; Wherein, the first breakdown result is used to indicate whether the plurality of first bits of the first breakdown condition have been broken down, and the step of determining the second breakdown condition from the plurality of first breakdown conditions based on the first breakdown result includes: The breakdown success rate of the first breakdown condition is determined based on the first breakdown result; The second breakdown condition is determined from the first breakdown condition in which the breakdown success rate is greater than or equal to a preset success rate threshold; Determining the second breakdown condition from the first breakdown condition where the breakdown success rate is greater than or equal to a preset success rate threshold includes: The first breakdown condition, in which the breakdown success rate is greater than or equal to a preset success rate threshold, is used as the third breakdown condition. The third breakdown condition that meets the preset conditions is determined as the second breakdown condition. The preset conditions are conditions for at least one parameter: false breakdown rate, current difference, breakdown time included in the first breakdown condition, and breakdown voltage included in the first breakdown condition. The current difference is the difference in current magnitude between non-broken bits and broken bits.

14. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to perform the method as described in any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a computing device, cause the computing device to implement the method as described in any one of claims 1 to 12.

16. A computer program, characterized in that, The computer program is used to perform the method according to any one of claims 1 to 12.

Images