Method and system for implementing zero-value registers in a multi-instruction set processor

Abstract

The application discloses a kind of implementation method and system of zero-value register in multiple instruction set processor, the present application includes in instruction decoding stage, if the number of zero-value register in instruction set architecture when instruction runs is different from the number of specified zero-value register, then the number of two registers is interchanged and only to the register corresponding to the number of specified zero-value register executes read zero write neglect processing, so that when multiple instruction set processor switches to privileged state, the register corresponding to the number of zero-value register under the instruction set architecture supported by user state before instruction set architecture switching of privileged state software preservation and recovery is a certain general register to be preserved and recovered under the instruction set architecture supported by this user state, the correct preservation and recovery of general register state under the instruction set architecture supported by user state are realized.The present application aims at realizing zero-value register in multiple instruction set processor, to ensure the correct preservation and recovery of general register state in multiple instruction set processor, hardware control is simple.

Description

Technical Field

[0001] This invention relates to the field of processor design technology, and specifically to a method and system for implementing a zero-value register in a multi-instruction set processor. Background Technology

[0002] The zero-value register is used to return the constant value 0. Using a zero-value register avoids the overhead of using other registers to store 0. Therefore, many instruction set architectures typically define a zero-value register, which is addressed in the same way as general-purpose registers. Some architectures use general-purpose register number 0 as the zero-value register (e.g., RISC-V), while others use the highest-numbered general-purpose register (e.g., Arm's zero-value register is number 31). Instruction set architecture specifications require that writes to the zero-value register be ignored, and reading the zero-value register always returns the constant value 0.

[0003] In processors that support only one instruction set architecture, there are several ways to implement zero-value registers. For example, in sequential processors, zero-value registers and general-purpose registers are organized into a data array, and this data array is indexed by register numbers to enable reading and writing of registers. For the data unit corresponding to the zero-value register, zero is read and ignored when written. In out-of-order processors, the zero-value register can always be renamed to a fixed data unit during the register renaming stage, and zero is read and ignored when written to that data unit. For multi-instruction set processors, simply adopting the zero-value register implementation method from single-instruction set processors will have problems. For example, Chinese patent document CN114116003A discloses a program execution method, computer device, and system that supports multi-instruction set architectures. This scheme proposes that N instruction set architectures, including Armv8 and RISC-V, can be supported simultaneously in user mode, while only one of the N instruction set architectures, such as Armv8, is supported in privileged mode. When a processor executes under a certain instruction set architecture, it determines which register number corresponds to the zero-value register based on the instruction set architecture type, and then processes that register using the implementation method of zero-value registers in a single-instruction-set processor. However, when the instruction set architecture changes, for example, when an exception occurs in a RISC-V program running in user mode, causing the processor to enter privileged mode that only supports the Armv8 instruction set architecture, the privileged software will first save its context before handling the exception, including saving the state of general-purpose registers. Because the privileged software is running under the Armv8 instruction set architecture, when saving the state of general-purpose register number 31, it will read zeros and ignore writes, thus failing to correctly save and restore the state of general-purpose register number 31 of the RISC-V application. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method and system for implementing a zero-value register in a multi-instruction set processor, which addresses the above-mentioned problems in the prior art. The present invention aims to implement a zero-value register in a multi-instruction set processor to ensure the correct saving and restoration of the state of general-purpose registers in the multi-instruction set processor and to simplify hardware control.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A method for implementing a zero-value register in a multi-instruction set processor includes, during the instruction decoding stage, if the number of the zero-value register in the instruction set architecture at instruction execution differs from the number of a specified zero-value register, then the numbers of the two registers are swapped, and read-zero-write ignore processing is performed only on the register corresponding to the number of the specified zero-value register. This ensures that when the multi-instruction set processor switches to privileged mode, the register corresponding to the zero-value register number under the instruction set architecture supported by user mode before the instruction set architecture switch, which is saved and restored by the privileged mode software, is a general-purpose register under the instruction set architecture supported by user mode that needs to be saved and restored. This achieves the correct saving and restoration of the state of general-purpose registers under the instruction set architecture supported by user mode. The specified zero-value register refers to a single read-zero-write ignore zero-value register implemented in hardware by the multi-instruction set processor.

[0007] Optionally, the multi-instruction set processor supports N instruction set architectures in user mode, namely Arch_1, Arch_2, ..., Arch_N, where N>1. The instruction set architecture supported in privileged mode is one of the N instruction set architectures, Arch_n, and the specified zero-value register is the zero-value register in the instruction set architecture Arch_n.

[0008] Optionally, the step of swapping the numbers of the two registers and performing read-zero-write ignore processing only on the register corresponding to the number of the specified zero-value register includes:

[0009] S101, during the instruction decoding stage, obtain the register number X accessed by the decoded instruction. d It also obtains the instruction set architecture Arch_i and the zero register number X under the current instruction execution of the multi-instruction set processor. i and the specified zero-value register number X n ;

[0010] S102, Determine the zero-value register number X under the Arch_i instruction set architecture. i Equal to the specified zero value register number X n If the condition is met, it is determined that the register number accessed by the instruction does not need to be converted, and the process jumps to step S105; otherwise, the process jumps to step S103.

[0011] S103, determine the register number X accessed by the instruction. d Equal to the zero register number X in the Arch_i instruction set architecture i If true, then the register number X accessed by the instruction is set. d Replace with the specified zero-value register number X n If yes, proceed to step S105; otherwise, proceed to step S104.

[0012] S104, determine the register number X accessed by the instruction. d Equal to the specified zero value register number X n If true, then the register number X accessed by the instruction is set. d Replace with the zero register number X under the Arch_i instruction set architecture. i If the instruction accesses a register number, proceed to step S105; otherwise, the register number accessed by the instruction does not need to be converted, and proceed directly to step S105.

[0013] S105, for the zero-value register number X n The corresponding zero-value register performs read-zero write-ignore processing.

[0014] Optionally, the multi-instruction set processor supports both RISC-V and Armv8 instruction set architectures in user mode, with Armv8 being the instruction set architecture supported in privileged mode, and the specified zero-value register being the zero-value register in the Armv8 instruction set architecture.

[0015] Furthermore, this invention also provides an implementation apparatus for a zero-value register in a multi-instruction set processor, including a zero-value register numbering processing unit located in the instruction decoder. This unit is used during the instruction decoding stage to swap the numbers of the two registers if the zero-value register number in the instruction set architecture at runtime differs from the number of a specified zero-value register. It then performs read-zero-write ignore processing only on the register corresponding to the specified zero-value register number. This ensures that when the multi-instruction set processor switches to privileged mode, the register corresponding to the zero-value register number under the user-mode supported instruction set architecture before the instruction set architecture switch, which is saved and restored by the privileged mode software, is a general-purpose register under that user-mode supported instruction set architecture that needs to be saved and restored. This achieves the correct saving and restoration of the state of the general-purpose registers under the user-mode supported instruction set architecture. The specified zero-value register refers to a single read-zero-write ignore zero-value register implemented in hardware by the multi-instruction set processor.

[0016] Optionally, the multi-instruction set processor supports N instruction set architectures in user mode, namely Arch_1, Arch_2, ..., Arch_N, where N>1. The instruction set architecture supported in privileged mode is one of the N instruction set architectures, Arch_n, and the specified zero-value register is the zero-value register in the instruction set architecture Arch_n.

[0017] Optionally, the step of swapping the numbers of the two registers and performing read-zero-write ignore processing only on the register corresponding to the number of the specified zero-value register includes: S101, obtaining the register number X accessed by the decoded instruction during the instruction decoding stage. d It also obtains the instruction set architecture Arch_i and the zero register number X under the current instruction execution of the multi-instruction set processor. i and the specified zero-value register number X n S102, determine the zero register number X under the Arch_i instruction set architecture. i Equal to the specified zero value register number X n If the condition is met, determine if the register number accessed by the instruction does not need to be converted, and jump to step S105; otherwise, jump to step S103; S103, determine the register number X accessed by the instruction. d Equal to the zero register number X in the Arch_i instruction set architecture i If true, then the register number X accessed by the instruction is set. d Replace with the specified zero-value register number X n If the instruction accesses a register, proceed to step S105; otherwise, proceed to step S104. S104: Determine the register number X accessed by the instruction. d Equal to the specified zero value register number X n If true, then the register number X accessed by the instruction is set. d Replace with the zero register number X under the Arch_i instruction set architecture. i If the instruction accesses a register number, proceed to step S105; otherwise, the register number does not need to be converted, proceed directly to step S105; S105, for the zero-value register number X... n The corresponding register performs read-out zero-write ignore processing.

[0018] Optionally, the multi-instruction set processor supports both RISC-V and Armv8 instruction set architectures in user mode, with Armv8 being the instruction set architecture supported in privileged mode, and the specified zero-value register being the zero-value register in the Armv8 instruction set architecture.

[0019] Furthermore, the present invention also provides an implementation system for a zero-value register in a multi-instruction set processor, comprising a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the implementation method of the zero-value register in the multi-instruction set processor.

[0020] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute a method for implementing a zero-value register in the multi-instruction set processor.

[0021] Compared with the prior art, the present invention has the following main advantages:

[0022] 1. This invention enables the correct saving and restoration of general-purpose register states in multi-instruction set processors. In designing a multi-instruction set processor, this invention implements only one zero-value register in hardware, which is ignored when read-zero and written-zero. When the zero-value register number during instruction execution differs from the number of the specified zero-value register, the two register numbers are swapped during the instruction decoding stage. This ensures that when the instruction set architecture switches from a user-mode supported instruction set architecture to a privileged-mode supported instruction set architecture, the register corresponding to the zero-value register number under the user-mode supported instruction set architecture before the switch, which is saved and restored by the privileged-mode software, is a specific general-purpose register under the new user-mode supported instruction set architecture that needs to be saved and restored. This achieves the correct saving and restoration of general-purpose register states under the user-mode supported instruction set architecture.

[0023] 2. The hardware control of this invention is simple. This invention implements zero-value registers for multi-instruction set processors. However, compared with the implementation method of zero-value registers in single-instruction set processors, it only requires changing the number of the zero-value register during the instruction decoding stage, resulting in a simple hardware design. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating the method of an embodiment of the present invention. Detailed Implementation

[0025] The implementation method of zero-value registers in the multi-instruction set processor of this embodiment includes the following steps during the instruction decoding stage: if the number of the zero-value register in the instruction set architecture during instruction execution is different from the number of the specified zero-value register, the numbers of the two registers are swapped, and read-zero-write ignore processing is performed only on the register corresponding to the number of the specified zero-value register. This ensures that when the multi-instruction set processor switches to privileged mode, the register corresponding to the zero-value register number under the instruction set architecture supported by user mode before the instruction set architecture switch, which is saved and restored by the privileged mode software, is a general-purpose register under the instruction set architecture supported by user mode that needs to be saved and restored. This achieves the correct saving and restoration of the state of general-purpose registers under the instruction set architecture supported by user mode. The specified zero-value register refers to a single read-zero-write ignore zero-value register implemented in hardware by the multi-instruction set processor.

[0026] Among them, the multi-instruction set processor supports N instruction set architectures in user mode, namely Arch_1, Arch_2, ..., Arch_N, where N>1. The instruction set architecture supported in privileged mode is one of the N instruction set architectures, Arch_n, and the specified zero-value register is the zero-value register in the instruction set architecture Arch_n.

[0027] like Figure 1 As shown, in this embodiment, swapping the numbers of the two registers and performing read-zero-write ignore processing only on the register corresponding to the specified zero-value register number includes:

[0028] S101, during the instruction decoding stage, obtain the register number X accessed by the decoded instruction. d It also obtains the instruction set architecture Arch_i and the zero register number X under the current instruction execution of the multi-instruction set processor. i and the specified zero-value register number X n ;

[0029] S102, Determine the zero-value register number X under the Arch_i instruction set architecture. i Equal to the specified zero value register number X n If the condition is met, it is determined that the register number accessed by the instruction does not need to be converted, and the process jumps to step S105; otherwise, the process jumps to step S103.

[0030] S103, determine the register number X accessed by the instruction. d Equal to the zero register number X in the Arch_i instruction set architecture i If true, then the register number X accessed by the instruction is set. d Replace with the specified zero-value register number X n If yes, proceed to step S105; otherwise, proceed to step S104.

[0031] S104, determine the register number X accessed by the instruction. d Equal to the specified zero value register number X n If true, then the register number X accessed by the instruction is set. d Replace with the zero register number X under the Arch_i instruction set architecture. i If the instruction accesses a register number, proceed to step S105; otherwise, the register number accessed by the instruction does not need to be converted, and proceed directly to step S105.

[0032] S105, for the zero-value register number X n The corresponding register performs read-out zero-write ignore processing.

[0033] See Figure 1 As can be seen, the register number accessed by the instruction will be resolved during the instruction decoding stage; let's assume it's X. d First, determine X. i Is it related to X? n If they are the same, it could be that the instruction set architecture Arch_i is Arch_n, or it could be that Arch_i and Arch_n have the same zero-value register number. In either case, X d No number change is required. If X i With X n If they are different, then continue to judge X. d Is it related to X? i If they are the same, then X will be the same. d Change to X n Otherwise, continue to judge X. d Is it related to X? n If they are the same, then X will be the same. d Change to X i Otherwise X d No numbering change is required. After the register numbering is changed during the decoding stage, any implementation method of the zero-value register in a single-instruction-set processor can be applied to the implementation of the zero-value register in a multi-instruction-set processor.

[0034] In this embodiment, the multi-instruction set processor supports both RISC-V and Armv8 instruction set architectures in user mode, and only supports the Armv8 instruction set architecture in privileged mode. The specified zero-value register is the zero-value register in the Armv8 instruction set architecture. The zero-value register number in the Armv8 instruction set architecture is 31, and in the RISC-V instruction set architecture, it is 0. Therefore, when a RISC-V instruction is executed, if the instruction accesses register 0 (the zero-value register), the register number 0 will be changed to 31; if the instruction accesses register 31, the register number will be changed to 0; accessing registers other than 0 and 31 will not result in any register number change. Through this register number change, in the RISC-V instruction set architecture, when an instruction accesses register 31, it actually accesses the hardware-implemented register 0, and when it accesses register 0, it actually accesses the hardware-implemented zero-value register. This conforms to the definition of the multi-instruction set architecture specification. When the instruction set architecture is switched from RISC-V to Arm v8, the 0 register that privileged software saves and restores under the Armv8 instruction set architecture is the 31 register under the RISC-V architecture before the instruction set architecture switch, thus realizing the correct saving and restoration of the state of the 31 general-purpose register of the RISC-V application.

[0035] In summary, the implementation method of zero-value registers in this embodiment of a multi-instruction set processor is suitable for designs where the user mode supports N instruction set architectures (Arch_1, Arch_2, ..., Arch_N), while the privileged mode only supports one architecture (Arch_n). In this case, only one zero-value register is specified for hardware implementation. During the decoding stage, if the zero-value register number in the instruction set architecture used by the current instruction is the same as the specified zero-value register number, no register number swapping occurs; otherwise, the numbers of the two zero-value registers are interchanged. After the register number swapping during the decoding stage, only the specified zero-value register needs to be read and written as zero. This invention enables the correct saving and restoration of the general-purpose register state in a multi-instruction set processor, and the hardware control is simple.

[0036] Furthermore, this embodiment also provides an implementation apparatus for a zero-value register in a multi-instruction set processor, including a zero-value register numbering processing unit located in the instruction decoder. This unit is used during the instruction decoding stage to swap the numbers of the two registers if the zero-value register number in the instruction set architecture at runtime differs from the number of a specified zero-value register. It then performs read-zero-write ignore processing only on the register corresponding to the specified zero-value register number. This ensures that when the multi-instruction set processor switches to privileged mode, the register corresponding to the zero-value register number under the user-mode supported instruction set architecture before the instruction set architecture switch, which is saved and restored by the privileged mode software, is a general-purpose register under that user-mode supported instruction set architecture that needs to be saved and restored. This achieves the correct saving and restoration of the state of the general-purpose registers under the user-mode supported instruction set architecture. The specified zero-value register refers to a single read-zero-write ignore zero-value register implemented in hardware by the multi-instruction set processor.

[0037] In this embodiment, the multi-instruction set processor supports N instruction set architectures in user mode, namely Arch_1, Arch_2, ..., Arch_N, where N>1. The instruction set architecture supported in privileged mode is one of the N instruction set architectures, Arch_n, and the specified zero-value register is the zero-value register in the instruction set architecture Arch_n.

[0038] In this embodiment, swapping the numbers of the two registers and performing read-zero-write ignore processing only on the register corresponding to the number of the specified zero-value register includes: S101, obtaining the register number X accessed by the decoded instruction during the instruction decoding stage. d It also obtains the instruction set architecture Arch_i and the zero register number X under the current instruction execution of the multi-instruction set processor. i and the specified zero-value register number X n S102, determine the zero register number X under the Arch_i instruction set architecture. i Equal to the specified zero value register number X n If the condition is met, determine if the register number accessed by the instruction does not need to be converted, and jump to step S105; otherwise, jump to step S103; S103, determine the register number X accessed by the instruction. d Equal to the zero register number X in the Arch_i instruction set architecture i If true, then the register number X accessed by the instruction is set. d Replace with the specified zero-value register number X n If the instruction accesses a register, proceed to step S105; otherwise, proceed to step S104. S104: Determine the register number X accessed by the instruction. dEqual to the specified zero value register number X n If true, then the register number X accessed by the instruction is set. d Replace with the zero register number X under the Arch_i instruction set architecture. i If the instruction accesses a register number, proceed to step S105; otherwise, the register number does not need to be converted, proceed directly to step S105; S105, for the zero-value register number X... n The corresponding register performs read-out zero-write ignore processing.

[0039] In this embodiment, the multi-instruction set processor supports both RISC-V and Armv8 instruction set architectures in user mode. The Armv8 instruction set architecture is the instruction set architecture supported in privileged mode, and the specified zero-value register is the zero-value register in the Armv8 instruction set architecture.

[0040] Furthermore, this embodiment also provides a system for implementing a zero-value register in a multi-instruction set processor, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the method for implementing the zero-value register in the multi-instruction set processor. Additionally, this embodiment also provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute the method for implementing the zero-value register in the multi-instruction set processor.

[0041] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0042] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for implementing a zero-value register in a multi-instruction set processor, characterized in that, Including during the instruction decoding stage, if the number of the zero-value register in the instruction set architecture at instruction runtime is different from the number of the specified zero-value register, the numbers of the two registers are swapped, and read-zero-write ignore processing is only performed on the register corresponding to the number of the specified zero-value register. This ensures that when the multi-instruction set processor switches to privileged mode, the register corresponding to the zero-value register number under the instruction set architecture supported by user mode before the instruction set architecture switch, which is saved and restored by the privileged mode software, is a general-purpose register under the instruction set architecture supported by user mode that needs to be saved and restored. This achieves the correct saving and restoration of the state of general-purpose registers under the instruction set architecture supported by user mode. The specified zero-value register refers to a single read-zero-write ignore zero-value register implemented in hardware by the multi-instruction set processor. The step of swapping the numbers of the two registers and performing read-zero-write ignore processing only on the register corresponding to the number of the specified zero-value register includes: S101, obtaining the register number X accessed by the decoded instruction during the instruction decoding stage. d It also obtains the instruction set architecture Arch_i and the zero register number X under the current instruction execution of the multi-instruction set processor. i and the specified zero-value register number X n S102, determine the zero register number X under the Arch_i instruction set architecture. i Equal to the specified zero value register number X n If the condition is met, determine if the register number accessed by the instruction does not need to be converted, and jump to step S105; otherwise, jump to step S103; S103, determine the register number X accessed by the instruction. d Equal to the zero register number X in the Arch_i instruction set architecture i If true, then the register number X accessed by the instruction is set. d Replace with the specified zero-value register number X n If the instruction accesses a register, proceed to step S105; otherwise, proceed to step S104. S104: Determine the register number X accessed by the instruction. d Equal to the specified zero value register number X n If true, then the register number X accessed by the instruction is set. d Replace with the zero register number X under the Arch_i instruction set architecture. i If the instruction accesses a register number, proceed to step S105; otherwise, the register number does not need to be converted, proceed directly to step S105; S105, for the zero-value register number X... n The corresponding register performs read-out zero-write ignore processing.

2. The method for implementing a zero-value register in a multi-instruction set processor according to claim 1, characterized in that, The multi-instruction set processor supports N instruction set architectures in user mode, namely Arch_1, Arch_2, ..., Arch_N, where N>1. The instruction set architecture supported in privileged mode is one of the N instruction set architectures, Arch_n. The specified zero-value register is the zero-value register in the instruction set architecture Arch_n.

3. The method for implementing a zero-value register in a multi-instruction set processor according to claim 1, characterized in that, The multi-instruction set processor supports both RISC-V and Armv8 instruction set architectures in user mode. The Armv8 instruction set architecture is the instruction set architecture supported in privileged mode, and the specified zero-value register is the zero-value register in the Armv8 instruction set architecture.

4. An implementation apparatus for a zero-value register in a multi-instruction set processor, characterized in that, The instruction decoder includes a zero-value register number processing unit. This unit, during the instruction decoding stage, if the zero-value register number in the instruction set architecture at runtime differs from the number of a specified zero-value register, swaps the two register numbers and performs read-zero-write ignore processing only on the register corresponding to the specified zero-value register number. This ensures that when the multi-instruction set processor switches to privileged mode, the register corresponding to the zero-value register number under the user-mode supported instruction set architecture, which is saved and restored by the privileged mode software before the instruction set architecture switch, is a general-purpose register under that user-mode supported instruction set architecture that needs to be saved and restored. This achieves the correct saving and restoration of the state of general-purpose registers under the user-mode supported instruction set architecture. The specified zero-value register refers to a single read-zero-write ignore zero-value register implemented in hardware by the multi-instruction set processor. The swapping of the two register numbers and performing read-zero-write ignore processing only on the register corresponding to the specified zero-value register number includes: S101, obtaining the register number X accessed by the decoded instruction during the instruction decoding stage. d It also obtains the instruction set architecture Arch_i and the zero register number X under the current instruction execution of the multi-instruction set processor. i and the specified zero-value register number X n S102, determine the zero register number X under the Arch_i instruction set architecture. i Equal to the specified zero value register number X n If the condition is met, determine if the register number accessed by the instruction does not need to be converted, and jump to step S105; otherwise, jump to step S103; S103, determine the register number X accessed by the instruction. d Equal to the zero register number X in the Arch_i instruction set architecture i If true, then the register number X accessed by the instruction is set. d Replace with the specified zero-value register number X n If the instruction accesses a register, proceed to step S105; otherwise, proceed to step S104. S104: Determine the register number X accessed by the instruction. d Equal to the specified zero value register number X n If true, then the register number X accessed by the instruction is set. d Replace with the zero register number X under the Arch_i instruction set architecture. i If the instruction accesses a register number, proceed to step S105; otherwise, the register number does not need to be converted, proceed directly to step S105; S105, for the zero-value register number X... n The corresponding register performs read-out zero-write ignore processing.

5. The apparatus for implementing a zero-value register in a multi-instruction set processor according to claim 4, characterized in that, The multi-instruction set processor supports N instruction set architectures in user mode, namely Arch_1, Arch_2, ..., Arch_N, where N>1. The instruction set architecture supported in privileged mode is one of the N instruction set architectures, Arch_n. The specified zero-value register is the zero-value register in the instruction set architecture Arch_n.

6. The apparatus for implementing a zero-value register in a multi-instruction set processor according to claim 4, characterized in that, The multi-instruction set processor supports both RISC-V and Armv8 instruction set architectures in user mode. The Armv8 instruction set architecture is the instruction set architecture supported in privileged mode, and the specified zero-value register is the zero-value register in the Armv8 instruction set architecture.

7. A system for implementing a zero-value register in a multi-instruction set processor, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to execute the method of implementing a zero-value register in a multi-instruction set processor according to any one of claims 1 to 3.

8. A computer-readable storage medium storing a computer program, characterized in that, The computer program is used to be programmed or configured by a microprocessor to execute the method for implementing a zero-value register in a multi-instruction set processor according to any one of claims 1 to 3.

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