Memory device and memory system having the same

Abstract

A memory device and a memory system having the same can be provided herein. The memory system includes a memory device including a plurality of memory blocks each including a pass block and page buffer blocks respectively coupled to the pass blocks, and a memory controller configured to control the memory device to perform an operation corresponding to a command on a consolidated pass block by merging pass blocks coupled to different page buffer blocks among the pass blocks including a memory block that is a pass block by block state information indicating that each pass block is one of a pass block and a bad block, the consolidated pass block being obtained by merging the pass blocks coupled to different page buffer blocks among the pass blocks including a memory block that is a pass block among memory blocks that are both a pass block and a bad block.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to electronic devices, and more specifically, to memory devices and memory systems having the memory devices. Background Technology

[0002] A memory system is a device that stores data under the control of a host system such as a computer or smartphone. A memory system may include memory devices that store data and memory controllers that control the memory devices. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0003] A volatile memory device can be a memory device that stores data only when powered on and loses the stored data when power is interrupted. Examples of volatile memory devices can include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0004] Non-volatile memory devices are memory devices that retain stored data even when power is interrupted. Examples of non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0005] One embodiment of this disclosure provides a memory system. The memory system may include: a memory device comprising a plurality of memory blocks, each including a piece, and page buffer blocks respectively connected to the pieces; and a memory controller configured to control the memory device to perform a command-corresponding operation on merging passing pieces based on piece status information indicating whether each piece is a passing piece or a bad piece, the merging of passing pieces being obtained by merging passing pieces connected to different page buffer blocks from among the passing pieces included in memory blocks that include both passing and bad pieces in each memory block.

[0006] One embodiment of this disclosure provides a memory device. The memory device may include: a plurality of memory blocks, each memory block including a chip block, each chip block including one of a pass chip block and a bad chip block; page buffer blocks respectively connected to the chip blocks; an address decoder configured to apply an operating voltage to a memory block selected from the plurality of memory blocks; a block register configured to store a block address corresponding to a merged pass chip block, the merged pass chip block being obtained by merging pass chips from each memory block including both pass chips and bad chips, which are connected to different page buffer blocks; and an operation controller configured to: when receiving a command and a block address from a memory controller, control the address decoder to apply an operating voltage corresponding to the command to the merged pass chip block selected by the block address. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating a memory system according to an embodiment.

[0008] Figure 2 This is a diagram illustrating the structure of a memory device according to an embodiment.

[0009] Figure 3 This is a diagram illustrating the structure of a storage block according to an implementation method.

[0010] Figure 4 This is a diagram illustrating the relationship between storage blocks and chunk blocks according to an implementation method.

[0011] Figure 5 This is a diagram illustrating the structure of a piece according to an embodiment.

[0012] Figure 6 This is a diagram illustrating the structure of a memory controller according to an embodiment.

[0013] Figure 7 This is a flowchart illustrating a method for storing information related to a piece according to an embodiment.

[0014] Figure 8 This is a flowchart illustrating a method for performing operations on a piece according to an embodiment.

[0015] Figure 9 This is a diagram illustrating a method for managing blocks according to an implementation method.

[0016] Figure 10 This is a flowchart illustrating a method for performing an erase operation on merged storage blocks according to an embodiment.

[0017] Figure 11 This is a flowchart illustrating a method for performing programming operations on merged storage blocks according to an embodiment.

[0018] Figure 12 This is a flowchart illustrating a method for performing a read operation on a merged storage block according to an embodiment.

[0019] Figure 13 This is a block diagram illustrating a memory card used in a memory system according to an implementation method.

[0020] Figure 14 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an implementation method.

[0021] Figure 15 This is a block diagram illustrating a user system using a memory system according to an implementation method. Detailed Implementation

[0022] Specific structural or functional descriptions of embodiments of the present disclosure as examples are provided to illustrate implementations based on the concepts of the present disclosure. Implementations based on the concepts of the present disclosure may be practiced in various forms and should not be construed as limited to the implementations described in the specification or application.

[0023] Various embodiments of this disclosure relate to memory devices capable of increasing the available capacity of memory blocks and memory systems having such memory devices.

[0024] Figure 1 This is a diagram illustrating a memory system according to an embodiment.

[0025] Reference Figure 1 The memory system 10 according to embodiments of the present disclosure may include a memory device 100 and a memory controller 200.

[0026] The memory system 10 can perform operations corresponding to a request received from the host system 20. For example, the memory system 10 can store data received from the host system 20. The memory system 10 can provide the stored data to the host system 20. The memory system 10 can erase the stored data. For this purpose, the memory system 10 can be connected to the host system 20 via various communication methods.

[0027] The memory system 10 can be classified according to communication protocols or data storage schemes into any of the following types of storage devices: solid-state drives (SSDs); multimedia cards such as MMC, embedded MMC (eMMC), reduced-size MMC (RS-MMC), or micro-MMC; secure digital cards such as SD, mini-SD, or micro-SD; universal serial bus (USB) storage devices; universal flash memory (UFS) devices; PCMCIA card-type storage devices; peripheral component interconnect (PCI) card-type storage devices; PCI rapid (PCI-e) card-type storage devices; compact flash memory (CF) cards; smart media cards and memory sticks.

[0028] The host system 20 can be one of various electronic devices such as desktop computers, laptop computers, mobile phones, smartphones, game consoles, televisions (TVs), tablet computers, and wearable devices. The host system 20 can request the memory system 10 to store, retrieve, or erase data via communication conforming to various communication protocols. The host system 20 can also receive and retrieve data from the memory system 10. Here, the host system 20 may be simply referred to as a "host".

[0029] The memory system 10 may include a memory device 100 and a memory controller 200. The number of memory devices 100 may be one or more. The memory devices 100 and the memory controller 200 may be interconnected via channels through which commands, addresses, or data can be exchanged.

[0030] The memory device 100 may include multiple memory blocks. A memory block may include multiple memory cells. Here, the memory cells may be semiconductor memory devices that store data bit by bit.

[0031] A memory block can include multiple pages. A page can include multiple memory cells. Each memory cell can represent a cell of data. For example, a memory cell can store electrical charge, and the threshold voltage of the corresponding memory cell can change according to the amount of charge. The programming state to which the threshold voltage of the corresponding memory cell belongs indicates the bit value of the data. Here, a page can be a set of memory cells that indicates a unit for performing a programming operation to store data or a read operation to retrieve the stored data. A memory block can be a set of memory cells that indicates a unit for performing an erase operation to erase data.

[0032] A memory block can include multiple chunks. A chunk can include multiple slices. Here, a chunk block can be a unit for dividing a memory block, and a slice can be a unit for dividing a page. Multiple memory cells included in a chunk block can be linked to multiple page buffers included in a page buffer block. See below for further details. Figure 4 and Figure 5 It is described in detail.

[0033] The memory controller 200 can control the overall operation of the memory system 10 and the memory device 100. For example, the memory controller 200 can control the memory device 100 to perform programming operations to store data, reading operations to read stored data, or erasing operations to erase stored data. Specifically, during a programming operation, the memory controller 200 can provide programming commands, addresses, and data to the memory device 100. During a reading operation, the memory controller 200 can provide reading commands and addresses to the memory device 100. During an erasing operation, the memory controller 200 can provide erasing commands and addresses to the memory device 100.

[0034] The memory controller 200 can control the memory device 100 based on block status information, causing it to perform an operation corresponding to a command on merging passing blocks. This merging is achieved by merging passing blocks that are linked to different page buffer blocks within each memory block that includes passing blocks and bad blocks. Here, the block status information can be information indicating whether each block is a passing block or a bad block. A bad block can be a block that is physically or logically damaged and from which stored data cannot be read normally. A passing block can be a block from which stored data can be read normally. When any memory block includes both passing blocks and bad blocks, the memory block can be referred to as an incompletely passing block.

[0035] According to embodiments, a memory device 100 capable of increasing the available capacity of a memory block and a memory system 10 having the memory device 100 can be provided. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0036] Figure 2 This is a diagram illustrating the structure of a memory device according to an embodiment.

[0037] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0038] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Given that the memory blocks can be configured with the same structure, any one of the memory blocks BLK1 to BLKz, BLKi, will be described below.

[0039] The memory block BLKi may include a substrate and multiple memory cells. The multiple memory cells may be arranged or stacked on the substrate. Here, each memory cell may be a semiconductor memory device. In an embodiment, each memory cell may be a non-volatile memory device. Each memory cell may store data according to a single-level cell (SLC) scheme capable of storing one data bit, a multi-level cell (MLC) scheme capable of storing two data bits, a three-level cell (TLC) scheme capable of storing three data bits, and a four-level cell (QLC) scheme capable of storing four data bits.

[0040] The memory block BLKi can be connected to the address decoder 121 of the peripheral circuitry 120 via row lines RL. Here, row lines RL can include multiple word lines. Memory cells included in the memory block BLKi can be connected to the respective page buffers PB1 to PBm of the peripheral circuitry 120 via bit lines BL1 to BLm. (See below for further details.) Figure 3 Describe the structure of the storage block BLKi in detail.

[0041] The peripheral circuitry 120 can drive the memory cell array 110 to perform specific operations. For example, the peripheral circuitry 120 can drive the memory cell array 110 to perform any one of a programming operation, a reading operation, and an erasing operation.

[0042] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read / write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0043] Address decoder 121 can be coupled to memory cell array 110 via row lines RL. Row lines RL may include drain select line DSL, multiple word lines WL1 to WLn, source select line SSL, and source line SL. In embodiments, address decoder 121 may include components such as row decoders, column decoders, and address buffers.

[0044] Address decoder 121 can operate in response to control of control logic 130. In this example, address decoder 121 can receive address ADDR from control logic 130. Address decoder 121 can decode the block address included in the received address ADDR. Address decoder 121 can select the memory block corresponding to the block address from memory blocks BLK1 to BLKz. Address decoder 121 can decode the page address included in the received address ADDR. Address decoder 121 can select the page (or word line) corresponding to the page address from the page (or word line) included in the memory block. Address decoder 121 can apply an operating voltage Vop provided from voltage generator 122 to the selected page (or selected word line) of the selected memory block.

[0045] For example, during a programming operation, the address decoder 121 may apply a programming voltage to the selected word line and a pass voltage having a level lower than the programming voltage to the unselected word line. During a programming verification operation, the address decoder 121 may apply a verification voltage to the selected word line and, in parallel with the application of the verification voltage, apply a pass voltage having a level higher than the verification voltage to the unselected word line. Furthermore, during a read operation, the address decoder 121 may apply a read voltage to the selected word line and, in parallel with the application of the read voltage, apply a pass voltage having a level higher than the read voltage to the unselected word line. Furthermore, during an erase operation, the address decoder 121 may apply a first erase voltage to the word line connected to the selected memory block and, in parallel with the application of the first erase voltage, apply a second erase voltage having a level higher than the first erase voltage to the substrate included in the selected memory block.

[0046] Voltage generator 122 can use external power supplied to memory device 100 to generate multiple operating voltages Vop. Here, external power can be stored power included in memory system 10 or power supplied from host system 20. For example, external power supplied to memory device 100 can be used to generate a first erase voltage, a second erase voltage, a programming voltage, a programming verification voltage, a pass voltage, a read voltage, etc.

[0047] The read / write circuit 123 may include multiple page buffers PB1 to PBm.

[0048] For example, each of the multiple page buffers PB1 to PBm can be connected to multiple memory blocks BLK1 to BLKz via corresponding bit lines of multiple bit lines BL1 to BLm. In an embodiment, when a programming voltage is applied to the selected word line, the multiple page buffers PB1 to PBm can transmit a signal corresponding to the data DATA received from the data input / output circuit 124 via the data line DL to the selected page of the selected memory block via the multiple bit lines BL1 to BLm. When a programming verification voltage is applied to the selected word line, the multiple page buffers PB1 to PBm can transmit a sensing voltage VPB received from the selected page of the selected memory block via the multiple bit lines BL1 to BLm to the sensing circuit 125. In an embodiment, when a read voltage is applied to the selected word line, the multiple page buffers PB1 to PBm can transmit data DATA corresponding to the signal received from the selected page of the selected memory block via the multiple bit lines BL1 to BLm to the data input / output circuit 124 via the data line DL.

[0049] Data input / output circuit 124 can be connected to read / write circuit 123 via data line DL. Data input / output circuit 124 can operate in response to control signals output from control logic 130. Data input / output circuit 124 may include multiple input / output buffers for receiving input data DATA. During programming operations, data input / output circuit 124 can receive data DATA from memory controller 200 and can transfer the received data DATA to read / write circuit 123. During read operations, data input / output circuit 124 can receive data DATA from multiple page buffers PB1 to PBm included in read / write circuit 123 and can output the received data DATA to memory controller 200.

[0050] When a programming verification voltage (or erase verification voltage) is applied to the selected chip (or block of selected chips), the sensing circuit 125 can generate a reference voltage in response to the enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal PASS or a failure signal FAIL for each chip (or block) to the control logic 130 based on the result of comparing the sensed voltage VPB of each chip (or block) received from the read / write circuit 123 with the reference voltage.

[0051] Control logic 130 can control the overall operation of memory device 100. Control logic 130 can control peripheral circuitry 120 to perform operations such as storing data in memory cell array 110, reading data from memory cell array 110, or erasing data from memory cell array 110. For this purpose, control logic 130 can be connected to peripheral circuitry 120. For example, control logic 130 can be connected to address decoder 121, voltage generator 122, read / write circuitry 123, data input / output circuitry 124, and sensing circuitry 125.

[0052] In this implementation, control logic 130 can provide various signals to peripheral circuitry 120 corresponding to the command CMD and address ADDR received from memory controller 200. For example, control logic 130 can generate an operation signal OPSIG, a read / write circuit control signal PBSIGNALS, and an enable bit VRYBIT. Control logic 130 can output the operation signal OPSIG to voltage generator 122, output the address ADDR to address decoder 121, output the read / write circuit control signal PBSIGNALS to read / write circuitry 123, and output the enable bit VRYBIT to sensing circuitry 125. Furthermore, control logic 130 can verify whether the programming operation has succeeded or failed in response to a pass signal PASS or a failure signal FAIL received from sensing circuitry 125.

[0053] Figure 3This is a diagram illustrating the structure of a storage block according to an implementation method.

[0054] Reference Figure 3 A storage block BLKi can include multiple strings. Since multiple strings can be configured equivalently, a string ST connected to the first bit line BL1 will be described in detail by example. The first end of any string ST can be connected to one of the bit lines BL1 to BLm. The second end of any string ST can be connected to the source line SL. A source line SL can be connected to multiple strings, while a bit line can be connected to one string.

[0055] The string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells C1 to Cn, and a drain selection transistor DST. In an embodiment, the string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may also include more memory cells than the memory cells C1 to Cn illustrated in the figure.

[0056] The gate of the source select transistor SST can be connected to the source select line SSL, and the gate of the drain select transistor DST can be connected to the drain select line DSL. The source of each source select transistor SST can be connected to the source line SSL, and the drain of each drain select transistor DST can be connected to the corresponding bit line.

[0057] The gates of multiple memory cells C1 to Cn can be connected to multiple word lines WL1 to WLn respectively. The multiple memory cells C1 to Cn can be connected in series to the source selection transistor SST and the drain selection transistor DST located between them.

[0058] A memory block BLKi can include multiple pages. A page PG can be defined as a group of memory cells commonly connected to the same word line. A page PG can store page data. Page data can include data bits corresponding to the number of memory cells C1 to Cn included in the page PG. In the example, when each of the memory cells C1 to Cn included in the page PG can store 1 bit of data, the page PG can store one page data segment. In the example, when each of the memory cells C1 to Cn included in the page PG can store 2 bits of data, the page PG can store two page data segments.

[0059] Furthermore, in this implementation, a page PG can be a group of memory cells corresponding to a unit performing a programming or reading operation. A memory block BLKi can be a group of memory cells corresponding to a unit performing an erase operation.

[0060] The Incremental Step Pulse Programming (ISPP) method can be used to perform programming operations. The ISPP method can be a method of repeatedly executing a programming loop, in which the programming voltage application operation and the verification voltage application operation are performed sequentially.

[0061] For example, a programming voltage application operation can be an operation in which the memory device 100 applies a programming voltage of a preset level to the selected page via a word line connected to the page selected by the address, so as to store page data in the selected page. A verification voltage application operation can be an operation in which the memory device 100 applies a verification voltage of a preset level to the selected page via a word line connected to the selected page and determines whether the corresponding programming cycle has passed or failed by comparing the data output from the selected page with the page data. Here, the memory device 100 can terminate the programming operation when the corresponding programming cycle passes. In contrast, when the corresponding programming cycle fails, the memory device 100 can proceed to the next programming cycle. The levels of the programming voltage and programming verification voltage to be applied in the next programming cycle can be set to levels different from the levels of the programming voltage and programming verification voltage applied in the previous programming cycle. When the number of times the programming cycle is executed is greater than a reference number, the memory device 100 can terminate the programming operation performed on the selected page. In this case, the memory device 100 can store the selected page as a bad sector.

[0062] During a read operation, in order to read data stored in the page selected by the address, the memory device 100 can apply a read voltage with a preset level to the selected page via a word line connected to the selected page, and can apply a pass voltage to the remaining word lines in parallel with the application of the read voltage. Here, the read voltage can be a voltage with a preset level according to a scheme such as single-level cell, multi-level cell, three-level cell, or four-level cell. The pass voltage can be a high voltage with a level higher than that required to form a channel in the memory cells included in the unselected page.

[0063] During the erase operation, in order to erase the data stored in the memory block selected by the address, the memory device 100 can apply a first erase voltage to the selected memory block via a word line connected to the selected memory block. Here, the first erase voltage can be, for example, a ground voltage or a low voltage with a level similar to a ground voltage. In parallel with the application of the first erase voltage, the memory device 100 can apply a second erase voltage to the substrate included in the selected memory block. The second erase voltage can be a high voltage with a level higher than the first erase voltage.

[0064] Figure 4 This is a diagram illustrating the relationship between storage blocks and fragments according to an implementation method.

[0065] The following will refer to Figure 4 describe Figure 2 The shown is any one of the storage blocks BLK1 to BLKz, BLKi.

[0066] Reference Figure 4 In (1), the storage block BLKi may include multiple pages PG1 to PGm connected to different word lines. Page PGj may include multiple memory cells that are commonly connected to a single word line.

[0067] Reference Figure 4 In (1) and (2), the memory block BLKi may include multiple slices CHK11 to CHKm1 and CHK12 to CHKm2. Page PGj may include slices CHKj1 and CHKj2 from among the multiple slices CHK11 to CHKm1 and CHK12 to CHKm2 that are connected to the same word line. For example, each of the multiple slices CHKj1 and CHKj2 may include some of the multiple memory cells included in page PGj. The multiple slices CHKj1 and CHKj2 may be connected to different page buffer blocks (or different bit lines).

[0068] Reference Figure 4 In (2) and (3), the storage block BLKi may include multiple slices bCHKi1 and bCHKi2. Each of the multiple slices bCHKi1 and bCHKi2 may include slices connected to the same page buffer block. For example, the first slice bCHKi1 may include multiple first slices CHK11 to CHKm1 that are commonly connected to the first page buffer block, and the second slice bCHKi2 may include multiple second slices CHK12 to CHKm2 that are commonly connected to the second page buffer block.

[0069] That is, each of pages PG1 to PGm can be a set of memory cells obtained by grouping the memory cells included in the memory block BLKi according to word lines, and each of slices bCHKi1 and bCHKi2 can be a set of memory cells obtained by grouping the memory cells included in the memory block BLKi according to page buffer blocks.

[0070] also, Figure 4 The number of fragments bCHKi1 and bCHKi2 shown in (2) and (3), as well as the number of fragments CHK11 to CHKm1 and CHK12 to CHKm2, are merely examples, and their numbers can be modified and implemented in various forms. In the following description, for ease of description, it will be described under the following assumption: the number of fragments bCHKi1 and bCHKi2 included in a storage block BLKi is 2.

[0071] Figure 5 This is a diagram illustrating the structure of a piece according to an embodiment.

[0072] Reference Figure 5 The memory cell array 110 may include multiple memory blocks BLK1 to BLK5.

[0073] Each of the multiple memory blocks BLK1 through BLK5 may include a first block bCHK11, bCHK21, bCHK31, bCHK41, or bCHK51 connected to the first page buffer block bPB1 via bit lines BL, and a second block bCHK12, bCHK22, bCHK32, bCHK42, or bCHK52 connected to the second page buffer block bPB2 via bit lines BL. Each of the first page buffer block bPB1 and the second page buffer block bPB2 may include multiple page buffers. The page buffers included in the first page buffer block bPB1 may be connected to memory cells included in each of the first blocks bCHK11, bCHK21, bCHK31, bCHK41, and bCHK51, respectively. The page buffers included in the second page buffer block bPB2 may be connected to memory cells included in each of the second blocks bCHK12, bCHK22, bCHK32, bCHK42, and bCHK52, respectively.

[0074] Each of the multiple memory blocks BLK1 to BLK5 can be connected to the address decoder 121 via word line WL. The address decoder 121 can apply an operating voltage corresponding to the command to the memory block selected by the address via the word line.

[0075] Return to reference Figure 2 The control logic 130 may include an operation controller 131, a block manager 132, and a block register 133.

[0076] When the operation controller 131 receives the command CMD and the address ADDR from the memory controller 200, it can control the peripheral circuit 120 to perform the operation indicated by the command CMD on the memory block selected by the address ADDR. The command CMD can be one of a programming command indicating a programming operation, a read command indicating a read operation, or an erase command indicating an erase operation.

[0077] Block manager 132 can manage multiple memory blocks BLK1 to BLKz included in memory cell array 110. In an embodiment, block manager 132 can acquire information about each memory block and store the acquired information in block register 133. For example, based on the result of performing programming operations on each memory block, block manager 132 can store block status information indicating a bad state or a pass state of a slice or slice status information indicating a bad state or a pass state of a slice in block register 133.

[0078] Block register 133 can store information about each memory block. Block register 133 may include at least one of the following: identifiers for multiple memory blocks BLK1 to BLKz; identifiers for the segments included in each memory block; identifiers for the slices included in each segment; segment status information indicating whether each segment is a bad segment or a pass segment; and slice status information indicating whether each slice is a pass slice storing recoverable data or a bad slice storing unrecoverable data. Here, the identifiers may indicate information used to identify memory blocks, segments, or slices.

[0079] In one implementation, the block manager 132 can assign an address indicating a memory block to a merged through-block based on the block status information stored in the block register 133, and can store the assigned address in the block register 133. For this operation, the block manager 132 can periodically determine whether there are through-blocks connected to different page buffer blocks in memory blocks, including bad blocks, based on the block status information stored in the block register 133. Furthermore, according to embodiments of this disclosure, the operation of the block manager 132 can be modified to be performed by the memory controller 200.

[0080] In one implementation, the operation controller 131 can control the address decoder 121 to repeatedly execute a programming cycle operation that sequentially applies a programming voltage and a programming verification voltage to the chips connected to the selected word line among the chips included in the chip block. After the programming verification voltage is applied to the chip connected to the selected word line, the operation controller 131 can determine whether the corresponding programming cycle operation for each chip has passed or failed based on a pass signal PASS or a failure signal FAIL received from the sensing circuit 125. When the corresponding programming cycle operation fails, the operation controller 131 can control the address decoder 121 to repeat the next programming cycle operation until the number of executions of the programming cycle operation exceeds a reference number.

[0081] In one implementation, the block manager 132 can identify a chip that outputs chip data while being programmed with a verification voltage and whose programming cycle execution count is within a reference number as a pass chip. Furthermore, the block manager 132 can identify a chip that outputs data that does not match the chip data while being programmed with a verification voltage and whose programming cycle execution count is within a reference number as a fail chip. Additionally, the block manager 132 can store chip status information indicating whether each chip is pass or fail in the block register 133. In another implementation, the operation controller 131 can control the address decoder 121 to sequentially apply a programming voltage and a programming verification voltage to the selected chip, and the operation controller 131 can transmit a pass signal (PASS) or a failure signal (FAIL) received through the sensing circuit 125 to the memory controller 200. In this case, the memory controller 200 can determine whether each chip is a fail chip or a pass chip based on the received pass signal (PASS) or failure signal (FAIL).

[0082] In this implementation, the block manager 132 can identify the number of bad chips included in a block based on chip status information. When the number of bad chips in a block is equal to or greater than a bad chip reference number, the block manager 132 can determine that the corresponding block is a bad block. When the number of bad chips in a block is less than the bad chip reference number, the block manager 132 can determine that the corresponding block is a pass block. Here, the bad chip reference number can be a preset value and can have any of various values. The block manager 132 can store block status information indicating whether each block is a bad block or a pass block in the block register 133.

[0083] In an implementation, block register 133 may store the address corresponding to a merged pass block obtained by merging pass blocks that are connected to different page buffer blocks in each storage block that includes both pass blocks and bad blocks.

[0084] In an implementation, the merged pass block may include a first pass block connected to a first page buffer block included in a page buffer block and a second pass block connected to a second page buffer block.

[0085] For example, assuming, referring to Figure 5The fragment status information stored in block register 133 indicates that among multiple memory blocks BLK1 to BLK2, the first memory block BLK1 includes a first passable fragment connected to the first page buffer block bPB1 and a second bad fragment connected to the second page buffer block bPB2, and the second memory block BLK2 includes a first bad fragment connected to the first page buffer block bPB1 and a second passable fragment connected to the second page buffer block bPB2. In this case, block manager 132 can merge the first passable fragment included in the first memory block BLK1 and the second passable fragment included in the second memory block BLK2 based on the fragment status information stored in block register 133, and can store the address corresponding to the merged passable fragment in block register 133. Here, the address can be a block address indicating a memory block.

[0086] In one implementation, the operation controller 131 can control the address decoder 121 to apply an operating voltage corresponding to the command CMD to the merging pass-through block. Here, the command CMD can be any of an erase command, a programming command, and a read command.

[0087] For example, merging pass-through blocks can include a first pass-through block included in any one of multiple memory blocks BLK1 to BLKz and a second pass-through block included in another memory block. Here, the first and second pass-through blocks can be blocks linked to different page buffer blocks.

[0088] As described above, according to embodiments of this disclosure, even if a portion of a storage block contains bad sectors, the corresponding storage block will not be treated as a bad block. Instead, regions comprised of the storage blocks with partial bad sectors can be merged to form a single storage block. Therefore, in this embodiment, the usable capacity of the storage block can be increased without the need for separate reserved storage blocks.

[0089] Figure 6 This is a diagram illustrating the structure of a memory controller according to an embodiment.

[0090] Reference Figure 6 The memory controller 200 may include a host interface (I / F) 210, a flash translation layer (FTL) 220, a processor 230, a memory interface (I / F) 240, a buffer memory 250, an error correction circuit 260, a block merge manager 270, and a block status register 280.

[0091] The host interface 210 can communicate with the host system 20 that conforms to various interface protocols. For example, the host interface 210 can perform communication according to any of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS) interface, and Universal Asynchronous Receiver / Transmitter (UART).

[0092] The host interface 210 can receive various requests from the host system 20. For example, requests may include write requests instructing the storage of data, read requests instructing the output of stored data, and erase requests to erase stored data. The host interface 210 can transmit the received requests to the processor 230.

[0093] The host interface 210 can receive data and logical addresses from the host system 20. Furthermore, the host interface 210 can transfer the received data to the buffer memory 250. The host interface 210 can transfer the received logical addresses to the flash translation layer 220 or the processor 230.

[0094] The flash memory translation layer 220 can store an address mapping table that indicates the mapping relationship between logical addresses and physical addresses. When a logical address is received from the host system 20, the flash memory translation layer 220 can transfer the physical address of the memory device 100 corresponding to the received logical address to the processor 230 based on the address mapping table.

[0095] Processor 230 can control the overall operation of memory controller 200. When power is applied to memory system 10, processor 230 can execute instructions. These instructions may be related to, for example, firmware (FW). Firmware may include host interface layer (HIL) and flash interface layer (FIL). Host interface layer can control communication between host system 20 and host interface 210. That is, the operation of host interface 210 can be controlled by host interface layer (HIL). Flash interface layer can control communication between memory interface 240 and memory device 100. Furthermore, although processor 230 and flash translation layer 220 are in... Figure 6 The components are illustrated as separate components, but this illustration is merely an example, and the operation of the flash conversion layer 220 can also be configured to be performed by the processor 230.

[0096] The memory interface 240 can exchange commands, addresses, and data between the memory controller 200 and the memory device 100 via a channel. For example, the memory interface 240 can send commands and addresses output from the processor 230 and data output from the buffer memory 250 to the memory device 100 via the channel. The memory interface 240 can also send data received from the memory device 100 to the buffer memory 250 via the channel.

[0097] For example, memory interface 240 can transmit programming commands, addresses, and data stored in buffer memory 250 to memory device 100. In this case, memory device 100 can store the data in a page of the memory block corresponding to the address. In another example, memory interface 240 can transmit read commands and addresses to memory device 100. In this case, memory interface 240 can receive data stored in a page of the memory block corresponding to the address from memory device 100. In yet another example, memory interface 240 can transmit erase commands and addresses to memory device 100. In this case, memory device 100 can erase the data stored in the memory block corresponding to the address.

[0098] The buffer memory 250 can temporarily store data received from the host system 20. Here, the data received from the host system 20 can be data to be stored in the memory device 100 in response to programming commands. For example, the buffer memory 250 can store data received from the host system 20. The buffer memory 250 can delete the stored data after it has been stored in the memory device 100.

[0099] The buffer memory 250 can temporarily store data received from the memory device 100. The data received from the memory device 100 may be data stored in the memory device 100 and to be provided to the host system 20 in response to a read command. For example, the buffer memory 250 can store data received from the memory device 100. The buffer memory 250 can delete the stored data after the data has been transferred to the host system 20.

[0100] For this operation, the buffer memory 250 can be implemented as a static random access memory (SRAM) that can continuously retain the stored data as long as power is supplied, or it can be implemented as a dynamic RAM (DRAM) that can retain the stored data only when a refresh operation is performed at predetermined time intervals. In an embodiment, a portion of the buffer memory 250 can be configured as the working memory of the memory controller 200, and it can also be used as a cache memory. In an embodiment, firmware can be stored in a portion of the buffer memory 250. The firmware stored in the buffer memory 250 can be run by the processor 230. However, this is only one embodiment, and the memory controller 200 may also include at least one of the following: working memory independent of the buffer memory 250, cache memory, and a separate memory for storing firmware. The term "predetermined" (such as "predetermined time") as used herein with respect to a parameter means that the value of the parameter is determined before it is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before it is used in the process or algorithm.

[0101] Error correction circuit 260 can perform an encoding operation to generate parity bits for data to be transmitted to memory device 100 using error correction codes. Error correction circuit 260 can perform the encoding operation for each data segment into which the data is divided. Here, the data may have a size corresponding to a page, and the data segments may have a size corresponding to a segment. Here, the parity bits can be codes used to detect or correct erroneous bits in the data. For example, parity bits can be inserted into positions in the actual data corresponding to the beginning or end of the data bits. In the example, parity bits can be inserted into positions corresponding to powers of 2, such as 1, 2, 4, 8, 16, ..., and the data bits in the actual data can be arranged in the remaining positions.

[0102] Error correction circuit 260 can perform a decoding operation to detect and correct erroneous bits in the data read from memory device 100 based on the parity bits included in the read data. Error correction circuit 260 can perform encoding or decoding operations using low-density parity-check (LDPC) codes, BCH (Bose, Chaudhri, Hocquenghem) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), or coded modulation such as lattice-coded modulation (TCM), block-coded modulation (BCM), or Hamming codes. Here, the decoding operation can be referred to as an "error correction operation."

[0103] Error correction circuit 260 can use parity bits contained in the data to detect error bits contained in the data. For example, error correction circuit 260 can use any of a variety of schemes such as parity check, block check, and cyclic redundancy check (CRC) to detect error bits contained in the data.

[0104] Error correction circuit 260 can correct erroneous bits in the data when the number of erroneous bits in the data is less than the error bit reference number. When the number of erroneous bits in the data is equal to or greater than the error bit reference number, error correction circuit 260 cannot correct the erroneous bits in the data. Here, the error bit reference number indicates the ability to correct erroneous bits.

[0105] The block merge manager 270 can manage multiple memory blocks BLK1 to BLKz included in the memory device 100. In an embodiment, the block merge manager 270 can acquire information about each memory block and store the acquired information in the block status register 280. For example, the block merge manager 270 can acquire the operation results of performing programming or reading operations on each memory block and can store fragment status information or slice status information in the block status register 280 based on the operation results. Here, the fragment status information may be information indicating the bad state or pass state of each fragment, and the slice status information may be information indicating the bad state or pass state of each slice.

[0106] The block status register 280 may store at least one of the following: the identifier of the slice block included in each memory block, slice status information, the identifier of the slice included in each slice block, and slice status information indicating whether each slice is a pass slice in which recoverable data is stored or a bad slice in which unrecoverable data is stored.

[0107] In one implementation, the processor 230 can control the memory device 100 based on the block status information, so that the operation corresponding to the command is performed on the merged through blocks. The merged through blocks are obtained by merging the through blocks that are connected to different page buffer blocks in each memory block that includes both through blocks and bad blocks.

[0108] Here, fragment status information can be stored in block status register 280. A block address indicating a storage block can be assigned to a fragment being merged. The block address can be stored in block status register 280.

[0109] In an implementation, the block merge manager 270 may assign a block address indicating a storage block to a merged fragment based on the fragment status information stored in the block status register 280, and may store the assigned block address in the block status register 280.

[0110] Furthermore, when the processor 230 receives a command and a logical address corresponding to the block address from the host system 20, it can control the memory device 100 to perform the operation corresponding to the command on the merged block. Here, the command can be one of an erase command, a programming command, or a read command.

[0111] In one embodiment, the processor 230 can control the memory device 100 to perform a read operation on a data segment stored in a chip connected to a selected word line within a chip included in the memory block.

[0112] In this scenario, upon receiving a data segment acquired through a read operation, the error correction circuit 260 can perform an error correction operation to correct erroneous bits contained in each data segment. Here, the data segment can be a piece of data. When the number of erroneous bits in the piece of data is equal to or greater than the reference number of erroneous bits, the error correction circuit 260 can determine that the error correction operation has failed. When the number of erroneous bits in the piece of data is less than the reference number of erroneous bits, the error correction circuit 260 can determine that the error correction operation has passed. Furthermore, the block merge manager 270 can determine that a segment containing data segments that failed the error correction operation is a bad segment, and a segment containing data segments that passed the error correction operation is a pass segment.

[0113] In one implementation, the processor 230 can control the memory device 100 to perform programming operations that store data segments within the chips included in the chip block, linked to the selected word line. Furthermore, the processor 230 can receive from the memory device 100 a signal indicating whether the programming operation was successful or failed. In this case, the block merge manager 270 can determine that chips that failed in the programming operation are bad chips, and chips that passed the programming operation are successful chips.

[0114] In this implementation, when the number of bad chips in a block is equal to or greater than the bad chip reference number, the block merge manager 270 can determine that the corresponding block is a bad block. When the number of bad chips in a block is less than the bad chip reference number, the block merge manager 270 can determine that the corresponding block is a pass block.

[0115] Furthermore, during the manufacturing process of the memory device 100, bad sectors may occur in the memory device 100 according to embodiments of the present disclosure, such as in the case of initial defects. In this case, an external device connected to the memory device 100 can detect bad blocks in each of the plurality of memory blocks included in the memory device 100. The external device can merge the through blocks included in the respective memory blocks having bad blocks into one memory block, and can assign a block address indicating said one memory block to the through blocks merged into said one memory block. The block address assigned by the external device can be stored in the memory device 100. In the example, the block address assigned by the external device can be stored in the memory controller 200. Here, the external device can be a test device for detecting defects in the memory device 100. However, this is only one embodiment, and the external device can be the host system 20 or the memory controller 200.

[0116] In other embodiments, bad sectors may arise due to degradation of the memory device 100 caused by the passage of time or repeated operations. In this case, the operation of allocating block addresses by fragments can be performed by the memory device 100 or the memory controller 200.

[0117] Figure 7 This is a flowchart illustrating a method for storing information related to a piece according to an embodiment.

[0118] Reference Figure 7 In step S710, the processor 230 of the memory controller 200 according to an embodiment of the present disclosure can control the memory device 100 to perform a read operation to read data stored in each of the plurality of memory blocks BLK1 to BLKz included in the memory device 100. In this case, data segments can be read sequentially from the plurality of pages included in the memory blocks. Data read from a page may include a slice data segment read from the slice corresponding to the corresponding page.

[0119] Furthermore, in step S720, the error correction circuit 260 of the memory controller 200 can perform error correction operations on the read chip data on a chip-by-chip basis. For example, the error correction circuit 260 can use parity bits contained in the chip data to detect error bits contained in the chip data.

[0120] When the number of error bits in the slice data is equal to or greater than the number of error bit references, the error correction circuit 260 of the memory controller 200 can determine that the error correction operation has failed (if "yes" is true in step S730). In this case, in step S740, the block merge manager 270 of the memory controller 200 can determine that the slice with the number of error bits in the output slice data is equal to or greater than the number of error bit references as a bad slice. In addition, the block merge manager 270 can store slice status information indicating that the slice is a bad slice in the block status register 280.

[0121] When the number of error bits in the slice data is less than the number of error bit references, the error correction circuit 260 of the memory controller 200 can determine that the error correction operation has passed (if step S730 is not true). In this case, in step S745, the block merge manager 270 of the memory controller 200 can determine the slice with slice data that outputs a number of error bits less than the number of error bit references as a passed slice. In addition, the block merge manager 270 can store slice status information indicating that the slice is a passed slice in the block status register 280.

[0122] When the number of bad chips in each block is equal to or greater than the bad chip reference number (if "yes" is true in step S750), in step S760, the block merge manager 270 can determine the block containing bad chips equal to or greater than the bad chip reference number as a bad block, and can store the block status information indicating that the block is a bad block in the block status register 280.

[0123] When the number of bad chips in each block is less than the bad chip reference number (in the case of "No" in step S750), in step S765, the block merge manager 270 can determine the block containing bad chips less than the bad chip reference number as a pass block, and can store the block status information indicating that the corresponding block is a pass block in the block status register 280.

[0124] Figure 8 This is a flowchart illustrating a method for performing operations on a piece according to an embodiment.

[0125] Reference Figure 8 In step S810, the processor 230 can select each memory block from a plurality of memory blocks, including both passed and bad memory blocks, based on the block status information. Here, the block status information can be stored in the block status register 280.

[0126] In step S820, the processor 230 can assign a physical address to a merged memory block for the pass-by-pass blocks that are linked to different page buffer blocks included in the selected memory block. Here, the physical address can be a block address indicating a memory block.

[0127] When a command and a logical address are received from the host system 20, the processor 230 can control the memory device 100 to perform a command-related operation on the memory block indicated by the physical address corresponding to the logical address. Here, when the physical address corresponding to the logical address indicates a merged memory block, in step S830, the processor 230 can control the memory device 100 to perform a command-related operation on the fragments included in the merged memory block.

[0128] Figure 9 This is a diagram illustrating a method for managing blocks according to an implementation method.

[0129] Reference Figure 9 In (1), the memory cell array 110 according to the embodiment may include a plurality of memory blocks BLK1 to BLK5.

[0130] For example, the first storage block BLK1 may include a first passable block bCHK11 and a first bad block bCHK12, and the second storage block BLK2 may include a second bad block bCHK21 and a second passable block bCHK22. The third storage blocks BLK3 to the fifth storage blocks BLK5 may respectively include passable blocks bCHK31 and bCHK32, bCHK41 and bCHK42, and bCHK51 and bCHK52.

[0131] Here, the first pass block bCHK11 and the second bad block bCHK21 can be set in the first column, and the first bad block bCHK12 and the second pass block bCHK22 can be set in the second column. The same column indicates that the blocks are associated with the same page buffer block. Different columns indicate that the blocks are associated with different page buffer blocks.

[0132] In this case, regarding Figure 9 The information in the table format shown in (2) can be stored in block register 133 or block status register 280. For example, block register 133 or block status register 280 can store at least one of the following: an identifier for each block, columns for the block, block status information indicating whether the block is bad or passable, and physical address. Here, the columns can indicate information about the page buffer blocks linked to the corresponding block. Furthermore, this is only one implementation, and various types of information can be stored in block register 133 or block status register 280.

[0133] Here, the block manager 132 or the block merger 270 can select, based on information stored in the block register 133 or the block status register 280, each of the multiple storage blocks BLK1 to BLK5, including both passable and bad blocks, a first storage block BLK1 and a second storage block BLK2. Furthermore, the block manager 132 or the block merger 270 can merge the first passable block bCHK11 and the second passable block bCHK22, which are set in different columns, into a single storage block within the first storage block BLK1 and the second storage block BLK2. The block manager 132 or the block merger 270 can assign a block address indicating a storage block to the merged storage block including the first passable block bCHK11 and the second passable block bCHK22, and can store the block addresses corresponding to the first passable block bCHK11 and the second passable block bCHK22 in the block register 133 or the block status register 280.

[0134] Figure 10 This is a flowchart illustrating a method for performing an erase operation on a merged storage block according to an embodiment.

[0135] Reference Figure 10 When an erase command is received, in step S1010, the memory device 100 may apply an erase voltage to the first pass block and the second pass block included in the merged memory block. Furthermore, in step S1020, the memory device 100 may apply an erase verification voltage to the first pass block and the second pass block included in the merged memory block. Then, in step S1030, the memory device 100 may determine whether the erase operation on the merged memory block succeeded or failed.

[0136] In a detailed implementation, the memory controller 200 may receive an erase command and a logical address from the host system 20. It is assumed that the logical address corresponds to a block address indicating a merged memory block. Furthermore, it is assumed that the merged memory block includes a first pass-through block of a first memory block and a second pass-through block of a second memory block.

[0137] In this case, the processor 230 of the memory controller 200 can transmit an erase command and a block address to the memory device 100, wherein the erase command is configured to execute control such that a first erase voltage is applied to a first memory block including a first pass-through block and a second memory block including a second pass-through block, and thereafter erase verification voltages are applied sequentially to the first memory block and the second memory block.

[0138] When an erase command and block address are received from the memory controller 200, in step S1010, the operation controller 131 of the memory device 100 can control the address decoder 121 to apply a first erase voltage to the first pass-through block and the second pass-through block included in the merged memory block. In parallel with the application of the first erase voltage, the operation controller 131 can control the address decoder 121 to apply a second erase voltage to the first substrate of the first memory block including the first pass-through block and the second substrate of the second memory block including the second pass-through block. In this case, the address decoder 121 can apply the first erase voltage to the word lines connected to the first and second memory blocks while simultaneously applying the second erase voltage to the first and second substrates.

[0139] Furthermore, the operation controller 131 can control the address decoder 121 to apply an erase verification voltage to the first pass block and the second pass block. In this case, the address decoder 121 can apply an erase verification voltage to the first word line connected to the first pass block, and then sequentially apply an erase verification voltage to the second word line connected to the second pass block.

[0140] Furthermore, the operation controller 131 can determine whether the erase operation on the merged memory block is successful or unsuccessful. For example, after an erase verification voltage is applied to the first memory block including the first pass-through chip, the operation controller 131 can determine whether the erase operation on the first pass-through chip is successful or unsuccessful based on the result of comparing a first sense voltage sensed by the sensing circuit 125 from the first page buffer block connected to the first pass-through chip with a reference voltage. Similarly, after an erase verification voltage is applied to the second memory block including the second pass-through chip, the operation controller 131 can determine whether the erase operation on the second pass-through chip is successful or unsuccessful based on the result of comparing a second sense voltage sensed by the sensing circuit 125 from the second page buffer block connected to the second pass-through chip with a reference voltage. The operation controller 131 can output a pass signal (PASS) or a failure signal (FAIL) to the memory controller 200 for the erase operation on the first and second pass-through chips.

[0141] Figure 11 This is a flowchart illustrating a method for performing programming operations on a merged storage block according to an embodiment.

[0142] Reference Figure 11Upon receiving a programming command, in step S1110, the memory device 100 may apply a programming voltage to the first pass block and the second pass block included in the merged memory block. Furthermore, in step S1120, the memory device 100 may apply a programming verification voltage to the first pass block and the second pass block included in the merged memory block. Then, in step S1130, the memory device 100 may determine whether the programming operation on the merged memory block succeeded or failed.

[0143] In a detailed implementation, the memory controller 200 may receive programming commands, logical addresses, and page data from the host system 20. Here, it is assumed that the logical address corresponds to the page address indicating one of the multiple pages included in the merged memory block. Furthermore, it is assumed that the merged memory block includes a first pass-through block of a first memory block and a second pass-through block of a second memory block, and that a page consists of a first slice included in the first pass-through block and a second slice included in the second pass-through block.

[0144] In this configuration, the processor 230 of the memory controller 200 can transmit programming commands, block addresses, and page data to the memory device 100. The programming commands are configured to execute control, causing programming voltages to be applied sequentially to the first slice of the first pass-through block and the second slice of the second pass-through block, followed by programming verification voltages. Furthermore, the operation controller 131 of the memory device 100 can receive programming commands and page addresses, and the data input / output circuit 124 of the memory device 100 can receive page data and transmit it to the read / write circuit 123. Here, the page data, divided into first and second slices, can be stored in the first and second page buffer groups of the read / write circuit 123, respectively.

[0145] The operation controller 131 can control the address decoder 121 to sequentially apply programming voltages to the first chip of the first pass-through block and the second chip of the second pass-through block included in the merged memory block. In this case, the address decoder 121 can apply programming voltages to the first word line connected to the first chip. Here, a signal corresponding to the data of the first chip can be transmitted from the first page buffer group to the first chip. Subsequently, programming voltages can be applied to the second word line connected to the second chip. In this case, a signal corresponding to the data of the second chip can be transmitted from the second page buffer group to the second chip.

[0146] Furthermore, the operation controller 131 can control the address decoder 121 to sequentially apply programming verification voltages to the first chip of the first pass block and the second chip of the second pass block included in the merged memory block. In this case, the address decoder 121 can apply programming verification voltages to the first word line connected to the first chip, and then sequentially apply programming verification voltages to the second word line connected to the second chip.

[0147] In addition, the operation controller 131 can determine whether a programming operation on the first slice of the first pass slice block and the second slice of the second pass slice block included in the merged memory block is successful or unsuccessful.

[0148] For example, after a programming verification voltage is applied to the first word line connected to the first chip of the first pass-through chip, the operation controller 131 can determine whether the programming operation on the first chip has succeeded or failed based on a comparison between a first sense voltage sensed by the sensing circuit 125 from the first page buffer block connected to the first chip and a reference voltage. In this case, after a programming verification voltage is applied to the second word line connected to the second chip of the second pass-through chip, the operation controller 131 can determine whether the programming operation on the second chip has succeeded or failed based on a comparison between a second sense voltage sensed by the sensing circuit 125 from the second page buffer block connected to the second chip and a reference voltage.

[0149] In addition, the operation controller 131 can output a pass signal PASS or a failure signal FAIL to the memory controller 200 for programming operations on the first and second chips.

[0150] Figure 12 This is a flowchart illustrating a method for performing a read operation on a merged storage block according to an embodiment.

[0151] Reference Figure 12 When a read command is received, in step S1210, the memory device 100 may apply a read voltage to the first pass-through block and the second pass-through block included in the merged memory block. Furthermore, in step S1220, the memory device 100 may output the read page data to a first page buffer block connected to the first pass-through block and a second page buffer block connected to the second pass-through block. The page data may include the first piece of read data output to the first page buffer block and the second piece of read data output to the second page buffer block.

[0152] In a detailed implementation, the memory controller 200 may receive read commands and logical addresses from the host system 20. Here, it is assumed that the logical address corresponds to a page address indicating one of a plurality of pages included in a merged memory block. Furthermore, it is assumed that the merged memory block includes a first pass-through block of a first memory block and a second pass-through block of a second memory block, and that a page consists of a first slice included in the first pass-through block and a second slice included in the second pass-through block.

[0153] In this configuration, processor 230 can transmit a read command and a page address to memory device 100, wherein the read command is configured to execute control such that a read voltage is sequentially applied to the first chip of the first pass-through block and the second chip of the second pass-through block. Furthermore, operation controller 131 of memory device 100 can receive the read command and the page address.

[0154] The operation controller 131 can control the address decoder 121 to apply read voltages sequentially to the first slice of the first pass block and the second slice of the second pass block included in the merged memory block.

[0155] In this configuration, the address decoder 121 can apply a read voltage to the first word line connected to the first chip. Here, a signal corresponding to the first chip data stored in the first chip can be transmitted to the first page buffer block connected to the first chip. Furthermore, the address decoder 121 can apply a read voltage to the second word line connected to the second chip. Here, a signal corresponding to the second chip data stored in the second chip can be transmitted to the second page buffer block connected to the second chip. The read first chip data transmitted to the first page buffer block and the read second chip data transmitted to the second page buffer block can form a page data segment. The page data stored together in the first and second page buffer blocks can be output to the memory controller 200 via the data input / output circuit 124.

[0156] Figure 13 This is a block diagram illustrating a memory card used in a memory system according to an implementation method.

[0157] Reference Figure 13 The memory card 2000 may include a memory device 2100, a memory controller 2200, and a connector 2300.

[0158] The memory device 2100 can perform programming operations to store data, reading operations to read data, or erasing operations to erase data. In embodiments, the memory device 2100 can be implemented as any of a variety of non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM). (Refer to above) Figure 1 The description of memory device 100 can be applied equally to memory device 2100, and its repeated description will be omitted.

[0159] Memory controller 2200 can control memory device 2100. For example, memory controller 2200 can execute instructions for controlling memory device 2100. Memory controller 2200 can control memory device 2100 to perform programming operations, read operations, or erase operations. Memory controller 2200 can transmit data, commands, etc., between memory device 2100 and host via communication. In embodiments, memory controller 2200 may include components such as RAM, processor, host interface, memory interface, and error correction circuitry. (Refer to above) Figure 1 The description of memory controller 200 can be applied equally to memory controller 2200, and its repeated description will be omitted below.

[0160] The memory controller 2200 can communicate with external devices via connector 2300. The memory controller 2200 can communicate with external devices (e.g., a host) based on a specific communication protocol. In embodiments, the memory controller 2200 can communicate with external devices via at least one of various interface protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) protocols. In embodiments, connector 2300 can be defined using at least one of the aforementioned communication protocols. The memory device 2100 and the memory controller 2200 can be integrated into a single semiconductor device to form a memory card. For example, memory device 2100 and memory controller 2200 can be integrated into a single semiconductor device, which can then be used to form memory cards such as PC cards (i.e., PCMCIA, Personal Computer Memory Card International Association), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC or eMMC), SD cards (SD, mini SD, micro SD or SDHC) or universal flash memory (UFS).

[0161] Figure 14 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an implementation method.

[0162] Reference Figure 14 The SSD system 3000 may include multiple non-volatile memories 3100_1 to 3100_n, an SSD controller 3200, a signal connector 3010, an auxiliary power supply 3030, and a buffer memory 3040.

[0163] The SSD system 3000 can communicate with the host 3300 via the signal connector 3010. The signal connector 3010 can be implemented in the form of an interface conforming to any of the various communication methods. For example, the signal connector 3010 can be one of the various communication methods conforming to: Serial ATA (SATA) interface, mini-SATA (mSATA) interface, PCIe interface, and M.2 interface.

[0164] Reference above Figure 1The description of memory device 100 can be equivalently applied to each of the plurality of non-volatile memories 3100_1 to 3100_n, and repeated descriptions thereof will be omitted below. (Refer to above) Figure 1 The description of memory controller 200 can be applied equivalently to SSD controller 3200, and its repeated description is omitted below.

[0165] External power can be supplied to the SSD system 3000 from the host 3300 via power connector 3020. An auxiliary power supply 3030 can be connected to the host 3300 via power connector 3020. Power can be supplied to the auxiliary power supply 3030 from the host 3300, and the auxiliary power supply 3030 can be charged. The auxiliary power supply 3030 can provide power to the SSD system 3000 when power supply from the host 3300 is not properly implemented. In this implementation, the auxiliary power supply 3030 can be located inside or outside the SSD system 3000. For example, the auxiliary power supply 3030 can be located within the motherboard and can also provide auxiliary power to the SSD system 3000.

[0166] Buffer memory 3040 can be used as a buffer memory for SSD system 3000. For example, buffer memory 3040 can temporarily store data received from host 3300 or data received from multiple non-volatile memories 3100_1 to 3100_n, or it can temporarily store metadata (e.g., mapping tables) of non-volatile memories 3100_1 to 3100_n. Buffer memory 3040 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0167] Figure 15 This is a block diagram illustrating a user system using a memory system according to an implementation method.

[0168] Reference Figure 15 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0169] Application processor 4100 can run user system 4000, operating system (OS), or components included in user programs. In some embodiments, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0170] The memory module 4200 can be used as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, the application processor 4100 and the memory module 4200 may be packaged based on a package stack (POP) and then provided as a single semiconductor package.

[0171] Network module 4300 can communicate with external devices. In some embodiments, network module 4300 may support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, Wireless LAN (WLAN), UWB, Bluetooth, or WiFi. In some embodiments, network module 4300 may be included in application processor 4100.

[0172] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. In embodiments, storage module 4400 can be implemented as a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a 3D structure. In embodiments, storage module 4400 can be provided as a removable drive such as a memory card or an external drive of user system 4000.

[0173] In the implementation method, the above references Figure 1 The description of memory system 10 can be equivalently applied to storage module 4400. For example, storage module 4400 may include multiple non-volatile memory devices. Hereinafter, reference is made to... Figure 1 The description of memory device 100 can be applied equally to each of the plurality of non-volatile memory devices.

[0174] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In embodiments, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0175] This disclosure provides a memory device capable of increasing the available capacity of a memory block and a memory system having the memory device. This disclosure also provides a memory device capable of increasing the available capacity of a memory block without requiring a separate reserved memory block, and a memory system having the memory device.

[0176] Cross-references to related applications

[0177] This application claims priority to Korean Patent Application No. 10-2021-0115135, filed on August 30, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory system comprising: A memory device comprising a plurality of memory blocks, each including a chip, and page buffer blocks respectively connected to said chip; as well as A memory controller, based on block status information indicating whether each block is a pass block or a bad block, controls the memory device to perform an operation corresponding to a command to merge pass blocks, which is obtained by merging pass blocks that are connected to different page buffer blocks in each memory block that includes both the pass blocks and the bad blocks.

2. The memory system according to claim 1, in, The page buffer block includes a first page buffer block and a second page buffer block, and The merged through-block includes a first through-block connected to the first page buffer block and a second through-block connected to the second page buffer block.

3. The memory system according to claim 2, wherein, The memory controller includes: The processor, when the command is an erase command, controls the memory device to apply erase voltages in parallel to a first memory block including the first pass-through block and a second memory block including the second pass-through block, and sequentially applies erase verification voltages to the first memory block and the second memory block.

4. The memory system according to claim 2, wherein, The memory controller includes: The processor, when the command is a programming command, controls the memory device to sequentially apply programming voltages to a first memory block including the first pass-through block and a second memory block including the second pass-through block, and sequentially apply programming verification voltages to the first memory block and the second memory block.

5. The memory system according to claim 2, wherein, The memory controller includes: The processor, when the command is a read command, controls the memory device to sequentially apply read voltages to a first memory block including the first pass-through block and a second memory block including the second pass-through block among the plurality of memory blocks.

6. The memory system according to claim 1, wherein, The memory controller includes: A block status register stores at least one of the following: an identifier of the slice included in each memory block, slice status information, an identifier of the slice included in each slice block, and slice status information indicating that each slice is either a pass slice storing recoverable data or a bad slice storing unrecoverable data.

7. The memory system according to claim 6, wherein, The memory controller also includes: A block merge manager, based on the fragment status information stored in the block status register, allocates an address indicating a storage block for the merge through the fragment, and stores the address in the block status register; and A processor, upon receiving the command and the logical address corresponding to the address from the host, controls the memory device to perform the operation corresponding to the command on the merged block. The command is one of the erase command, programming command, and read command.

8. The memory system according to claim 1, wherein, The memory controller includes: A processor that controls the memory device to perform a read operation on a data segment stored in a chip connected to a selected word line, which is included in the block of chips; and An error correction circuit that performs error correction operations on error bits included in the data segments acquired through the read operation; and A block merge manager that determines that a block containing data that has failed in the error correction operation is a bad block, and determines that a block containing data that has passed the error correction operation is a pass block.

9. The memory system according to claim 8, wherein, The block merging manager determines the selected block as the bad block when the number of bad blocks contained in the selected block within the block is equal to or greater than the bad block reference number, and determines the selected block as the pass block when the number of bad blocks contained in the selected block within the block is less than the bad block reference number.

10. The memory system according to claim 1, wherein, The memory controller includes: A processor that controls the memory device to perform programming operations that store data segments in the chips included in the block, linked to the selected word line; and A block merge manager that determines which of the slices has failed in the programming operation as bad slices and which of the slices has passed the programming operation as pass slices.

11. A memory device comprising: Multiple storage blocks, each of the multiple storage blocks comprising a fragment block, each of the fragment blocks comprising one of a pass fragment block and a bad fragment block; Page buffer blocks, each of which is connected to a slice block; An address decoder applies an operating voltage to a memory block selected from the plurality of memory blocks; A block register stores the block address corresponding to the merged pass block, which is obtained by merging pass blocks that are connected to different page buffer blocks in each storage block that includes both the pass block and the bad block; as well as An operation controller, upon receiving a command and a block address from a memory controller, controls the address decoder to apply an operating voltage corresponding to the command to the merged pass-through block selected by the block address.

12. The memory device according to claim 11, in, The page buffer block includes a first page buffer block and a second page buffer block, and The merged pass-through block includes a first pass-through block connected to the first page buffer and a second pass-through block connected to the second page buffer block.

13. The memory device according to claim 12, wherein, When the command is an erase command, the operation controller controls the address decoder to apply erase voltages in parallel to the first memory block, which includes the first pass block, and the second memory block, which includes the second pass block, and applies erase verification voltages to the first memory block and the second memory block in sequence.

14. The memory device according to claim 12, wherein, When the command is a programming command, the operation controller controls the address decoder to sequentially apply programming voltages to the first storage block, which includes the first pass-through block, and the second storage block, which includes the second pass-through block, and sequentially apply programming verification voltages to the first storage block and the second storage block.

15. The memory device according to claim 12, wherein, When the command is a read command, the operation controller controls the address decoder to sequentially apply read voltages to the first storage block, which includes the first pass-through block, and the second storage block, which includes the second pass-through block, among the plurality of storage blocks.

16. The memory device according to claim 11, wherein, The block register stores at least one of the following: the identifier of the slice included in each memory block, slice status information, the identifier of the slice included in each slice block, and slice status information indicating that each slice is either a pass slice storing recoverable data or a bad slice storing unrecoverable data.

17. The memory device of claim 11, further comprising: A block manager, based on the fragment status information stored in the block register, assigns an address of a storage block to the merged fragment and stores the address in the block register.

18. The memory device according to claim 11, wherein, Each of the plurality of storage blocks includes a plurality of pages connected to different word lines, and Each of the plurality of pages includes a slice that is connected to the same word line among the slices included in each of the slice blocks.

19. The memory device according to claim 11, wherein, When the operation controller receives programming commands, addresses, and chip data from the memory controller, it controls the address decoder to repeatedly execute a programming cycle operation. This programming cycle operation sequentially applies programming voltages and programming verification voltages to the chips included in the chip block that are commonly connected to the word lines selected by the address. The memory device includes: A block manager, among the chips to which the programming verification voltage is applied, determines chips that output chip data while the number of executions of the programming loop operation is within a reference number as pass chips, and determines chips that output data that does not match the chip data while the number of executions of the programming loop operation is within a reference number as bad chips.

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