Display panel and display device

Abstract

The display panel and the display device belong to the technical field of display, and the display panel comprises a pixel driving circuit and a signal line; the pixel driving circuit comprises a driving transistor and a bias transistor, and the signal line comprises a bias signal line; the driving transistor comprises a gate, a first electrode and a second electrode; the bias transistor is electrically connected between the bias signal line and at least one of the first electrode and the second electrode of the driving transistor; the bias signal line comprises first sub-bias signal lines extending along a first direction and arranged along a second direction, and second sub-bias signal lines extending along the second direction and arranged along the first direction; the first direction intersects the second direction, and the first sub-bias signal lines are electrically connected with the second sub-bias signal lines. Thus, by setting the bias signal line to comprise the first sub-bias signal lines and the second sub-bias signal lines extending along different directions and being electrically connected in cross, the overall resistance of the bias signal line can be reduced, the signal transmission stability can be improved, and the influence of the coupling interference can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of display technology, in order to reduce energy consumption, a low-frequency driving method can be used to drive the display panel when displaying static images. At the same time, to ensure image display quality, adjustments have been made to the pixel driving circuit, such as the emergence of an 8T1C structure pixel driving circuit. Compared to the typical 7T1C structure, this 8T1C structure pixel driving circuit adds a bias transistor. This bias transistor is connected between the bias signal line and the first or second terminal of the driving transistor, so that when selectively turned on, it provides a bias voltage signal to one terminal of the driving transistor.

[0003] In related technologies, the bias signal line is easily affected by the coupling interference of signal changes transmitted on other signal lines, which will affect the display quality of the display panel, meaning that the display quality needs to be further improved. Summary of the Invention

[0004] In order to solve the above-mentioned technical problems, or at least partially solve the above-mentioned technical problems, this disclosure provides a display panel and a display device.

[0005] In a first aspect, this disclosure provides a display panel, including a pixel driving circuit and signal lines; The pixel driving circuit includes a driving transistor and a bias transistor, and the signal line includes a bias signal line; The driving transistor includes a gate, a first electrode, and a second electrode; the bias transistor is electrically connected between the bias signal line and at least one of the first electrode and the second electrode of the driving transistor. The bias signal line includes a first sub-bias signal line extending along a first direction and arranged along a second direction, and a second sub-bias signal line extending along the second direction and arranged along the first direction; wherein the first direction intersects the second direction, and the first sub-bias signal line and the second sub-bias signal line are electrically connected.

[0006] Secondly, this disclosure also provides a display device, including any of the above-mentioned display panels.

[0007] The technical solution provided in this disclosure has the following advantages compared with the prior art: In the display panel and display device provided in this disclosure, by setting the bias signal line to include a first sub-bias signal line and a second sub-bias signal line that extend in different directions and are electrically connected to each other, the overall size of the bias signal line can be increased and the overall resistance of the bias signal line can be reduced, thereby improving the signal transmission stability of the bias signal line and reducing the influence of coupling interference from signals transmitted by other signal lines, which is beneficial to improving the display quality of the display panel. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0009] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of a driving timing provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of a display panel film layer stacking structure provided in an embodiment of the present disclosure; Figure 6 This is a partial layout diagram of a display panel provided in an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the structure of a polycrystalline silicon semiconductor layer provided in an embodiment of the present disclosure; Figure 8 This is a schematic diagram of the structure of a first gate metal layer provided in an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the structure of a capacitor metal layer provided in an embodiment of the present disclosure; Figure 10 This is a schematic diagram of an oxide semiconductor layer provided in an embodiment of the present disclosure; Figure 11 This is a schematic diagram of the structure of a second gate metal layer provided in an embodiment of the present disclosure; Figure 12This is a schematic diagram of the structure of a source / drain electrode layer provided in an embodiment of the present disclosure; Figure 13 This is a schematic diagram of a stacked structure of a polycrystalline silicon semiconductor layer to a source / drain electrode layer provided in an embodiment of the present disclosure; Figure 14 This is a schematic diagram of the structure of a first auxiliary metal layer provided in an embodiment of the present disclosure; Figure 15 This is a schematic diagram of the structure of a second auxiliary metal layer provided in an embodiment of the present disclosure; Figure 16 This is a schematic diagram of the structure of a reflective electrode layer provided in an embodiment of the present disclosure; Figure 17 This is a schematic diagram of a stacked structure from a first auxiliary electrode layer to a reflective electrode layer provided in an embodiment of the present disclosure; Figure 18 For along Figure 6 A schematic diagram of the cross-sectional structure of A1A2; Figure 19 For along Figure 6 Schematic diagram of the cross-sectional structure of B1B2; Figure 20 For along Figure 13 Schematic diagram of the cross-sectional structure of A3A4; Figure 21 For along Figure 13 Schematic diagram of the cross-sectional structure of B3B4; Figure 22 A partial layout structure diagram of another display panel provided in an embodiment of this disclosure; Figure 23 This is a schematic diagram of another capacitor metal layer structure provided in an embodiment of the present disclosure; Figure 24 This is a schematic diagram of another structure of the second gate metal layer provided in an embodiment of the present disclosure; Figure 25 This is a schematic diagram of another source / drain electrode layer structure provided in an embodiment of the present disclosure; Figure 26 This is a schematic diagram of another stacked structure of polysilicon semiconductor layer to source / drain electrode layer provided in an embodiment of this disclosure; Figure 27 For along Figure 26 A schematic diagram of the cross-sectional structure of C3C4; Figure 28 For along Figure 22 A schematic diagram of the cross-sectional structure of D1D2; Figure 29 For along Figure 22 Schematic diagram of the cross-sectional structure of E1E2; Figure 30 For along Figure 22A schematic diagram of the cross-sectional structure of C1C2; Figure 31 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure; Figure 32 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure; Figure 33 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure; Figure 34 A cross-sectional structural schematic diagram of another display panel provided in an embodiment of this disclosure; Figure 35 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0011] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0012] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0013] In the display panel provided in this embodiment, the pixel driving circuit based on the 8T1C structure can achieve low-frequency driving and reduce the power consumption of the display panel. At the same time, by setting the bias signal line to include a first sub-bias signal line and a second sub-bias signal line that extend in different directions and are electrically connected in a cross direction, the overall size of the bias signal line can be increased and the overall resistance of the bias signal line can be reduced. This improves the signal transmission stability of the bias signal line and reduces the influence of coupling interference from signals transmitted by other signal lines, thereby helping to improve the image display quality of the display panel.

[0014] The display panel and display device provided in the embodiments of this disclosure will be described by way of example below with reference to the accompanying drawings.

[0015] For example, Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure. (Refer to...) Figure 1The display panel 10 includes a pixel driving circuit 20 and a signal line 30. The pixel driving circuit 20 includes a driving transistor T3 and a bias transistor T8. The signal line 30 includes a bias signal line DVH and may also include a bias control signal line SP. The driving transistor T3 includes a gate g3, a first electrode p31, and a second electrode p32. The bias transistor T8 is electrically connected between the bias signal line DVH and at least one of the first electrode p31 and the second electrode p32 of the driving transistor T3; that is, the bias transistor T8 is electrically connected between the bias signal line DVH and the first electrode p31 of the driving transistor T3. Figure 1 As shown; and / or, bias transistor T8 is electrically connected between bias signal line DVH and the second terminal p32 of driving transistor T3, not shown in the figure. The bias signal line DVH includes a first sub-bias signal line DVH1 extending along a first direction X and arranged along a second direction Y, and a second sub-bias signal line DVH2 extending along the second direction Y and arranged along the first direction X; wherein the first direction X intersects the second direction Y, and the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are electrically connected.

[0016] The signal line 30 is configured to provide voltage and / or current signals to the pixel driving circuit 20; the pixel driving circuit 20 is configured to drive the light-emitting elements to emit light and control the brightness of the light-emitting elements. For example, the display panel 10 may include an array of light-emitting elements and the pixel driving circuit 20, with the pixel driving circuit 20 driving different light-emitting elements to emit light according to a target brightness, so that the display panel 10 displays a target image.

[0017] The pixel driving circuit 20 may include multiple transistors, which may include a driving transistor T3 and a bias transistor T8. The first terminal p81 of the bias transistor T8 is electrically connected to the bias signal line DVH, and the second terminal p82 of the bias transistor T8 is electrically connected to the first terminal p31 of the driving transistor T3, or the second terminal p82 of the bias transistor T8 is electrically connected to both the first terminal p31 and the second terminal p32 of the driving transistor T3. Figure 1 The diagram exemplarily illustrates the electrical connection between the second terminal p82 of the bias transistor T8 and the first terminal p31 of the driving transistor T3, with the gate g8 of the bias transistor T8 electrically connected to the bias control signal line SP. The pixel driving circuit 20 can be configured in various ways; for example, it can be a circuit with a structure such as "7T1C", "7T2C", or "8T1C", where "T" represents a transistor and "C" represents a capacitor. The following description uses an "8T1C" structure as an example.

[0018] The bias transistor T8 is configured to be selectively turned on under the control of the bias control signal provided by the bias control signal line SP, so as to transmit the bias voltage signal transmitted by the bias signal line DVH to the first pole p31 or the second pole p32 of the driving transistor T3.

[0019] The bias control signal can be one type of scan signal; each scan signal can include an enable level and an enable level; the enable level turns the transistor on, and the enable level turns the transistor off. When the transistor is an N-type semiconductor transistor (NMOS), the enable level is high and the enable level is low; when the transistor is a P-type semiconductor transistor (PMOS), the enable level is low and the enable level is high. The same understanding applies to the transistor type, the high and low levels of the enable and enable levels, and the transistor's on or off state at other scan signal locations in the following text, and will not be elaborated further.

[0020] For example, the bias control signal includes an enable level and a disable level. The enable level turns on the bias transistor T8, and the disable level turns it off. When the bias control signal line SP turns on the bias transistor T8, the bias transistor T8 can transmit the bias voltage transmitted on the bias signal line DVH to the first terminal p31 of the driving transistor T3, thereby resetting the first terminal p31 of the driving transistor T3 (i.e., the second node N2 in the following text). This improves the brightness of the first frame during image display, avoids excessively low brightness in the first frame, and ensures good consistency in image display. Furthermore, before resetting the gate g3 of the driving transistor T3, by controlling the bias transistor T8 to turn on, the bias voltage provided by the bias signal line DVH can be written to the first terminal p31 of the driving transistor T3, refreshing the potential of the first terminal p31 of the driving transistor T3. This sets the device characteristics of the driving transistor T3 to a defined initial state, eliminating the influence of the data signal written in the previous frame on the device characteristics of the driving transistor T3. After writing data voltage to the driving transistor T3, leakage current will occur at the first terminal p31 of the driving transistor T3, especially under low-frequency driving, the leakage current will be more obvious, causing the potential of the first terminal p31 of the driving transistor T3 to shift significantly. At this time, by controlling the bias transistor T8 to conduct, the bias transistor T8 writes bias voltage to the first terminal p31 of the driving transistor T3, so that the bias state of the driving transistor T3 can be kept consistent with the bias state when the data voltage was just written, thereby improving the stability of the working state of the driving transistor T3, reducing low-frequency flicker, and thus improving the display effect of the display panel 10.

[0021] In this embodiment of the disclosure, the bias signal line DVH may include a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2 that extend in different directions and are electrically connected to each other; wherein, the first sub-bias signal line DVH1 extends along a first direction X and is arranged along a second direction Y, and the second sub-bias signal line DVH2 extends along the second direction Y and is arranged along the first direction X; wherein, the first direction X and the second direction Y intersect.

[0022] For example, there can be multiple first sub-bias signal lines DVH1 and DVH2, and multiple intersection points between the multiple first sub-bias signal lines DVH1 and multiple second sub-bias signal lines DVH2. The first sub-bias signal lines DVH1 and DVH2 can be electrically connected at all intersection points, such as... Figure 1 As shown; or, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 may be electrically connected at a partial intersection. Specifically, each first sub-bias signal line DVH1 may be connected to at least one second sub-bias signal line DVH2, and each second sub-bias signal line DVH2 may be connected to at least one first sub-bias signal line DVH1.

[0023] In some embodiments, the first direction X is perpendicular to the second direction Y; for example, the first direction X is a row direction and the second direction Y is a column direction. In other embodiments, the first direction X and the second direction Y are not perpendicular and form an angle greater than 0 degrees and less than 90 degrees.

[0024] In the display panel 10 provided in this embodiment, by setting the bias signal line DVH to include a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2 that extend in different directions and are electrically connected in a cross direction, the overall size of the bias signal line DVH can be increased and the overall resistance of the bias signal line DVH can be reduced, thereby improving the signal transmission stability of the bias signal line DVH. As a result, the bias signal line DVH is less affected by coupling interference from other signal lines 30 (such as bias control signal line SP), which is beneficial to improving the display quality of the display panel 10.

[0025] For example, when the display area of ​​the display panel includes an opening, the embodiments of this disclosure can improve the problem of split-screen display at the location of the opening in the display area. For example, a camera or other structural components may be installed at the location of the opening in the display area, and are not limited thereto.

[0026] For example, the first terminal p31 of the driving transistor T3 can be electrically connected to the first power line PVDD. Specifically, the first terminal p31 of the driving transistor T3 can be directly electrically connected to the first power line PVDD, or the first terminal p31 of the driving transistor T3 can be indirectly electrically connected to the first power line PVDD via a thin-film transistor, capacitor, or other components, as described below. Figure 2 An example is provided.

[0027] For example, Figure 2 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present disclosure. Figure 3 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure. (Refer to...) Figure 2 and Figure 3 The pixel driving circuit 20 includes multiple thin-film transistors, which may include a power writing transistor T1, a data writing transistor T2, a driving transistor T3, a compensation transistor T4, a first reset transistor T7, a second reset transistor T5, a light emission control transistor T6, and a bias transistor T8. The pixel driving circuit may also include a storage capacitor Cst. Correspondingly, the signal lines 30 may include scan signal lines, reset signal lines, power signal lines, and data lines DL; wherein the scan signal lines include a first scan signal line S1, a second scan signal line S2, a light emission control scan signal line EMIT, and a third scan signal line SP. And bias control signal line SP; reset signal line includes at least one of first reset signal line VREF1 and second reset signal line VREF2; power signal line includes first power line PVDD and second power line PVEE.

[0028] Specifically, the first terminal of power writing transistor T1 is electrically connected to the first power line PVDD, the second terminal of power writing transistor T1 is electrically connected to the second node N2, and the gate of power writing transistor T1 is electrically connected to the light emission control scan signal line EMIT. The first terminal of data writing transistor T2 is electrically connected to the data line DL, the second terminal of data writing transistor T2 is electrically connected to the second node N2, and the gate of data writing transistor T2 is electrically connected to the third scan signal line SP. Electrical connections: The first terminal of driving transistor T3 is electrically connected to the second node N2, the second terminal of driving transistor T3 is electrically connected to the third node N3, and the gate of driving transistor T3 is electrically connected to the first node N1. The first terminal of compensation transistor T4 is electrically connected to the first node N1, the second terminal of compensation transistor T4 is electrically connected to the third node N3, and the gate of compensation transistor T4 is electrically connected to the second scan signal line S2. The first terminal of second reset transistor T5 is electrically connected to the second reset signal line VREF2, the second terminal of second reset transistor T5 is electrically connected to the first node N1, and the gate of second reset transistor T5 is electrically connected to the first scan signal line S1. The first terminal of light-emitting control transistor T6 is electrically connected to the third node N3, the second terminal of light-emitting control transistor T6 is electrically connected to the fourth node N4, and the gate of light-emitting control transistor T6 is electrically connected to the light-emitting control scan signal line EMIT. The first terminal of first reset transistor T7 is electrically connected to the first reset signal line VREF1, the second terminal of first reset transistor T7 is electrically connected to the fourth node N4, and the gate of second reset transistor T7 is electrically connected to the bias control signal line SP. The first terminal of bias transistor T8 is electrically connected to the bias signal line DVH, the second terminal of bias transistor T8 is electrically connected to the second node N2, and the gate of bias transistor T8 is electrically connected to the bias control signal line SP. The first plate of storage capacitor Cst is electrically connected to the first node N1, and the second plate of storage capacitor Cst is electrically connected to the first power supply line PVDD. This realizes the pixel driving circuit 20 with an 8T1C structure.

[0029] It is understood that when the compensation transistor T4 and the second reset transistor T5 are IGZO transistors and top-bottom dual-gate transistors, their gates are controlled by two scan signal lines. These two scan signal lines are electrically connected in the non-display area and located in different film layers in the display area. They are named with the same reference numerals in this application.

[0030] Specifically, regarding the operation of the pixel driving circuit 20, refer to... Figure 2 and Figure 4 For example, the first scan signal VS1 of the first scan signal line S1 controls the on or off state of the second reset transistor T5 of the pixel driving circuit 20. When the second reset transistor T5 is on, the gate potential of the driving transistor T3 is reset. That is, the second reset signal of the second reset signal line VREF2 is transmitted to the second reset transistor T5, and the connection node (first node N1) of the driving transistor T3, the second reset transistor T5, the compensation transistor T4, and the storage capacitor Cst is reset. The third scan signal line SP The third scan signal VSP The pixel driving circuit 20 controls the switching on and off of the data writing transistor T2. When the data writing transistor T2 is on, the data signal on the data signal line DL is written to the gate of the driving transistor T3. The second scan signal VS2 of the second scan signal line S2 controls the switching on and off of the compensation transistor T4, and compensates the threshold voltage of the driving transistor T3 when the compensation transistor T4 is on. Simultaneously, the bias control signal line SP controls the switching on and off of the first reset transistor T7, and resets the anode of the light-emitting element 200 connected to the pixel driving circuit 20 when the first reset transistor T7 is on, i.e., the first reset signal of the first reset signal line VREF1 is transmitted to the anode of the light-emitting element 200. The light-emitting control scan signal VEMIT of the light-emitting control scan signal line EMIT controls the switching on and off of the power writing transistor T1 and the light-emitting control transistor T6, and transmits the first power signal transmitted by the first power line PVDD to the light-emitting element 200 when the power writing transistor T1 and the second light-emitting control transistor T6 are on, thereby realizing the display and light emission of the light-emitting element 200. The bias control signal VSP of the bias control signal line SP controls the conduction or cutoff of the bias transistor T8. When the bias transistor T8 is on, the bias of the drive transistor T3 is adjusted. That is, the bias signal of the bias signal line DVH is transmitted to the bias transistor T8, and the bias of the connection node (second node N2) of the drive transistor T3, the power write transistor T1, and the data write transistor T2 is adjusted to ensure the working stability of the drive transistor T3.

[0031] like Figure 2 As shown, the thin-film transistors in the pixel driver 20 are diverse, and can simultaneously include oxide transistors (Indium Gallium Zinc Oxide, IGZO) and low-temperature polycrystalline silicon transistors (LTPS). Oxide transistors have advantages such as low leakage current, while low-temperature polycrystalline silicon transistors have advantages such as high switching speed, high carrier mobility, and low power consumption. The display panel 10 combines LTPO and IGZO to create LTPO (Low Temperature Polycrystalline Oxide). This display panel 10 not only possesses the advantages of LTPS display panels such as high resolution, high response speed, high brightness, and high aperture ratio, but also the advantage of IGZO's low leakage current.

[0032] like Figure 3As shown, the transistors in the pixel driving circuit 20 can all be low-temperature poly-silicon (LTPS) transistors. This makes the fabrication process of the display panel 10 simple and reduces the cost of the film layer design. Based on the specific type of display panel 10, this embodiment of the invention is not limited and can be adapted to actual production needs.

[0033] In some embodiments, all thin-film transistors in the pixel driving circuit 20 are transistors of the same channel type, such as all P-type transistors or all N-type transistors, for example... Figure 2 As shown. Alternatively, the thin-film transistors in the pixel driving circuit 20 can also be transistors of different channel types, such as... Figure 3 As shown. Combined with Figure 2 , Figure 3 As mentioned above, oxide transistors are N-type transistors, and low-temperature polysilicon transistors are P-type transistors.

[0034] For example, the power write transistor T1, data write transistor T2, drive transistor T3, first reset transistor T7, light-emitting control transistor T6, and bias transistor T8 can be P-type transistors. Alternatively, the power write transistor T1, data write transistor T2, drive transistor T3, first reset transistor T7, light-emitting control transistor T6, and bias transistor T8 can be PMOS transistors. For example, the power write transistor T1, data write transistor T2, drive transistor T3, first reset transistor T7, light-emitting control transistor T6, and bias transistor T8 can be polysilicon transistors, and the channel of the polysilicon transistor can be constructed of polysilicon. The polysilicon transistor can be a low-temperature polysilicon (LTPS) transistor. Polysilicon transistors have high electron mobility, therefore they have fast drive characteristics.

[0035] The compensation transistor T4 and the second reset transistor T5 can be N-type transistors. For example, the compensation transistor T4 and the second reset transistor T5 can be NMOS transistors. For example, the channels of the compensation transistor T4 and the second reset transistor T5 can be constructed of oxide semiconductor; exemplarily, the oxide semiconductor can include indium gallium zinc oxide (IGZO). Compared with polycrystalline silicon, oxide semiconductor transistors have lower charge mobility. Therefore, the amount of leakage current generated in the off-state of an oxide semiconductor transistor is smaller than the amount of leakage current generated in the off-state of a polycrystalline silicon transistor.

[0036] Therefore, in addition to providing the bias voltage of the bias signal line DVH to the first terminal p31 and / or the second terminal p32 of the driving transistor T3, the compensation transistor T4 and the second reset transistor T5 can also be set as oxide semiconductor transistors, such as IGZO transistors, to reduce the influence of the leakage current of the second reset transistor T5 and the compensation transistor T4 on the potential of the gate g3 of the driving transistor T3, improve the stability of the working state of the driving transistor T3, and thus improve the display effect of the display panel 10.

[0037] It is understandable that the first node N1, the second node N2, the third node N3, and the fourth node N4 can be virtual connection nodes or actual connection nodes.

[0038] For example, Figure 4 This is a schematic diagram of a driving timing provided by an embodiment of the present disclosure, illustrating the provision of a driving timing within one driving cycle. Figure 2 The signals of the pixel driving circuit shown are illustrated. (Refer to...) Figure 4 Taking the compensation transistor T4 in the pixel driving circuit 20 as an N-type transistor and the light-emitting control transistor T6 as a P-type transistor as an example, the gate of the light-emitting control transistor T6 is electrically connected to the light-emitting control scan signal line EMIT. The disabled level of the light-emitting control scan signal VEMIT is high, and the enabled level of the light-emitting control scan signal VEMIT is low; the enabled level of the second scan signal VS2 transmitted by the second scan signal line S2 is high, and the disabled level of the second scan signal S2 transmitted by the second scan signal line S2 is low. In one driving cycle of the pixel driving circuit 20, the light-emitting control scan signal VEMIT transmitted by the light-emitting control scan signal line EMIT includes multiple disabled level stages and multiple enabled level stages, which alternate in a cycle; when the light-emitting control scan signal VEMIT is disabled, the light-emitting control transistor T6 is turned off, and when the light-emitting control scan signal VEMIT is enabled, the light-emitting control transistor T6 is turned on. In one driving cycle of the pixel driving circuit 20, there are a data writing stage P1 and a light-emitting holding stage P2. The data writing stage P1 includes a non-enabled level stage of the light-emitting control scan signal VEMIT. In the light-emitting holding stage P2, the light-emitting control scan signal VEMIT includes multiple non-enabled level stages and multiple enabled level stages. In the data writing stage P1, the second scan signal VS2 transmitted by the second scan signal line S2 includes at least one high level stage to transmit the data signal DL to the gate of the driving transistor T3. In the light-emitting holding stage P2, the second scan signal VS2 transmitted by the second scan signal line S2 is at a low level, controlling the compensation transistor T4 to be turned off.

[0039] It is understandable that during the luminescence retention phase P2, Figure 4 The two enable levels of VSP corresponding to a non-enable level stage of VEMIT can be adjusted to one, and the duration of this enable level stage can be increased or decreased relative to the duration of an enable level stage of VSP in the data writing stage P1. The frequency of the light emission control scan signal VEMIT is greater than the frequency of the signal transmitted by the second scan signal line S2.

[0040] Figure 4 The driving timing is shown in the low-frequency drive mode. In practice, when the display panel needs to have different refresh rates, the duration of the light-holding phase P2 can be adjusted appropriately. When the display panel requires a high-frequency drive mode, the duration of the light-holding phase P2 can be shortened as much as possible compared to the low-frequency drive mode. For example, except for retaining a non-enabled level phase of VEMIT adjacent to the data writing phase P1, the remaining time periods in the light-holding phase P2 can be left unset, and the process can re-enter the next data writing phase P1.

[0041] It should be noted that, as Figure 2 and Figure 3 The pixel driving circuit diagram shown is merely an example and is not intended to limit the embodiments of this disclosure. In other embodiments, the display panel 10 may also include pixel driving circuits 20 with other circuit structures. Figure 4 The driving timing shown is only an example and is not a limitation on the embodiments of this disclosure. In other embodiments, the display panel 10 may be driven using other timings.

[0042] In this display panel 10, the first reset signal line VREF1 and the second reset signal line VREF2 can transmit the same reset signal, meaning that a single reset signal can be used to reset both the first node N1 and the fourth node N4. In other embodiments, the reset signals transmitted by the first reset signal line VREF1 and the second reset signal line VREF2 can be different; that is, the reset voltage of the first node N1 may not be equal to the reset voltage of the fourth node N4, which is not limited here.

[0043] like Figure 3 As shown, in the display panel 10, the compensation transistor T4 and the second reset transistor T5 can be dual-gate transistors to reduce the leakage current of the transistors and improve the display effect of the display panel.

[0044] For example, the compensation transistor T4 may include a first sub-transistor T41 and a second sub-transistor T42; the first terminal of the first sub-transistor T41 is electrically connected to the gate of the driving transistor T3, the second terminal of the first sub-transistor T41 is electrically connected to the first terminal of the second sub-transistor T42, and the second terminal of the second sub-transistor T42 is electrically connected to the second terminal of the driving transistor T3; the gates of the first sub-transistor T41 and the second sub-transistor T42 are both connected to the second scan signal line S2; the intermediate node T4N is located at the connection between the second terminal of the first sub-transistor T41 and the first terminal of the second sub-transistor T42.

[0045] Therefore, the structure of the compensation transistor T4 can be understood as a structure of two sub-transistors connected in series. Specifically, the compensation transistor T4 includes a first sub-transistor T41 and a second sub-transistor T42 connected in series. The first terminal of the first sub-transistor T41 is electrically connected to the gate of the driving transistor T3 as the first terminal of the compensation transistor T4. The second terminal of the second sub-transistor T42 is electrically connected to the second terminal of the driving transistor T3 as the second terminal of the compensation transistor T4. The second terminal of the first sub-transistor T41 is electrically connected to the first terminal of the second sub-transistor T42 to realize the series connection of the two sub-transistors. The gates of the first sub-transistor T41 and the second sub-transistor T42 are both connected to the second scan signal line S2. That is, the gates of the first sub-transistor T41 and the second sub-transistor T42 are connected to the same second scan signal line S2, and are turned off or on based on the same second scan signal VS2. The connection point where the second terminal of the first sub-transistor T41 and the first terminal of the second sub-transistor T42 are electrically connected can be understood as the intermediate node T4N of the compensation transistor T4.

[0046] In the film layer structure of the display panel 10, the active portion of the first sub-transistor T41 and the active portion of the second sub-transistor T42 together form the active portion of the compensation transistor T4. When the active portion is semiconductor-based, the active portion of the first sub-transistor T41 may include a channel region and a first electrode and a second electrode located on both sides of the channel region, respectively. The active portion of the second sub-transistor T42 may also include a channel region and a first electrode and a second electrode located on both sides of the channel region, respectively. The portion connecting the channel regions of the first sub-transistor T41 and the second sub-transistor T42 can be understood as the intermediate node T4N of the compensation transistor T4. The channel region can be understood as the area where the gate of the transistor overlaps with the active portion.

[0047] It should be noted that the position and structure of the intermediate node T4N of the compensation transistor T4 in the display panel film layer structure are not described in detail in this embodiment. The specific position and structure can be set according to the layout of the panel and are not limited here.

[0048] Similarly, the second reset transistor T5 may include a third sub-transistor T51 and a fourth sub-transistor T52; the first terminal of the third sub-transistor T51 is electrically connected to the second reset signal line VREF2, the second terminal of the third sub-transistor T51 is electrically connected to the first terminal of the fourth sub-transistor T52, and the second terminal of the fourth sub-transistor T52 is electrically connected to the first terminal of the driving transistor T3; the gates of the third sub-transistor T51 and the fourth sub-transistor T52 are both connected to the first scan signal line S1; the intermediate node T5N is located at the connection between the second terminal of the third sub-transistor T51 and the first terminal of the fourth sub-transistor T52.

[0049] Therefore, the structure of the second reset transistor T5 can be understood as a structure of two sub-transistors connected in series. Specifically, the second reset transistor T5 includes a third sub-transistor T51 and a fourth sub-transistor T52 connected in series. The first terminal of the third sub-transistor T51 is electrically connected to the second reset signal line VREF2 as the first terminal of the second reset transistor T5. The second terminal of the fourth sub-transistor T52 is electrically connected to the first terminal of the driving transistor T3 as the second terminal of the second reset transistor T5. The second terminal of the third sub-transistor T51 is electrically connected to the first terminal of the fourth sub-transistor T52 to realize the series connection of the two sub-transistors. The gates of the third sub-transistor T51 and the fourth sub-transistor T52 are both connected to the first scan signal line S1, that is, the gates of the third sub-transistor T51 and the fourth sub-transistor T52 are connected to the same first scan signal line S1, and are turned off or on based on the same first scan signal VS1. The connection point where the second terminal of the third sub-transistor T51 and the first terminal of the fourth sub-transistor T52 are electrically connected can be understood as the intermediate node T5N of the second reset transistor T5.

[0050] In the film layer structure of the display panel 10, the active portion of the third sub-transistor T51 and the active portion of the fourth sub-transistor T52 together form the active portion of the second reset transistor T5. When the active portion is semiconductor-based, the active portion of the third sub-transistor T51 may include a channel region and a first electrode and a second electrode located on both sides of the channel region, respectively. The active portion of the fourth sub-transistor T52 may also include a channel region and a first electrode and a second electrode located on both sides of the channel region, respectively. The portion connecting the channel regions of the third sub-transistor T51 and the fourth sub-transistor T52 can be understood as the intermediate node T5N of the second reset transistor T5. The channel region can be understood as the area where the gate of the transistor overlaps with the active portion.

[0051] It should be noted that the position and structure of the intermediate node T5N of the second reset transistor T5 in the display panel film layer structure are not described in detail in this embodiment. The specific position and structure can be set according to the layout of the panel, and are not limited here.

[0052] In the field of display technology, the thin-film transistors and storage capacitors in the pixel driving circuit 20 are all implemented by film layer stacking. For clarity, the embodiments of this disclosure also provide an exemplary description of the film layer stacking method of the display panel 10.

[0053] For example, Figure 5 This is a schematic diagram of a display panel film stacking structure provided in an embodiment of the present disclosure, illustrating the film stacking structure of a low-temperature polycrystalline silicon oxide (LTPO) narrow-bezel panel with fanout traces in the display area (Fanout in AA, FIAA). (Refer to...) Figure 5 The display panel 10 may include a substrate 010 and a buffer layer 011, a first active layer 012, a first gate insulating layer 013, a first gate metal layer 014, an interlayer dielectric layer 015, a capacitor metal layer 016, a second gate insulating layer 017, a second active layer 018, a third gate insulating layer 019, a second gate metal layer 020, a passivation layer 021, a source / drain electrode layer 022, a first auxiliary planarization layer 023, a first auxiliary metal layer 024, a second auxiliary planarization layer 025, a second auxiliary metal layer 026, a planarization layer 027, a reflective electrode layer 028, a light-emitting material layer 029, a counter electrode layer 030, and an encapsulation layer 031, all stacked on one side of the substrate 010. In this paper, the first gate metal layer 014 can also be labeled as M1, the capacitor metal layer 016 can also be labeled as MC, the second gate metal layer 020 can also be labeled as MG, the source / drain electrode layer 022 can also be labeled as M2, the first auxiliary metal layer can also be labeled as M3, and the second auxiliary metal layer 026 can also be labeled as M4.

[0054] The substrate 010 is configured to support the film layer disposed thereon. The substrate 010 may include a rigid substrate, such as glass or silicon wafer, or a flexible substrate, such as thin glass, stainless steel, polyimide, etc., which are not limited herein.

[0055] The buffer layer 011 is configured to flatten and passivate the substrate 010 to facilitate the smooth deposition of subsequent functional films and to prevent the components in the substrate 010 from affecting the performance of subsequent films.

[0056] Both the first active layer 012 and the second active layer 018 are semiconductor layers; for example, the first active layer 012 may be a silicon semiconductor layer, such as a polycrystalline silicon (poly-Si) semiconductor layer; the second active layer 018 may be an oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) semiconductor layer.

[0057] The first gate metal layer 014, capacitor metal layer 016, second gate metal layer 020, source / drain electrode layer 022, first auxiliary metal layer 024, and second auxiliary metal layer 026 can all be metal layers, which are patterned to form pixel driving circuits, signal lines, and other conductor structures in the display panel. The passivation layer 021 is configured to optimize the electrical performance of the conductor structures it covers.

[0058] The reflective electrode layer 028 can be a composite film layer, such as an indium tin oxide (ITO) / silver (Ag) / ITO layer, and the counter electrode layer 030 can be a thinner metal composite layer, such as a magnesium (Mg) / silver (Ag) layer, to improve light transmittance and facilitate the emission of light generated by the light-emitting material layer 029 in the light-emitting element 200. The light-emitting material layer 029 is configured to emit light with target brightness and target color based on the photoelectric effect, in response to signals provided by the reflective electrode layer 028 and the counter electrode layer 030, under the drive of the pixel driving circuit 20, so that the display panel 10 displays the target image.

[0059] The first gate insulating layer 013, interlayer dielectric layer 015, second gate insulating layer 017, third gate insulating layer 019, and passivation layer 021 are typically inorganic insulating layers, while the first auxiliary planarization layer 023, second auxiliary planarization layer 025, and planarization layer 027 are typically organic insulating layers. Through vias within the layers, via electrical connections of corresponding conductor structures can be achieved to form devices in the pixel driving circuit. The encapsulation layer 031 may include an inorganic layer-organic layer-inorganic layer, thereby achieving the encapsulation function.

[0060] It should be noted that the number and stacking order of the above-mentioned film layers are only illustrative and the position or order of the film layers can be added, deleted or adjusted according to actual needs; the materials of the above-mentioned film layers can also be other materials known to those skilled in the art, and can be set according to the needs of the display panel 10, and are not limited here.

[0061] also, Figure 5 The illustration only provides an example of a film layer stacking structure for a display panel combining LTPO and FIAA, and does not constitute a limitation on the embodiments of this disclosure; in other embodiments, the display panel may also adopt other film layer stacking structures, such as the film layer structure of an LTPS panel, the film layer structure of an LTPS panel combined with FIAA, etc., which are not limited herein.

[0062] The following description focuses on the planar patterning of the metal and semiconductor layers in the display panel to illustrate the display panel.

[0063] For example, Figure 6 This is a partial layout diagram of a display panel provided in an embodiment of the present disclosure. Figure 7This is a schematic diagram of the structure of a polycrystalline silicon semiconductor layer provided in an embodiment of this disclosure. Figure 8 This is a schematic diagram of the structure of a first gate metal layer provided in an embodiment of the present disclosure. Figure 9 This is a schematic diagram of the structure of a capacitor metal layer provided in an embodiment of this disclosure. Figure 10 This is a schematic diagram of an oxide semiconductor layer provided in an embodiment of the present disclosure. Figure 11 This is a schematic diagram of the structure of a second gate metal layer provided in an embodiment of the present disclosure. Figure 12 This is a schematic diagram of the structure of a source / drain electrode layer provided in an embodiment of the present disclosure. Figure 13 This is a schematic diagram of a stacked structure from a polycrystalline silicon semiconductor layer to a source / drain electrode layer, provided in an embodiment of this disclosure. Figure 14 This is a schematic diagram of the structure of a first auxiliary metal layer provided in an embodiment of the present disclosure. Figure 15 This is a schematic diagram of the structure of a second auxiliary metal layer provided in an embodiment of the present disclosure. Figure 16 This is a schematic diagram of the structure of a reflective electrode layer provided in an embodiment of the present disclosure. Figure 17 This is a schematic diagram of a stacked structure from a first auxiliary electrode layer to a reflective electrode layer provided in an embodiment of this disclosure. Figure 5 On this basis, Figures 6-17 according to Figure 5 The layer stacking order shown in the figure provides an example of layering the active layer and metal layer in the display panel 10, and Figure 13 An example of the stacking of LTPO-related film layers was provided. Figure 17 An example of the stacking of FIAA-related membrane layers was provided.

[0064] For example, Figure 18 For along Figure 6 The cross-sectional structural diagram of A1A2 shows the cross-electrical connection structure of the bias signal line DVH between different film layers. (Refer to...) Figure 6 , Figure 13 and Figure 18 The bias signal line DVH may include a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2 that extend in different directions and are electrically connected at intersections. The first sub-bias signal line DVH1 extends along a first direction X and is arranged along a second direction Y, while the second sub-bias signal line DVH2 extends along the second direction Y and is arranged along the first direction X. The first sub-bias signal line DVH1 may be located in the capacitor metal layer 016, and the second sub-bias signal line DVH2 may be located in the source / drain electrode layer 022. At the intersection of the second sub-bias signal line DVH2 and the first sub-bias signal line DVH1, a via is provided to achieve electrical connection between them. In other embodiments, the bias signal line DVH may also be formed based on the electrical connection of traces in other metal layers, which is not limited here.

[0065] In some embodiments, continue to refer to Figure 2 and Figure 6 The pixel driving circuit 20 may also include a first reset transistor T7, and the signal line 30 may also include a first reset signal line VREF1; the first reset transistor T7 is electrically connected between the first reset signal line VREF1 and the light-emitting element 200, and the gate of the first reset transistor T7 is connected to the bias control signal line SP.

[0066] The first reset transistor T7 is configured to selectively conduct under the control of the bias control signal provided by the bias control signal line SP. When the bias control signal line SP controls the first reset transistor T7 to conduct, the first reset signal transmitted on the first reset signal line VREF1 is transmitted to the anode of the light-emitting element 200, thereby resetting the fourth node N4 to avoid the influence of the previous frame on the display of the current frame and to ensure good consistency of the image display effect.

[0067] In some embodiments, continue to refer to Figure 6 The first reset signal line VREF1 includes a first sub-reset signal line VREF11 extending along the first direction X and arranged along the second direction Y, and a second sub-reset signal line VREF12 extending along the second direction Y and arranged along the first direction X; wherein the first sub-reset signal line VREF11 and the second sub-reset signal line VREF12 are electrically connected.

[0068] The first reset signal line VREF1 includes a first sub-reset signal line VREF11 and a second sub-reset signal line VREF12 that extend in different directions and are electrically connected at intersections. The first sub-reset signal line VREF11 extends along a first direction X and is arranged along a second direction Y, while the second sub-reset signal line VREF12 extends along the second direction Y and is arranged along the first direction X. There can be multiple first sub-reset signal lines VREF11 and VREF12, and the intersections of these multiple first sub-reset signal lines VREF11 and VREF12 can be multiple. The first sub-reset signal lines VREF11 and VREF12 can be electrically connected at all intersection locations; alternatively, the first sub-reset signal lines VREF11 and VREF12 can be electrically connected at some intersection locations. Specifically, each first sub-reset signal line VREF11 can be connected to at least one second sub-reset signal line VREF12, and each second sub-reset signal line VREF12 can be connected to at least one first sub-reset signal line VREF11.

[0069] In the display panel 10 provided in this embodiment, by setting the first reset signal line VREF1 to include a first sub-reset signal line VREF11 and a second sub-reset signal line VREF12 extending in different directions and electrically connected in a cross direction, the overall size of the first reset signal line VREF1 can be increased and the overall resistance of the first reset signal line VREF1 can be reduced. This makes the first reset signal line VREF1 less affected by the coupling interference of other signal lines 30, thereby improving the consistency of the first reset signal at different positions of the display panel 10, improving the low grayscale consistency, and thus helping to improve the display quality of the display panel 10. For example, it can improve the display splitting problem corresponding to the opening position of the display area.

[0070] In some embodiments, Figure 19 For along Figure 6 The cross-sectional structural diagram of B1B2 shows the cross-electrical connection structure of the first reset signal line VREF1 between different film layers. (Refer to...) Figure 6 , Figure 13 and Figure 19 The first reset signal line VREF1 may include a first sub-reset signal line VREF11 and a second sub-reset signal line VREF12 that extend in different directions and are electrically connected at intersections. The first sub-reset signal line VREF11 extends along a first direction X and is arranged along a second direction Y, while the second sub-reset signal line VREF12 extends along the second direction Y and is arranged along the first direction X. The first sub-reset signal line VREF11 may be located in the capacitor metal layer 016, and the second sub-reset signal line VREF12 may be located in the source / drain electrode layer 022. At the intersection of the second sub-reset signal line VREF12 and the first sub-reset signal line VREF11, an electrical connection is achieved between them by providing vias. In other embodiments, the first reset signal line VREF1 may also be formed by electrical connections based on crossovers of traces in other metal layers, which is not limited here.

[0071] In some embodiments, refer to Figure 18 The first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are configured on different layers; refer to Figure 19 The first sub-reset signal line VREF11 and the second sub-reset signal line VREF12 are set on different layers.

[0072] Among them, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are two signal lines with different extension directions that constitute the bias signal line DVH. The two signal lines with different extension directions are arranged in different layers, that is, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are located in different film layers, which helps to reduce the difficulty of laying out the signal lines.

[0073] For example, combined Figure 6 or Figure 13 The first sub-bias signal line DVH1 may be located in the capacitor metal layer, and the second sub-bias signal line DVH2 may be located in the source-drain electrode layer. In other embodiments, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 may also be disposed in other two different metal layers, for example, the first sub-bias signal line DVH1 is located in the capacitor metal layer, and the second sub-bias signal line DVH2 is located in the second gate metal layer, which is not limited here.

[0074] Similarly, the first sub-reset signal line VREF11 and the second sub-reset signal line VREF12 are two signal lines with different extension directions that constitute the first reset signal line VREF1. The two signal lines with different extension directions are arranged in different layers, that is, the first sub-reset signal line VREF11 and the second sub-reset signal line VREF12 are located in different film layers, which helps to reduce the difficulty of laying out the signal lines.

[0075] For example, combined Figure 6 or Figure 13 The first sub-reset signal line VREF11 may be located in the capacitor metal layer, and the second sub-reset signal line VREF12 may be located in the source-drain electrode layer. In other embodiments, the first sub-reset signal line VREF11 and the second sub-reset signal line VREF12 may also be arranged in other two different metal layers, for example: the first sub-reset signal line VREF11 is located in the capacitor metal layer, and the second sub-reset signal line VREF12 is located in the second gate metal layer, which is not limited here.

[0076] In the display panel 10 provided in this embodiment, by setting two signal lines that constitute the bias signal line DVH and the first reset signal line VREF1 with different extension directions, they are located in different film layers, which helps to reduce the difficulty of laying out the signal lines.

[0077] In some embodiments, the first reset signal line VREF1 and the bias signal line DVH are at least partially disposed on the same layer and insulated from each other.

[0078] The first reset signal line VREF1 and the bias signal line DVH both include signal lines extending along a first direction X and a second direction Y. Based on this, the first reset signal line VREF1 and the bias signal line DVH, whose signal lines extend in at least one direction, can be arranged on the same layer and are electrically insulated. For example, signal lines extending along the first direction X can be arranged on the same layer, such as the first sub-bias signal line DVH1 and the first sub-reset signal line VREF11 being arranged on the same layer, and / or the second sub-bias signal line DVH2 and the second sub-reset signal line VREF12 being arranged on the same layer.

[0079] For example, referring to the above, in the first reset signal line VREF1 and the bias signal line DVH, the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 are both located in the capacitor metal layer, and the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 can both be located in the source-drain electrode layer. That is, the first reset signal line VREF1 and the bias signal line DVH are all disposed in the same layer, occupying two film layers. Alternatively, the first sub-reset signal line VREF11 can be located in the capacitor metal layer, the first sub-bias signal line DVH1 can be located in the second gate metal layer, and the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 can both be located in the source-drain electrode layer. That is, the first reset signal line VREF1 and the bias signal line DVH are partially disposed in the same layer, occupying three film layers.

[0080] In this embodiment, the first reset signal line VREF1 and the bias signal line DVH are at least partially disposed on the same layer and insulated from each other. This helps to reduce the total number of metal layers occupied by the first reset signal line VREF1 and the bias signal line DVH, which is beneficial to achieving a thinner and lighter design for the display panel. At the same time, by forming two different signal lines in the same film layer, it is beneficial to improve the utilization rate of the film layer, improve the uniformity of the film layer wiring, thereby improving the uniformity of the electrical performance of the display panel 10 and improving the display effect.

[0081] In some embodiments, combined with Figure 5 and Figure 6 The display panel 10 includes a substrate 01, a first metal layer MC and a second metal layer M2, with the second metal layer M2 located on the side of the first metal layer MC away from the substrate 01.

[0082] For example, substrate 01 may include base 010 and buffer layer 011; first metal layer MC may be capacitor metal layer 016 and second metal layer M2 may be source / drain electrode layer 022.

[0083] The first metal layer MC includes a first sub-reset signal line VREF11 and a first sub-bias signal line DVH1. That is, the capacitor metal layer 016 may include a portion of the first reset signal line VREF11 and the first sub-bias signal line DVH1 extending along the first direction X, and the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 are insulated to transmit the first reset signal and the bias voltage signal, respectively.

[0084] The second metal layer M2 includes a second sub-reset signal line VREF12 and a second sub-bias signal line DVH2. That is, the source-drain electrode layer 022 may include a portion of the first reset signal line VREF11 and the first sub-bias signal line DVH1 extending along the second direction Y. The second sub-reset signal line VREF12 is insulated from the second sub-bias signal line DVH2 to transmit the first reset signal and the bias voltage signal, respectively.

[0085] In this embodiment, by setting the first metal layer MC to include a first sub-reset signal line VREF11 and a first sub-bias signal line DVH1, and the second metal layer M2 to include a second sub-reset signal line VREF12 and a second sub-bias signal line DVH2, the first reset signal line VREF1 and the bias signal line DVH are distributed in the two metal layers, and the same metal layer includes signal lines extending in the same direction, while signal lines extending in different directions are located in different metal layers. This reduces the difficulty of routing within the same metal layer, reduces the film layer occupancy, and facilitates the thin and light design of the display panel 10.

[0086] In some embodiments, continue to refer to Figure 1 or Figure 6 The pixel driving circuit 20 can be arranged in an array, such as in multiple rows and columns, to drive the corresponding light-emitting elements respectively to achieve screen display.

[0087] In some embodiments, combined with Figure 1 , Figure 6 as well as Figure 9 The number of first sub-reset signal lines VREF11 is N11, the number of first sub-bias signal lines DVH1 is N12, and the number of rows of pixel driving circuit 20 is N10. Where N11≤N10, N12≤N10, and N10, N11, and N12 are all positive integers.

[0088] With reference to the number of rows in the pixel driving circuit 20, the number of the first sub-reset signal line VREF11 can be equal to or less than the number of rows in the pixel driving circuit 20, and the number of the first sub-bias signal line DVH1 can also be equal to or less than the number of rows in the pixel driving circuit.

[0089] In some embodiments, for the same row of pixel driving circuits 20, both a first sub-reset signal line VREF11 and a first sub-bias signal line DVH1 can be provided, and along the second direction Y, the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 can be located on the upper and lower sides of the row of pixel driving circuits 20; at this time, N10=N11=N12, thus simultaneously increasing the number of the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1, which is beneficial to increase the overall size of the first reset signal line VREF1 and the bias signal line DVH, reduce the overall resistance of the bias signal line DVH and the first reset signal line VREF1, improve the signal transmission stability of the bias voltage signal and the first reset signal, thereby reducing coupling interference and improving the display effect of the display panel.

[0090] Alternatively, for the pixel driving circuit 20, the first sub-reset signal line VREF11 can be set in some rows, and the first sub-bias signal line DVH1 can be set in other rows. In this case, N10>N11 and N10>N12, which reduces the arrangement density of the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 to a certain extent. While reducing coupling interference and improving the display effect, it can also reduce the difficulty of signal line layout.

[0091] In some embodiments, along the second direction Y, the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 are arranged alternately; and N10≥N11+N12.

[0092] This configuration can improve the uniformity of the distribution of the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 in the display panel, thereby improving the wiring uniformity within the film layer, which is beneficial to improving the overall signal consistency of the display panel and enhancing the display effect.

[0093] The first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 can be arranged alternately in a certain ratio; for example, a single first sub-reset signal line VREF11 and a single first sub-bias signal line DVH1 can be arranged alternately in a ratio of 1:1; or two first sub-reset signal lines VREF11 and a single first sub-bias signal line DVH1 can be arranged alternately in a ratio of 2:1; or other ratios can be used, which are not limited here.

[0094] For example, with Figure 6 and Figure 9 For example, for two adjacent rows of pixel driving circuits 20, a first sub-reset signal line VREF11 and a first sub-bias signal line DVH1 are respectively set, and the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 are arranged alternately in sequence; at this time, N10=N11+N12.

[0095] With this configuration, a row of pixel driving circuits 20 is spaced between the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1. This improves the wiring uniformity of the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1, while increasing the spacing between the two signal lines and reducing their mutual influence. This helps to improve the distribution consistency of the first reset signal and the bias voltage signal within the display panel, thus improving the display effect.

[0096] In some embodiments, for certain rows of pixel driving circuits 20, neither the first sub-reset signal line VREF11 nor the first sub-bias signal line DVH1 may be provided; instead, signal lines for transmitting other signals may be provided. In this case, N10 > N11 + N12. This configuration improves the display effect while also meeting the requirement of providing different functional signal lines within a limited film layer.

[0097] In other embodiments, the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 may be arranged in other ways, which are not limited here.

[0098] In some embodiments, combined with Figure 1 , Figure 6 , Figure 12 as well as Figure 13 The number of second sub-reset signal lines VREF12 is N21, the number of second sub-bias signal lines DVH2 is N22, and the number of columns of pixel driving circuit 20 is N20. Where N21≤N20, N22≤N20, and N20, N21, and N22 are all positive integers.

[0099] With reference to the number of columns of the pixel driving circuit 20, the number of the second sub-reset signal line VREF12 can be equal to or less than the number of columns of the pixel driving circuit 20, and the number of the second sub-bias signal line DVH2 can also be equal to or less than the number of columns of the pixel driving circuit.

[0100] In some embodiments, for the same column of pixel driving circuits 20, both a second sub-reset signal line VREF12 and a second sub-bias signal line DVH2 can be provided, and along the first direction X, the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 can be located on the left and right sides of the column of pixel driving circuits 20; at this time, N20=N21=N22, thus simultaneously increasing the number of the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2, which is beneficial to increase the overall size of the first reset signal line VREF1 and the bias signal line DVH, reduce the overall resistance of the bias signal line DVH and the first reset signal line VREF1, improve the signal transmission stability of the bias voltage signal and the first reset signal, thereby reducing coupling interference and improving the display effect of the display panel.

[0101] Alternatively, for the pixel driving circuit 20, the second sub-reset signal line VREF12 can be partially arranged in rows, and the second sub-bias signal line DVH2 can be arranged in rows in another row. In this case, N20>N21 and N20>N22, which reduces the arrangement density of the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 to a certain extent. While reducing coupling interference and improving the display effect, it can also reduce the difficulty of signal line arrangement.

[0102] In some embodiments, along the first direction X, the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 are arranged alternately; and N20≥N21+N22.

[0103] This configuration can improve the uniformity of the distribution of the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 in the display panel, thereby improving the uniformity of wiring within the film layer, which is beneficial to improving the overall signal consistency of the display panel and enhancing the display effect.

[0104] The second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 can be arranged alternately in a certain ratio; for example, a single second sub-reset signal line VREF12 and a single second sub-bias signal line DVH2 can be arranged alternately in a ratio of 1:1; or two second sub-reset signal lines VREF12 and a single second sub-bias signal line DVH2 can be arranged alternately in a ratio of 2:1; or other ratios can be used, which are not limited here.

[0105] For example, with Figure 6 and Figure 12 For example, for two adjacent pixel driving circuits 20, a second sub-reset signal line VREF12 and a second sub-bias signal line DVH2 are respectively set, and the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 are arranged alternately in sequence; at this time, N20=N21+N22.

[0106] With this configuration, a column of pixel driving circuits 20 is spaced between the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2. This improves the wiring uniformity of the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2, while increasing the spacing between the two signal lines and reducing their mutual influence. This helps to improve the distribution consistency of the first reset signal and the bias voltage signal within the display panel, thus improving the display effect.

[0107] In some embodiments, for certain columns of pixel driving circuits 20, neither the second sub-reset signal line VREF12 nor the second sub-bias signal line DVH2 may be provided. Instead, signal lines for transmitting other signals may be laid out. In this case, N20 > N21 + N22. This configuration improves the display effect while also meeting the requirement of laying out different functional signal lines within a limited film layer.

[0108] In other embodiments, the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 may be arranged in other ways, which are not limited here.

[0109] In some embodiments, continue to refer to Figure 12 and Figure 13 The second sub-reset signal line VREF12 includes a main body extending along the second direction Y, and the second sub-bias signal line DVH2 includes a main body extending along the second direction Y; in two adjacent column pixel driving circuits 20, the main body of the second sub-reset signal line VREF12 and the main body of the second sub-bias signal line DVH2 are symmetrically arranged along the second direction Y.

[0110] The axis of symmetry between the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 can be represented by the dashed line along the second direction Y in the figure. For ease of description, the dashed lines along the first direction X and the second direction Y in the figure are used to roughly delineate the area of ​​the pixel driving circuit.

[0111] In this embodiment of the disclosure, by symmetrically arranging the main body of the second sub-reset signal line VREF12 and the main body of the second sub-bias signal line DVH2, the wiring difficulty can be reduced through symmetrical design.

[0112] In some embodiments, continue to refer to Figure 2 and Figure 6 The pixel driving circuit 20 also includes a second reset transistor T5, and the signal line 30 also includes a second reset signal line VREF2; the second reset transistor T5 is electrically connected between the second reset signal line VREF2 and the gate of the driving transistor T3.

[0113] The signal line 30 may further include a first scan signal line S1, and the gate of the second reset transistor T5 is connected to the first scan signal line S1; the second reset transistor T5 is configured to be selectively turned on under the control of the first scan signal provided by the first scan signal line S1.

[0114] The first scan signal can be any type of scan signal, including an enable level and a disable level. The enable level turns on the second reset transistor T5; the disable level turns off the second reset transistor T5. When the first scan signal line S1 controls the second reset transistor T5 to turn on, the second reset signal transmitted on the second reset signal line VREF2 is transmitted to the gate of the driving transistor T3 to reset the first node N1, thereby ensuring good consistency in the image display.

[0115] In some embodiments, continue to refer to Figure 6 and Figure 11 The second reset signal line VREF2 includes a portion extending along at least one of the first direction X and the second direction Y. Figure 6 and Figure 11 The example shows a second reset signal line VREF2 extending along a first direction X. In other embodiments, the second reset signal line VREF2 may also extend along a second direction Y; or, the second reset signal line VREF2 may include portions extending along the first direction X and the second direction Y respectively and electrically connected to each other, which may be configured based on the needs of the display panel 10 and is not limited herein.

[0116] In some embodiments, Figure 20 For along Figure 13 A schematic cross-sectional view of section A3A4. (Refer to...) Figure 13 and Figure 20 The second reset signal line VREF2 includes a third sub-reset signal line VREF20 extending along the first direction X, and the third sub-reset signal line VREF20 is disposed on a different layer from the bias signal line DVH.

[0117] For example, combined Figure 9 , Figure 11 and Figure 12 The third sub-reset signal line VREF20 can be located in the second gate metal layer 020 / MG, and the bias signal line DVH is located in the capacitor metal layer 016 / MC and the source / drain electrode layer 022 / M2.

[0118] In this embodiment of the disclosure, by setting the third sub-reset signal line VREF20 and the bias signal line DVH on different layers, the spacing between the third sub-reset signal line VREF20 and the bias signal line DVH can be increased, signal coupling can be reduced, and the display effect can be improved.

[0119] In some embodiments, continue to refer to Figure 13 and Figure 20 Along the direction Z perpendicular to the plane of the substrate, the third sub-reset signal line VREF20 and the first sub-bias signal line DVH1 at least partially overlap. The direction Z perpendicular to the plane of the substrate is the thickness direction Z of the display panel 10, which is perpendicular to the plane defined by the first direction X and the second direction Y.

[0120] This configuration helps to reduce the planar area occupied by the third sub-reset signal line VREF20 and the first sub-bias signal line DVH1 in the display panel 10, which helps to increase the spatial density of the signal lines, improve the pixel density, and thus improve the display effect.

[0121] In some embodiments, Figure 21 For along Figure 13 A schematic cross-sectional view of section B3B4. (Refer to...) Figure 13 and Figure 21 The third sub-reset signal line VREF20 can also be set on a different layer than the first reset signal line VREF1.

[0122] Exemplarily, in combination with Figure 9 、 Figure 11 and Figure 12 , the third sub-reset signal line VREF20 is located in the second gate metal layer, and the first reset signal line VREF1 is located in the capacitor metal layer and the source-drain electrode layer.

[0123] In the embodiments of the present disclosure, by arranging the third sub-reset signal line VREF20 and the first reset signal line VREF1 in different layers, the distance between the third sub-reset signal line VREF20 and the first reset signal line VREF1 can be increased, signal coupling can be reduced, and the display effect can be improved.

[0124] In some embodiments, continue to refer to Figure 13 and Figure 21 , along the direction Z perpendicular to the plane of the substrate, the third sub-reset signal line VREF20 and the first reset signal line VREF1 at least partially overlap.

[0125] With such an arrangement, it is beneficial to reduce the planar occupation area of the third sub-reset signal line VREF20 and the first reset signal line VREF1 in the display panel 10, beneficial to increase the space density of the signal lines, increase the pixel density, and further improve the display effect.

[0126] In some embodiments, continue to refer to Figure 11 and Figure 13 , the number of the third sub-reset signal lines VREF20 is N13, and the number of rows of the pixel driving circuit 20 is N10, where N13 ≤ N10, and both N13 and N10 are positive integers.

[0127] Exemplarily, for each row of the pixel driving circuit 20, a third sub-reset signal line VREF20 can be correspondingly arranged, N13 = N10, that is, the ratio between the number of rows of the pixel driving circuit 20 and the number of the third sub-reset signal lines VREF20 can be 1:1.

[0128] In other embodiments, the number of the third sub-reset signal lines VREF20 can also be less than the number of rows of the pixel driving circuit 20, that is, N13 < N10. For example, one third sub-reset signal line VREF20 corresponds to every two rows of the pixel driving circuit 20, so as to reduce the number of the third sub-reset signal lines VREF20, reduce the interference of the signals transmitted by it to other signal lines, and improve the display effect.

[0129] In the above embodiments, the bias signal line DVH, the first reset signal line VREF1, and the second reset signal line VREF2 are exemplarily described. Next, the other structures shown in Figures 5-21 will be described.

[0130] Combination Figure 5 , Figure 6 , Figure 7 and Figure 8 The polysilicon semiconductor layer includes a channel region p8 of a bias transistor T8. Along a direction perpendicular to the plane of the substrate, i.e., in a direction perpendicular to the plane formed by the first direction X and the second direction Y, the channel region p8 of the bias transistor T8 and the bias control signal line SP at least partially overlap. Optionally, the channel region p8 of the bias transistor T8 is the region of the polysilicon semiconductor layer directly opposite the bias control signal line SP. The overlapping portion of the bias control signal line SP and the channel region p8 of the bias transistor T8 is the gate g8 of the bias transistor T8, so that the gate g8 of the bias transistor T8 is electrically connected to the bias control signal line SP.

[0131] Combination Figure 5 , Figure 6 , Figure 7 and Figure 18 The bias transistor T8 includes a channel region p8 located in the polysilicon semiconductor layer, and a first electrode p81 and a second electrode p82 connected to the channel region p8. The first electrode p81 of the bias transistor is electrically connected to the second sub-bias signal line DVH2 located in the source-drain electrode layer, and the second sub-bias signal line DVH2 is electrically connected to the first sub-bias signal line DVH1 located in the capacitor metal layer. The second electrode p82 of the bias transistor T8 is connected to the second electrode p12 of the power supply writing transistor T1 through the connection part K6 located in the source-drain electrode layer, and is connected to the first electrode p31 of the driving transistor T3, that is, connected to the second node N2.

[0132] Combination Figure 5 , Figure 6 , Figure 7 and Figure 8 The polysilicon semiconductor layer includes a channel region p3 of a driving transistor T3. The gate g3 of the driving transistor T3 is located in a first gate metal layer. In a direction perpendicular to the plane of the substrate, the gate g3 of the driving transistor T3 at least partially overlaps with the channel region p3 of the driving transistor T3. The gate g3 of the driving transistor T3 is electrically connected to a compensation transistor T4 and a second reset transistor T5 through a first connection portion K3 located in the source-drain electrode layer.

[0133] The driving transistor T3 includes a channel region p3 located in the polysilicon semiconductor layer, and a first electrode p31 and a second electrode p32 connected to the channel region. The second electrode p32 of the driving transistor T3 is connected to the first electrode p61 of the light-emitting control transistor T6.

[0134] It should be noted that, Figure 7 and Figure 10 In the diagram, the portion of each transistor located in the polysilicon semiconductor layer is divided into regions, for example... Figure 7The diagram also shows the active region p1, first electrode p11, and second electrode p12 of the power write transistor; the active region p2, first electrode p21, and second electrode p22 of the data write transistor; the active region p6, first electrode p61, and second electrode p62 of the light-emitting control transistor; and the active region p7, first electrode p71, and second electrode p72 of the first reset transistor. Figure 10 The diagram also shows the active region p4, first electrode p41, and second electrode p42 of the compensation transistor, and the active region p5, first electrode p51, and second electrode p52 of the second reset transistor, but this is not intended to limit specific regions. Furthermore, the connections between different transistors can be achieved through connection portions located in the metal layer. Therefore, the gates, first electrodes, or second electrodes of different transistors can correspond to the same node and have the same potential.

[0135] The different names and labels used in the figures in this document are only for the purpose of better explaining the embodiments of this disclosure.

[0136] It should be noted that, Figure 8 , Figure 9 and Figure 11 In the diagram, the portions of each transistor located in the first gate metal layer, capacitor metal layer, and second gate metal layer are divided into regions, such as gate g1, gate g2, gate g4, gate g5, gate g6, gate g7, etc. Figure 8 and Figure 9 The first plate Cst1 and the second plate Cst2 of the storage capacitor Cst are marked, and in Figure 9 The diagram illustrates the cross-connection and cross-non-connection structures for the bias signal line DVH and the first reset signal line VREF1. The following section discusses these structures in conjunction with... Figure 9 , Figure 12 , Figure 13 as well as Figure 18 and Figure 19 Please provide an explanation.

[0137] For example, Figure 9 The capacitor metal layer shown includes a first sub-bias signal line DVH1 extending along a first direction X, a first sub-reset signal line VREF11, a connection portion Z16 and a dummy portion Z06 electrically connected to the first sub-bias signal line DVH1, and a connection portion Z15 and a dummy portion Z05 electrically connected to the first sub-reset signal line VREF11. Figure 12The source / drain electrode layer shown includes a second sub-bias signal line DVH2 extending along the second direction Y, a second sub-reset signal line VREF12, a connection portion Z24 and a dummy portion Z07 electrically connected to the second sub-bias signal line DVH2, and a connection portion Z23 and a dummy portion Z08 electrically connected to the second sub-reset signal line VREF12; wherein, the dummy portions Z05 and Z07 can overlap in the thickness direction Z of the display panel, and the dummy portions Z06 and Z08 overlap in the thickness direction Z of the display panel. The connecting parts Z15 and Z23 can overlap in the thickness direction Z of the display panel and are electrically connected to each other to achieve a cross electrical connection between the first sub-reset signal line VREF11 and the second sub-signal VREF12; the connecting parts Z16 and Z24 can overlap in the thickness direction Z of the display panel and are electrically connected to each other to achieve a cross electrical connection between the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2.

[0138] In some embodiments, the first power line PVDD in the display panel may be located in the capacitor metal layer and the first auxiliary metal layer, and both the first power line PVDD in the capacitor metal layer and the first power line PVDD in the first auxiliary metal layer extend along the first direction X and can be electrically connected through the connection portion Z13 located in the capacitor metal layer to transmit the first power signal; at the same time, since the first power line PVDD is arranged in two different metal layers, its overall size is increased and its overall resistance is reduced, thereby improving the coupling effect of other signals on the first power signal, which is beneficial to enhancing the stability of the first power signal and improving the display effect of the display panel.

[0139] In some embodiments, Figure 12The diagram also illustrates other connection / transition structures that the source and drain electrode layers may include. For example, transition section K1 represents a transition section between the polysilicon semiconductor layer and the anode layer. It can serve as a pad layer to realize the electrical connection between the second electrode of the light-emitting control transistor T6 and the anode of the light-emitting element 200. Furthermore, by providing this transition section K1, the via between the polysilicon semiconductor layer and the anode layer at this location is divided into two shallower vias, reducing the difficulty of drilling and improving the overall structural stability. For example, transition section K2 represents a transition between the driving transistor T3 and the compensation transistor T4, specifically corresponding to the transition between the second electrode of the driving transistor T3 and the first electrode of the compensation transistor T4, realizing the electrical connection between the LTPS transistor based on the polysilicon semiconductor layer (i.e., the driving transistor T3) and the IGZO transistor based on the oxide semiconductor layer (i.e., the compensation transistor T4). For example, transition portion K5 represents a transition portion located between the first power line PVDD in the first auxiliary metal layer and the first electrode of the power writing transistor T1. The position of transition portion K5 can correspond to the position of connection portion Z13 located in the capacitor metal layer, that is, transition portion K5 and connection portion Z13 at least partially overlap in the thickness direction of the display panel, so as to realize that the first power line PVDD is connected to the first electrode of the power writing transistor T1. For example, transition portion K7 represents a transition portion between the bias signal line DVH and the first electrode of the driving transistor T3, used to realize the electrical connection between the bias signal line DVH and the first electrode of the driving transistor T3. For example, transition portion K8 represents a transition portion between the data line DL in the second auxiliary metal layer and the data writing transistor T2, used to realize the electrical connection between the data line DL and the first electrode of the data writing transistor T2. In other embodiments, the source and drain electrode layers may also include other structures, which are not limited here.

[0140] In some embodiments, Figures 14-17 An optional patterned structure of a first auxiliary metal layer, a second auxiliary metal layer, and a reflective electrode layer is shown. For example, refer to... Figures 14-17 The first auxiliary metal layer may contain signal lines and connection structures extending along the first direction X, and the second auxiliary metal layer may contain signal lines and connection structures extending along the second direction Y. The reflective metal layer may contain the anode RE of the light-emitting element and the connection structure. For details, please refer to the explanation of the FIAA structure below.

[0141] The above embodiments provide an exemplary description of the structure of the display panel 10 provided in this disclosure. Other optional structures of the display panel 10 are shown below, wherein the structures of some film layers (such as film layers other than the second gate metal layer, capacitor metal layer and source / drain electrode layer) may be the same as those described above, and can be understood with reference to the above description, and will not be repeated below.

[0142] In some embodiments, Figure 22 This is a partial layout diagram of another display panel provided in an embodiment of this disclosure. Figure 23 This is a schematic diagram of another capacitor metal layer provided in an embodiment of this disclosure. Figure 24 This is a schematic diagram of another structure of the second gate metal layer provided in an embodiment of this disclosure. Figure 25 This is a schematic diagram of another source / drain electrode layer structure provided in an embodiment of this disclosure. Figure 26 This is a schematic diagram of another polysilicon semiconductor layer to source / drain electrode layer stacked structure provided in an embodiment of this disclosure. In this embodiment, the structures of other film layers in the display panel, such as the first active layer, the first gate metal layer, the second active layer, the first auxiliary metal layer, the second auxiliary metal layer, and the reflective electrode layer, are the same as those described above and can be understood with reference to the explanation above. They will not be repeated below.

[0143] In some embodiments, the display panel 10 includes a substrate 01, a first metal layer MC, a second metal layer M2, and a third metal layer MG. The second metal layer MG is located on the side of the first metal layer MC away from the substrate 01, and the third metal layer MG is located between the first metal layer MC and the second metal layer M2.

[0144] For example, such as Figure 5 The substrate 01 may include a base 010 and a buffer layer 011; the first metal layer MC may be a capacitor metal layer 016, the second metal layer M2 may be a source / drain electrode layer 022, and the third metal layer MG may be a second gate metal layer 020.

[0145] The first metal layer MC includes a first sub-reset signal line VREF11, meaning the capacitor metal layer 016 may include the first sub-reset signal line VREF11; the third metal layer MG includes a first sub-bias signal line DVH1, meaning the second gate metal layer 020 may include the first sub-bias signal line DVH1; the second metal layer M2 includes a second sub-reset signal line VREF12 and a second sub-bias signal line DVH2, meaning the source / drain electrode layer 022 may include the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2; and the second sub-reset signal line VREF12 and the second sub-bias signal line DVH2 are insulated from each other to transmit the first reset signal and the bias voltage signal, respectively.

[0146] Specifically, the portions of the bias signal line DVH and the first reset signal line VREF1 extending along the first direction X can be respectively disposed in the second gate metal layer 020 and the capacitor metal layer 016, while the portions of the bias signal line DVH and the first reset signal line VREF1 extending along the second direction Y are disposed in the source and drain electrode layers 022. By disposing of different portions of the bias signal line DVH and the first reset signal line VREF1 in three different metal layers, the signal coupling effect between the bias signal line DVH and the first reset signal line VREF1 can be reduced, thereby improving the display effect.

[0147] In some embodiments, Figure 27 For along Figure 26 A schematic diagram of the cross-sectional structure of C3C4. (Combined with...) Figure 26 and Figure 27 Along the direction perpendicular to the plane of the substrate (i.e., the thickness direction Z of the display panel 10), the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 at least partially overlap.

[0148] This configuration helps to reduce the planar area occupied by the first sub-reset signal line VREF11 and the first sub-bias signal line DVH1 in the display panel 10, which helps to increase the spatial density of the signal lines, improve the pixel density, and thus improve the display effect.

[0149] In some embodiments, such as Figure 22 , Figure 25 and Figure 26 As shown, the second sub-reset signal line VREF12 includes a plurality of first sub-segments VF122 extending along the second direction Y and arranged along the second direction Y; the first sub-segments VF122 are connected to the first sub-reset signal line VREF11, and the first sub-segments VF122 in this document may include a connecting portion connected to the first sub-reset signal line VREF11.

[0150] The pixel driving circuit 20 occupies space in Figure 25 The image is shown in dashed boxes, where dashed lines along the first direction X and the second direction Y intersect to define the dashed boxes, and each dashed box can represent the space occupied by a pixel driving circuit 20.

[0151] The first sub-reset signal line VREF11 can be continuous along the first direction X, and the second sub-reset signal line VREF12 can be disconnected along the second direction Y and connected to the first sub-reset signal line VREF11. The first sub-reset signal line VREF11 can be disposed between two adjacent rows of pixel driving circuits 20 along the first direction X. The second sub-reset signal line VREF12 includes a plurality of first sub-segments VF122 discrete in the second direction Y, each first sub-segment VF122 being connected to at least one first sub-reset signal line VREF11 overlapping with it in the thickness direction of the display panel. For example, Figure 28 For along Figure 22 A schematic diagram of the cross-sectional structure of D1D2. (Combined with...) Figure 22 and Figure 28 The first sub-segment VF122 is connected to the first sub-reset signal line VREF11 via a via.

[0152] In some embodiments, such as Figure 22 , Figure 25 and Figure 26 As shown, the second sub-bias signal line DVH2 includes a plurality of second sub-segments DVH22 extending along the second direction Y and arranged along the second direction Y. The second sub-segments DVH22 cross at least one pixel driving circuit 20 along the second direction Y. The second sub-segments DVH22 are connected to the first sub-bias signal line DVH1. The second sub-segment DVH22 in this document includes a connection portion that connects to the first sub-reset signal line VREF11.

[0153] The first sub-bias signal line DVH1 can be continuous along the first direction X, and the second sub-bias signal line DVH2 can be disconnected along the second direction Y and connected to the first sub-bias signal line DVH1. The first sub-bias signal line DVH1 can be disposed between two adjacent rows of pixel driving circuits 20 along the first direction X, which can cover the dashed line in the figure. The second sub-bias signal line DVH2 includes a plurality of second sub-segments DVH22 discrete in the second direction Y, and each second sub-segment DVH22 is connected to at least one first sub-bias signal line DVH1 that overlaps with it in the thickness direction of the display panel. For example, Figure 29 For along Figure 22 A schematic diagram of the cross-sectional structure of E1E2. (Combined with...) Figure 22 and Figure 29 The second sub-segment DVH22 is connected to the first sub-bias signal line DVH1 via a via.

[0154] In some embodiments, such as Figure 22 , Figure 25 and Figure 26 As shown, along the second direction Y, the first sub-segment VF122 and the second sub-segment DVH22 are alternately set.

[0155] Along the second direction Y, the first sub-segment VF122 and the second sub-segment DVH22 can be alternated in a certain number; for example, a single first sub-segment VF122 and a single second sub-segment DVH22 can be arranged alternately in a ratio of 1:1; or, two first sub-segments VF122 and a single second sub-segment DVH22 can be arranged alternately in a ratio of 2:1; or, they can be arranged alternately in other ratios, which are not limited here.

[0156] This configuration helps improve the wiring uniformity of the first sub-segment VF122 and the wiring uniformity of the second sub-segment DVH22, thereby improving the distribution consistency of the first reset signal and bias voltage signal within the display panel and enhancing the display effect.

[0157] In some embodiments, continue to refer to Figure 25 Along the second direction Y, the length W1 of the first sub-segment VF122 is equal to or greater than the length W0 of the pixel driving circuit 20.

[0158] This configuration facilitates the electrical connection between the first sub-segment VF122 and the first sub-reset signal line VREF11.

[0159] The length W0 of the pixel driving circuit 20 can be the distance between the two dashed lines used to define the pixel driving circuit 20. The length of the first sub-segment VF122 can be understood as the straight-line length of the first sub-segment VF122 along the second direction Y, or as the total length of the first sub-segment VF122 including signal line bends. By setting the length of the first sub-segment VF122 to be equal to or greater than the length W0 of the pixel driving circuit 20, it is beneficial to increase the total length of the first reset signal line VREF1, increase the overall size of the signal line, reduce resistance, thereby reducing signal coupling interference and improving the display effect.

[0160] In some embodiments, continue to refer to Figure 25 The length W2 of the second sub-segment DVH22 is equal to or greater than the length W0 of the pixel driving circuit 20.

[0161] This configuration facilitates the electrical connection between the second sub-segment DVH22 and the first sub-bias signal line DVH1.

[0162] The length W0 of the pixel driving circuit 20 can be the distance between the two dashed lines used to define the pixel driving circuit 20. The length of the second sub-segment DVH22 can be understood as the straight-line length of the second sub-segment DVH22 along the second direction Y, or as the total length of the second sub-segment DVH22 including signal line bends. By setting the length of the second sub-segment DVH22 to be equal to or greater than the length W0 of the pixel driving circuit 20, it is beneficial to increase the total length of the bias signal line DVH, increase the overall size of the signal line, reduce resistance, thereby reducing signal coupling interference and improving the display effect.

[0163] It should be noted that, Figure 22 , Figure 25 and Figure 26 The first segment VF122 and the second segment DVH22 are shown only by way of example, and their lengths in the second direction Y are comparable to those of a single pixel driving circuit 20. This is not intended to limit the embodiments of this disclosure. In other embodiments, the lengths of the first segment VF122 and / or the second segment DVH22 in the second direction Y relative to the length of the pixel driving circuit 20 may be 2 times, 3 times, or more, and are not limited herein.

[0164] In some embodiments, continue to refer to Figure 25 and Figure 26 Along the second direction Y, in the same column of pixel driving circuits 20, the number of pixel driving circuits 20 is N30; in the same column of signal lines 30 arranged along the second direction Y, the number of first sub-segment VF122 is N31, and the number of second sub-segment DVH22 is N32; where N30≥N31+N32, and N30, N31 and N32 are all positive integers.

[0165] Specifically, for pixel driving circuits 20 at different positions within the same column of pixel driving circuits 20, a first sub-segment VF122 or a second sub-segment DVH122 can be set; for example, such as Figure 25 or Figure 26 As shown, for adjacent pixel driving circuits 20 in the second direction Y, a first sub-segment VF122 and a second sub-segment DVH22 are respectively set; the first sub-segment VF122 and the second sub-segment DVH22 are set alternately. That is, along the second direction Y, for the same column of pixel driving circuits 20, the first sub-segment VF122 and the second sub-segment DVH22 are set alternately and cyclically, and the lengths of the first sub-segment VF122 and the second sub-segment DVH22 are both equivalent to the length of the pixel driving circuit 20. At this time, N30 = N31 + N32. This setting makes the distribution uniformity of the first sub-segment VF122 and the second sub-segment DVH22 better, which is beneficial to improving signal uniformity and display effect.

[0166] In other embodiments, a portion of the pixel driving circuits 20 within the same column of pixel driving circuits 20 can be reserved. For this portion of pixel driving circuits 20, neither the first sub-segment VF122 nor the second sub-segment DVH22 can be set, but instead, signal lines for transmitting other signals can be laid out; in this case, N30 > N31 + N32. This setting improves the display effect while also meeting the requirement of laying out different functional signal lines within a limited film layer.

[0167] In other embodiments, the first sub-segment VF122 and the second sub-segment DVH22 may be arranged in other ways, which are not limited here.

[0168] In some embodiments, within the source / drain electrode layer, along the second direction Y, a first sub-segment VF122 and a second sub-segment DVH22 are disposed adjacently and respectively connected to a first sub-reset signal line VREF11 located in the capacitor metal layer and a first sub-bias signal line DVH1 located in the second gate metal layer. To avoid signal coupling between the first sub-segment VF122 and the second sub-segment DVH22, the ends of at least one of them can be bent to stagger the two signal lines and maintain a certain distance, thereby reducing signal coupling and improving the display effect.

[0169] In some embodiments, continue to refer to Figure 25 and Figure 26 Along the first direction X, the pixel driving circuits 20 are arranged in an array; the first sub-segment VF122 and the second sub-segment DVH22 are in the same position relative to the corresponding pixel driving circuits 20.

[0170] For example, the position of the pixel driving circuit 20 can be marked by the position of the first connection part K3, the position of the via H1 on the second plate Cst2 of the storage capacitor Cst, etc.; relative to the pixel driving circuit 20, the first sub-segment VF122 and the second sub-segment DVH22 are both bent toward the same side away from the first connection part K3 (or via H1) in the first direction X, and occupy the same spatial position.

[0171] This configuration ensures good routing regularity for the first sub-segment VF122 and the second sub-segment DVH22, which helps reduce the difficulty of wiring.

[0172] In some embodiments, continue to refer to Figure 25 and Figure 26 Along the first direction X, the first sub-segment VF122 and the second sub-segment DVH22 are arranged alternately.

[0173] Along the first direction X, the first sub-segment VF122 and the second sub-segment DVH22 can be alternated in a certain number; for example, a single first sub-segment VF122 and a single second sub-segment DVH22 can be arranged alternately in sequence with a quantity ratio of 1:1; or, two first sub-segments VF122 and a single second sub-segment DVH22 can be arranged alternately in sequence with a quantity ratio of 2:1; or, they can be arranged alternately according to other quantity ratios, which are not limited here.

[0174] This configuration helps improve the wiring uniformity of the first sub-segment VF122 and the wiring uniformity of the second sub-segment DVH22, thereby improving the distribution consistency of the first reset signal and bias voltage signal within the display panel and enhancing the display effect.

[0175] In some embodiments, in the same metal layer, for all pixel driving circuits 20 in the same row of pixel driving circuits 20, a first sub-segment VF122 or a second sub-segment DVH122 can be set to make full use of the metal layer wiring, improve film layer utilization and wiring uniformity.

[0176] In other embodiments, a portion of the pixel driving circuits 20 within the same row of pixel driving circuits 20 may be reserved. For this portion of the pixel driving circuits 20, neither the first sub-segment VF122 nor the second sub-segment DVH22 may be provided; instead, it may be used to lay signal lines for transmitting other signals. This arrangement improves the display effect while also meeting the requirement of laying different functional signal lines within a limited film layer.

[0177] For example, at least one column of pixel driving circuits 20 is spaced apart between the pixel driving circuit 20 corresponding to the first sub-segment VF122 adjacent along the first direction X and the pixel driving circuit 20 corresponding to the second sub-segment DVH22.

[0178] For example, in three adjacent pixel driving circuits 20 along the first direction X, the first sub-segment VF122 and the second sub-segment DVH22 correspond to the first and last pixel driving circuits 20, respectively, while the middle pixel driving circuit 20 does not correspond to either the first sub-segment VF122 or the second sub-segment DVH22; or, in three adjacent pixel driving circuits 20 along the first direction X, the middle pixel driving circuit 20 corresponds to either the first sub-segment VF122 or the second sub-segment DVH22, while the first and last pixel driving circuits 20 do not correspond to either the first sub-segment VF122 or the second sub-segment DVH22. This allows a single column of pixel driving circuits 20 to be spaced apart from the pixel driving circuits 20 corresponding to the first sub-segment VF122 and the second sub-segment DVH22 along the first direction X. In other embodiments, the pixel driving circuit 20 corresponding to the first sub-segment VF122 and the pixel driving circuit 20 corresponding to the second sub-segment DVH22 may be spaced apart by two, three or more columns of pixel driving circuits 20, which is not limited here.

[0179] In this embodiment of the present disclosure, the first sub-segment VF122 and the second sub-segment DVH22 are both located in the source-drain electrode layer. The above arrangement makes the distance between the first sub-segment VF122 and the second sub-segment DVH22 located in the source-drain electrode layer larger in the first direction X, thereby reducing the signal interference between them. This is beneficial for the precise control of the first reset signal and bias voltage signal related to the display screen, and helps to improve the display effect.

[0180] In some embodiments, continue to refer to Figure 25 and Figure 26 The second metal layer, namely the source and drain electrode layer, may also include a second reset signal line VREF2, and the second reset signal line VREF2 extends along the second direction Y.

[0181] This configuration ensures that all signal lines laid in the second metal layer extend along the second direction Y, reducing the difficulty of laying signal lines in the metal layer. At the same time, the second metal layer includes the first sub-segment VF122, the second sub-segment DVH22, and the second reset signal line VREF2, instead of setting up a separate metal layer for each type of signal line. This improves the wiring utilization rate and wiring uniformity of the second metal layer, which is beneficial to improving the uniformity and stability of the signal.

[0182] For example, Figure 30 For along Figure 22 The cross-sectional structural diagram of C1C2 shows the film structure of the second reset signal line VREF2 at the via location. (Refer to...) Figure 30 and combined Figure 10The second reset signal line VREF2, located in the source-drain electrode layer, is connected to the first electrode p51 of the second reset transistor T5, located in the oxide semiconductor layer 018, through a via.

[0183] In other embodiments, the second reset signal line VREF2 may also be located in at least one of the first metal layer (i.e., the capacitor metal layer) and the third metal layer (i.e., the second gate metal layer), and extend along the first direction X, which is not limited here.

[0184] In some embodiments, continue to refer to Figure 25 and Figure 26 At least one second reset signal line VREF2 is spaced between the first sub-segment VF122 and the second sub-segment DVH22 adjacent along the first direction X.

[0185] For example, a second reset signal line VREF2 may be spaced between the first sub-segment VF122 and the second sub-segment DVH22 adjacent along the first direction X; in other embodiments, two or more second reset signal lines VREF2 may be spaced between the first sub-segment VF122 and the second sub-segment DVH22 adjacent along the first direction X, or other signal lines may be spaced, which is not limited here.

[0186] This configuration helps to balance the second reset signal line VREF2, the first reset signal line VREF1, and the bias signal line DVH in the entire display panel, thereby improving the overall stability of the second reset signal, the first reset signal, and the bias voltage signal, and enhancing the display effect of the display panel.

[0187] In some embodiments, continue to refer to Figure 25 and Figure 26 In the same row of pixel driving circuits 20, the number of pixel driving circuits 20 is N40; in the same row of signal lines arranged along the first direction X, the number of first sub-segment VF122 is N41, the number of second sub-segment DVH22 is N42, and the number of second reset signal lines VREF2 is N43; where N40≥N41+N42+N43, and N40, N41, N42 and N43 are all positive integers.

[0188] Specifically, for pixel driving circuits 20 at different positions in the same row of pixel driving circuits 20, a first sub-segment VF122, a second sub-segment DVH22, or a second reset signal line VREF2 can be set. For example, along the first direction X, for two adjacent pixel driving circuits 20, a second reset signal line VREF2 and a first sub-segment VF122 can be set respectively; or a second reset signal line VREF2 and a second sub-segment DVH22 can be set respectively.

[0189] For example, such as Figure 25 or Figure 26As shown, N40 = N41 + N42 + N43. Specifically, for a row of pixel driving circuits 20 arranged along the first direction X, the second reset signal line VREF2, the first sub-segment VF122, the second reset signal line VREF2, and the second sub-segment DVH22 can be arranged alternately and cyclically. The signal line corresponding to the first pixel driving circuit 20 can be the second reset signal line VREF2, the first sub-segment VF122, or the second sub-segment DVH22, which is not limited here.

[0190] For example, such as Figure 25 or Figure 26 As shown, in odd-numbered columns, along the second direction Y, the first sub-segment VF122 and the second sub-segment DVH22 are alternately arranged at intervals. In even-numbered columns, the second reset signal line VREF2 extends continuously along the second direction. Furthermore, in the same row, the first sub-segment VF122 and the second sub-segment DVH22 are alternately arranged at intervals, and the second reset signal line VREF2 is positioned between adjacent first sub-segments VF122 and second sub-segments DVH22. Alternatively, in even-numbered columns, along the second direction Y, the first sub-segment VF122 and the second sub-segment DVH22 are alternately arranged at intervals. In odd-numbered columns, the second reset signal line VREF2 extends continuously along the second direction. Furthermore, in the same row, the first sub-segment VF122 and the second sub-segment DVH22 are alternately arranged at intervals, and the second reset signal line VREF2 is positioned between adjacent first sub-segments VF122 and second sub-segments DVH22.

[0191] For example, the second reset signal line VREF2 is only disposed in the source-drain electrode layer, while the bias signal line DVH and the first reset signal line VREF1 are disposed in other metal layers besides the source-drain electrode layer. By setting the ratio of the number of the second reset signal line VREF2, the first sub-segment VF122 and the second sub-segment DVH22 relative to the pixel driving circuit 20, the number of second reset signal lines VREF2 in the same row is greater than the number of first sub-segments VF122, and the number of second reset signal lines VREF2 in the same row is greater than the number of second sub-segments DVH22. This helps to balance the placement space of the second reset signal line VREF2, the first reset signal line VREF1 and the bias signal line DVH in the entire display panel, so that their resistances are all small, thereby reducing coupling interference, improving the stability of the second reset signal, the first reset signal and the bias voltage signal, and improving the display effect of the display panel.

[0192] In other embodiments, a portion of the pixel driving circuits 20 within the same row of pixel driving circuits 20 can be reserved. For this portion of the pixel driving circuits 20, neither the first sub-segment VF122 nor the second sub-segment DVH22 nor the second reset signal line VREF2 can be set. Instead, it can be used to lay signal lines for transmitting other signals. In this case, N40 > N41 + N42 + N43. This setting improves the display effect while also meeting the requirement of laying different functional signal lines within a limited film layer.

[0193] In some embodiments, continue to refer to Figure 25 and Figure 26 The pixel driving circuit 20 also includes a first connection portion K3, which connects the gate of the second reset transistor T5 and the gate of the driving transistor T3. Along the first direction X, the first sub-segment VF122 and the second sub-segment DVH22 are both located on the first side of the first connection portion K3, and the second reset signal line VREF2 is located on the second side of the first connection portion K3. The first side and the second side are different sides of the first connection portion K3. This facilitates the symmetrical design of signal lines in the same metal layer, i.e., the source and drain electrode layer, reducing the difficulty of signal line routing.

[0194] For example, with Figure 25 Taking the orientation shown as an example, the first sub-segment VF122 and the second sub-segment DVH22 are both located on the right side of the first connecting part K3, and the second reset signal line VREF2 is located on the left side of the first connecting part K3.

[0195] In other embodiments, the first sub-segment VF122, the second sub-segment DVH22, and the second reset signal line VREF2 may be routed in other spatial relative positions, which are not limited here.

[0196] In some embodiments, continue to refer to Figure 22 The display panel 10 also includes a plurality of sub-pixels P11, which include a first color sub-pixel P111, a second color sub-pixel P112, and a third color sub-pixel P113.

[0197] The sub-pixel P11 may include a pixel driving circuit 20 and a light-emitting element 200. Different colored sub-pixels P11 can be distinguished based on the different emitted colors of the light from different light-emitting elements 200. Specifically, the light-emitting element 200 may include an anode, a light-emitting material layer 029, and a cathode; the light-emitting element 200 may emit different colors of light based on the different properties of the light-emitting material layer 029.

[0198] For example, the first color, the second color, and the third color are all different, so that the display panel 10 can present display effects based on different color combinations.

[0199] In some embodiments, the first color sub-pixel P111, the second color sub-pixel P112, and the third color sub-pixel P113 are each one of the following: red sub-pixel R, green sub-pixel G, and blue sub-pixel B, and are all different. With this configuration, the display panel 10 can achieve full-color display.

[0200] For example, the first color sub-pixel P111 can be a red sub-pixel R, the second color sub-pixel P112 can be a blue sub-pixel B, and the third color sub-pixel P113 can be a green sub-pixel G. Figure 22 The arrangement and shape of subpixels are exemplarily indicated by the arrangement and shape of the anode.

[0201] In other embodiments, the first color, the second color, and the third color may be other colors, which are not limited here.

[0202] For example, continue to refer to Figure 22 Multiple first-color sub-pixels P111 and second-color sub-pixels P112 form a first virtual quadrilateral. First-color sub-pixels P111 are located at the first vertex of the first virtual quadrilateral, and the center of second-color sub-pixels P112 is located at the second vertex of the first virtual quadrilateral. The first and second vertices alternate and are spaced apart. A third-color sub-pixel P113 is located inside the first virtual quadrilateral. Multiple third-color sub-pixels P113 form a second virtual quadrilateral. The centers of the multiple third-color sub-pixels P113 are located at the vertices of the second virtual quadrilateral, and either first-color sub-pixels P111 or second-color sub-pixels P112 are located inside the second virtual quadrilateral. This windmill arrangement achieves good display effects while being highly energy-efficient.

[0203] In this configuration, the second reset signal line VREF2 overlaps with the pixel driving circuit 20 of the third color sub-pixel P113; the first sub-segment VF122 and the second sub-segment DVH22 overlap with the pixel driving circuit 20 of the first color sub-pixel P111 and the pixel driving circuit 20 of the second color sub-pixel P112, respectively, and are different from each other. For example, the first sub-segment VF122 overlaps with the pixel driving circuit 20 of the first color sub-pixel P111, and the second sub-segment DVH22 overlaps with the pixel driving circuit of the second color sub-pixel P112; or, the first sub-segment VF122 overlaps with the pixel driving circuit of the second color sub-pixel P112, and the second sub-segment DVH22 overlaps with the pixel driving circuit of the first color sub-pixel P111.

[0204] For example, the second reset signal line VREF2 overlaps with the pixel driving circuit 20 of the green sub-pixel G, and the first sub-segment VF122 and the second sub-segment DVH22 overlap with the pixel driving circuit 20 of the red sub-pixel R and the pixel driving circuit 20 of the blue sub-pixel B, respectively, and are different from each other; specifically, the first sub-segment VF122 overlaps with the pixel driving circuit 20 of the red sub-pixel R, and the second sub-segment DVH22 overlaps with the pixel driving circuit 20 of the blue sub-pixel B, or the first sub-segment VF122 overlaps with the pixel driving circuit 20 of the blue sub-pixel B, and the second sub-segment DVH22 overlaps with the pixel driving circuit 20 of the red sub-pixel R.

[0205] In this embodiment, the third color sub-pixel P113 (e.g., green sub-pixel G) can be arranged in a solid color column along the second direction Y; the first color sub-pixel P111 and the second color sub-pixel P112 (e.g., red sub-pixel R and blue sub-pixel B) can be arranged in a mixed color column along the second direction Y at intervals. Correspondingly, the continuously extending second reset signal line VREF2 can overlap with the pixel driving circuit 20 of the solid color column sub-pixel P11; the interval-arranged and segmented first sub-segment VF122 and second sub-segment DVH22 can overlap with the pixel driving circuit 20 of the mixed color column sub-pixel P11, and the first sub-segment VF122 and the second sub-segment DVH22 overlap with the pixel driving circuit 20 of sub-pixels P11 of different colors, respectively. With this configuration, the signal lines can be set according to the arrangement rules of the sub-pixels, reducing the difficulty of laying the signal lines.

[0206] In other embodiments, the correspondence between signal line layout and sub-pixel arrangement may be other relationships, which are not limited here.

[0207] In this embodiment of the disclosure, Figure 5 , Figure 6 and Figure 22 The display panel shown is an LTPO combined with a FIAA display panel, as detailed below.

[0208] In some embodiments, Figure 31 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure. (Refer to...) Figure 31 The display panel 10 includes a display area AA and a non-display area NA that at least partially surrounds the display area AA; the non-display area NA includes a fan-out area A1 located on one side of the display area AA along the second direction Y, so as to... Figure 31 Taking the shown orientation as an example, the fan-out area A1 is located below the display area AA; the display area AA includes a first display area AA1 and a second display area AA2, and the second display area AA2 is located along the first direction X on at least one side of the first display area AA1. Figure 31Taking the orientation shown as an example, the second display area AA2 is located to the left and right of the first display area AA1. In other embodiments, the second display area AA2 may also be located to the left or right of the first display area AA1, which is not limited here.

[0209] The display area AA is used to display the image and may include an array of sub-pixels. Each sub-pixel includes a pixel driving circuit and a light-emitting element to achieve active light emission control, thereby realizing image display. The non-display area NA at least partially surrounds the display area AA. For example, the non-display area NA may be located within at least a portion of the space on at least one side of the display area AA, used for routing peripheral circuits and wiring to transmit display signals such as driving signals and power signals to the display area AA. The non-display area NA is not used to display the image and can also be called the bezel area. The smaller its proportion in the planar area of ​​the display panel 10, the higher the proportion of the display area AA, and the easier it is to achieve a narrow bezel full-screen display.

[0210] The fan-out area A1 includes multiple fan-out traces S0. The first display area AA1 and the second display area AA2 both include multiple data lines DL extending along the second direction Y and arranged along the first direction X. The data lines DL are connected to the fan-out traces S0. The data lines DL of the second display area AA2 are connected to the fan-out traces S0 through connecting traces L0. The connecting traces L0 are located in the display area AA and include a first connecting segment L1 extending along the first direction X and a second connecting segment L2 extending along the second direction Y. The first connecting segment L1 is electrically connected to the data lines DL in the second display area AA2, and the second connecting segment L2 is electrically connected to the fan-out traces S0.

[0211] Among them, with Figure 31 Taking the structure shown as an example, the first display area AA1 can be located in the middle area of ​​the display panel 10, and the second display area AA2 is located on both sides of the first display area AA1. Thus, the display panel 10 can be designed symmetrically from left to right, reducing the difficulty of signal line laying.

[0212] In this design, the data line DL in the first display area AA1 is directly electrically connected to the fan-out traces S0 distributed in the fan-out area A1; the data line DL in the second display area AA2 is electrically connected to the fan-out traces S0 in the fan-out area A1 through a first connecting segment L1 extending along the first direction X and a second connecting segment L2 extending along the second direction Y in the connecting trace L0. This eliminates the need to lay fan-out traces near the lower left and / or lower right bezels of the display panel 10, thus providing more space for compressing the bezels of the display panel 10 and the display device. This facilitates a narrow bezel design for the display panel 10 and the display device, and is beneficial for achieving a full-screen display.

[0213] In some embodiments, the display area AA further includes an auxiliary line 11; the auxiliary line 11 includes at least one of a first auxiliary line 111 extending along a first direction X and a second auxiliary line 112 extending along a second direction Y; the first auxiliary line 111 is disposed on the same layer as the first connecting line segment L1 and is insulated from the first connecting line segment L1 and the second connecting line segment L2; the second auxiliary line 112 is disposed on the same layer as the second connecting line segment L2 and is insulated from the first connecting line segment L1 and the second connecting line segment L2.

[0214] The auxiliary power line 11 is located within the display area AA to compensate for uneven wiring within the display area AA, thereby improving the uniformity of wiring within the display area AA.

[0215] The auxiliary line 11 and the connecting line L0 can be at least partially set in the same layer and electrically insulated, so as to make full use of the wiring in the membrane layer and improve the uniformity of the wiring in the membrane layer by setting the auxiliary line 11 in at least part of the membrane layer where the connecting line L0 is located.

[0216] The auxiliary lines 11 may include a first auxiliary line 111 and a second auxiliary line 112 whose extension directions intersect. The first auxiliary line 111 is disposed in the same layer as the first connecting line segment L1 and can both extend along the first direction X. Electrical insulation between the two can be achieved by setting a gap between the lines. The first auxiliary line 111 is also electrically insulated from the second connecting line segment L2. The second auxiliary line 112 is disposed in the same layer as the second connecting line segment L2 and can both extend along the second direction Y. Electrical insulation between the two can be achieved by setting a gap between the lines. The second auxiliary line 112 is also insulated from the first connecting line segment L1. By setting the first auxiliary line 111 in the film layer where the first connecting line segment L1 is located, and / or setting the second auxiliary line 112 in the film layer where the second connecting line segment L2 is located, it is beneficial to improve the uniformity of the wiring density in the film layers where the first connecting line segment L1 and / or the second connecting line segment L2 are located. This is beneficial to improve the display non-uniformity that may be caused by uneven wiring density and to improve the display uniformity of the display panel 10.

[0217] It should be noted that, Figure 31 The connection relationship between the data line DL, fan-out line S0, connection line L0 and auxiliary line 11 included on the display panel is only illustrated and exemplified above. The number of data lines DL, fan-out line S0, connection line L0 and auxiliary line 11 actually included on the display panel 10 is not limited.

[0218] What is understandable is that Figure 31 The structure of the display panel 10, including the lower bezel side, is shown only by way of example. The structure of the upper bezel side can be any structure known to those skilled in the art, and will not be described in detail or limited herein.

[0219] In some embodiments, the auxiliary line 11 may be floating; or the auxiliary line 11 may be used as a power signal line for transmitting power signals. Exemplarily, the auxiliary line 11 may be connected to a first power line PVDD for transmitting a first power signal; and / or the auxiliary line 11 may be connected to a second power line PVEE for transmitting a second power signal. This can balance the voltage drop at different locations in the display panel, which is beneficial for improving display uniformity, but is not limited herein.

[0220] In some embodiments, Figure 32 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure. Figure 33 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure. (Refer to...) Figure 32 or Figure 33 The non-display area NA also includes a power bus 12; auxiliary lines 11 are connected to the power bus 12 and can be used to transmit corresponding power signals. For example, the power bus 12 may be located in the reflective electrode layer.

[0221] For example, such as Figure 32 As shown, within the non-display area NA, the power bus 12 can be a block-shaped or linear integral structure; or, as... Figure 33 As shown, within the non-display area NA, the power bus 12 may include a first bus 121 and a second bus 122 that are spaced apart and electrically connected; wherein, there is a cutout area between the first bus 121 and the second bus 122, which is used to overlap with the pixel definition layer to reduce the overlap area between the reflective electrode layer and the pixel definition layer within the non-display area NA, thereby significantly reducing the ability of electrostatic discharge generated by the pixel definition layer to be conducted downward along the overlap portion, thereby reducing the generation of dark spots, improving the display effect and product yield.

[0222] In some embodiments, the first connecting segment L1 in each connecting trace L0 is disposed in the same layer as the first auxiliary line 111 in each auxiliary line 11, and the extension direction of the first auxiliary line 111 is the same as the extension direction of the first connecting segment L1; the second connecting segment L2 in each connecting trace L0 is disposed in the same layer as the second auxiliary line 112 in the auxiliary line 11, and the extension direction of the second auxiliary line 112 is the same as the extension direction of the second connecting segment L2; this is beneficial to improving the uniformity of the trace density of the film layer where the first connecting segment L1 and the second connecting segment L2 are located, thereby helping to improve the display non-uniformity that may be caused by uneven trace density, and thus improving the display uniformity of the display panel.

[0223] Meanwhile, the first connecting line segment L1 in all connecting lines L0 and the first auxiliary line 111 in all auxiliary lines 11 are set on the same layer, and the second connecting line segment L2 in all connecting lines L0 and the second auxiliary line 112 in all auxiliary lines 11 are set on another layer. The first connecting line segment L1 and the first auxiliary line 111 extending along the first direction X are set in one of the two film layers, and the second connecting line segment L2 and the second auxiliary line 112 extending along the second direction Y are set in the other film layer. The extension direction of the lines in a single film layer is consistent, which simplifies the patterned graphics in a single film layer, reduces the process difficulty, and helps to improve the yield.

[0224] In some embodiments, the display panel further includes a substrate, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, wherein the second metal layer is located on the side of the first metal layer away from the substrate, the third metal layer is located between the first metal layer and the second metal layer, the fourth metal layer is located on the side of the second metal layer away from the first metal layer, and the fifth metal layer is located on the side of the fourth metal layer away from the second metal layer.

[0225] For example, combined Figures 5-30 The first metal layer can be a capacitor metal layer, the second metal layer can be a source / drain electrode layer, the third metal layer can be a second gate metal layer, the fourth metal layer can be a first auxiliary metal layer, and the fifth metal layer can be a second auxiliary metal layer.

[0226] The first metal layer and the second metal layer include bias signal lines; or the second metal layer and the third metal layer include bias signal lines; the fourth metal layer includes a first auxiliary line and a first connecting line segment; and the fifth metal layer includes a second auxiliary line and a second connecting line segment.

[0227] That is, the bias signal lines can be distributed in the first and second metal layers, or in the second and third metal layers. The first and second auxiliary lines in the auxiliary lines can be distributed in the fourth and fifth metal layers, and the first and second connecting segments in the connecting traces can be distributed in the fourth and fifth metal layers.

[0228] For example, in conjunction with the above, the first auxiliary metal layer is used to lay signal lines along the first direction X, and the second auxiliary metal layer is used to lay signal lines along the second direction Y; and both the fourth metal layer and the fifth metal layer are provided with connecting parts / transition parts to realize electrical connections between different signal lines and / or different circuit devices.

[0229] Specifically, such as Figure 14 The first auxiliary metal layer shown may include a first connecting line segment L1 extending along the first direction X, a first auxiliary line L1, and connecting portions, each of which is shown as Z31, Z32, Z33, Z34, and Z35 respectively; as Figure 15 The second auxiliary metal layer shown may include a second connecting line segment L2 extending along the second direction Y, a second auxiliary line 112, and connecting portions, each of which is shown as Z41, Z42, and Z43, respectively. In some embodiments, data lines DL may also be arranged in the second auxiliary metal layer and / or the first auxiliary metal layer, which is not limited herein.

[0230] The connecting part Z31 and the connecting part Z41 overlap at least partially and are electrically connected through a via to realize the electrical connection between the first connecting line segment L1 and the second connecting line segment L2; the connecting part Z32 and the connecting part Z42 overlap at least partially and are electrically connected through a via to realize the electrical connection between the first auxiliary line 111 and the second auxiliary line 112.

[0231] in, Figure 14 The connecting part Z34 and Figure 15 The connecting portion Z43 in the middle is used as a pad metal, which can at least partially overlap and electrically connect with the transition portion K1 located in the source and drain electrode layer to realize the electrical connection between the transistor (e.g., the light-emitting control transistor T6) and the anode.

[0232] Auxiliary line 11 can be used to transmit the first power signal. At this time, Figure 14 The connecting part Z33 is used to connect the first power line located in other film layers (such as capacitor metal layers); the connecting part Z35 is used to connect downward through the via to the first electrode of the power writing transistor T1.

[0233] In some embodiments, the display area AA further includes at least one of a first power line PVDD and a data line DL; the first power line PVDD is connected to the gate of the driving transistor T3; at least one of the fourth metal layer and the fifth metal layer includes the first power line PVDD, and the first power line PVDD is electrically insulated from the connecting trace L0.

[0234] In some embodiments, the fifth metal layer includes a data line DL.

[0235] In this embodiment of the disclosure, in addition to the auxiliary line 11 and the connecting trace L0, the fourth metal layer and the fifth metal layer may also be provided with at least one of the first power line PVDD and the data line DL. For example, the auxiliary line 11 can be used as the first power line PVDD. Figure 15 The diagram shows the data lines DL routed within the fifth metal layer. This allows for full utilization of both the fourth and fifth metal layers and improves trace uniformity.

[0236] In other embodiments, other signal lines may be arranged in the fourth metal layer and / or the fifth metal layer, which are not limited here.

[0237] In some embodiments, Figure 34This is a cross-sectional structural schematic diagram of another display panel provided in an embodiment of this disclosure. (Refer to...) Figure 34 The pixel driving circuit 20 may include multiple transistors such as oxide transistors and low-temperature polysilicon transistors.

[0238] For example, combined Figure 6 or Figure 22 In the pixel driving circuit 20, the compensation transistor T4 and the second reset transistor T5 can be IGZO transistors to reduce leakage current; the driving transistor T3, the bias transistor T8, the first reset transistor T7, the power writing transistor T1, the data writing transistor T2 and the light-emitting control transistor T6 can be LTPS transistors.

[0239] In other embodiments, the structure of the pixel driving circuit 20 and the type of transistor therein may be other combinations, which are not limited here.

[0240] Based on the above embodiments, this disclosure also provides a display device.

[0241] For example, Figure 35 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 35 As shown, the display device 1 may include any of the display panels 10 provided in the above embodiments, and has corresponding beneficial effects. To avoid repetition, these will not be described in detail here.

[0242] For example, the display device includes, but is not limited to, mobile phones, tablets, in-vehicle computers, smart wearable devices with display functions, and other structural components with display functions, which are not described in detail or limited herein.

[0243] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0244] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: Pixel driving circuit and signal lines; The pixel driving circuit includes a driving transistor, a bias transistor, a first reset transistor, and a light-emitting element. The signal line includes a bias signal line and a first reset signal line. The first reset transistor is electrically connected between the first reset signal line and the light-emitting element. The driving transistor includes a gate, a first electrode, and a second electrode; the bias transistor is electrically connected between the bias signal line and at least one of the first electrode and the second electrode of the driving transistor. The bias signal line includes a first sub-bias signal line extending along a first direction and arranged along a second direction, and a second sub-bias signal line extending along the second direction and arranged along the first direction; wherein the first direction intersects the second direction, and the first sub-bias signal line and the second sub-bias signal line are electrically connected. The first reset signal line includes a first sub-reset signal line extending along the first direction and arranged along the second direction, and a second sub-reset signal line extending along the second direction and arranged along the first direction; wherein the first sub-reset signal line and the second sub-reset signal line are electrically connected. The second sub-reset signal line includes a plurality of first sub-segments extending along the second direction and arranged along the second direction, the first sub-segments being electrically connected to the first sub-reset signal line; The second sub-bias signal line includes a plurality of second sub-segments extending along the second direction and arranged along the second direction, and the second sub-segments are electrically connected to the first sub-bias signal line; Along the second direction, the first sub-segment and the second sub-segment are alternately arranged.

2. The display panel according to claim 1, characterized in that, The first sub-bias signal line and the second sub-bias signal line are configured on different layers, and the first sub-reset signal line and the second sub-reset signal line are configured on different layers.

3. The display panel according to claim 2, characterized in that, The first reset signal line and the bias signal line are at least partially on the same layer and are insulated from each other.

4. The display panel according to claim 2, characterized in that, The display panel includes a substrate, a first metal layer, and a second metal layer, wherein the second metal layer is located on the side of the first metal layer away from the substrate; The first metal layer includes the first sub-reset signal line and the first sub-bias signal line, and the first sub-reset signal line is insulated from the first sub-bias signal line; The second metal layer includes the second sub-reset signal line and the second sub-bias signal line, and the second sub-reset signal line is insulated from the second sub-bias signal line.

5. The display panel according to claim 4, characterized in that, The pixel driving circuit array arrangement; The number of the first sub-reset signal lines is N11, the number of the first sub-bias signal lines is N12, and the number of rows of the pixel driving circuit is N10, wherein N11≤N10, N12≤N10, and N10, N11, and N12 are all positive integers.

6. The display panel according to claim 5, characterized in that, Along the second direction, the first sub-reset signal line and the first sub-bias signal line are arranged alternately; and N10≥N11+N12.

7. The display panel according to claim 4, characterized in that, The pixel driving circuit array arrangement; The number of the second sub-reset signal lines is N21, the number of the second sub-bias signal lines is N22, and the number of columns of the pixel driving circuit is N20, wherein N21≤N20, N22≤N20, and N20, N21, and N22 are all positive integers.

8. The display panel according to claim 7, characterized in that, Along the first direction, the second sub-reset signal line and the second sub-bias signal line are arranged alternately; and N20≥N21+N22.

9. The display panel according to claim 4, characterized in that, The pixel driving circuit further includes a second reset transistor, and the signal line further includes a second reset signal line; the second reset transistor is electrically connected between the second reset signal line and the gate of the driving transistor; The second reset signal line includes a portion extending along at least one of the first direction and the second direction.

10. The display panel according to claim 9, characterized in that, The second reset signal line includes a third sub-reset signal line extending along the first direction, and the third sub-reset signal line is disposed on a different layer from the bias signal line.

11. The display panel according to claim 10, characterized in that, Along a direction perpendicular to the plane of the substrate, the third sub-reset signal line at least partially overlaps with the first sub-bias signal line.

12. The display panel according to claim 10, characterized in that, The pixel driving circuit array arrangement; The number of the third sub-reset signal lines is N13, and the number of rows of the pixel driving circuit is N10; where N13≤N10, and N13 and N10 are both positive integers.

13. The display panel according to claim 2, characterized in that, The display panel includes a substrate, a first metal layer, a second metal layer, and a third metal layer, wherein the second metal layer is located on the side of the first metal layer away from the substrate, and the third metal layer is located between the first metal layer and the second metal layer; The first metal layer includes the first sub-reset signal line; The second metal layer includes the second sub-reset signal line and the second sub-bias signal line, and the second sub-reset signal line is insulated from the second sub-bias signal line; The third metal layer includes the first sub-bias signal line.

14. The display panel according to claim 13, characterized in that, Along a direction perpendicular to the plane of the substrate, the first sub-reset signal line and the first sub-bias signal line at least partially overlap.

15. The display panel according to claim 1, characterized in that, Along the second direction, the length of the first sub-segment is equal to or greater than the length of the pixel driving circuit, and the length of the second sub-segment is equal to or greater than the length of the pixel driving circuit.

16. The display panel according to claim 15, characterized in that, Along the second direction, in the same column of pixel driving circuits, the number of pixel driving circuits is N30; in the same column of signal lines arranged along the second direction, the number of the first sub-segment is N31, and the number of the second sub-segment is N32; wherein, N30≥N31+N32, and N30, N31, and N32 are all positive integers.

17. The display panel according to claim 1, characterized in that, Along the first direction, the first sub-segment and the second sub-segment are alternately arranged.

18. The display panel according to claim 13, characterized in that, The pixel driving circuit further includes a second reset transistor, and the signal line further includes a second reset signal line; the second reset transistor is electrically connected between the second reset signal line and the gate of the driving transistor; The second metal layer further includes the second reset signal line, and the second reset signal line extends along the second direction.

19. The display panel according to claim 18, characterized in that, At least one second reset signal line is spaced between the first sub-segment and the second sub-segment adjacent to each other along the first direction.

20. The display panel according to claim 18, characterized in that, In the same row of pixel driving circuits, the number of pixel driving circuits is N40; in the same row of signal lines arranged along the first direction, the number of the first sub-segment is N41, the number of the second sub-segment is N42, and the number of the second reset signal lines is N43; wherein, N40≥N41+N42+N43, and N40, N41, N42, and N43 are all positive integers.

21. The display panel according to claim 18, characterized in that, The pixel driving circuit further includes a first connection portion, which is connected between the second reset transistor and the gate of the driving transistor; Along the first direction, the first sub-segment and the second sub-segment are both located on the first side of the first connection portion, and the second reset signal line is located on the second side of the first connection portion. The first side and the second side are different sides of the first connection portion.

22. The display panel according to claim 18, characterized in that, The display panel further includes a plurality of sub-pixels, the plurality of sub-pixels including a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; The first color sub-pixel and the second color sub-pixel form a first virtual quadrilateral. The center of the first color sub-pixel is located at the first vertex of the first virtual quadrilateral, and the center of the second color sub-pixel is located at the second vertex of the first virtual quadrilateral. The first vertex and the second vertex are alternately set, and the third color sub-pixel is located inside the first virtual quadrilateral. The third color sub-pixel forms a second virtual quadrilateral, the center of the third color sub-pixel is located at the vertex of the second virtual quadrilateral, and the first color sub-pixel or the second color sub-pixel is located inside the second virtual quadrilateral; Wherein, the sub-pixel further includes the pixel driving circuit; the second reset signal line overlaps with the pixel driving circuit of the third color sub-pixel; the first sub-segment overlaps with the pixel driving circuit of the first color sub-pixel, and the second sub-segment overlaps with the pixel driving circuit of the second color sub-pixel; or, the first sub-segment overlaps with the pixel driving circuit of the second color sub-pixel, and the second sub-segment overlaps with the pixel driving circuit of the first color sub-pixel.

23. The display panel according to claim 22, characterized in that, The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are each one of red, green, and blue sub-pixels, and they are all different.

24. The display panel according to claim 1, characterized in that, The display panel includes a display area and a non-display area that at least partially surrounds the display area; The non-display area includes a fan-out area located on one side of the display area along the first direction; the display area includes a first display area and a second display area, wherein the second display area is located on at least one side of the first display area along the first direction. The fan-out area includes multiple fan-out traces, and both the first display area and the second display area include multiple data lines extending along the second direction and arranged along the first direction; The data line is connected to the fan-out routing line; wherein, the data line of the second display area is connected to the fan-out routing line through a connecting routing line; The connection trace is located in the display area and includes a first connection segment extending along the first direction and a second connection segment extending along the second direction. The first connection segment is electrically connected to the data line in the second display area, and the second connection segment is electrically connected to the fan-out trace.

25. The display panel according to claim 24, characterized in that, The pixel driving circuit also includes a light-emitting element, a first reset transistor, and a second reset transistor; The first reset transistor is electrically connected between the driving transistor and the light-emitting element, and the second reset transistor is electrically connected to the gate of the driving transistor; The driving transistor, the bias transistor, and the first reset transistor each comprise a low-temperature polysilicon transistor; The second reset transistor includes an oxide transistor.

26. The display panel according to claim 24, characterized in that, The display area also includes auxiliary lines; The auxiliary line includes at least one of a first auxiliary line extending along the first direction and a second auxiliary line extending along the second direction; The first auxiliary line is disposed on the same layer as the first connecting line segment and is insulated from the first connecting line segment and the second connecting line segment; the second auxiliary line is disposed on the same layer as the second connecting line segment and is insulated from the first connecting line segment and the second connecting line segment.

27. The display panel according to claim 26, characterized in that, The non-display area also includes a power bus; the auxiliary line is connected to the power bus.

28. The display panel according to claim 26, characterized in that, The display panel further includes a substrate, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer. The second metal layer is located on the side of the first metal layer away from the substrate. The third metal layer is located between the first metal layer and the second metal layer. The fourth metal layer is located on the side of the second metal layer away from the first metal layer. The fifth metal layer is located on the side of the fourth metal layer away from the second metal layer. The first metal layer and the second metal layer include the bias signal line; or the second metal layer and the third metal layer include the bias signal line. The fourth metal layer includes the first auxiliary line and the first connecting line segment; The fifth metal layer includes the second auxiliary line and the second connecting line segment.

29. The display panel according to claim 28, characterized in that, The signal line further includes at least one of a first power line and a data line; the first power line is connected to the first terminal of the driving transistor. At least one of the fourth metal layer and the fifth metal layer includes the first power line, and the first power line is electrically insulated from the connection trace.

30. The display panel according to claim 29, characterized in that, The fifth metal layer also includes the data line.

31. A display device, characterized in that, Includes the display panel as described in any one of claims 1-30.

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