Method, system, device and storage medium for testing PCIe module parallel transceiver performance

Abstract

The present invention provides a method, system, device and storage medium for testing the parallel transceiver performance of a PCIe module. The processor adopted supports multiple PCIe interfaces and Ethernet interfaces, and the data of the multiple PCIe modules and Ethernet modules can run simultaneously, and the sending data delay and receiving data delay of each channel of a DPU chip are determined by testing the sending time and receiving time of a message in each channel. It can be seen that the present invention not only has the ability of simultaneously processing data by multiple PCIe modules, but also simplifies the data processing flow, and can test the sending data delay and receiving data delay of a DPU chip without complex data processing flow and processing method, thereby greatly improving the data processing rate, which is completely different from a traditional X86 server test system.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and in particular relates to a method, system, device and storage medium for testing the parallel transceiver performance of a PCIe module. Background Art

[0002] The DPU chip is an ultra-high-speed data processing chip with multiple PCIe modules for processing data. Testing the maximum transceiver throughput and latency of data processing supported by the chip is the most important part of chip testing. At present, some test systems on the market for testing DPU chips only have the ability to test one PCIe module; while others have the ability to test multiple PCIe modules, their application in the development of upper-level applications is limited by the complex data processing flow and processing methods of the upper-level applications, resulting in the inability of the test system to test the maximum transceiver throughput and latency parameters of the DPU chip data processing.

[0003] The traditional X86 server test system used to test the maximum transceiver throughput and latency of DPU chip data processing has the ability to test multiple PCIe modules and can test the transceiver throughput and latency parameters of various APP applications. However, due to the complex data processing flow and processing methods of the X86 server system, the system cannot test the maximum transceiver throughput and latency parameters of DPU chip data processing, which are the most important part of DPU chip testing.

[0004] It can be seen that in order to test the maximum transceiver throughput and delay parameters of DPU chip data processing, a test system needs to be redesigned. It not only needs to have the ability to test multiple PCIe modules at the same time, but also needs to have the ability to test the maximum transceiver throughput and delay of data processing. Summary of the invention

[0005] To solve the above problems, the present invention provides a method, system, device, and storage medium for testing the parallel transceiver performance of a PCIe module, which has the ability to test multiple PCIe modules simultaneously and the ability to test the maximum transceiver data throughput and latency of DPU chip data processing.

[0006] In a first aspect, a method for testing the parallel transceiver performance of a PCIe module, the method comprising: a processor converting N test messages sent by a network tester into PCIe data respectively through N channels, and then outputting the N PCIe data to PCIe interfaces 1-N of a DPU chip to be tested through its own PCIe interfaces 1-N; after the DPU chip processes the N PCIe data, the DPU chip outputs the processed data message to the network tester through its own network interface 1-N; the network tester obtains the difference between the sending time and the receiving time of the same message, and uses the N groups of differences as N total sending delays, and subtracts the sending delays of the N channels of the processor from the N total sending delays to obtain the sending data delays of the N channels of the DPU chip;

[0007] After the DPU chip processes the N test messages sent by the network tester, it outputs the processed PCIe data to the PCIe interfaces 1-N of the processor through its own PCIe interfaces 1-N; the processor converts the N PCIe data into data messages through N channels, and then outputs the N data messages to the network tester through its own network interfaces 1-N; the network tester obtains the difference between the sending time and the receiving time of the same message, and uses the N groups of differences as N total receiving delays, and subtracts the receiving delays of the N channels of the processor from the N total receiving delays to obtain the receiving data delays of the N channels of the DPU chip.

[0008] Furthermore, a method for testing the parallel transceiver performance of a PCIe module further includes:

[0009] The maximum value of the sending data delay of the N channels of the DPU chip is used as the sending data delay of the entire DPU chip; the maximum value of the receiving data delay of the N channels of the DPU chip is used as the receiving data delay of the entire DPU chip.

[0010] Furthermore, a test method for testing the parallel transceiver performance of a PCIe module further includes:

[0011] After obtaining the data transmission delay of N channels of the DPU chip, continuously increase the test message transmission rate of the network tester until an error or packet loss occurs in the data message returned to any channel of the network tester, record the maximum error-free or packet-free transmission rate of the channel of the network tester, and use the transmission rate as the maximum transmission data throughput when the DPU chip processes data on the channel;

[0012] After obtaining the maximum transmit data throughput of all channels of the DPU chip when performing data processing, the sum of the maximum transmit data throughput of all channels is used as the maximum transmit data throughput of the entire DPU chip.

[0013] Furthermore, a test method for testing the parallel transceiver performance of a PCIe module further includes:

[0014] After obtaining the receiving data delay of the N channels of the DPU chip, the test message sending rate of the network tester is continuously increased until an error or packet loss occurs in the data message returned to any channel of the network tester, and the maximum error-free or packet-free sending rate of the channel of the network tester is recorded, and the sending rate is used as the maximum receiving data throughput when the DPU chip processes data on the channel;

[0015] After obtaining the maximum receive data throughput of all channels of the DPU chip when performing data processing, the sum of the maximum receive data throughput of all channels is used as the maximum receive data throughput of the entire DPU chip.

[0016] Furthermore, a method for testing the parallel transceiver performance of a PCIe module, wherein the method for obtaining the transmission delay and the reception delay of N channels of the processor comprises:

[0017] S1: respectively use the N channels of the processor as the first channel to perform the first operation, and at the same time, the numbers of the network interface and the PCIe interface of the processor included in the first channel are both recorded as n, and the port number of the network tester corresponding to the first channel is also recorded as n, wherein the first operation is:

[0018] The PCIe interface n of the first channel of the processor is connected to itself through a cable, and the test message output by the port n of the network tester is simultaneously input into the network interface n of the processor and the oscilloscope channel 1; the test message input into the network interface n of the processor is converted by Ethernet to PCIe protocol, and then output to the PCIe interface n of the processor; the PCIe interface n of the processor returns the converted signal and outputs it to the oscilloscope channel 2; the signal returned by the PCIe interface n of the processor is converted by PCIe to Ethernet protocol, and then output to the network interface n of the processor; the network interface n of the processor outputs the signal converted by PCIe to Ethernet protocol to the port n of the network tester and the oscilloscope channel 3 at the same time;

[0019] S2: The network tester sends a test message through its own port n, and obtains the time t1 when the test message first appears at the network interface n of the processor, the time t2 when it appears at the PCIe interface n of the processor, and the time t3 when it appears for the second time at the network interface n of the processor through an oscilloscope; wherein the difference between t2 and t1 is the conversion time of the first channel processing Ethernet data to PCIe data, and is also the sending delay of the first channel; the difference between t3 and t2 is the conversion time of the first channel processing PCIe data to Ethernet data, and is also the receiving delay of the first channel.

[0020] Furthermore, a method for testing the parallel transceiver performance of a PCIe module further includes:

[0021] After obtaining the sending delay and receiving delay of the N channels of the processor, for each first channel, the sending rate of the network tester test message is continuously increased until an error or packet loss occurs in the data message returned to the network tester port n, and the maximum error-free packet and packet loss-free sending rate of the network tester port n is recorded, and this rate is used as the maximum throughput of the first channel data processing of the processor; at the same time, after obtaining the maximum throughput of all channels of the processor for data processing, the sum of the maximum throughput of all channels is used as the maximum throughput of the entire processor.

[0022] In a second aspect, a system for testing the parallel transceiver performance of a PCIe module includes a processor and a network tester;

[0023] The processor converts N test messages sent by the network tester into PCIe data through N channels, and then outputs the N PCIe data to PCIe interfaces 1-N of the DPU chip to be tested through its own PCIe interfaces 1-N;

[0024] After the DPU chip has processed N PCIe data, it outputs the processed data packets to the network tester through its own network interfaces 1 to N;

[0025] The network tester obtains the difference between the sending time and the receiving time of the same message, and uses N groups of differences as N total sending delays, and subtracts the sending delays of the N channels of the processor from the N total sending delays to obtain the sending data delays of the N channels of the DPU chip;

[0026] After the DPU chip processes the N test messages sent by the network tester, it outputs the processed PCIe data to the PCIe interfaces 1 to N of the processor through its own PCIe interfaces 1 to N;

[0027] The processor converts N PCIe data into data messages through N channels, and then outputs the N data messages to the network tester through its own network interfaces 1 to N;

[0028] The network tester obtains the difference between the sending time and the receiving time of the same message, and uses N groups of differences as N total receiving delays, subtracts the receiving delay of N channels of the processor from the N total receiving delays, and obtains the receiving data delay of N channels of the DPU chip.

[0029] Furthermore, in a system for testing the parallel transceiver performance of a PCIe module, the transmission data delay of the entire DPU chip is the maximum value of the transmission data delay of each channel of the DPU chip; the reception data delay of the entire DPU chip is the maximum value of the reception data delay of each channel of the DPU chip.

[0030] In a third aspect, a device for testing the parallel receiving and transmitting performance of a PCIe module is provided, the device comprising: a host computer and a memory for storing a computer program that can be run on the host computer; wherein, when the host computer is used to run the computer program, the steps of the method described in the first aspect are executed.

[0031] In a fourth aspect, a computer-readable storage medium stores a computer program, which implements the steps of the method in the first aspect when executed by a host computer.

[0032] Beneficial effects:

[0033] 1. The present invention provides a method for testing the parallel transceiver performance of a PCIe module. The processor used supports multiple PCIe interfaces and Ethernet interfaces, and the data of multiple PCIe modules and Ethernet modules can run simultaneously, and the sending data delay and receiving data delay of each channel of a DPU chip are determined by testing the sending time and receiving time of messages in each channel. It can be seen that the present invention not only has the ability to process data simultaneously with multiple PCIe modules, but also simplifies the data processing flow, and does not require complex data processing flows and processing methods to test the sending data delay and receiving data delay of a DPU chip, thereby greatly improving the data processing rate, which is completely different from the traditional X86 server test system.

[0034] 2. The present invention provides a method for testing the parallel transceiver performance of a PCIe module by continuously increasing the test message sending rate of a network tester until an error or packet loss occurs in the data message returned to any channel of the network tester, thereby testing the maximum transceiver data throughput and delay capabilities of each channel of the DPU chip; that is, the present invention can test the maximum transceiver data throughput and delay parameters of the DPU chip data processing without the need for complex data processing procedures and processing methods.

[0035] 3. The present invention provides a method for testing the parallel receiving and transmitting performance of a PCIe module. The processor used does not need to perform complex data calculations and modifications, but only performs data protocol conversion, which greatly improves the data processing rate.

[0036] 4. The present invention provides a system for testing the parallel receiving and sending performance of PCIe modules. The system not only has the ability to process data of multiple PCIe modules simultaneously, but also simplifies the data processing process. It does not require complicated data processing processes and processing methods to test the sending data delay and receiving data delay of the DPU chip, greatly improving the data processing rate, which is completely different from the traditional X86 server testing system.

[0037] 5. The present invention provides a device for testing the parallel receiving and sending performance of a PCIe module. The device not only has the ability to process data of multiple PCIe modules simultaneously, but also simplifies the data processing process. It does not require a complicated data processing process and processing method to test the sending data delay and receiving data delay of the DPU chip, greatly improving the data processing rate, which is completely different from the traditional X86 server test system.

[0038] 6. The present invention provides a storage medium for testing the parallel receiving and sending performance of PCIe modules. It not only has the ability to process data of multiple PCIe modules simultaneously, but also simplifies the data processing process. It does not require complicated data processing processes and processing methods to test the sending data delay and receiving data delay of the DPU chip, greatly improving the data processing rate, which is completely different from the traditional X86 server test system. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 The schematic diagram of the present invention for testing the parallel transceiver performance of multiple PCIe modules;

[0040] Figure 2 This is a schematic diagram of the transmission delay and reception delay of the test processor of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0042] It should be noted that in order to test multiple PCIe modules at the same time and have the ability to test the maximum data throughput and latency of DPU chip data processing, a high-performance processor is first required. The processor used in the present invention needs to support multiple PCIe interfaces and Ethernet interfaces, and the data of multiple PCIe modules and Ethernet modules can be processed simultaneously; at the same time, the processor of the present invention supports DDR3 memory channels, and mounting 16G memory can realize the data protocol conversion requirements of multiple PCIe modules and Ethernet modules.

[0043] Furthermore, in order to test the maximum data transmission and reception throughput and delay parameters of the DPU chip data processing, the data processing rate of the processor adopted in the present invention is significantly higher than the data processing rate of the DPU chip; therefore, the processor needs to be programmed so that the processor does not need to perform complex data calculations and modifications, but only performs data protocol conversion; since only data protocol conversion is performed on the processor and no data modification is performed, the data processing speed is faster than that of the X86 server system; through actual measurements, a data processing performance of 128G can be achieved, which is better than the processing performance of about 90G of the X86 server; therefore, the test system of the present invention can test the maximum data transmission and reception throughput and delay parameters of the DPU chip data processing.

[0044] Based on this, the present invention provides a method for testing the parallel transceiver performance of a PCIe module, the method comprising: a processor converts N test messages sent by a network tester into PCIe data respectively through N channels, and then outputs the N PCIe data to PCIe interfaces 1-N of a DPU chip to be tested through its own PCIe interfaces 1-N; after the DPU chip processes the N PCIe data, it outputs the processed data message to the network tester through its own network interface 1-N; the network tester obtains the difference between the sending time and the receiving time of the same message, and uses the N groups of differences as N total sending delays, and subtracts the sending delays of the N channels of the processor from the N total sending delays to obtain the sending data delays of the N channels of the DPU chip;

[0045] Furthermore, after obtaining the data transmission delays of the N channels of the DPU chip, the maximum value of the data transmission delays of the N channels of the DPU chip is used as the data transmission delay of the entire DPU chip; at the same time, the test message transmission rate of the network tester is continuously increased until an error or packet loss occurs in the data message returned to any channel of the network tester, and the maximum error-free or packet-free transmission rate of the channel of the network tester is recorded, and the transmission rate is used as the maximum transmission data throughput when the DPU chip performs data processing on the channel;

[0046] After obtaining the maximum data transmission throughput of all channels of the DPU chip when processing data, the sum of the maximum data transmission throughput of all channels is used as the maximum data transmission throughput of the entire DPU chip;

[0047] After the DPU chip processes the N test messages sent by the network tester, it outputs the processed PCIe data to the PCIe interfaces 1 to N of the processor through its own PCIe interfaces 1 to N; the processor converts the N PCIe data into data messages through N channels, and then outputs the N data messages to the network tester through its own network interfaces 1 to N; the network tester obtains the difference between the sending time and the receiving time of the same message, and uses the N groups of differences as the N total receiving delays, and subtracts the receiving delays of the N channels of the processor from the N total receiving delays to obtain the receiving delays of the N channels of the DPU chip;

[0048] Furthermore, after obtaining the receiving data delay of the N channels of the DPU chip, the maximum value of the receiving data delay of the N channels of the DPU chip is used as the receiving data delay of the entire DPU chip; at the same time, the test message sending rate of the network tester is continuously increased until an error or packet loss occurs in the data message returned to any channel of the network tester, and the maximum error-free or packet-free sending rate of the channel of the network tester is recorded, and the sending rate is used as the maximum receiving data throughput when the DPU chip performs data processing on the channel;

[0049] After obtaining the maximum receive data throughput of all channels of the DPU chip when performing data processing, the sum of the maximum receive data throughput of all channels is used as the maximum receive data throughput of the entire DPU chip.

[0050] Specifically, use Figure 1 The test environment shown is used to test the maximum data transmission throughput and latency of the DPU chip data processing.

[0051] First, use a network tester to send a test message through each of the network test ports 1 to N of the network tester, and the test message enters the processor through the processor network interfaces 1 to N.

[0052] After the processor receives the test message, it first stores it in the memory space allocated to the Ethernet module; the processor converts the stored Ethernet data into PCIe data according to the queue order, and the PCIe data after the protocol conversion will be stored in the memory space allocated to the PCIe module; finally, the processor extracts the PCIe data from the memory space to the corresponding PCIe interfaces 1 to N in turn according to the queue relationship for output.

[0053] The PCIe data output by the processor PCIe interface 1~N will directly enter the PCIe interface 1~N of the DPU chip to be tested through the cable, and then the DPU chip processes the received PCIe data. It should be noted that since the DPU belongs to the chip to be tested, the present invention does not elaborate on its internal data processing process and method.

[0054] After the DPU chip processes the received PCIe data, it will output it through the DPU network interface 1~N, and finally return it to the network test port N+1~2N of the network tester; the network tester monitors the sending time and receiving time of the same message, and the time difference calculated is the delay T of each channel of the test system composed of the processor and DPU chip to process the sending data. transmit-delay , after actual testing, T transmit-delay The value is between 7 and 13us.

[0055] For each channel, T transmit-delay The latency includes the processor’s transmission latency and the DPU chip’s transmission latency, so T transmit-delay The delay minus the processor's transmission delay is the maximum transmission data delay of the DPU chip data processing that needs to be tested in the system under test, that is, T dpu-transmit-delay =T transmit-delay -T cpu-transmit-delay , where T cpu-transmit-delay =0.87us; After actual testing, the maximum data transmission delay of DPU chip data processing is T dpu-transmit-delay The value is between 6.13us and 12.13us.

[0056] It should be noted that the maximum data transmission delay value of DPU chip data processing tested by traditional X86 servers is generally between 2 and 5 ms, and there is a significant difference between its delay value and the delay value tested by the test system of the present invention. Therefore, it is inaccurate to use X86 servers to test the delay value. The main reason is that X86 servers are aimed at multi-device interconnection and intelligent applications, and the data processing process and method are much more complicated, so the single data processing performance is not as good as a simple processor system.

[0057] For each channel, the maximum data transmission delay T of the DPU chip data processing is tested. dpu-transmit-delay After that, the network tester continues to increase the test message sending rate on the current channel until the message returned to the network tester on this channel has an error or packet loss, and records the maximum error-free packet and packet loss sending rate of the network tester on the current channel, which is the maximum data throughput S of the DPU chip for data processing on the current channel. dpu-transmit , due to S dpu-transmit The value will be less than the maximum data processing throughput S of the processor cpu Therefore, the throughput tested by the network tester in the current channel is the maximum data throughput of the DPU chip in the current channel. dpu-transmit The value is between 98Gbps and 125Gbps.

[0058] It should be noted that the maximum data throughput of DPU chip data processing tested by traditional X86 servers is generally 75 to 92 Gbps, which is significantly different from the throughput tested by the system of the present invention.

[0059] Furthermore, using Figure 1 The test environment shown is used to test the maximum receiving data throughput and latency of the DPU chip data processing.

[0060] First, use a network tester to send a test message through each of the network test ports N+1~2N of the network tester. The test message enters the DPU chip through the DPU chip network interfaces 1~N.

[0061] After the DPU chip receives the test message, the DPU chip processes the received Ethernet data; it should be noted that the DPU belongs to the chip to be tested, and the present invention does not elaborate on its internal data processing process and method; after the DPU chip processes the received Ethernet data, it will output it through the DPU chip PCIe interface 1~N.

[0062] The PCIe data output by the PCIe interfaces 1 to N of the DPU chip will directly enter the PCIe interfaces 1 to N of the processor through the cable.

[0063] After the processor receives the PCIe data, it is first stored in the memory space allocated to the PCIe module; the processor converts the stored PCIe data into Ethernet data according to the queue order, and the Ethernet data after the protocol conversion will be stored in the memory space allocated to the Ethernet module; finally, the processor extracts the Ethernet data from the memory space to the corresponding network interface 1~N output in sequence according to the queue relationship.

[0064] The Ethernet data output from the processor network interface 1 to N is finally returned to the network test port 1 to N of the network tester. The network tester monitors the sending time and receiving time of the same message, and the time difference calculated is the delay T of each channel of the test system in processing the received data. receiver-delay , after actual testing, T receiver-delay The value is between 9 and 21us.

[0065] For each channel, T receiver-delay The delay includes the processor's receiving delay and the DPU chip's receiving delay. Therefore, the receiver-delay delay minus the processor's receiving delay is the maximum receiving data delay of the DPU chip data processing that needs to be tested in the system under test, that is, T dpu-receiver-delay =T receiver-delay -T cpu-receiver-delay , where T cpu-receiver-delay=1.23us; After actual testing, the maximum receiving data delay of DPU chip data processing is T dpu-receiver-delay The value is between 7.77us and 19.77us.

[0066] It should be noted that the maximum receiving data delay value of DPU chip data processing tested by the traditional X86 server is generally between 2 and 5 ms, and there is a significant difference between the delay value and the delay value tested by the test system of the present invention. Therefore, it is inaccurate to use the X86 server to test the delay value. The main reason is that the X86 server is aimed at multi-device interconnection and intelligent applications, and the data processing process and method are much more complicated, so the single data processing performance is not as good as the simple processor system.

[0067] For each channel, the maximum receiving data delay T after testing the DPU chip data processing dpu-receiver-delay After that, the network tester continues to increase the test message sending rate on the current channel until the message returned to the network tester on this channel has an error or packet loss, and records the maximum error-free packet and packet loss-free sending rate of the network tester on the current channel, which is the maximum receiving data throughput S of the DPU chip for data processing on the current channel. dpu-receiver , due to S dpu-receiver The value will be less than the maximum data processing throughput S of the processor cpu Therefore, the throughput tested by the network tester in the current channel is the maximum receiving data throughput of the DPU chip in the current channel. dpu-receiver The value is between 90Gbps and 110Gbps.

[0068] It should be noted that the maximum receiving data throughput value of DPU chip data processing tested by traditional X86 servers is generally 75 to 92 Gbps, which is also significantly different from the throughput tested by the system of the present invention.

[0069] It can be seen that the test system of the present invention can not only realize the simultaneous testing of multi-channel PCIe of the DPU chip, but also can test the maximum processing throughput and delay parameters of the DPU chip sending and receiving data. The tested parameter values ​​are obviously better than the values ​​tested by the X86 server, as shown in Table 1.

[0070] Table 1

[0071] Test parameter values Test system of the present invention X86 Server System Data processing maximum send data throughput 98Gbps~125Gbps 75~92Gbps Data processing maximum data sending delay 6.13us~12.13us 2~5ms Data processing maximum receiving data throughput 90Gbps~110Gbps 75~92Gbps Data processing maximum receiving data delay 7.77us~19.77us 2~5ms

[0072] Furthermore, as mentioned above, when calculating the maximum data transmission delay T of the data processing of each channel of the DPU chip, dpu-transmit-delay The maximum receiving data delay T of each channel of the DPU chip dpu-receiver-delayWhen the processor sends the delay T of each channel, it is necessary to know cpu-transmit-delay and receiving delay T cpu-receiver-delay Therefore, the transmission delay T of each channel of the processor used in the present invention is described in detail below. cpu-transmit-delay and receiving delay T cpu-receiver-delay .

[0073] Pre-test preparation:

[0074] ① The processor driver needs to be installed. The driver includes the interface driver, Ethernet and PCIe data conversion program, and other processor running programs;

[0075] ② After the processor has installed the interface driver, the processor can identify various PCIe devices, various Ethernet devices and DDR3 devices;

[0076] ③After the processor installs the Ethernet and PCIe data conversion program, each channel of PCIe data and Ethernet data can be converted to each other and output from the corresponding port;

[0077] ④The network tester can send and receive Ethernet data normally;

[0078] ⑤The DPU chip under test can normally send and receive multiple PCIe data and Ethernet data;

[0079] ⑥The processor can normally send and receive multiple PCIe data and Ethernet data;

[0080] ⑦ Test the throughput and latency of each PCIe data to Ethernet data of the processor respectively. Take the throughput and latency test of the first PCIe data to Ethernet data as an example. The other channels can refer to this example:

[0081] S1: Build Figure 2 The test environment shown:

[0082] The PCIe interface 1 of the current channel 1 of the processor is connected to itself through a cable, and the test message output by the port 1 of the network tester is simultaneously input to the network interface 1 of the processor and the oscilloscope channel 1; the test message input by the network interface 1 of the processor is converted by Ethernet to PCIe protocol, and then output to the PCIe interface 1 of the processor; the PCIe interface 1 of the processor returns the converted signal and outputs it to the oscilloscope channel 2; the signal returned by the PCIe interface 1 of the processor is converted by PCIe to Ethernet protocol, and then output to the network interface 1 of the processor; the network interface 1 of the processor outputs the signal converted by PCIe to Ethernet protocol to the port 1 of the network tester and the oscilloscope channel 3 at the same time;

[0083] S2: the network tester sends a test message through port 1 of the current channel, and obtains the time t1 when the test message first appears at the network interface 1 of the processor, the time t2 when the test message appears at the PCIe interface 1 of the processor, and the time t3 when the test message second appears at the network interface 1 of the processor through the oscilloscope;

[0084] Among them, the difference between t2 and t1, t2-t1=Tcpu-transmit-delay, is the conversion time of the current channel 1 of the processor to process Ethernet data to PCIe data, and is also the transmission delay of the current channel 1 of the processor. After actual testing, Tcpu-transmit-delay=0.87us; the difference between t3 and t2, t3-t2=Tcpu-receiver-delay, is the conversion time of the current channel 1 of the processor to process PCIe data to Ethernet data, and is also the receiving delay of the current channel 1 of the processor; after actual testing, Tcpu-receiver-delay=1.23us;

[0085] After obtaining the sending delay and receiving delay of N channels of the processor, for each first channel, the sending rate of the network tester test message is continuously increased until an error or packet loss occurs in the data message returned to the network tester port n, and the maximum error-free packet and packet loss-free sending rate of the network tester port n is recorded, and the rate is used as the maximum throughput of the processor's first channel data processing; for example, after actual testing, the maximum throughput of processor channel 1 Scpu = 128Gbps; at the same time, after obtaining the maximum throughput of all channels of the processor for data processing, the sum of the maximum throughput of all channels is used as the maximum throughput of the entire processor.

[0086] Furthermore, the comparative data of the data processing performance of the test system of the present invention is shown in Table 2:

[0087] Table 2

[0088]

[0089] As another implementation, a system for testing the parallel transceiver performance of a PCIe module includes a processor and a network tester;

[0090] The processor converts N test messages sent by the network tester into PCIe data through N channels, and then outputs the N PCIe data to PCIe interfaces 1-N of the DPU chip to be tested through its own PCIe interfaces 1-N;

[0091] After the DPU chip has processed N PCIe data, it outputs the processed data packets to the network tester through its own network interfaces 1 to N;

[0092] The network tester obtains the difference between the sending time and the receiving time of the same message, and uses N groups of differences as N total sending delays, and subtracts the sending delays of the N channels of the processor from the N total sending delays to obtain the sending data delays of the N channels of the DPU chip;

[0093] After the DPU chip processes the N test messages sent by the network tester, it outputs the processed PCIe data to the PCIe interfaces 1 to N of the processor through its own PCIe interfaces 1 to N;

[0094] The processor converts N PCIe data into data messages through N channels, and then outputs the N data messages to the network tester through its own network interfaces 1 to N;

[0095] The network tester obtains the difference between the sending time and the receiving time of the same message, and uses N groups of differences as N total receiving delays, subtracts the receiving delay of N channels of the processor from the N total receiving delays, and obtains the receiving data delay of N channels of the DPU chip.

[0096] As another implementation method, the present invention also provides a device for testing the parallel transceiver performance of a PCIe module, the device comprising: a host computer and a memory for storing a computer program that can be run on the host computer; wherein, when the host computer is used to run the computer program, it executes the various steps of the method for testing the parallel transceiver performance of multiple PCIe modules as described above.

[0097] As another implementation, the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is run by a host computer, the steps of the method for testing the parallel transceiver performance of multiple PCIe modules as described above are executed, which are not described in detail here. The storage medium can be a tangible storage medium, such as an optical disk, a USB flash drive, a floppy disk, a hard disk, etc.

[0098] In summary, the test method, system, device, and storage medium of the present invention have the ability of multiple PCIe modules working simultaneously, and the actual data processing capability is better than the data processing capability of the DPU chip and the data processing capability of the X86 server test system; therefore, the present invention not only solves the problem that multiple PCIe modules of the DPU chip cannot work simultaneously, but also solves the problem that the maximum data throughput and delay parameters of the DPU chip data processing cannot be tested.

[0099] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may certainly make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A method for testing the parallel transceiver performance of a PCIe module, characterized in that: The method comprises: the processor converts the test message sent from the port of the network tester 1 into PCIe format data and sends it to the processor PCIe interface 1, and then sends the data to the DPU chip PCIe interface 1 through the processor PCIe interface 1; the processor converts the test message sent from the port of the network tester 2 into PCIe format data and sends it to the processor PCIe interface 2, and then sends the data to the DPU chip PCIe interface 2 through the processor PCIe interface 2; in this way, the processor converts N test messages sent from the network tester into PCIe data respectively through N channels, and then outputs the N PCIe data to the PCIe interfaces 1~N of the DPU chip to be tested through its own PCIe interfaces 1~N; the DPU chip processes the test message received by the PCIe interface 1 through the PCIe interface 2, and then sends the test message to the DPU chip PCIe interface 2 through the PCIe interface 2. The DPU chip sends the test message received by the PCIe interface 2 through the DPU chip network interface 1, and then sends it to the N+1 port of the network tester; the DPU chip processes the test message received by the PCIe interface 2, sends it through the DPU chip network interface 2, and then sends it to the N+2 port of the network tester; in this way, after the DPU chip processes N PCIe data, it outputs the processed data message to the N+1~2N port of the network tester through its own network interface 1~N; the network tester obtains the difference between the sending time and the receiving time of the same message, and uses the N groups of differences as the N total sending delays, and subtracts the sending delay of the N channels of the processor from the N total sending delays to obtain the sending data delay of the N channels of the DPU chip; the sending delay of the N channels of the processor is the conversion time of the N channels of the processor to process Ethernet data to PCIe data respectively; For the delay in receiving data, the DPU chip network interface 1 processes the test message sent from the network tester's N+1 port, sends it out through the DPU chip PCIe interface 1, and then sends it to the processor PCIe interface 1; the DPU chip network interface 2 processes the test message sent from the network tester's N+2 port, sends it out through the DPU chip PCIe interface 2, and then sends it to the processor PCIe interface 2; in this way, after the DPU chip processes the N test messages sent from the network tester, it outputs the processed PCIe data to the processor's PCIe interface 1~N through its own PCIe interface 1~N; the processor converts the test data received by PCIe interface 1 into a data message and sends it through the processor network interface 1 out, and then sent to the port 1 of the network tester; after the processor converts the test data received by the PCIe interface 2 into a data message, it is sent out through the processor network interface 2, and then sent to the port 2 of the network tester; in this way, the processor converts N PCIe data into data messages through N channels, and then outputs the N data messages to the network tester through its own network interface 1~N; the network tester obtains the difference between the sending time and the receiving time of the same message, and uses the N groups of differences as N total receiving delays, and subtracts the receiving delays of the N channels of the processor from the N total receiving delays to obtain the receiving data delay of the N channels of the DPU chip; the receiving delay of the N channels of the processor is the conversion time of the N channels of the processor processing the PCIe data to Ethernet data respectively.

2. A method for testing the parallel transceiver performance of a PCIe module as claimed in claim 1, characterized in that: Also includes: The maximum value of the data transmission delay of the N channels of the DPU chip is used as the data transmission delay of the entire DPU chip; The maximum value of the receiving data delay of the N channels of the DPU chip is taken as the receiving data delay of the entire DPU chip.

3. A method for testing the parallel transceiver performance of a PCIe module as claimed in claim 1, characterized in that: Also includes: After obtaining the data transmission delay of N channels of the DPU chip, continuously increase the test message transmission rate of the network tester until an error or packet loss occurs in the data message returned to any channel of the network tester, record the maximum error-free or packet-free transmission rate of the channel of the network tester, and use the transmission rate as the maximum transmission data throughput when the DPU chip processes data on the channel; After obtaining the maximum transmit data throughput of all channels of the DPU chip when performing data processing, the sum of the maximum transmit data throughput of all channels is used as the maximum transmit data throughput of the entire DPU chip.

4. A method for testing the parallel transceiver performance of a PCIe module as claimed in claim 1, characterized in that: Also includes: After obtaining the receiving data delay of the N channels of the DPU chip, the test message sending rate of the network tester is continuously increased until an error or packet loss occurs in the data message returned to any channel of the network tester, and the maximum error-free or packet-free sending rate of the channel of the network tester is recorded, and the sending rate is used as the maximum receiving data throughput when the DPU chip processes data on the channel; After obtaining the maximum receive data throughput of all channels of the DPU chip when performing data processing, the sum of the maximum receive data throughput of all channels is used as the maximum receive data throughput of the entire DPU chip.

5. A method for testing the parallel transceiver performance of a PCIe module as claimed in any one of claims 1 to 4, characterized in that: The method for acquiring the transmission delay and the reception delay of N channels of the processor includes: Take the N channels of the processor as the first channel respectively, record the numbers of the network interface and PCIe interface of the processor included in the first channel as n, and record the port number of the network tester corresponding to the first channel as n, and perform the following operations: The PCIe interface n of the first channel of the processor is connected to itself through a cable, and the test message output by the port n of the network tester is simultaneously input into the network interface n of the processor and the oscilloscope channel 1; the test message input into the network interface n of the processor is converted by Ethernet to PCIe protocol, and then output to the PCIe interface n of the processor; the PCIe interface n of the processor returns the converted signal and outputs it to the oscilloscope channel 2; the signal returned by the PCIe interface n of the processor is converted by PCIe to Ethernet protocol, and then output to the network interface n of the processor; the network interface n of the processor outputs the signal converted by PCIe to Ethernet protocol to the port n of the network tester and the oscilloscope channel 3 at the same time; The network tester sends a test message through its own port n, and obtains the time t1 when the test message first appears at the network interface n of the processor, the time t2 when it appears at the PCIe interface n of the processor, and the time t3 when it appears for the second time at the network interface n of the processor through an oscilloscope; wherein the difference between t2 and t1 is the conversion time of the first channel processing Ethernet data to PCIe data, and is also the sending delay of the first channel; the difference between t3 and t2 is the conversion time of the first channel processing PCIe data to Ethernet data, and is also the receiving delay of the first channel.

6. A method for testing the parallel transceiver performance of a PCIe module as claimed in claim 5, characterized in that: Also includes: After obtaining the sending delay and receiving delay of the N channels of the processor, for each first channel, the sending rate of the network tester test message is continuously increased until an error or packet loss occurs in the data message returned to the network tester port n, and the maximum error-free or loss-free sending rate of the network tester port n is recorded, and this rate is used as the maximum throughput of the first channel data processing of the processor; at the same time, after obtaining the maximum throughput of all channels of the processor for data processing, the sum of the maximum throughput of all channels is used as the maximum throughput of the entire processor.

7. A system for testing the parallel transceiver performance of a PCIe module, characterized in that: Includes processor and network testers; The processor converts the test message sent from the network tester 1 port into PCIe format data and sends it to the processor PCIe interface 1, and then sends the data to the DPU chip PCIe interface 1 through the processor PCIe interface 1; The processor converts the test message sent from the port of the network tester 2 into PCIe format data and sends it to the processor PCIe interface 2, and then sends the data to the DPU chip PCIe interface 2 through the processor PCIe interface 2; in this way, the processor converts the N test messages sent from the network tester into PCIe data respectively through N channels, and then outputs the N PCIe data to the PCIe interfaces 1~N of the DPU chip to be tested through its own PCIe interfaces 1~N; The DPU chip processes the test message received by PCIe interface 1, sends it out through DPU chip network interface 1, and then sends it to the N+1 port of the network tester; the DPU chip processes the test message received by PCIe interface 2, sends it out through DPU chip network interface 2, and then sends it to the N+2 port of the network tester; in this way, after the DPU chip processes N PCIe data, it outputs the processed data message to the N+1~2N port of the network tester through its own network interface 1~N; The network tester obtains the difference between the sending time and the receiving time of the same message, and uses N groups of differences as N total sending delays, and subtracts the sending delay of the N channels of the processor from the N total sending delays to obtain the sending data delay of the N channels of the DPU chip; the sending delay of the N channels of the processor is the conversion time of the N channels of the processor processing Ethernet data to PCIe data respectively; For the delay in receiving data, the DPU chip network interface 1 processes the test message sent from the network tester's N+1 port, sends it out through the DPU chip PCIe interface 1, and then sends it to the processor PCIe interface 1; the DPU chip network interface 2 processes the test message sent from the network tester's N+2 port, sends it out through the DPU chip PCIe interface 2, and then sends it to the processor PCIe interface 2; in this way, after the DPU chip processes the N test messages sent from the network tester, it outputs the processed PCIe data to the processor's PCIe interfaces 1~N through its own PCIe interfaces 1~N; After the processor converts the test data received by PCIe interface 1 into a data message, it is sent out through processor network interface 1, and then sent to port 1 of network tester; after the processor converts the test data received by PCIe interface 2 into a data message, it is sent out through processor network interface 2, and then sent to port 2 of network tester; in this way, the processor converts N PCIe data into data messages respectively through N channels, and then outputs the N data messages to the network tester through its own network interfaces 1~N; The network tester obtains the difference between the sending time and the receiving time of the same message, and uses N groups of differences as N total receiving delays. The receiving delays of the N channels of the processor are subtracted from the N total receiving delays to obtain the receiving data delay of the N channels of the DPU chip; the receiving delay of the N channels of the processor is the conversion time of the N channels of the processor to process PCIe data into Ethernet data respectively.

8. A system for testing the parallel transceiver performance of a PCIe module as claimed in claim 7, characterized in that: The transmission data delay of the entire DPU chip is the maximum value of the transmission data delay of each channel of the DPU chip; the reception data delay of the entire DPU chip is the maximum value of the reception data delay of each channel of the DPU chip.

9. A device for testing the parallel transceiver performance of a PCIe module, characterized in that: The device comprises: a host computer and a memory for storing a computer program that can be run on the host computer; wherein, when the host computer is used to run the computer program, the steps of any one of the methods of claims 1 to 6 are executed.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a host computer, the steps of any method described in claims 1 to 6 are implemented.

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