Heterogeneous chip stacking device

Abstract

The present application provides a kind of heterogeneous chip stacking equipment, including substrate bearing structure, limiting substrate structure, first cover plate structure, second cover plate structure and chip bearing structure, limiting substrate structure is detachably arranged on substrate bearing structure, first cover plate structure is detachably arranged above limiting substrate structure, second cover plate structure is detachably arranged on first cover plate structure, chip bearing structure is movably arranged above substrate bearing structure, limiting substrate structure has multiple limiting grooves for accommodating multiple first chips respectively, first cover plate structure is configured to be arranged on multiple first chips and tightly press multiple first chips, and first cover plate structure has multiple first openings for accommodating multiple second chips respectively, second cover plate structure has multiple second openings configured to be communicated with multiple first openings respectively, and second cover plate structure is configured to allow a part of chip bearing structure to be accommodated in any second opening.

Description

Technical Field

[0001] This invention relates to a stacking device, and more particularly to a heterogeneous chip stacking device. Background Technology

[0002] In existing technologies, multiple heterogeneous chips are mostly individually mounted on a circuit board, which makes inefficient use of the layout space on the circuit board. Furthermore, before a chip is to be mounted on the circuit board using flip-chip technology, pre-prepared solder balls are implanted on the circuit board to secure the chip to the circuit board. However, solder balls have a predetermined size limitation; when the chip's pad size or pad spacing is too small, solder balls cannot be used for securing the chip to the circuit board. Summary of the Invention

[0003] The problem to be solved by the present invention is to provide a heterogeneous chip stacking device that addresses the shortcomings of the prior art, so that the multiple first bonding ends of the multiple first protruding pad structures of the first chip can be directly contacted and tightly bonded to each other with the multiple second bonding ends of the multiple second protruding pad structures of the second chip, thereby stacking two heterogeneous chips.

[0004] To address the aforementioned problems, one technical approach employed by this invention is to provide a heterogeneous chip stacking device, comprising:

[0005] A substrate support structure;

[0006] A limiting substrate structure is detachably mounted on the substrate support structure;

[0007] A first cover plate structure is detachably disposed above the limiting base plate structure;

[0008] A second cover structure, the second cover structure being detachably mounted on the first cover structure; and

[0009] A chip carrier structure is movably disposed above the substrate carrier structure;

[0010] The limiting substrate structure has multiple limiting grooves configured to accommodate multiple first chips respectively.

[0011] The first cover structure is configured to be disposed on and press against the plurality of first chips, and the first cover structure has a plurality of first openings configured to accommodate a plurality of second chips respectively.

[0012] The second cover structure has a plurality of second openings configured to communicate with a plurality of first openings respectively, and the second cover structure is configured to allow a portion of the chip carrier structure to be accommodated within any of the second openings;

[0013] The chip carrier structure is configured to pick up the second chip and place the second chip on the corresponding first chip, such that the plurality of first bonding ends of the plurality of first protruding pad structures of the first chip are in direct contact with and tightly bonded to the plurality of second bonding ends of the plurality of second protruding pad structures of the second chip.

[0014] Another technical approach employed in this invention is to provide another heterogeneous chip stacking device, comprising:

[0015] A substrate support structure;

[0016] A limiting substrate structure is detachably mounted on the substrate support structure;

[0017] A first cover plate structure is detachably disposed above the limiting base plate structure;

[0018] A second cover structure, the second cover structure being detachably mounted on the first cover structure; and

[0019] A chip carrier structure is movably disposed above the substrate carrier structure;

[0020] The limiting substrate structure has multiple limiting grooves configured to accommodate multiple first chips respectively.

[0021] The first cover structure is configured to be disposed on and press against the plurality of first chips, and the first cover structure has a plurality of first openings configured to accommodate a plurality of second chips respectively.

[0022] The second cover structure has a plurality of second openings configured to communicate with a plurality of the first openings, and the second cover structure is configured to allow a portion of the chip carrier structure to be accommodated within any of the second openings.

[0023] One of the beneficial effects of the present invention is that the heterogeneous chip stacking device provided by the present invention can stack two heterogeneous chips by means of the following technical solutions: "a limiting substrate structure having a plurality of limiting grooves configured to respectively accommodate a plurality of first chips", "a first cover plate structure configured to be disposed on and press against the plurality of first chips, and the first cover plate structure having a plurality of first openings configured to respectively accommodate a plurality of second chips", and "a second cover plate structure having a plurality of second openings configured to respectively communicate with the plurality of first openings, and the second cover plate structure configured to allow a portion of the chip carrier structure to be accommodated in any of the second openings". For example, the chip carrier structure can be configured to pick up the second chip and place the second chip on the corresponding first chip, such that the plurality of first bonding ends of the plurality of first protruding pad structures of the first chip are in direct contact and tightly bonded to each other with the plurality of second bonding ends of the plurality of second protruding pad structures of the second chip.

[0024] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0025] Figure 1 This is a flowchart of the heterogeneous chip stacking method provided by the present invention.

[0026] Figure 2 This is a three-dimensional schematic diagram of the first chip provided by the present invention.

[0027] Figure 3 This is a top view schematic diagram of the first chip provided by the present invention.

[0028] Figure 4 for Figure 3 An enlarged schematic diagram of part IV.

[0029] Figure 5 This is a side view schematic diagram of the first chip provided by the present invention.

[0030] Figure 6 This is a three-dimensional schematic diagram of the second chip provided by the present invention.

[0031] Figure 7 This is a top view schematic diagram of the second chip provided by the present invention.

[0032] Figure 8 This is a bottom view of the second chip provided by the present invention.

[0033] Figure 9 This is a side view schematic diagram of the second chip provided by the present invention.

[0034] Figure 10 This is a three-dimensional schematic diagram of the heterogeneous chip stacking structure provided by the present invention.

[0035] Figure 11 This is a side view of the heterogeneous chip stacking structure provided by the present invention.

[0036] Figure 12 This is a three-dimensional exploded view of the heterogeneous chip stacking device provided by the present invention.

[0037] Figure 13 This is a three-dimensional schematic diagram of the heterogeneous chip stacking device provided by the present invention.

[0038] Figure 14 This is a three-dimensional schematic diagram of one type of chip carrier structure of the heterogeneous chip stacking device provided by the present invention.

[0039] Figure 15 for Figure 14 An enlarged schematic diagram of the XV portion.

[0040] Figure 16 This is an enlarged schematic diagram of another chip carrier structure of the heterogeneous chip stacking device provided by the present invention.

[0041] Figure 17 for Figure 13 A partial cross-sectional schematic diagram of the XVII-XVII section line.

[0042] Figure 18 for Figure 17 An enlarged schematic diagram of section XVIII.

[0043] Figure 19 This is a schematic diagram of the chip pad surface leveling device provided by the present invention (before the leveling glass substrate moves downward to contact the end of the pad).

[0044] Figure 20 This is a schematic diagram of the chip pad surface leveling device provided by the present invention (when the leveling glass substrate moves downward to contact the end of the pad).

[0045] Figure label:

[0046] P - Heterogeneous chip stack structure; 1 - First chip; 10 - First convex pillar type pad structure; 100 - First bonding end; 1000 - Pad end; 1002 - Upper surface; 11 - Top conductive pad; 12 - Bottom conductive pad; 13 - Conductive through-body; A1 - First alignment mark; 2 - Second chip; 20 - Second convex pillar type pad structure; 200 - Second bonding end; 2000 - Pad end; 2001 - Receiving groove; 2002 - Lower surface; 20A - Convex pillar type substrate; 20B - Convex pillar type conductor; 211 - Light-emitting area; 212 - Outer frame area; 213 - Nozzle contact area; A2 - Second alignment mark; D1 - First diameter; D2 - Second diameter; D3 - Third diameter; H1 - First height; H2 - Second height; H3 - Third height; G1 - First pad spacing; G2 - Second pad spacing; G3 - Chip vertical spacing; F - Insulating filler material; S - Heterogeneous chip stacking equipment; S1 - Substrate support structure; S100 - Vacuum suction hole; S2 - Limiting substrate structure; S200 - Limiting groove; S3 - First cover plate structure; S300 - First opening; S4 - Second cover plate structure; S400 - Second opening; S5 - Chip support structure; S51 - Connecting part; S52 - Rotating part; S53 - Suction nozzle part; S531 - Contact area; S532 - Opening area; SN - Suction nozzle opening; S6 - Machine body structure; M - Chip pad surface leveling equipment; M1 - Signal control module; M2 - Glass support module; M21 - Suction nozzle structure; M22 - Drive structure; M3 - Temperature control module; M4 - Chip support module; M5 - Surface roughness detection module; M6 - Pressure sensing module; GS - Leveling glass substrate. Detailed Implementation

[0047] The following specific embodiments illustrate the implementation of the "heterogeneous chip stacking device" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, it should be stated in advance that the drawings of this invention are for simple illustration only and are not depictions based on actual dimensions. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" used herein may include, depending on the actual situation, any combination of any one or more of the associated listed items.

[0048] First Embodiment

[0049] See Figures 1 to 11As shown, the first embodiment of the present invention provides a heterogeneous chip stacking method, which may include at least: firstly, cooperating with Figure 1 as well as Figures 2 to 5 As shown, a first chip 1 is provided, the first chip 1 having a plurality of first protruding pad structures 10 that gradually form (or grow outward from) the first chip 1 within a first pre-time period, each first protruding pad structure 10 having a first bonding end 100 (step S100); then, in conjunction with Figure 1 as well as Figures 6 to 9 As shown, a second chip 2, different from the first chip 1, is provided (for example, the base materials of the first chip 1 and the second chip 2 are different, or the materials of other parts of the first chip 1 and the second chip 2 are different). The second chip 2 has a plurality of second protruding pillar-shaped solder pad structures 20 that gradually form (or grow outward) from the second chip 2 within a second pre-time period. Each second protruding pillar-shaped solder pad structure 20 has a second bonding end 200 (step S102); then, in conjunction with... Figure 1 , Figure 10 and Figure 11 As shown, a first chip 1 is disposed on a second chip 2 such that the plurality of first bonding ends 100 of the plurality of first protruding pad structures 10 of the first chip 1 are in direct contact with the plurality of second bonding ends 200 of the plurality of second protruding pad structures 20 of the second chip 2, without the need for any other connecting material (or, in another feasible embodiment, a conductive material may be formed between the first bonding ends 100 and the second bonding ends 200, so that the first bonding ends 100 and the second bonding ends 200 may be in indirect contact) (step S104); Next, in conjunction with Figure 1 , Figure 10 and Figure 11 As shown, at least one of a predetermined pressure (e.g., between 500g and 2000g), a predetermined temperature (e.g., between 20°C and 35°C), and a predetermined ultrasonic wave (frequency between 40 and 42 kHz) is applied to ensure that the plurality of first bonding ends 100 of the plurality of first pillar-type pad structures 10 of the first chip 1 are tightly bonded to the plurality of second bonding ends 200 of the plurality of second pillar-type pad structures 20 of the second chip 2 (step S106). It is worth noting that, since the size of the first pillar-type pad structure 10 and the second pillar-type pad structure 20 is very small, the first pillar-type pad structure 10 is not formed by "directly implanting (or directly placing) a pre-prepared solder ball (e.g., a pre-fabricated solder ball or gold ball) into the first chip 1", and the second pillar-type pad structure 20 is not formed by "directly implanting (or directly placing) another pre-prepared solder ball (e.g., a pre-fabricated solder ball or gold ball) into the second chip 2".

[0050] Using this passage as an example, in conjunction with Figure 1 as well as Figures 2 to 5 As shown, in step S100 of providing the first chip 1, a plurality of first protruding pillar-shaped bonding pad structures 10 (e.g., upright cylindrical structures, or upright cylindrical bonding pads) of the first chip 1 can be gradually formed on the first chip 1 within a first predetermined time through sputtering, evaporation, or any other feasible forming method. The first chip 1 can be a silicon (Si)-containing single-photon avalanche diode (SPAD) chip, or any type of semiconductor photodetector, or any type of silicon substrate chip. Furthermore, in conjunction with… Figure 3 and Figure 4 As shown, the plurality of first protrusion-type pad structures 10 of the first chip 1 can be divided into a plurality of series-connected pad regions that are separated from each other (e.g., Figure 4 The multiple series solder pad areas shown are arranged in a straight line and are staggered, and the multiple first protruding pillar-shaped solder pad structures 10 in each series solder pad area can be connected in series with each other through conductive lines (not shown). In addition, in conjunction with Figure 2 and Figure 3 As shown, the first chip 1 includes a plurality of top conductive pads 11 electrically connected to a plurality of series-connected pad regions via conductive lines (not shown), a plurality of bottom conductive pads 12 corresponding to the plurality of top conductive pads 11, and a plurality of conductive through-holes 13 correspondingly connected between the plurality of top conductive pads 11 and the plurality of bottom conductive pads 12, thereby forming a plurality of through-silicon vias (TSVs) formed on the first chip 1. It is worth noting that the first chip 1 provided by the present invention may also omit the use of the plurality of bottom conductive pads 12 and the plurality of conductive through-holes 13, retaining only the plurality of top conductive pads 11 disposed on the first chip 1. Furthermore, in conjunction with… Figure 4 and Figure 5As shown, the first convex-type pad structure 10 has a first diameter D1 whose diameter ranges from 15μm to 30μm (e.g., any positive integer between 15μm and 30μm) and a first height H1 whose height ranges from 10μm to 20μm (e.g., any positive integer between 10μm and 20μm). The surface flatness of the multiple pad ends 1000 of the multiple first convex-type pad structures 10 of the first chip 1 can be no greater than 1μm (e.g., any positive integer less than 1000nm), and the first pad spacing G1 between any two adjacent first convex-type pad structures 10 of the first chip 1 can be between 35μm and 45μm (e.g., any positive integer between 35μm and 45μm). However, the examples given above are only one possible embodiment and are not intended to limit the present invention.

[0051] Using this passage as an example, in conjunction with Figure 1 as well as Figures 6 to 9 As shown, in step S102 of providing the second chip 2, a plurality of second protruding pillar-shaped bonding pad structures 20 of the second chip 2 (e.g., stepped cylindrical structures, or stepped cylindrical bonding pads) can be gradually formed within a receiving groove 2001 of the second chip 2 within a second predetermined time through sputtering, evaporation, or any other feasible forming method. The second chip 2 can be a vertical cavity surface-emitting laser (VCSEL) chip containing gallium arsenide (GaAs), or any type of surface-emitting laser (SEL). Furthermore, in conjunction with… Figure 6 , Figure 7 and Figure 8 As shown, the second chip 2 has a plurality of second protruding pad structures 20 separated from each other by a predetermined distance. The second chip 2 has a light-emitting region 211 larger than the distribution range of the plurality of second protruding pad structures 20, an outer frame region 212 surrounding the light-emitting region 211, and a nozzle contact region 213 located between the light-emitting region 211 and the outer frame region 212. The second protruding pad structures 20 and the light-emitting region 211 of the second chip 2 are respectively disposed on two opposite surfaces of the second chip 2. In addition, in conjunction with Figure 6 , Figure 7 and Figure 9As shown, the receiving groove 2001 of the second chip 2 is recessed from the lower surface 2002 of the second chip 2. Each second pillar-shaped pad structure 20 includes a pillar-shaped base 20A disposed in the receiving groove 2001 and a pillar-shaped conductor 20B disposed on the pillar-shaped base 20A. The top surface (i.e., the pad end 2000) of the pillar-shaped base 20A of each second pillar-shaped pad structure 20 is flush with the lower surface 2002 of the second chip 2. Furthermore, in conjunction with... Figure 7 and Figure 9 As shown, each second convex-type pad structure 20 has a convex-type substrate 20A with a diameter ranging from 25μm to 35μm (e.g., any positive integer between 25μm and 35μm) and a second height H2 with a height ranging from 5μm to 10μm (e.g., any positive integer between 5μm and 10μm). Furthermore, each second convex-type pad structure 20 has a convex-type conductor 20B with a diameter ranging from 15μm to 25μm (e.g., any positive integer between 15μm and 25μm) and a third height H3 with a height ranging from 3μm to 8μm (e.g., any positive integer between 3μm and 8μm). Furthermore, the surface flatness of the multiple pad ends 2000 of the multiple second pillar-shaped pad structures 20 of the second chip 2 may not exceed 1 μm (e.g., any positive integer less than 1000 nm), and the second pad spacing G2 of any two adjacent second pillar-shaped pad structures 20 of the second chip 2 may be between 35 μm and 45 μm (e.g., any positive integer between 35 μm and 45 μm). However, the examples given above are merely one possible embodiment and are not intended to limit the present invention.

[0052] It is worth noting, for example, in conjunction with Figure 2 and Figure 6 As shown, each first chip 1 has two first alignment marks A1 arranged diagonally or arbitrarily on its top end, and each second chip 2 has two second alignment marks A2 arranged diagonally or arbitrarily on its bottom end. Thus, as... Figure 10 As shown, when the first chip 1 is disposed on the second chip 2, the two first alignment marks A1 of the first chip 1 can be adjacent to and correspond to the two second alignment marks A2 of the second chip 2, respectively. That is, the two first alignment marks A1 (cross-shaped and circular) of the first chip 1 can correspond to the two second alignment marks A2 (cross-shaped and circular) of the second chip 2, thereby ensuring that the orientation of the first chip 1 relative to the second chip 2 is correct. Furthermore, in conjunction with… Figure 2 , Figure 6 , Figure 10and Figure 11 As shown, in step S104, where the first chip 1 is disposed on the second chip 2, an insulating filler material F can be configured to fill between the first chip 1 and the second chip 2, thereby increasing the bonding strength after the first chip 1 and the second chip 2 are joined. The insulating filler material can be any type of underfill. Additionally, in conjunction with… Figure 10 and Figure 11 As shown, when the first chip 1 is disposed on the second chip 2, the vertical chip spacing G3 between the lower surface 2002 of the second chip 2 and an upper surface 1002 of the first chip 1 can be between 10 μm and 15 μm (e.g., any positive integer between 10 μm and 15 μm). That is, when the first chip 1 is disposed on the second chip 2, the plurality of first bonding ends 100 of the plurality of first protruding pad structures 10 of the first chip 1 will directly contact and tightly bond with the plurality of second bonding ends 200 of the plurality of second protruding pad structures 20 of the second chip 2, and the bodies of the first chip 1 and the second chip 2 will avoid direct contact due to the barrier of the insulating filler material F, thus the bodies of the first chip 1 and the second chip 2 will be separated by a predetermined vertical distance. However, the above example is only one possible embodiment and is not intended to limit the present invention.

[0053] It is worth noting, for example, in conjunction with Figure 1 , Figure 2 , Figure 6 , Figure 19 and Figure 20 As shown, before step S104 of placing the first chip 1 on the second chip 2, the heterogeneous chip stacking method further includes: using a chip pad surface leveling device M to level the multiple pad ends 1000 of the multiple first pillar-type pad structures 10 of the first chip 1 or the multiple pad ends 2000 of the multiple second pillar-type pad structures 20 of the second chip 2 (that is, to level the multiple pad ends 1000 of the multiple first pillar-type pad structures 10 of the first chip 1 or the multiple pad ends 2000 of the multiple second pillar-type pad structures 20 of the second chip 2). Figure 19 and Figure 20 The first chip 1 is replaced with the second chip 2) and leveled (step S1 or step S2), so that the surface roughness of the plurality of pad ends 1000 of the plurality of first protruding pad structures 10 of the first chip 1 or the surface roughness of the plurality of pad ends 2000 of the plurality of second protruding pad structures 20 of the second chip 2 is not greater than 1 μm (e.g., any positive integer less than 1000 nm). However, the above examples are only one possible embodiment and are not intended to limit the present invention.

[0054] Continuing from the above, for example, in conjunction with Figure 19 and Figure 20As shown, the chip pad surface leveling device M includes a signal control module M1, a glass carrier module M2 electrically connected to the signal control module M1, and a temperature control module M3 electrically connected to the signal control module M1. Furthermore, the glass carrier module M2 can be configured to carry a leveling glass substrate GS (e.g., a glass substrate with a predetermined surface flatness) and move the leveling glass substrate GS to contact a plurality of first pillar-type pad structures 10 of the first chip 1 or a plurality of second pillar-type pad structures 20 of the second chip 2. Additionally, the temperature control module M3 can be configured to apply a predetermined temperature (e.g., a heating temperature between 20°C and 35°C) to the plurality of first pillar-type pad structures 10 of the first chip 1 or the plurality of second pillar-type pad structures 20 of the second chip 2 (i.e., to... Figure 19 and Figure 20 The first chip 1 is replaced with the second chip 2), and the glass carrier module M2 can be configured to apply a predetermined pressure (e.g., a downward pressure between 100g and 1500g) to a plurality of first protruding pad structures 10 of the first chip 1 or a plurality of second protruding pad structures 20 of the second chip 2 through a flattening glass substrate GS (i.e., to replace the first chip 1 ... Figure 19 and Figure 20 The first chip 1 is replaced with the second chip 2, thereby ensuring that the surface roughness of the plurality of pad ends 1000 of the plurality of first protruding pad structures 10 of the first chip 1 or the surface roughness of the plurality of pad ends 2000 of the plurality of second protruding pad structures 20 of the second chip 2 is not greater than 1 μm through surface leveling processing by the chip pad surface leveling equipment M. However, the above-described example is only one possible embodiment and is not intended to limit the present invention.

[0055] Second Embodiment

[0056] See Figures 2 to 11 As shown, the second embodiment of the present invention provides a heterogeneous chip stacking structure P, which includes at least a first chip 1 and a second chip 2. (In conjunction with...) Figures 2 to 5 As shown, the first chip 1 has a plurality of first protruding pad structures 10 that gradually form outward from the first chip 1 within a first pre-time period, and each first protruding pad structure 10 has a first bonding end 100. Figures 6 to 9 As shown, the second chip 2 has a plurality of second protruding pad structures 20 that gradually form outward from the second chip 2 within a second pre-time period, and each second protruding pad structure 20 has a second bonding end 200. Figure 10 and Figure 11As shown, a first chip 1 is configured to be disposed on a second chip 2, such that the plurality of first bonding ends 100 of the plurality of first protruding pad structures 10 of the first chip 1 are in direct contact with and tightly bonded to the plurality of second bonding ends 200 of the plurality of second protruding pad structures 20 of the second chip 2. It is worth noting that, because the sizes of the first protruding pad structures 10 and the second protruding pad structures 20 are very small, the first protruding pad structure 10 cannot be formed by "directly implanting (or directly placing) a pre-prepared solder ball (e.g., a pre-fabricated solder ball or gold ball) into the first chip 1", and the second protruding pad structure 20 cannot be formed by "directly implanting (or directly placing) another pre-prepared solder ball (e.g., a pre-fabricated solder ball or gold ball) into the second chip 2".

[0057] For example, the heterogeneous chip stacking structure P provided in the second embodiment of the present invention can be fabricated using the heterogeneous chip stacking method provided in the first embodiment of the present invention. Furthermore, the first chip 1 and the second chip 2 of the heterogeneous chip stacking structure P provided in the second embodiment of the present invention may be equivalent to or different from the first chip 1 and the second chip 2 used in the heterogeneous chip stacking method provided in the first embodiment of the present invention. However, the examples given above are merely feasible embodiments and are not intended to limit the present invention.

[0058] Third Embodiment

[0059] See Figures 12 to 18 As shown, the third embodiment of the present invention provides a heterogeneous chip stacking device S, which includes a substrate support structure S1, a limiting substrate structure S2, a first cover plate structure S3, a second cover plate structure S4, and a chip support structure S5 (or multiple chip support structures S5).

[0060] Furthermore, in coordination Figure 12 , Figure 13 and Figure 18As shown, the limiting substrate structure S2 is detachably disposed on the substrate support structure S1, the first cover plate structure S3 is detachably disposed above the limiting substrate structure S2, the second cover plate structure S4 is detachably disposed on the first cover plate structure S3, and the chip support structure S5 is movably disposed above the substrate support structure S1. Furthermore, the limiting substrate structure S2 has multiple limiting grooves S200 configured to respectively accommodate multiple first chips 1, and the multiple first chips 1 can be equivalent to the multiple first chips 1 provided in the first embodiment or the second embodiment. In addition, the first cover plate structure S3 can be configured to be disposed on the multiple first chips 1 and press against the multiple first chips 1 (but will not contact the limiting substrate structure S2), and the first cover plate structure S3 has multiple first openings S300 configured to respectively accommodate multiple second chips 2. In addition, the second cover structure S4 has a plurality of second openings S400 configured to communicate with the plurality of first openings S300 respectively, and the second cover structure S4 can be configured to allow a portion of the chip carrier structure S5 to be accommodated within any of the second openings S400.

[0061] For example, coordination Figure 12 , Figure 17 and Figure 18 As shown, the substrate support structure S1 has a plurality of vacuum suction holes S100 configured for positioning and limiting the substrate structure S2, thereby allowing the limiting substrate structure S2 to be detachably mounted on the substrate support structure S1 through the suction of the plurality of vacuum suction holes S100. Furthermore, in conjunction with Figure 2 and Figure 18 As shown, the two first alignment marks A1 of the first chip 1 can be disposed on an outer surrounding area of ​​the first chip 1, and a portion of the outer surrounding area of ​​each first chip 1 is not covered by the first cover structure S3 (that is, the two first alignment marks A1 of each first chip 1 can be exposed by the corresponding first opening S300 and the corresponding second opening S400). Furthermore, in conjunction with... Figure 13 and Figure 18 As shown, the limiting substrate structure S2 and the first cover plate structure S3 can cooperate with each other through magnetic attraction, so that multiple first chips 1 can be pressed tightly between the limiting substrate structure S2 and the first cover plate structure S3 by a fixed or adjustable magnetic force. Furthermore, multiple magnetic structures (not shown) for providing magnetic force can be disposed on the surface or inside of at least one of the limiting substrate structure S2 and the first cover plate structure S3. Additionally, in cooperation with… Figure 13 and Figure 18 As shown, the second opening S400 of the second cover structure S4 is larger than the first opening S300 of the first cover structure S3, so that a portion of the chip carrier structure S5 can be accommodated unobstructed within either second opening S400. It is worth noting that, in conjunction with... Figure 13 and Figure 17 As shown, the substrate support structure S1, the limiting substrate structure S2, the first cover plate structure S3, and the second cover plate structure S4 can be sequentially stacked on a machine body structure S6 of the heterogeneous chip stacking device S, and the chip support structure S5 is detachably connected to the machine body structure S6. However, the above example is only one possible embodiment and is not intended to limit the present invention.

[0062] For example, coordination Figure 17 and Figure 18 As shown, the chip carrier structure S5 can be configured to pick up the second chip 2 and place the second chip 2 on the corresponding first chip 1, so that the plurality of first bonding ends 100 of the plurality of first protruding pad structures 10 of the first chip 1 can directly contact and tightly bond with the plurality of second bonding ends 200 of the plurality of second protruding pad structures 20 of the second chip 2. Furthermore, in conjunction with... Figure 14 , Figure 15 Figure 16 and Figure 17 As shown, the chip carrier structure S5 includes a connecting portion S51 detachably connected to the machine body structure S6, a rotating portion S52 connected to the connecting portion S51, and a suction nozzle portion S53 disposed on the rotating portion S52. The connecting portion S51 of the chip carrier structure S5 has an external thread configured to connect to the machine body structure S6 for mutual engagement with an internal thread provided by the machine body structure S6. The connecting portion S51 and the rotating portion S52 of the chip carrier structure S5 can cooperate to form a hexagonal bolt, and the rotating portion S52 of the chip carrier structure S5 can be configured to be rotated by the operation of a locking tool. The suction nozzle portion S53 of the chip carrier structure S5 has a contact area S531 (or a protruding polished area to avoid damaging the second chip 2 due to friction) and an opening area S532 surrounded by the contact area S531, and the opening area S532 can be a suction nozzle opening SN (e.g., gas connected to a gas guiding channel) Figure 15 (as shown) or two suction nozzle openings SN (such as) Figure 16 (As shown). However, the examples given above are merely one possible embodiment and are not intended to limit the invention.

[0063] For example, coordination Figure 8 , Figure 15 and Figure 18As shown, when the opening area S532 is a suction opening SN, the contact area S531 of the suction part S53 of the chip support structure S5 can be configured to contact the suction contact area 213 of the second chip 2, and the opening area S532 of the suction part S53 of the chip support structure S5 can be configured to contact the entire light-emitting area 211 of the second chip 2 (that is, the vertical projection of the light-emitting area 211 of the second chip 2 and the vertical projection of the receiving groove 2001 will fall completely on the opening area S532 of the suction part S53). It is worth noting that the contact area S531 of the nozzle portion S53 of the chip carrier structure S5 can be configured to be separated from the light-emitting area 211 and the outer frame area 212 of the second chip 2 by a predetermined distance between 40μm and 60μm (e.g., any positive integer between 40μm and 60μm). (That is, the vertical projection of the contact area S531 of the nozzle portion S53 will not fall on the light-emitting area 211 and the receiving groove 2001 of the second chip 2 at all.) However, the example given above is only one possible embodiment and is not intended to limit the present invention.

[0064] For example, coordination Figure 8 and Figure 16 As shown, when the opening area S532 consists of two nozzle openings SN, the contact area S531 of the nozzle portion S53 of the chip carrier structure S5 can be configured to contact the nozzle contact area 213 and the light-emitting area 211 of the second chip 2, and the opening area S532 of the nozzle portion S53 of the chip carrier structure S5 can be configured to be separated from the light-emitting area 211 of the second chip 2 by a predetermined distance between 15μm and 35μm (for example, any positive integer between 15μm and 35μm). (That is, the vertical projection of the light-emitting area 211 of the second chip 2 and the vertical projection of the receiving groove 2001 will not fall on the opening area S532 of the nozzle portion S53.) It is worth noting that the contact area S531 of the nozzle portion S53 of the chip carrier structure S5 can be configured to be separated from the outer frame area 212 of the second chip 2 by a predetermined distance between 30μm and 50μm (e.g., any positive integer between 30μm and 50μm), and the vertical projection of the light-emitting area 211 of the second chip 2 and the vertical projection of the receiving groove 2001 will fall completely on the contact area S531 of the nozzle portion S53 of the chip carrier structure S5. However, the example given above is only one possible embodiment and is not intended to limit the present invention.

[0065] Fourth embodiment

[0066] See Figure 19 and Figure 20As shown, the fourth embodiment of the present invention provides a chip pad surface leveling device M, which includes a signal control module M1 (e.g., may include any processor such as CPU, GPU, MCU, DSP, MPU, etc.), a glass carrier module M2, and a temperature control module M3. More specifically, the glass carrier module M2 is electrically connected to the signal control module M1, and the temperature control module M3 is electrically connected to the signal control module M1. Additionally, the glass carrier module M2 can be configured to support a leveling glass substrate GS (e.g., ...). Figure 18 As shown, for example, a glass substrate with a predetermined surface flatness), and the glass carrier module M2 can be configured to move the flattening glass substrate GS to contact a plurality of first protruding pad structures 10 of a first chip 1 (e.g., Figure 19 (as shown) or multiple second bump-type solder pad structures 20 that contact a second chip 2 (e.g., can be...) Figure 19 The first chip 1 shown is replaced with the first chip 2, so that the surface roughness of the multiple pad ends 1000 of the multiple first protruding pad structures 10 of the first chip 1 or the surface roughness of the multiple pad ends 2000 of the multiple second protruding pad structures 20 of the second chip 2 can be processed by the surface leveling of the chip pad surface leveling equipment M and is not greater than 1 μm (e.g., any positive integer less than 1000 nm).

[0067] For example, such as Figure 20 As shown, when the glass carrier module M2 is configured to move the leveling glass substrate GS to contact the plurality of first protruding pad structures 10 of the first chip 1 or to contact the plurality of second protruding pad structures 20 of a second chip 2 (for example, it can be used to...) Figure 20(The first chip 1 shown is replaced by the first chip 2). The temperature control module M3 can be configured to directly apply a predetermined temperature to the plurality of first protruding pad structures 10 of the first chip 1 or the plurality of second protruding pad structures 20 of the second chip 2. The glass carrier module M2 can be configured to apply a predetermined pressure to the plurality of first protruding pad structures 10 of the first chip 1 or the plurality of second protruding pad structures 20 of the second chip 2 through the leveling glass substrate GS. This ensures that the surface roughness of the plurality of pad ends 1000 of the plurality of first protruding pad structures 10 of the first chip 1 or the plurality of pad ends 2000 of the plurality of second protruding pad structures 20 of the second chip 2 is not greater than 1 μm through the surface leveling process of the chip pad surface leveling device M. It is worth noting that, depending on different usage requirements, the glass carrier module M2 is configured to indirectly apply a predetermined pressure to the plurality of first protruding pad structures 10 of the first chip 1 or the plurality of second protruding pad structures 20 of the second chip 2, which can be between 100g and 1000g (e.g., any positive integer between 100g and 1000g), and the temperature control module M3 is configured to directly apply a predetermined temperature to the plurality of first protruding pad structures 10 of the first chip 1 or the plurality of second protruding pad structures 20 of the second chip 2, which can be between 250°C and 290°C (e.g., any positive integer between 250°C and 290°C). However, the examples given above are merely one possible embodiment and are not intended to limit the present invention.

[0068] For example, coordination Figure 19 and Figure 20 As shown, the chip pad surface leveling device M further includes a chip carrier module M4 (e.g., a device platform). The chip carrier module M4 can be fixedly or movably disposed below the glass carrier module M2, and the chip carrier module M4 can be configured to carry the first chip 1 or the second chip 2 through vacuum suction or a clamping device. However, the above examples are merely one possible embodiment and are not intended to limit the present invention.

[0069] For example, coordination Figure 19 and Figure 20 As shown, the chip pad surface leveling device M further includes a surface roughness detection module M5. The surface roughness detection module M5 is electrically connected to the signal control module M1, or it can be a separate detection device independent of the chip pad surface leveling device M. It is worth noting that when the leveling glass substrate GS is far from the first chip 1 or the second chip 2 (e.g....), Figure 19 (as shown) or when the flattening glass substrate GS is placed on the first chip 1 or the second chip 2 (e.g.) Figure 20As shown), the surface roughness detection module M5 can be configured to detect the surface roughness of the multiple pad ends 1000 of the multiple first protruding pad structures 10 of the first chip 1 or the surface roughness of the multiple pad ends 2000 of the multiple second protruding pad structures 20 of the second chip 2 (for example, it can be used to detect the surface roughness of the multiple pad ends 2000 of the multiple first protruding pad structures 20 of the second chip 2). Figure 20 (The first chip 1 shown is replaced with the first chip 2). However, the examples given above are merely one possible embodiment and are not intended to limit the invention.

[0070] For example, coordination Figure 19 and Figure 20 As shown, the glass carrier module M2 includes a suction nozzle structure M21 (which can be used to provide a vacuum suction force) and a drive structure M22 (which can be used to provide a driving force) connected to the suction nozzle structure M21. The suction nozzle structure M21 can be configured to pick up the leveling glass substrate GS under the control of the signal control module M1, and the drive structure M22 can be configured to drive the suction nozzle structure M21, which has picked up the leveling glass substrate GS, to move in any direction under the control of the signal control module M1. Furthermore, the drive structure M22 is configured to drive the suction nozzle structure M21 downward at the same predetermined speed or a different predetermined speed (for example, a first predetermined speed or a second predetermined speed greater than the first predetermined speed can be selected), so that the leveling glass substrate GS picked up by the suction nozzle structure M21 contacts and presses down on the multiple pad ends 1000 of the multiple first protruding type pad structures 10 of the first chip 1 or the multiple pad ends 2000 of the multiple second protruding type pad structures 20 of the second chip 2 (for example, the multiple first protruding type pad structures 20 of the second chip 2 can be pressed down on). Figure 19 and Figure 20 (The first chip 1 shown is replaced with the first chip 2). However, the examples given above are merely one possible embodiment and are not intended to limit the invention.

[0071] For example, coordination Figure 19 and Figure 20 As shown, the chip pad surface leveling device M further includes a pressure sensing module M6, and the pressure sensing module M6 is electrically connected to the signal control module M1. More specifically, the pressure sensing module M6 can be connected to the glass carrier module M2 to determine whether the leveling glass substrate GS contacts the multiple pad ends 1000 of the multiple first pillar-type pad structures 10 of the first chip 1 or the multiple pad ends 2000 of the multiple second pillar-type pad structures 20 of the second chip 2 (for example, it can be...). Figure 19 and Figure 20 (The first chip 1 shown is replaced with the first chip 2). However, the examples given above are merely one possible embodiment and are not intended to limit the invention.

[0072] One of the beneficial effects of the present invention is that the heterogeneous chip stacking device S provided by the present invention can stack two heterogeneous chips by means of the following technical solutions: "a limiting substrate structure S2 has a plurality of limiting grooves S200 configured to respectively accommodate a plurality of first chips 1", "a first cover structure S3 is configured to be disposed on a plurality of first chips 1 and press against a plurality of first chips 1, and the first cover structure S3 has a plurality of first openings S300 configured to respectively accommodate a plurality of second chips 2" and "a second cover structure S4 has a plurality of second openings S400 configured to respectively communicate with a plurality of first openings S300, and the second cover structure S4 is configured to allow a portion of the chip carrier structure 5 to be accommodated in any of the second openings S400". For example, the chip carrier structure 5 can be configured to pick up the second chip 2 and place the second chip 2 on the corresponding first chip 1, such that the plurality of first bonding ends 100 of the plurality of first protruding pad structures 10 of the first chip 1 are in direct contact and tightly bonded to each other with the plurality of second bonding ends 200 of the plurality of second protruding pad structures 20 of the second chip 2.

[0073] The above-disclosed content is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.

Claims

1. A heterogeneous chip stacking device, characterized in that, include: A substrate support structure; A limiting substrate structure is detachably mounted on the substrate support structure; A first cover plate structure is detachably disposed above the limiting base plate structure; A second cover plate structure is detachably mounted on the first cover plate structure; as well as A chip carrier structure is movably disposed above the substrate carrier structure; The limiting substrate structure has multiple limiting grooves configured to accommodate multiple first chips respectively. The first cover structure is configured to be disposed on and press against the plurality of first chips, and the first cover structure has a plurality of first openings configured to accommodate a plurality of second chips respectively. The second cover structure has a plurality of second openings configured to communicate with a plurality of first openings respectively, and the second cover structure is configured to allow a portion of the chip carrier structure to be accommodated within any of the second openings; The chip carrier structure is configured to pick up the second chip and place the second chip on the corresponding first chip, such that the plurality of first bonding ends of the plurality of first protruding pad structures of the first chip are in direct contact with and tightly bonded to the plurality of second bonding ends of the plurality of second protruding pad structures of the second chip.

2. The heterogeneous chip stacking device as described in claim 1, characterized in that, The substrate support structure has a plurality of vacuum suction holes configured for positioning the limiting substrate structure; Each of the first chips has two first alignment marks arranged diagonally on its top end, and each of the second chips has two second alignment marks arranged diagonally on its bottom end. The two first alignment marks of the first chip are adjacent to and correspond to the two second alignment marks of the second chip. The two first alignment marks of the first chip are disposed on an outer surrounding area of ​​the first chip, and a portion of the outer surrounding area of ​​each of the first chips is not covered by the first cover plate structure; The two first alignment marks of each of the first chips are exposed by the corresponding first opening and the corresponding second opening; The limiting substrate structure and the first cover plate structure cooperate with each other through magnetic attraction, so that multiple first chips are pressed tightly between the limiting substrate structure and the first cover plate structure. The second opening of the second cover structure is larger than the first opening of the first cover structure.

3. The heterogeneous chip stacking device as described in claim 1, characterized in that, The substrate support structure, the limiting substrate structure, the first cover plate structure, and the second cover plate structure are sequentially stacked on a machine body structure of the heterogeneous chip stacking equipment, and the chip support structure is detachably connected to the machine body structure. The chip carrier structure includes a connecting part detachably connected to the machine body structure, a rotating part connected to the connecting part, and a suction nozzle part disposed on the rotating part; The outer surface of the connecting portion of the chip carrier structure has an external thread configured to connect to the machine body structure. The connecting portion and the rotating portion of the chip carrier structure cooperate with each other to form a hexagonal bolt, and the rotating portion of the chip carrier structure is configured to be rotated by the operation of a tool. The second chip has a light-emitting region that is larger than the distribution range of the plurality of second protruding pillar-shaped pad structures, an outer frame region surrounding the light-emitting region, and a nozzle contact region located between the light-emitting region and the outer frame region; The nozzle portion of the chip carrier structure has a contact area and an opening area surrounded by the contact area, and the opening area is one nozzle opening or two nozzle openings. When the opening area is a suction nozzle opening, the contact area of ​​the suction nozzle portion of the chip carrier structure is configured to contact the suction nozzle contact area of ​​the second chip, the opening area of ​​the suction nozzle portion of the chip carrier structure is configured to contact the light-emitting area of ​​the second chip, and the contact area of ​​the suction nozzle portion of the chip carrier structure is configured to be separated from the light-emitting area of ​​the second chip and the outer frame area by a predetermined distance between 40μm and 60μm. When the opening area consists of two suction nozzle openings, the contact area of ​​the suction nozzle portion of the chip carrier structure is configured to contact the suction nozzle contact area and the light-emitting area of ​​the second chip. The opening area of ​​the suction nozzle portion of the chip carrier structure is configured to be separated from the light-emitting area of ​​the second chip by a predetermined distance between 15μm and 35μm. The contact area of ​​the suction nozzle portion of the chip carrier structure is configured to be separated from the outer frame area of ​​the second chip by a predetermined distance between 30μm and 50μm. The vertical projection of the light-emitting area of ​​the second chip falls entirely on the contact area of ​​the suction nozzle portion of the chip carrier structure.

4. The heterogeneous chip stacking device as described in claim 1, characterized in that, The first chip is a silicon-containing single-photon avalanche diode chip, and the second chip is a gallium arsenide-containing vertical cavity surface-emitting laser chip. The first chip has a plurality of first protruding pad structures that are separated from each other into a plurality of serially connected pad regions, and the plurality of first protruding pad structures in each of the serially connected pad regions are connected in series with each other. The first chip includes a plurality of top conductive pads electrically connected to a plurality of series pad regions, a plurality of bottom conductive pads corresponding to the plurality of top conductive pads, and a plurality of conductive through-body segments correspondingly connected between the plurality of top conductive pads and the plurality of bottom conductive pads; The second chip has a plurality of second protruding pad structures that are separated from each other. The second chip has a light-emitting area that is larger than the distribution range of the plurality of second protruding pad structures. The second protruding pad structures and the light-emitting area of ​​the second chip are respectively disposed on two opposite surfaces of the second chip. The second chip has a lower surface and a receiving groove recessed from the lower surface. Each second convex pad structure includes a convex substrate disposed in the receiving groove and a convex conductor disposed on the convex substrate. A top surface of the convex substrate of each second convex pad structure is flush with the lower surface of the second chip. Each of the first chips has two first alignment marks arranged diagonally on its top end, and each of the second chips has two second alignment marks arranged diagonally on its bottom end. The two first alignment marks of the first chip are adjacent to and correspond to the two second alignment marks of the second chip.

5. The heterogeneous chip stacking device as described in claim 4, characterized in that: The first convex pillar-shaped pad structure has a first diameter ranging from 15 μm to 30 μm and a first height ranging from 10 μm to 20 μm; Each of the second convex-shaped pad structures has a second diameter ranging from 25 μm to 35 μm and a second height ranging from 5 μm to 10 μm, and each of the second convex-shaped pad structures has a third diameter ranging from 15 μm to 25 μm and a third height ranging from 3 μm to 8 μm. The surface roughness of the multiple pad ends of the multiple first protruding type pad structures of the first chip is not greater than 1 μm, and the surface roughness of the multiple pad ends of the multiple second protruding type pad structures of the second chip is not greater than 1 μm. The spacing between the first pads of any two adjacent first protruding pad structures of the first chip is between 35 μm and 45 μm, and the spacing between the second pads of any two adjacent second protruding pad structures of the second chip is between 35 μm and 45 μm. The vertical spacing between the lower surface of the second chip and the upper surface of the first chip is between 10 μm and 15 μm.

6. A heterogeneous chip stacking device, characterized in that, include: A substrate support structure; A limiting substrate structure is detachably mounted on the substrate support structure; A first cover plate structure is detachably disposed above the limiting base plate structure; A second cover plate structure is detachably mounted on the first cover plate structure; as well as A chip carrier structure is movably disposed above the substrate carrier structure; The limiting substrate structure has multiple limiting grooves configured to accommodate multiple first chips respectively. The first cover structure is configured to be disposed on and press against the plurality of first chips, and the first cover structure has a plurality of first openings configured to accommodate a plurality of second chips respectively. The second cover structure has a plurality of second openings configured to communicate with a plurality of the first openings, and the second cover structure is configured to allow a portion of the chip carrier structure to be accommodated within any of the second openings.

7. The heterogeneous chip stacking apparatus as described in claim 6, characterized in that, The substrate support structure has a plurality of vacuum suction holes configured for positioning the limiting substrate structure; Each of the first chips has two first alignment marks arranged diagonally on its top end, and each of the second chips has two second alignment marks arranged diagonally on its bottom end. The two first alignment marks of the first chip are adjacent to and correspond to the two second alignment marks of the second chip. The two first alignment marks of the first chip are disposed on an outer surrounding area of ​​the first chip, and a portion of the outer surrounding area of ​​each of the first chips is not covered by the first cover plate structure; The two first alignment marks of each of the first chips are exposed by the corresponding first opening and the corresponding second opening; The limiting substrate structure and the first cover plate structure cooperate with each other through magnetic attraction, so that multiple first chips are pressed tightly between the limiting substrate structure and the first cover plate structure. The second opening of the second cover structure is larger than the first opening of the first cover structure.

8. The heterogeneous chip stacking apparatus as described in claim 6, characterized in that, The substrate support structure, the limiting substrate structure, the first cover plate structure, and the second cover plate structure are sequentially stacked on a machine body structure of the heterogeneous chip stacking equipment, and the chip support structure is detachably connected to the machine body structure. The chip carrier structure includes a connecting part detachably connected to the machine body structure, a rotating part connected to the connecting part, and a suction nozzle part disposed on the rotating part; the outer surface of the connecting part of the chip carrier structure has an external thread configured to connect to the machine body structure. The connecting portion and the rotating portion of the chip carrier structure cooperate with each other to form a hexagonal bolt, and the rotating portion of the chip carrier structure is configured to be rotated by the operation of a tool. The second chip has a plurality of second convex-shaped pad structures, a light-emitting area larger than the distribution range of the plurality of second convex-shaped pad structures, an outer frame area surrounding the light-emitting area, and a nozzle contact area located between the light-emitting area and the outer frame area; The nozzle portion of the chip carrier structure has a contact area and an opening area surrounded by the contact area, and the opening area is one nozzle opening or two nozzle openings. When the opening area is a suction nozzle opening, the contact area of ​​the suction nozzle portion of the chip carrier structure is configured to contact the suction nozzle contact area of ​​the second chip, the opening area of ​​the suction nozzle portion of the chip carrier structure is configured to contact the light-emitting area of ​​the second chip, and the contact area of ​​the suction nozzle portion of the chip carrier structure is configured to be separated from the light-emitting area of ​​the second chip and the outer frame area by a predetermined distance between 40μm and 60μm. When the opening area consists of two suction nozzle openings, the contact area of ​​the suction nozzle portion of the chip carrier structure is configured to contact the suction nozzle contact area and the light-emitting area of ​​the second chip. The opening area of ​​the suction nozzle portion of the chip carrier structure is configured to be separated from the light-emitting area of ​​the second chip by a predetermined distance between 15μm and 35μm. The contact area of ​​the suction nozzle portion of the chip carrier structure is configured to be separated from the outer frame area of ​​the second chip by a predetermined distance between 30μm and 50μm. The vertical projection of the light-emitting area of ​​the second chip falls entirely on the contact area of ​​the suction nozzle portion of the chip carrier structure.

9. The heterogeneous chip stacking device as described in claim 6, characterized in that, The first chip is a silicon-containing single-photon avalanche diode chip, and the second chip is a gallium arsenide-containing vertical cavity surface-emitting laser chip. The first chip has a plurality of first protruding pad structures that are separated from each other into a plurality of serially connected pad regions, and the plurality of first protruding pad structures in each of the serially connected pad regions are connected in series with each other. The first chip includes a plurality of top conductive pads electrically connected to a plurality of series pad regions, a plurality of bottom conductive pads corresponding to the plurality of top conductive pads, and a plurality of conductive through-body segments correspondingly connected between the plurality of top conductive pads and the plurality of bottom conductive pads; The second chip has multiple second protruding pad structures that are separated from each other. The second chip has a light-emitting area that is larger than the distribution range of the multiple second protruding pad structures. The second protruding pad structures and the light-emitting area of ​​the second chip are respectively disposed on two opposite surfaces of the second chip. The second chip has a lower surface and a receiving groove recessed from the lower surface. Each second convex pad structure includes a convex substrate disposed in the receiving groove and a convex conductor disposed on the convex substrate. A top surface of the convex substrate of each second convex pad structure is flush with the lower surface of the second chip. Each of the first chips has two first alignment marks arranged diagonally on its top end, and each of the second chips has two second alignment marks arranged diagonally on its bottom end. The two first alignment marks of the first chip are adjacent to and correspond to the two second alignment marks of the second chip.

10. The heterogeneous chip stacking apparatus as described in claim 6, characterized in that, The first protruding pad structure of the first chip has a first diameter ranging from 15μm to 30μm and a first height ranging from 10μm to 20μm; The second chip has a second diameter in the form of a second convex pad structure with a convex substrate having a diameter in the range of 25 μm to 35 μm and a second height in the range of 5 μm to 10 μm, and the second convex pad structure has a third diameter in the range of 15 μm to 25 μm and a third height in the range of 3 μm to 8 μm. The surface roughness of the multiple pad ends of the multiple first protruding type pad structures of the first chip is not greater than 1 μm, and the surface roughness of the multiple pad ends of the multiple second protruding type pad structures of the second chip is not greater than 1 μm. The spacing between the first pads of any two adjacent first protruding pad structures of the first chip is between 35 μm and 45 μm, and the spacing between the second pads of any two adjacent second protruding pad structures of the second chip is between 35 μm and 45 μm. The vertical spacing between the lower surface of the second chip and the upper surface of the first chip is between 10 μm and 15 μm.

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