storage device

Abstract

Embodiments of this disclosure relate to a storage device. The storage device includes: a printed circuit board; an interposer disposed on the printed circuit board; a group of storage cells disposed on the interposer; a control unit disposed on the printed circuit board and configured to control the group of storage cells; and a first transmission line electrically connected between the control unit and the group of storage cells and configured to transmit commands or addresses. The first transmission line includes a trunk electrically connected to the control unit, a first-level branch electrically connected to the trunk, and a second-level branch electrically connected to the first-level branch, the second-level branch being electrically connected to the group of storage cells. The trunk and the first-level branch are disposed in the printed circuit board, and the second-level branch is disposed in the interposer.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein generally relate to the field of computers, and more particularly to a storage device. Background Technology

[0002] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM, also known as DDR memory) can transfer data twice within one clock cycle, once on the rising edge and once on the falling edge of the clock. Low-power DDR SDRAM (LPDDR SDRAM, also known as LPDDR memory) is a type of DDR SDRAM, known for its low power consumption and small size, and is specifically designed for mobile electronic products.

[0003] Due to the trade-off between the storage capacity and price of a single memory chip, multiple small-capacity DDR SDRAM chips are often used to form large-capacity storage devices, such as using four 2GB chips to form an 8GB storage device. In this process, considering the actual routing on the printed circuit board (PCB), multiple DDR SDRAM chips need to employ a specific topology to meet timing requirements.

[0004] When using four chips to form a large-capacity storage device, for DDR memory, four individual chips can be used to form a four-chip single-channel DDR memory, while for LPDDR memory, four chips can be packaged together to form a single-chip quad-channel LPDDR memory. If a set of command and address lines (CA lines) is used, the common topologies that four chips can use include Fly-by topology, T+Fly-by topology, and dual-T topology. Summary of the Invention

[0005] In a first aspect of this disclosure, a storage device is provided. The storage device includes: a printed circuit board; an interposer disposed on the printed circuit board; a group of storage cells disposed on the interposer; a control unit disposed on the printed circuit board and configured to control the group of storage cells; and a first transmission line electrically connected between the control unit and the group of storage cells and configured to transmit commands or addresses. The first transmission line includes a trunk electrically connected to the control unit, a first-level branch electrically connected to the trunk, and a second-level branch electrically connected to the first-level branch, the second-level branch being electrically connected to the group of storage cells. The trunk and the first-level branch are disposed in the printed circuit board, and the second-level branch is disposed in the interposer.

[0006] It should be understood that the content described in this section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0007] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0008] Figure 1 A topology diagram of a storage device according to some embodiments of the present disclosure is shown;

[0009] Figure 2A and Figure 2B A schematic diagram of the structure of a transmission line according to some embodiments of the present disclosure is shown;

[0010] Figure 3 A schematic diagram of the structure of a storage device according to some embodiments of the present disclosure is shown;

[0011] Figure 4 It shows Figure 3 A schematic diagram showing a relative arrangement of storage cells and an intermediary layer in a storage device;

[0012] Figure 5 It shows Figure 3 A schematic diagram showing another relative arrangement of storage cells and intermediary layer in the storage device shown;

[0013] Figure 6 A schematic diagram of the structure of a storage device according to some embodiments of the present disclosure is shown;

[0014] Figure 7 It shows Figure 6 A schematic diagram showing a relative arrangement of storage cells and an interposer layer in a storage device; and

[0015] Figure 8 It shows Figure 6 This is a schematic diagram of another relative arrangement of storage cells and intermediary layers in the storage device shown. Detailed Implementation

[0016] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0017] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below.

[0018] As mentioned above, for quad-chip DDR memory or quad-channel LPDDR memory, the common topologies that can be used for the four chips include Fly-by topology, T+Fly-by topology, and dual-T topology. Dual-T topology is simpler in terms of overall timing control than Fly-by topology and T+Fly-by topology; however, the PCB design of dual-T topology is more difficult to implement.

[0019] Figure 1 A topological diagram of a storage device according to some embodiments of the present disclosure is shown. For example... Figure 1 As shown, the storage device 100 has a dual-T topology, which includes a control unit 11, a storage unit group 13, and a first transmission line 12. The first transmission line 12 connects the control unit 11 and the storage unit group 13 and is used to transmit commands or addresses. The control unit 11 can control the storage unit group 13 via the first transmission line 12, for example, to perform read and write operations on the storage units in the storage unit group 13.

[0020] In some embodiments, such as Figure 1As shown, the storage unit group 13 includes a first storage unit 13-1, a second storage unit 13-2, a third storage unit 13-3, and a fourth storage unit 13-4. The first transmission line 12 includes a main trunk 120 electrically connected to the control unit 11, a first-level branch 121 electrically connected to the main trunk 120, and a second-level branch 122 electrically connected to the first-level branch 121. The first-level branch 121 includes a first sub-branch 121-1 and a second sub-branch 121-2 electrically connected to the main trunk 120. The second-level branch 122 includes a first sub-branch 122-1 and a second sub-branch 122-2 electrically connected to the first sub-branch 121-1, and a third sub-branch 122-3 and a fourth sub-branch 122-4 electrically connected to the second sub-branch 121-2. The first sub-branch 122-1 is electrically connected to the first storage unit 13-1. The second sub-branch 122-2 is electrically connected to the second storage unit 13-2. The third sub-branch 122-3 is electrically connected to the third storage unit 13-3. The fourth sub-branch 122-4 is electrically connected to the fourth storage unit 13-4.

[0021] In some embodiments, each of the first storage cell 13-1, the second storage cell 13-2, the third storage cell 13-3, and the fourth storage cell 13-4 is a DDR SDRAM. Accordingly, the control unit 11 is a DDR controller. Hereinafter, the principles of this disclosure will be described using DDR SDRAM and a DDR controller as examples. However, it should be understood that the DDR SDRAM and the DDR controller are merely exemplary and are not intended to limit the scope of this disclosure. In other embodiments, each of the first storage cell 13-1, the second storage cell 13-2, the third storage cell 13-3, and the fourth storage cell 13-4 may be other types of storage cells, and correspondingly, the control unit 11 may be other types of control units.

[0022] In the first transmission line 12, considering the signal return loss (hereinafter referred to as return loss), the characteristic impedance of the first transmission line 12 needs to be doubled from the trunk 120 to the first-level branch 121 and from the first-level branch 121 to the second-level branch 122. For example, in one embodiment, considering the PCB manufacturing process, the impedance of the trunk 120 can be 30 ohms. Therefore, to achieve impedance matching, the impedance of the first branch 121-1 and the second branch 121-2 in the first-level branch 121 should be 60 ohms, while the impedance of the first sub-branch 122-1, the second sub-branch 122-2, the third sub-branch 122-3, and the fourth sub-branch 122-4 in the second-level branch 122 should be 120 ohms. It should be noted that the figures, values, etc. mentioned above and elsewhere in this disclosure are exemplary and are not intended to limit the scope of this disclosure in any way. Any other suitable figures or values ​​are possible.

[0023] For PCB manufacturing processes, transmission lines with characteristic impedances of 30 ohms and 60 ohms are relatively easy to implement, but transmission lines with high characteristic impedances of 120 ohms are very difficult to implement.

[0024] To implement transmission lines with high characteristic impedance in PCBs, there are currently two main approaches: Figure 2A and Figure 2B As shown. In Figure 2A In the illustrated scheme, portions of reference planes 21 and 22 in the layers adjacent to transmission line 25 are removed, forming notches 211 and 221. With this arrangement, transmission line 25 can utilize reference planes 20 and 23, which are farther away than reference planes 21 and 22, as references, increasing the distance between transmission line 25 and the reference planes, and thus correspondingly increasing the thickness of the dielectric layer between transmission line 25 and the reference planes. In this way, the characteristic impedance of transmission line 25 can be increased. Figure 2B In the scheme shown, with Figure 2A Compared to the previous scheme, this directly increases the distance between transmission line 25 and reference planes 20 and 23, thus correspondingly increasing the thickness of the dielectric layer between transmission line 25 and reference planes 20 and 23. In this way, the characteristic impedance of transmission line 25 can also be increased.

[0025] Although Figure 2A and Figure 2B The proposed solutions can increase the characteristic impedance of transmission line 25, but these solutions will greatly increase the number of PCB layers and thickness, which will reduce the reliability of the PCB and lead to a sharp increase in cost.

[0026] To address the reduced reliability and drastically increased cost associated with implementing a double-T topology on a PCB, embodiments of this disclosure provide a transmission line arrangement scheme. In this scheme, an interposer layer is inserted between the memory cell and the PCB. The main trunk and first-level branches of the transmission line are arranged on the PCB, while the second-level branches are arranged in the interposer layer. This approach avoids adding additional layers to the PCB and frees up PCB routing space, thereby reducing the overall cost of the memory device and improving its reliability. The following will combine... Figures 3 to 8 To describe an exemplary embodiment of the storage device.

[0027] Figure 3 A schematic diagram of the structure of a storage device according to some embodiments of the present disclosure is shown. Figure 4 It shows Figure 3 The diagram shows a relative arrangement of storage cells and an intermediary layer in a storage device. Figure 4 It is along Figure 3When viewed in the direction indicated by arrow 40, the relative arrangement of storage cells 13-1, 13-2, 13-3, and 13-4 with the intermediary layer 15 is shown. Figure 3 The storage device 300 shown can be regarded as Figure 1 A specific implementation of the storage device 100 shown.

[0028] like Figure 3 As shown, the storage device 300 includes a PCB 10, an interposer 15, a memory cell group 13, a control unit 11, and a first transmission line 12. The interposer 15 is disposed on the PCB 10 and electrically connected to the PCB 10 via solder balls 18. The memory cell group 13 is disposed on the interposer 15 and electrically connected to the interposer 15 via solder balls 19. With this arrangement, the interposer 15 can transmit signals between the PCB 10 and the memory cell group 13. The control unit 11 is disposed on the PCB 10 and electrically connected to the PCB 10 via solder balls 17, for controlling the memory cell group 13 via the first transmission line 12.

[0029] In some embodiments, such as Figure 3 and Figure 4 As shown, the intermediary layer 15 is a single intermediary layer, and the first storage cell 13-1, the second storage cell 13-2, the third storage cell 13-3, and the fourth storage cell 13-4 are individually arranged on the intermediary layer 15. In other words, the first storage cell 13-1, the second storage cell 13-2, the third storage cell 13-3, and the fourth storage cell 13-4 are individually packaged and individually arranged on the intermediary layer 15.

[0030] Combination Figure 1 and Figure 3 The first transmission line 12 is electrically connected between the control unit 11 and the storage unit group 13. Figure 3 Only the first branch 121-1 in the first-level branch 121 of transmission line 12 and the first sub-branch 122-1 and the second sub-branch 122-2 electrically connected to the first branch 121-1 in the second-level branch 122 are shown, while the second branch 121-2 in the first-level branch 121 and the third sub-branch 121-3 and the fourth sub-branch 122-4 electrically connected to the second branch 121-2 in the second-level branch 122 are not shown, in order to clearly show the structural details in the storage device 300. It should be understood that the second branch 121-2 in the first-level branch 121 and the third sub-branch 121-3 and the fourth sub-branch 122-4 in the second-level branch 122 can be arranged in a similar manner to the first branch 121-1 in the first-level branch 121 and the first sub-branch 122-1 and the second sub-branch 122-2 in the second-level branch 122.

[0031] In some embodiments, such as Figure 3 As shown, the main trunk 120 of the first transmission line 12 and the first branch 121-1 of the first-level branch 121 are arranged in the PCB 10. The first sub-branch 122-1 and the second sub-branch 122-2 of the second-level branch 122 of the first transmission line 12 are arranged in the interposer layer 15. The main trunk 120 is electrically connected to via 101-1 in the PCB 10, and via 101-1 is electrically connected to the control unit 11 via solder balls 17. One end of the first branch 121-1 in the first-level branch 121 is electrically connected to the main trunk 120, and the other end is electrically connected to via 101-2 in the PCB 10. Via 101-2 is electrically connected to via 151-1 in the interposer layer 15 via solder balls 18. One end of the first sub-branch 122-1 and the second sub-branch 122-2 in the second-level branch 122 are respectively electrically connected to via 151-1. The other end of the first sub-branch 122-1 is electrically connected to a via 151-2 disposed in the interposer layer 15. The via 151-2 is electrically connected to the memory cell 13-1 via solder ball 19. The other end of the second sub-branch 122-2 is electrically connected to a via 151-3 disposed in the interposer layer 15. The via 151-3 is electrically connected to the memory cell 13-2 via solder ball 19.

[0032] Similarly, the second branch 121-2 in the first-level branch 121 of the first transmission line 12 can be arranged in the PCB 10, while the third sub-branch 122-3 and the fourth sub-branch 122-4 in the second-level branch 122 of the first transmission line 12 can be arranged in the interposer layer 15. Furthermore, the second branch 121-2 in the first-level branch 121 can be electrically connected to the third sub-branch 122-3 and the fourth sub-branch 122-4 in the second-level branch 122 via vias and solder balls. The third sub-branch 122-3 and the fourth sub-branch 122-4 in the second-level branch 122 can also be electrically connected to the memory cells 13-3 and 13-4 respectively via vias and solder balls. The specific arrangement of the second branch 121-2 in the first-level branch 121 and the third sub-branch 122-3 and the fourth sub-branch 122-4 in the second-level branch 122 of the first transmission line 12 will not be described in detail here.

[0033] In some embodiments, the trunk 120 of the first transmission line 12 and the first branch 121-1 in the first-level branch 121 can be formed in the same layer of the PCB 10. In other embodiments, the trunk 120 of the first transmission line 12 and the first branch 121-1 in the first-level branch 121 can be formed in different layers of the PCB 10 and connected by vias provided in the PCB 10.

[0034] Similarly, in some embodiments, the trunk 120 of the first transmission line 12 and the second branch 121-2 in the first-level branch 121 can be formed in the same layer of the PCB 10. In other embodiments, the trunk 120 of the first transmission line 12 and the second branch 121-2 in the first-level branch 121 can be formed in different layers of the PCB 10 and connected by vias provided in the PCB 10. Furthermore, the first branch 121-1 and the second branch 121-2 in the first-level branch 121 can be formed in the same layer or different layers of the PCB 10, and the embodiments of this disclosure are not limited in this respect.

[0035] By placing the second-stage branch 122 of the first transmission line 12 within the interposer layer 15, the increase in the number of additional layers on the PCB 10 can be avoided. This allows the PCB 10 to still employ a conventional design, while providing the second-stage branch 122 with high characteristic impedance using only the smaller interposer layer 15. In this way, on the one hand, a sharp increase in the cost of the memory device can be prevented, and on the other hand, PCB wiring space can be freed up, thereby improving the reliability of the memory device.

[0036] In some embodiments, the interposer 15 includes a packaging substrate, in which the second-level branch 122 is disposed. In other embodiments, the interposer 15 includes another printed circuit board, in which the second-level branch 122 is disposed. Compared to the manufacturing process of the printed circuit board, the manufacturing process of the packaging substrate can achieve a finer linewidth. Therefore, when the second-level branch 122 is disposed in the packaging substrate, crosstalk introduced on the second-level branch 122 can be optimized, further improving the reliability of the memory device.

[0037] In some embodiments, such as Figure 3 As shown, the storage device 300 also includes a second transmission line 16. The second transmission line 16 is electrically connected between the control unit 11 and the storage unit group 13 for data transmission. The second transmission line 16 is arranged in the PCB 10. One end of the second transmission line 16 is electrically connected to a via 101-3 provided in the PCB 10, and the other end is electrically connected to a via 101-4 provided in the PCB 10. The via 101-3 is electrically connected to the control unit 11 via solder ball 17. The via 101-4 is electrically connected to a via 151-4 provided in the interposer layer 15 via solder ball 18. The via 151-4 is electrically connected to the storage unit 13-1 via solder ball 19. The control unit 11 and other storage units in the storage unit group 13 can transmit data using the data transmission line in a similar manner, which will not be described further here.

[0038] In some embodiments, the size of the interposer layer 15 may be close to the size of the memory cell group 13. In some embodiments, the size of the interposer layer 15 may be larger than the size of the memory cell group 13 to facilitate the provision of test points thereon for testing the signals of the memory device 300. By introducing such test points, subsequent testing of the high-speed signals of the memory device 300 can be facilitated.

[0039] Figure 5 It shows Figure 3 This is a schematic diagram of another relative arrangement of storage cells and intermediary layers in the storage device shown. Figure 5 It is along Figure 3 When viewed in the direction indicated by arrow 40, storage cells 13-1, 13-2, 13-3, and 13-4 are arranged opposite to the intermediary layer 15. (See image.) Figure 3 and Figure 5 As shown, the intermediary layer 15 includes a first intermediary layer 15-1 and a second intermediary layer 15-2. The first storage cell 13-1 and the second storage cell 13-2 are separately arranged on the first intermediary layer 15-1. The third storage cell 13-3 and the fourth storage cell 13-4 are separately arranged on the second intermediary layer 15-2.

[0040] In some embodiments, such as Figure 3 and Figure 5 As shown, the first interposer layer 15-1 and the second interposer layer 15-2 are disposed on the same surface of the PCB 10. In other embodiments, the first interposer layer 15-1 and the second interposer layer 15-2 may be disposed on different surfaces of the PCB 10. The embodiments of this disclosure are not limited in this respect.

[0041] In some embodiments, at least a portion of the storage cells 13-1, 13-2, 13-3, and 13-4 may be packaged into a single package and then placed on the interposer layer 15. The following will be combined with... Figures 6 to 8 This arrangement will be described.

[0042] Figure 6 A schematic diagram of the structure of a storage device according to some embodiments of the present disclosure is shown. Figure 7 It shows Figure 6 The diagram shows a relative arrangement of storage cells and an intermediary layer in a storage device. Figure 8 It shows Figure 6 This is a schematic diagram of another relative arrangement of storage cells and intermediary layers in the storage device shown. Figure 6 The storage device 400 shown and Figure 3The storage device 300 shown has a similar structure, the only difference being that at least a portion of the storage cells 13-1, 13-2, 13-3, and 13-4 can be packaged into a single package. The identical parts will not be described again here, but the differences between the two will be described in detail.

[0043] In some embodiments, such as Figure 6 and Figure 7 As shown, the first memory cell 13-1, the second memory cell 13-2, the third memory cell 13-3, and the fourth memory cell 13-4 are packaged into a single package 30. The package 30 is electrically connected to the interposer layer 15 via solder balls 19.

[0044] In some embodiments, such as Figure 6 and Figure 8 As shown, the interposer layer 15 includes a first interposer layer 15-1 and a second interposer layer 15-2. The first memory cell 13-1 and the second memory cell 13-2 are packaged into a single package 30-1. The third memory cell 13-3 and the fourth memory cell 13-4 are packaged into a single package 30-2. Package 30-1 is electrically connected to the first interposer layer 15-1 via solder balls 19. Package 30-2 is electrically connected to the second interposer layer 15-2 via solder balls 19.

[0045] In some embodiments, such as Figure 6 and Figure 8 As shown, the first interposer layer 15-1 and the second interposer layer 15-2 are disposed on the same surface of the PCB 10. In other embodiments, the first interposer layer 15-1 and the second interposer layer 15-2 may be disposed on different surfaces of the PCB 10. The embodiments of this disclosure are not limited in this respect.

[0046] In embodiments according to this disclosure, by placing a second-level branch of the transmission line used for transmitting commands or addresses in an interposer layer, the increase in the number of additional layers on the PCB can be avoided, reducing the overall system cost. Furthermore, by placing the second-level branch in the interposer layer, PCB routing space can be freed up, optimizing crosstalk for signal integrity.

[0047] Although the principles of this disclosure have been described above with respect to a dual-T topology, it should be understood that the concept of setting an intermediary layer between the PCB and the memory cell can also be applied to other topologies, and the scope of this disclosure is not limited in this respect.

[0048] Various implementations of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A storage device, comprising: Printed circuit board (10); An intermediate layer (15) is disposed on the printed circuit board (10); Storage cell group (13) is arranged on the intermediary layer (15); A control unit (11) is disposed on the printed circuit board (10) and configured to control the memory cell group (13); and A first transmission line (12) is electrically connected between the control unit (11) and the storage unit group (13) and is configured to transmit commands or addresses. The first transmission line (12) includes a trunk (120) electrically connected to the control unit (11), a first-level branch (121) electrically connected to the trunk (120), and a second-level branch (122) electrically connected to the first-level branch (121). The second-level branch (122) is electrically connected to the storage unit group (13). The trunk (120) and the first-level branch (121) are arranged in the printed circuit board (10), and the second-level branch (122) is arranged in the interposer layer (15). The first-level branch (121) includes a first branch line (121-1) and a second branch line (121-2), and the second-level branch (122) includes a first sub-branch line (122-1) and a second sub-branch line (122-2) electrically connected to the first branch line (121-1), as well as a third sub-branch line (122-3) and a fourth sub-branch line (122-4) electrically connected to the second branch line (121-2).

2. The storage device according to claim 1, wherein the interposer (15) comprises a packaging substrate, and the second-level branch (122) is disposed in the packaging substrate.

3. The storage device according to claim 1, wherein the intermediary layer (15) includes another printed circuit board, and the second-level branch (122) is disposed in the other printed circuit board.

4. The storage device according to claim 1, wherein the storage unit group (13) includes a first storage unit (13-1), a second storage unit (13-2), a third storage unit (13-3), and a fourth storage unit (13-4), wherein the first sub-branch (122-1) is electrically connected to the first storage unit (13-1), the second sub-branch (122-2) is electrically connected to the second storage unit (13-2), the third sub-branch (122-3) is electrically connected to the third storage unit (13-3), and the fourth sub-branch (122-4) is electrically connected to the fourth storage unit (13-4).

5. The storage device according to claim 4, wherein the intermediary layer (15) is a single intermediary layer.

6. The storage device according to claim 5, wherein the first storage unit (13-1), the second storage unit (13-2), the third storage unit (13-3) and the fourth storage unit (13-4) are individually arranged on the interposer layer (15).

7. The storage device according to claim 5, wherein the first storage unit (13-1) and the second storage unit (13-2) are packaged into a single package, and / or the third storage unit (13-3) and the fourth storage unit (13-4) are packaged into a single package.

8. The storage device according to claim 5, wherein the first storage unit (13-1), the second storage unit (13-2), the third storage unit (13-3), and the fourth storage unit (13-4) are packaged into a single package.

9. The storage device according to claim 4, wherein the intermediary layer (15) includes a first intermediary layer (15-1) and a second intermediary layer (15-2), the first storage cell (13-1) and the second storage cell (13-2) are disposed on the first intermediary layer (15-1), and the third storage cell (13-3) and the fourth storage cell (13-4) are disposed on the second intermediary layer (15-2).

10. The storage device according to claim 9, wherein the first interposer (15-1) and the second interposer (15-2) are disposed on the same side or different sides of the printed circuit board (10).

11. The storage device according to claim 9, wherein the first storage unit (13-1) and the second storage unit (13-2) are individually arranged on the first intermediary layer (15-1), and / or the third storage unit (13-3) and the fourth storage unit (13-4) are individually arranged on the second intermediary layer (15-2).

12. The storage device of claim 9, wherein the first storage unit (13-1) and the second storage unit (13-2) are packaged into a single package, and / or the third storage unit (13-3) and the fourth storage unit (13-4) are packaged into a single package.

13. The storage device according to claim 1, wherein the intermediary layer (15) includes test points for testing signals of the storage device.

14. The storage device according to claim 1, further comprising: The second transmission line (16) is electrically connected between the control unit (11) and the storage unit group (13) and is configured to transmit data. The second transmission line (16) is arranged in the printed circuit board (10) and electrically connected to the storage unit group (13) via vias (151-4) provided in the interposer layer (15).

15. The storage device according to claim 1, wherein the storage cell group (13) comprises a plurality of double-rate synchronous dynamic random access memories (DDR SDRAM).

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