An insulated gate bipolar transistor and a method of manufacturing the same

Abstract

The application provides an insulated gate bipolar transistor and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor layer comprising a substrate, a cell region, a transition region and a terminal region; performing ion implantation of a second conductive type in the cell region to form a first body region; forming a plurality of interval arranged groove structures in the cell region; forming a shielding layer on the upper surface of the semiconductor layer to expose the cell region, and forming an emitter region and a second body region based on the shielding layer, the bottom surface of the second body region is below the first body region, the upper surface of the second body region is in the first body region, the first body region and the second body region form a body region, and rapid annealing is performed on the second body region and the emitter region. The body region is formed by twice ion implantation of low energy and high energy, so that the concentration peak of the doping particles is located in the body region, the threshold voltage consistency of the device is ensured, rapid annealing is performed on the second body region and the emitter region, and the influence of thermal stress on the device is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to an insulated gate bipolar transistor and its fabrication method. Background Technology

[0002] Insulated Gate Bipolar Transistors (IGBTs) combine the voltage control of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with the conductance modulation of Bipolar Junction Transistors (BJTs). They feature high input impedance, low switching losses, high speed, and low voltage drive power, making them widely used in power transmission and transformation, high-speed train traction, industrial drives, clean energy, and many other fields. Due to their inherent high voltage and high current characteristics, IGBTs have undergone continuous power dissipation reductions with each generation to improve energy conversion efficiency. This involves shrinking the cell pitch while reducing channel length and increasing channel density to lower chip area and power consumption. However, this also leads to significantly increased fabrication difficulty and a substantial decrease in IGBT short-circuit capability.

[0003] Currently, with the advancement of high-density trench technology, wafer stress has increased significantly. The wafer stress caused by the thermal process after polysilicon etching is the most prominent. The wafer warpage and torsion caused by wafer stress prevent the proper alignment of subsequent layers, especially hole lithography, affecting threshold voltage consistency, chip performance, and yield. In severe cases, it can prevent the wafer from flowing to the next process.

[0004] The reduced short-circuit capability is mainly reflected in the fact that as the channel density increases, the short-circuit current flowing through the IGBT during a short circuit can reach more than 12 times the rated current, and the chip cannot withstand such a high power density. The IGBT will burn out due to overheating within microseconds.

[0005] Therefore, there is an urgent need to find a method for fabricating insulated gate bipolar transistors that reduces trench stress and short-circuit current. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an insulated gate bipolar transistor and its fabrication method, which solves the problems of high wafer stress and high short-circuit current after trenching process of insulated gate bipolar transistors in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating an insulated gate bipolar transistor, comprising the following steps:

[0008] A semiconductor layer is provided, the semiconductor layer including a first conductivity type substrate and a dielectric layer with an opening, the substrate being divided in a horizontal direction into a cell region, a terminal region and a transition region located between the cell region and the terminal region, the upper surface of the transition region and the terminal region being provided with at least one second conductivity type ring region, and the dielectric layer being located on the upper surface of the terminal region, the opening of the dielectric layer exposing the ring region;

[0009] Based on the dielectric layer, ion implantation of a second conductivity type is performed on the upper surface of the semiconductor layer to obtain a first body region located on the upper surface of the cell region and the transition region, the first body region being in contact with the ring region;

[0010] A shielding layer is formed on the upper surface of the semiconductor layer to expose the cell region. A second body region of a second conductivity type is formed in the cell region based on the shielding layer. The bottom surface of the second body region is located below the first body region, and the upper surface of the second body region is located in the first body region. The first body region and the second body region constitute a body region.

[0011] Based on the shielding layer, a first conductivity type emission region is formed on the upper surface of the first body region in the cell region, and the emission region and the second body region are subjected to rapid annealing.

[0012] Optionally, the method for forming the first body region includes ion implantation, and the method for forming the second body region includes ion implantation.

[0013] Optionally, the ion implantation energy range for forming the first body region is 60 keV to 160 keV, and the ion implantation dose range is 5 × 10⁻⁶. 12 / cm 2 ~5×10 13 / cm 2 The ion implantation energy range for forming the second body region is 400 keV to 1.2 MeV, and the ion implantation dose range is 5 × 10⁻⁶. 12 / cm 2 ~5×10 13 / cm 2 .

[0014] Optionally, after forming the first body region and before forming the shielding layer, the method further includes the step of forming a plurality of spaced trench structures in the cell region.

[0015] Optionally, after annealing the emitter region and the second body region, the process further includes the step of forming a plurality of spaced trench structures in the cell region.

[0016] Optionally, the method further includes the step of forming a first conductivity type carrier storage layer below the body region based on the shielding layer, wherein the upper surface of the carrier storage layer is in contact with the lower surface of the body region.

[0017] Optionally, the material of the shielding layer includes photoresist.

[0018] Optionally, the method of forming the ring region includes lateral doping.

[0019] Optionally, the method further includes the step of forming a plurality of emitter contact holes and terminal contact holes, wherein the bottom of the emitter contact holes extends into the first body region and the bottom of the terminal contact holes extends into the annular region.

[0020] The present invention also provides an insulated gate bipolar transistor structure, comprising:

[0021] A semiconductor layer includes a first conductivity type substrate, a cell region, a terminal region, and a transition region located between the cell region and the terminal region. At least one second conductivity type ring region is provided on the upper surface of the transition region and the terminal region.

[0022] Multiple spaced-apart trench structures are located in the cell region;

[0023] The body region is composed of a first body region of the second conductivity type and a second body region of the second conductivity type. The first body region is located on the upper surface of the cell region and the transition region. The first body region is in contact with the ring region. The bottom surface of the second body region is located below the first body region. The upper surface of the second body region is located in the first body region.

[0024] The first conductivity type emission region is located on the upper surface layer of the first body region.

[0025] As described above, the insulated-gate bipolar transistor and its fabrication method of the present invention reduce fabrication costs by forming a shielding layer on the upper surface of the semiconductor layer after forming the first body region, exposing the cell region, and forming the emitter region, the second body region, and the carrier storage layer in the semiconductor layer based on the shielding layer; the second body region is located below the first body region and partially overlaps with the first body region, causing the doping concentration peak of the body region to shift from the upper surface of the semiconductor layer to the body region, away from the surface of the trench structure with the greatest stress. This improves the threshold voltage V of the device. thThe consistency of the structure is ensured, and the second body region is formed by high-energy injection to form reverse doping in the semiconductor layer, which solves the short-channel effect of the device. This effectively reduces the short-circuit current when the device is short-circuited, improving the short-circuit capability of the device without affecting the channel during normal conduction. In addition, the emitter region, the second body region, and the carrier storage layer after the formation of the trench structure are rapidly annealed to reduce the high-temperature time, thereby reducing the impact of the thermal process. Since the impact of the thermal process and the influence of trench stress on the device threshold are reduced, the short-channel effect is suppressed. This structure is suitable for the fabrication of trench-type insulated-gate bipolar transistors with high trench density and has high industrial application value. Attached Figure Description

[0026] Figure 1 The diagram shown is a process flow diagram of the fabrication method of the insulated gate bipolar transistor of the present invention.

[0027] Figure 2 The diagram shows an ion implantation of a semiconductor layer as part of the fabrication method of the insulated gate bipolar transistor of the present invention.

[0028] Figure 3 The diagram shows an ion implantation of another semiconductor layer as part of the fabrication method of the insulated gate bipolar transistor of the present invention.

[0029] Figure 4 The diagram shown is a cross-sectional view of the insulated gate bipolar transistor fabrication method of the present invention after the formation of the first body region.

[0030] Figure 5 The diagram shows a cross-sectional structure after forming a patterned mask layer in the fabrication method of the insulated gate bipolar transistor of the present invention.

[0031] Figure 6 The diagram shows a cross-sectional structure after trench formation in the fabrication method of the insulated gate bipolar transistor of the present invention.

[0032] Figure 7 The diagram shown is a cross-sectional view of the trench structure formed according to the fabrication method of the insulated gate bipolar transistor of the present invention.

[0033] Figure 8 The diagram shown is a cross-sectional view of the insulated gate bipolar transistor fabrication method of the present invention after the formation of the shielding layer.

[0034] Figure 9 The diagram shown is a cross-sectional view of the insulated gate bipolar transistor fabrication method of the present invention after forming the emitter region, the second body region, and the carrier storage layer.

[0035] Figure 10The diagram shows the impurity concentration distribution of the substrate from the upper surface to the lower surface of the carrier storage layer after rapid annealing of the emitter region, the second body region, and the carrier storage layer in the fabrication method of the insulated gate bipolar transistor of the present invention.

[0036] Figure 11 The diagram shows a cross-sectional view of the fabrication method of the insulated gate bipolar transistor of the present invention after forming an emitter contact hole and a terminal contact hole in a semiconductor layer.

[0037] Figure 12 The diagram shows a cross-sectional view of the fabrication method of the insulated gate bipolar transistor of the present invention after forming an emitter contact hole and a terminal contact hole in another semiconductor layer.

[0038] Explanation of icon numbers

[0039] 1 Semiconductor layer

[0040] 10 Substrates

[0041] 11 cell regions

[0042] 111 First Body Area

[0043] 112 Second Body Area

[0044] Launch Area 113

[0045] 114 body area

[0046] 115 Carrier Storage Layer

[0047] 12 Terminal Area

[0048] 121 Ring Road

[0049] 122 Dielectric Layer

[0050] 13 Transition Zone

[0051] 2. Trench Structure

[0052] 21. Trench

[0053] 22 Gate dielectric layer

[0054] 23 Gate conductive layer

[0055] 3. Shielding layer

[0056] 4. Mask layer

[0057] 5 Interlayer dielectric layer

[0058] 51 Emitter Contact Hole

[0059] 52 Terminal area contact hole Detailed Implementation

[0060] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0062] Example 1

[0063] This embodiment provides a method for fabricating an insulated-gate bipolar transistor, such as... Figure 2 The diagram shown is a process flow chart of the fabrication method of the insulated gate bipolar transistor, including the following steps:

[0064] S1: A semiconductor layer is provided, the semiconductor layer including a first conductivity type substrate and a dielectric layer with an opening, the substrate being divided in a horizontal direction into a cell region, a terminal region and a transition region located between the cell region and the terminal region, the upper surface of the transition region and the terminal region being provided with at least one second conductivity type ring region, and the dielectric layer being located on the upper surface of the terminal region, the opening of the dielectric layer exposing the ring region;

[0065] S2: Based on the dielectric layer, perform ion implantation of the second conductivity type on the upper surface of the semiconductor layer to obtain a first body region located on the upper surface of the cell region and the transition region, wherein the first body region is in contact with the ring region;

[0066] S3: A shielding layer is formed on the upper surface of the semiconductor layer to expose the cell region. A second body region of a second conductivity type is formed in the cell region based on the shielding layer. The bottom surface of the second body region is located below the first body region. The upper surface of the second body region is located in the first body region. The first body region and the second body region constitute a body region.

[0067] S4: Based on the shielding layer, a first conductive type emission region is formed on the upper surface of the first body region in the cell region, and the emission region and the second body region are rapidly annealed.

[0068] Please see Figures 2 to 4The steps S1 and S2 are performed as follows: a semiconductor layer 1 is provided, the semiconductor layer 1 including a first conductivity type substrate 10 and a dielectric layer 122 with an opening, the substrate 1 being divided in a horizontal direction into a cell region 11, a terminal region 12 and a transition region 13 located between the cell region 11 and the terminal region 12, at least one second conductivity type ring region 121 being provided on the upper surface of the transition region 13 and the terminal region 12, and the dielectric layer 122 being located on the upper surface of the terminal region 12, the opening of the dielectric layer 122 exposing the ring region 121; based on the dielectric layer 122, second conductivity type ion implantation is performed on the upper surface of the semiconductor layer 1 to obtain a first body region 111 located on the upper surface of the cell region 11 and the transition region 13, the first body region 111 being in contact with the ring region 121.

[0069] Specifically, the doping concentration range of the substrate 10 can be selected according to the actual situation, and is not limited here.

[0070] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0071] Specifically, the substrate 10 is made of silicon, silicon germanium, silicon carbide, or other suitable semiconductor materials.

[0072] Specifically, the size of the cell region 11 can be selected according to the actual situation, and is not limited here; the size of the terminal region 12 can be selected according to the actual situation, and is not limited here.

[0073] Specifically, the terminal process forming the terminal region 12 is compatible with field oxide layer process (FOX process), local oxidation of silicon (LOCOS) process and variable lateral doping (VLD) process, and can also be compatible with other suitable terminal processes.

[0074] As an example, the method of forming the ring region 121 includes lateral doping, or other suitable methods.

[0075] Specifically, the size and doping concentration of the ring region 121 formed by the lateral variable doping process can be selected according to the actual situation, and are not limited here.

[0076] Specifically, the ring region 121 is formed by lateral doping, and there is only one ring region 121 in the semiconductor layer 1 located on the upper surface of the transition region 13 and the terminal region 12. The opening may not be provided in the dielectric layer 122 located on the upper surface of the terminal region 12.

[0077] Specifically, a field oxygen process can be used to form a shielding layer, and the ring region 121 formed by using a patterned field oxygen layer as a shielding layer can be formed by using a conventional ion implantation method.

[0078] As an example, such as Figure 2 and Figure 3 The diagrams shown illustrate ion implantation of a semiconductor layer 1 with multiple ring regions 121 and ion implantation of a semiconductor layer 1 with ring regions 121 formed using a horizontal-vertical doping method. The method for forming the first body region 111 includes ion implantation or other suitable methods. In this embodiment, the first body region 111 is formed using ion implantation. During ion implantation, the dielectric layer 122 located in the terminal region 12 is used as a shielding layer, and a boron source is selected as the ion source to directly implant ions into the cell region 11 to form the first body region 111.

[0079] Specifically, such as Figure 4 As shown, this is a cross-sectional structural diagram after the formation of the first body region 111. The sidewall of the first body region 111 that contacts the ring region 121 extends into the ring region 121 in the transition region 13, which is adjacent to the cell region 11.

[0080] As an example, the ion implantation energy range for forming the first body region 111 is 60 keV to 160 keV, and the ion implantation dose range is 5 × 10⁻⁶. 12 / cm 2 ~5×10 13 / cm 2 .

[0081] Specifically, after forming the first body region 111, the process also includes activating and pushing the first body region 111 into a trap. This involves utilizing the high diffusion rate of impurity particles at high temperatures to achieve a predetermined junction depth in the first body region 111. Alternatively, a trench structure can be formed subsequently (see later). Figure 7 The high temperature generated by the gate dielectric layer in the ) is used for push-sinking.

[0082] Please see again Figures 5 to 12Then, perform steps S3 and S4: form a shielding layer 3 on the upper surface of the semiconductor layer 1 to expose the cell region 11; form a second conductivity type second body region 112 in the cell region 11 based on the shielding layer 3; the bottom surface of the second body region 112 is located below the first body region 111; the upper surface of the second body region 112 is located in the first body region 111; the first body region 111 and the second body region 112 constitute a body region 114; form a first conductivity type emitter region 113 on the upper surface of the first body region 111 based on the shielding layer 3; and perform rapid annealing on the emitter region 113 and the second body region 112.

[0083] As an example, after forming the first body region 111 and before forming the shielding layer 3, the method further includes the step of forming a plurality of spaced trench structures 2 in the cell region 11.

[0084] As an example, after annealing the emission region 113 and the second body region 112, the process further includes forming a plurality of spaced groove structures 2 in the cell region 11.

[0085] Specifically, the trench structure 2 includes a trench 21, a gate dielectric layer 22 located on the inner wall and bottom surface of the trench 21, and a gate conductive layer 23 filling the trench 21.

[0086] Specifically, before forming the trench structure 2, the process includes forming a mask layer 4 covering the upper surface of the semiconductor layer 1, that is, after forming the first body region 111 or after annealing the second body region 112 and the emitter region 113, the mask layer is formed on the upper surface of the semiconductor layer 1.

[0087] Specifically, such as Figure 5 The diagram shown is a cross-sectional view of the patterned mask layer 4. The thickness of the mask layer 4 can be selected according to the actual situation and is not limited here.

[0088] Specifically, the method for forming the mask layer 4 includes physical vapor deposition, chemical vapor deposition, or other suitable methods.

[0089] Specifically, such as Figure 6 and Figure 7The figures show cross-sectional view diagrams of the trench structure 21 and the trench structure 2, respectively. The formation of the trench structure 2 includes the following steps: patterning the mask layer 4 and forming multiple trenches 21 spaced at a predetermined distance based on the patterned mask layer 4; forming the gate dielectric layer 22 on the inner wall and bottom surface of the trenches 21; and forming the gate conductive layer 23 in the trenches 21 to fill the trenches 21 to obtain the trench structure 2, wherein the gate dielectric layer 22 wraps the sidewall and bottom surface of the gate conductive layer 23.

[0090] Specifically, the method for forming the trench 21 includes dry etching, wet etching, or other suitable methods; while ensuring device performance, the opening size and depth of the trench 21 can be selected according to the actual situation, and are not limited here.

[0091] Specifically, while ensuring device performance, the distance between two adjacent trenches 21 can be selected according to the actual situation, and is not limited here.

[0092] Specifically, after forming the trench 21 and before forming the gate dielectric layer 22, the process further includes the step of removing the mask layer 4 from the upper surface of the semiconductor layer 1.

[0093] Specifically, after removing the mask 4 and before forming the gate dielectric layer 22, the process further includes forming a sacrificial layer (not shown).

[0094] Specifically, the sacrificial layer is formed to eliminate defects in the semiconductor layer 1; the method for forming the sacrificial layer includes thermal oxidation or other suitable methods.

[0095] Specifically, after the sacrificial layer is formed but before the gate dielectric layer 22 is formed, the step of removing the sacrificial layer is included; the method of removing the sacrificial layer includes wet etching or other suitable methods.

[0096] Specifically, the gate dielectric layer 22 is made of silicon oxide, silicon nitride, or other suitable dielectric materials.

[0097] Specifically, the method for forming the gate dielectric layer 22 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods. In this embodiment, thermal oxidation is used to form the gate dielectric layer 22.

[0098] Specifically, the gate dielectric layer 22 also covers the exposed surface of the semiconductor layer 1; while ensuring device performance, the thickness of the gate dielectric layer 22 can be selected according to the actual situation, and is not limited here.

[0099] Specifically, the material of the gate conductive layer 23 includes polycrystalline silicon or other suitable conductive materials.

[0100] As an example, such as Figure 8 The diagram shown is a cross-sectional view of the shielding layer 3 after its formation. The shielding layer 3 is made of photoresist or other suitable shielding materials. In this embodiment, a photoresist layer is used as the shielding layer 3.

[0101] Specifically, the method for forming the shielding layer 3 includes coating or other suitable methods.

[0102] As an example, such as Figure 9 The diagram shown is a cross-sectional view of the structure after the formation of the second body region 112, the emitter region 113, and the carrier storage layer 115. The method for forming the second body region 112 includes ion implantation or other suitable methods. In this embodiment, the second body region 112 is formed by ion implantation.

[0103] As an example, the ion implantation energy range for forming the second body region 112 is 400 keV to 1.2 MeV, and the ion implantation dose range is 5 × 10⁻⁶. 12 / cm 2 ~5×10 13 / cm 2 .

[0104] Specifically, the bottom surface of the second body region 112 is located below the first body region 111, and the upper surface of the second body region 112 is located in the first body region 111. That is, the first body region 111 and the second body region 112 partially overlap, thereby causing the concentration peak region of the second conductivity type impurity particles to be located in the overlapping area between the first body region 111 and the second body region 112. That is, the concentration peak region of the doped particles is located inside the body region 114, so that the concentration peak region of the second conductivity type impurity particles is far away from the upper surface of the semiconductor layer 1 with the greatest trench stress, thereby ensuring the consistency of the threshold voltage of the device.

[0105] Specifically, such as Figure 10The diagram shows the impurity concentration distribution between the upper surface of the substrate 10 and the lower surface of the carrier storage layer 115 after rapid annealing of the second body region 112, the emitter region 113, and the carrier storage layer 115. Since the ion implantation energy for forming the second body region 112 is higher than the ion implantation energy for forming the first body region 111, reverse doping is formed after annealing (the doping concentration of the second body region 112 located below the lower surface of the first body region 111 is lower than the doping concentration of the second body region 112 located above the lower surface of the first body region 111). That is, the doping concentration of the channel region in the body region 114 is higher than the doping concentration at the bottom of the body region 114, which suppresses the short-channel effect. This allows the short-circuit current to be effectively reduced when the device is short-circuited, and it does not affect the normal conduction of the conductive channel in the device.

[0106] As an example, the method for forming the emission region 113 includes ion implantation or other suitable methods. In this embodiment, an arsenic source is selected as the ion implantation source, and the emission region 113 is formed by ion implantation.

[0107] As an example, the ion implantation energy range for forming the emission region 113 is 60 keV to 100 keV, and the implantation dose range is 5 × 10⁻⁶. 15 / cm 2 ~5×10 16 / cm 2 .

[0108] As an example, the method also includes the step of forming a first conductivity type carrier storage layer 115 below the body region 114 based on the shielding layer 3, wherein the upper surface of the carrier storage layer 115 is in contact with the lower surface of the body region 114.

[0109] Specifically, the method for forming the carrier storage layer 115 includes ion implantation or other suitable methods. In this embodiment, a phosphorus source is selected as the ion source, and the carrier storage layer 115 is formed by ion implantation.

[0110] Specifically, the ion implantation energy range for forming the carrier storage layer 115 is 800 keV to 2 MeV, and the implantation dose range is 2 × 10⁻⁶. 12 / cm 2 ~2×10 13 / cm 2 .

[0111] Specifically, since the ion implantation energies for forming the emitter region 113, the second body region 112, and the current carrier storage layer 115 are different, that is, the positions of the emitter region 113, the second body region 112, and the current carrier storage layer 115 are different, the order in which the emitter region 113, the second body region 112, and the current carrier storage layer 115 are formed can be arbitrary. That is, the emitter region 113 can be formed first, followed by the second body region 112 and the current carrier storage layer 115, or the current carrier storage layer 115 and the second body region 112 can be formed in sequence; the second body region 112 can be formed first, followed by the emitter region 113 and the current carrier storage layer 115, or the current carrier storage layer 115 and the emitter region 113 can be formed in sequence; or the current carrier storage layer 115 can be formed first, followed by the emitter region 113 and the second body region 112, or the second body region 112 and the emitter region 113 can be formed in sequence.

[0112] Specifically, the emission region 113, the second body region 112, and the carrier storage layer 115 can be formed after the first body region 111 is formed and before the trench 21 is formed.

[0113] Specifically, the trench structure 2 penetrates the emitter region 113, the body region 114, and the carrier storage layer 115, and the bottom surface of the gate conductive layer 23 in the trench structure 2 is lower than the bottom surface of the carrier storage layer 115.

[0114] Specifically, since the emitter region 113, the second body region 112 and the carrier storage layer 115 share a shielding layer 3, and the shielding layer 3 shields the transition region 13 and the terminal region 12, the problem of device latch-up and damage to the terminal region 12 is avoided, and the manufacturing cost is saved.

[0115] Specifically, after forming the emitter region 113, the second body region 112, and the carrier storage layer 115, the emitter region 113, the second body region 112, and the carrier storage layer 115 are subjected to rapid annealing to reduce the time the device is exposed to high temperatures, thereby reducing the deformation stress (wafer warping) caused by high temperatures, maintaining a better reverse doping morphology, and improving the alignment accuracy of subsequent contact hole formation.

[0116] Specifically, after rapidly annealing the emitter region 113, the second body region 112, and the carrier storage layer 115, the process further includes forming an interlayer dielectric layer 5 covering the upper surface of the semiconductor layer 1.

[0117] Specifically, the method for forming the interlayer dielectric layer 5 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0118] Specifically, the material of the interlayer dielectric layer 5 includes silicon oxide, silicon nitride, or other suitable dielectric materials. In this embodiment, the dielectric layer 122, the gate dielectric layer 22, and the interlayer dielectric layer 5 are all made of the same material, namely silicon oxide.

[0119] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 5 can be selected according to the actual situation, and is not limited here.

[0120] As an example, such as Figure 11 and Figure 12 The diagrams shown are cross-sectional views of the semiconductor layer 1 after forming the emitter contact hole 51 and the terminal contact hole 52 in one type of semiconductor layer 1, and cross-sectional views of the semiconductor layer 1 after forming the emitter contact hole 51 and the terminal contact hole 52 in another type of semiconductor layer 1. The method also includes the step of forming multiple emitter contact holes 51 and terminal contact holes 52. The bottom of the emitter contact hole 51 extends into the first body region 111, and the bottom of the terminal contact hole 52 extends into the annular region 121. In this embodiment, the distance between the bottom surface of the emitter contact hole 51 and the upper surface of the semiconductor layer 1 ranges from 0.3 μm to 0.6 μm, and the distance between the bottom surface of the terminal contact hole 52 and the upper surface of the semiconductor layer 1 ranges from 0.3 μm to 0.6 μm.

[0121] Specifically, forming the emitter contact hole 51 and the terminal contact hole 52 includes the following steps: forming a photoresist layer on the upper surface of the interlayer dielectric layer 5 and patterning the photoresist layer; based on the patterned photoresist layer, etching the interlayer dielectric layer 5, the gate dielectric layer 22, the dielectric layer 122, the emitter region 113, the first body region 111, and the ring region 121 respectively to obtain the emitter contact hole 51 and the terminal contact hole 52.

[0122] Specifically, the method for forming the emitter contact hole 51 includes dry etching, wet etching, or other suitable methods; the method for forming the terminal contact hole 52 includes dry etching, wet etching, or other suitable methods.

[0123] Specifically, after forming the emitter contact hole 51 and the terminal contact hole 52, the method further includes forming an emitter (not shown), a gate (not shown), and a terminal lead-out electrode (not shown). The emitter fills the emitter contact hole 51, the gate is electrically connected to the gate conductive layer 23, and the terminal lead-out electrode fills the terminal contact hole 52. In this embodiment, the emitter and the terminal lead-out electrode are electrically connected.

[0124] Specifically, the method for forming the emitter, the gate, and the terminal lead-out electrode is a conventional method, which will not be described in detail here.

[0125] Specifically, the material of the emitter includes one of titanium, titanium nitride, silver, gold, copper, aluminum, and tungsten, or other suitable conductive materials; the material of the gate includes one of titanium, titanium nitride, silver, gold, copper, aluminum, and tungsten, or other suitable conductive materials; the material of the terminal lead electrode includes one of titanium, titanium nitride, silver, gold, copper, aluminum, and tungsten, or other suitable conductive materials.

[0126] Specifically, after forming the emitter, the gate, and the terminal lead-out electrode, the process includes the following steps: sequentially forming a first conductivity type field cutoff layer (not shown) and a second conductivity type collector region (not shown) on the lower surface layer of the cell region 11; forming a collector electrode (not shown) on the lower surface of the collector region, wherein the collector electrode is in electrical contact with the collector region.

[0127] Specifically, the method for forming the field cutoff layer includes ion implantation or other suitable methods; the method for forming the current collector region includes ion implantation or other suitable methods.

[0128] Specifically, the doping concentration of the field stop layer is higher than that of the substrate.

[0129] Specifically, the doping concentration of the current collector region can be selected according to the actual situation, and is not limited here.

[0130] Specifically, the methods for forming the current collector include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0131] Specifically, the material of the current collector includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0132] Specifically, because the above-described method for fabricating insulated gate bipolar transistors reduces the influence of thermal stress and trench stress on the device threshold, it suppresses the short-channel effect and can be applied to the fabrication of trench-type insulated gate bipolar transistors with high trench density.

[0133] The fabrication method of the insulated-gate bipolar transistor in this embodiment improves the fabrication process of the insulated-gate bipolar transistor. First, low-energy injection is used to form the first body region 111 on the upper surface of the cell region 11. Then, low-energy injection is used to form the emitter region 113 on the upper surface of the first body region 111. High-energy injection is then used to form the second body region 112, with the lower surface of the second body region 112 lower than the lower surface of the first body region 111. The upper surface of the second body region 112 is located within the first body region 111. The first body region 111 and the second body region 112 together form the body region 114, so that the emitter region 113 is formed. The peak doping concentration region of the body region 114 is located inside the body region 114, thereby keeping the peak doping concentration region of the body region 114 away from the upper surface of the semiconductor layer 1 where the trench stress is greatest, thus ensuring the consistency of the threshold voltage of the device. The second body region 112 formed by high-energy ion implantation produces a reverse doping phenomenon, so that the doping concentration of the channel region forming the conductive channel is higher than the doping concentration of the second body region 112 located below the first body region 111, suppressing the short-channel effect, so that when the device is short-circuited, the short-circuit current can be effectively reduced, and it has no effect on the normal conduction of the conductive channel in the device. Furthermore, the emitter region 113, the carrier storage layer 115, and the second body region 112 are formed using the same shielding layer 3, and the emitter region 113, the carrier storage layer 115, and the second body region 112 are simultaneously subjected to rapid annealing, which saves costs, reduces the thermal process, and reduces the impact of stress generated by the thermal process. Moreover, since the fabrication method of the insulated gate bipolar transistor described in this invention reduces the impact of thermal stress and the impact of trench stress on the device threshold, it suppresses the short-channel effect and is suitable for the fabrication of trench-type insulated gate bipolar transistors with high trench density.

[0134] Example 2

[0135] This embodiment provides an insulated-gate bipolar transistor, such as Figure 11 and Figure 12The figures shown are cross-sectional schematic diagrams of a partial structure of an insulated gate bipolar transistor (IGBT) and another partial structure of an IGBT, respectively. The IGBT includes a semiconductor layer 1, a body region 114, and a first conductivity type emitter region 113. The semiconductor layer 1 includes a first conductivity type substrate 10, a cell region 11, a terminal region 12, and a transition region 13 located between the cell region 11 and the terminal region 12. At least one second conductivity type ring region 121 is disposed on the upper surface of the transition region 13 and the terminal region 12. The body region 114 is composed of a second conductivity type first body region 111 and a second conductivity type second body region 112. The first body region 111 is located on the upper surface of the cell region 11 and the transition region 13, and is in contact with the ring region 121. The bottom surface of the second body region 112 is located below the first body region 111, and the upper surface of the second body region 112 is located within the first body region 111. The emitter region 113 is located on the upper surface of the first body region 111.

[0136] Specifically, the insulated gate bipolar transistor is prepared using the insulated gate bipolar transistor preparation method described in Example 1.

[0137] Specifically, the cell region 11, the terminal region 12, and the transition region 13 are located in the substrate 10.

[0138] Specifically, the thickness of the substrate 10 can be selected according to the actual situation, and is not limited here.

[0139] Specifically, the size and doping concentration of the ring region 121 can be set according to the actual situation, and are not limited here.

[0140] Specifically, the cell region 11 is provided with a plurality of spaced trench structures 2. The trench structure 2 includes a trench 21 located in the substrate 10, a gate dielectric layer 22 located on the inner wall and bottom surface of the trench 21, and a gate conductive layer 23 filling the trench 21. The gate dielectric layer 22 wraps the sidewall and bottom surface of the gate conductive layer 23.

[0141] Specifically, while ensuring device performance, the junction depth of the first body region 111 can be set according to the actual situation, and is not limited here.

[0142] Specifically, the thickness of the emission region 113 is no greater than 0.6 μm, where the thickness refers to the distance between the upper surface and the lower surface of the emission region 113.

[0143] Specifically, while ensuring device performance, the thickness of the overlapping region between the first body region 111 and the second body region 112 can be set according to the actual situation, and is not limited here. That is, the region of the peak doping concentration in the body region 114. The thickness here refers to the distance between the upper surface of the second body region 112 and the lower surface of the first body region 111.

[0144] Specifically, a first conductivity type carrier storage layer 115 is also provided below the body region 114, and the upper surface of the carrier storage layer 115 is in contact with the lower surface of the body region 114.

[0145] Specifically, while ensuring device performance, the thickness of the carrier storage layer 115 can be set according to actual conditions, and is not limited here. The thickness here refers to the distance between the upper surface and the lower surface of the carrier storage layer 115.

[0146] Specifically, the insulated gate bipolar transistor further includes an emitter contact hole 51, a terminal contact hole 52, an emitter, a gate, a terminal lead-out electrode, a first conductivity type field cutoff layer, a collector region, and a collector electrode. The emitter fills the emitter contact hole 51 and is electrically contacted with the body region 114. The terminal lead-out electrode fills the terminal contact hole 52 and is electrically contacted with the ring region 121. The gate is electrically contacted with the gate conductive layer 23. The collector region is located on the lower surface of the substrate 10, and its lower surface is flush with the lower surface of the substrate 10. The field cutoff layer is located on the upper surface of the collector region, and its upper surface is flush with the lower surface of the field cutoff layer. The collector electrode is located on the lower surface of the collector region and is electrically contacted with it.

[0147] Specifically, provided that the device performance and the doping concentration of the field stop layer are higher than those of the substrate 10, the thickness and doping concentration of the field stop layer can be set according to actual conditions, and are not limited here. The thickness here refers to the distance between the upper surface and the lower surface of the field stop layer.

[0148] Specifically, the thickness of the current collector area can be set according to actual conditions, and is not limited here. The thickness here refers to the distance between the upper surface and the lower surface of the current collector area.

[0149] The insulated gate bipolar transistor of this embodiment improves the consistency of the device threshold voltage by setting the doped peak region in the body region 114 within the body region 114.

[0150] In summary, the insulated-gate bipolar transistor and its fabrication method of the present invention improve the fabrication process of the insulated-gate bipolar transistor by first using low-energy ion implantation to directly form a first body region in the cell region, and then forming a second body region based on a shielding layer and an emitter region located on the upper surface of the first body region. The second body region and the first body region together form a body region, with the lower surface of the second body region located below the lower surface of the first body region and the upper surface of the second body region located in the first body region. This ensures that the peak doping concentration of impurity particles is located in the body region, keeping the peak concentration region of impurity particles away from the upper surface of the semiconductor layer with the greatest trench stress, thus guaranteeing the consistency of the device threshold voltage. The second body region is formed by high-energy implantation, followed by inverted doping, so that the doping concentration of the conductive channel is higher than that of the bottom of the body region, suppressing the short-channel effect. This effectively reduces the short-circuit current during short-circuit events without affecting the normal conduction of the conductive channel. Furthermore, the use of the same shielding layer and rapid annealing during the formation of the second body region and the emitter region reduces manufacturing costs, minimizes the thermal process, and reduces the impact of stress generated during the thermal process. Simultaneously, the fabrication method of the insulated gate bipolar transistor of this invention reduces the impact of thermal stress and trench stress on the device threshold, suppresses the short-channel effect, and is suitable for the fabrication of transistors with high trench density. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0151] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an insulated gate bipolar transistor, characterized in that, Includes the following steps: A semiconductor layer is provided, the semiconductor layer including a first conductivity type substrate and a dielectric layer with an opening, the substrate being divided in a horizontal direction into a cell region, a terminal region and a transition region located between the cell region and the terminal region, the upper surface of the transition region and the terminal region being provided with at least one second conductivity type ring region, and the dielectric layer being located on the upper surface of the terminal region, the opening of the dielectric layer exposing the ring region; Based on the dielectric layer, ion implantation of a second conductivity type is performed on the upper surface of the semiconductor layer to obtain a first body region located on the upper surface of the cell region and the transition region, the first body region being in contact with the ring region; A shielding layer is formed on the upper surface of the semiconductor layer to expose the cell region. A second body region of a second conductivity type is formed in the cell region based on the shielding layer. The bottom surface of the second body region is located below the first body region, and the upper surface of the second body region is located in the first body region. The first body region and the second body region constitute a body region. Based on the shielding layer, a first conductivity type emission region is formed on the upper surface of the first body region in the cell region, and the emission region and the second body region are subjected to rapid annealing.

2. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: The method for forming the first body region includes ion implantation, and the method for forming the second body region includes ion implantation.

3. The method for fabricating an insulated gate bipolar transistor according to claim 2, characterized in that: The ion implantation energy range for forming the first body region is 60 keV to 160 keV, and the ion implantation dose range is 5 × 10⁻⁶. 12 / cm 2 ~5×10 13 / cm 2 The ion implantation energy range for forming the second body region is 400 keV to 1.2 MeV, and the ion implantation dose range is 5 × 10⁻⁶. 12 / cm 2 ~5×10 13 / cm 2 .

4. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: After forming the first body region and before forming the shielding layer, the method further includes the step of forming a plurality of spaced trench structures in the cell region.

5. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: After annealing the emission region and the second body region, the process further includes the step of forming a plurality of spaced trench structures in the cell region.

6. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: It also includes the step of forming a first conductivity type carrier storage layer below the body region based on the shielding layer, wherein the upper surface of the carrier storage layer is in contact with the lower surface of the body region.

7. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: The material of the shielding layer includes photoresist.

8. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: The method for forming the ring region includes lateral doping.

9. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: It also includes the step of forming multiple emitter contact holes and terminal contact holes, wherein the bottom of the emitter contact holes extends into the first body region and the bottom of the terminal contact holes extends into the annular region.

10. An insulated-gate bipolar transistor, characterized in that, The insulated gate bipolar transistor is fabricated using the method for fabricating an insulated gate bipolar transistor as described in any one of claims 1 to 9, comprising: A semiconductor layer includes a first conductivity type substrate, a cell region, a terminal region, and a transition region located between the cell region and the terminal region. At least one second conductivity type ring region is provided on the upper surface of the transition region and the terminal region. Multiple spaced-apart trench structures are located in the cell region; The body region is composed of a first body region of the second conductivity type and a second body region of the second conductivity type. The first body region is located on the upper surface of the cell region and the transition region. The first body region is in contact with the ring region. The bottom surface of the second body region is located below the first body region. The upper surface of the second body region is located in the first body region. The first conductivity type emission region is located on the upper surface layer of the first body region.

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