Split-gate flash memory and method of manufacturing the same

Abstract

The application provides a split-gate flash memory and a manufacturing method thereof. The memory comprises a semiconductor substrate, has an active region and an isolation structure, and part of the surface of the isolation structure is lower than the surface of the active region to form a groove; a coupling medium layer covers the top and sidewall of the active region; a floating gate is located on the surface of the coupling medium layer and surrounds the top and sidewall of the active region and does not completely fill the groove; an inter-electrode medium layer is located on the surface of the floating gate; a control gate is located on the surface of the inter-electrode medium layer and fills the remaining part of the groove; a word line is located on the sidewall of the floating gate and the control gate; and a tunneling medium layer is located between the word line and the floating gate, the control gate and the substrate. The application enhances the control force by three-dimensionally surrounding the channel with the floating gate, reduces the risk of punch-through, increases the coupling rate by filling the groove with the control gate, reduces the operating voltage, and improves the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a gate-divided flash memory and its manufacturing method. Background Technology

[0002] Flash memory, as a type of non-volatile memory, is widely used in various electronic devices because it retains data even when power is off and has electrically erasable and rewritable characteristics. With the continuous miniaturization of semiconductor process nodes, the industry has placed higher demands on the integration density, power consumption, erasure and write efficiency, and reliability of flash memory.

[0003] Currently, the mainstream split-gate flash memory cell structures each have their own advantages and disadvantages. Please refer to... Figure 1 The second-generation ESF2 (Extra Flash Memory) structure not only has a larger device area, but also higher dynamic power consumption during read operations, making it difficult to meet the requirements of low-power applications. Please refer to [reference needed]. Figure 2 While the third-generation ESF3 flash memory structure has a relatively small device area, its manufacturing process is complex, and the excessively high source line (SL) resistance affects device performance. Please refer to [reference needed]. Figure 3 Although the fourth-generation ultra-fast flash memory (ESF4, similar to a low threshold voltage cell) has a relatively simple process, its device area is large, and it also suffers from the problem of excessive source line resistance.

[0004] Furthermore, as memory cell sizes continue to shrink, the lateral diffusion effect of the source / drain junction (S / D junction) becomes increasingly significant. This not only easily leads to severe punch-through risks but also causes a shift in the floating gate threshold voltage (Vtfg shift), thus severely compressing the operating window of the memory cell and reducing product yield and reliability. Meanwhile, the erase efficiency of traditional floating gate structures is often limited by the structure itself, making further improvements difficult.

[0005] Therefore, the industry urgently needs a new flash memory storage structure and its manufacturing process to simplify the process, be compatible with existing processes, effectively improve the floating gate's control over the channel, reduce the risk of punch-through, and improve erasure efficiency and product reliability. Summary of the Invention

[0006] To address the technical problems faced by existing segmented flash memories as device sizes continue to shrink, such as severe short-channel effects, high risk of punch-through, lateral diffusion of source-drain junctions leading to floating gate threshold voltage shift, reduced operating window, high read power consumption, and complex manufacturing processes, the present invention aims to provide a novel segmented flash memory and its manufacturing method to improve the floating gate's control over the channel, increase coupling efficiency, and simplify the manufacturing process.

[0007] This invention provides a gate-divided flash memory, comprising:

[0008] A semiconductor substrate having an active region and an isolation structure, wherein a portion of the surface of the isolation structure is lower than the surface of the active region to form a groove between adjacent active regions and expose a portion of the sidewalls of the active region.

[0009] A coupling dielectric layer covers the top of the active region and the exposed sidewalls of the active region;

[0010] A floating gate is located on the surface of the coupling dielectric layer, the floating gate surrounds the top of the active region and the exposed sidewalls of the active region, and does not completely fill the groove;

[0011] An inter-electrode dielectric layer is located on the surface of the floating gate;

[0012] A control gate is located on the surface of the inter-electrode dielectric layer, and the control gate extends downward and fills the remaining portion of the groove;

[0013] The tunneling dielectric layer is located on the sidewall of the floating grid;

[0014] The character line is located on the sidewall of the tunneling medium layer;

[0015] The source and drain doped regions are located within the semiconductor substrate on both sides of the word line and the floating gate.

[0016] Preferably, the floating gate, the control gate, and the word line are made of polycrystalline silicon.

[0017] Preferably, the inter-electrode dielectric layer comprises a silicon oxide-silicon nitride-silicon oxide composite layer.

[0018] Preferably, it further includes a hard mask layer located on top of the control gate above the groove.

[0019] Preferably, the material of the hard mask layer includes silicon nitride.

[0020] Preferably, it further includes a source / drain sidewall located on the sidewall of the word line away from the floating grid and the sidewall of the control grid away from the word line.

[0021] The present invention also provides a method for manufacturing a gate-divided flash memory, comprising:

[0022] Step 1: Provide a semiconductor substrate, wherein an active region and an isolation structure are formed within the semiconductor substrate;

[0023] Step 2: Etch a portion of the isolation structure so that the surface of a portion of the isolation structure is lower than the surface of the active region, thereby forming a groove between adjacent active regions and exposing a portion of the sidewalls of the active region;

[0024] Step 3: Form a coupling dielectric layer on the top of the active region and the exposed sidewalls of the active region;

[0025] Step 4: A first conductive layer is formed on the surface of the coupling dielectric layer. The first conductive layer surrounds the top of the active region and the exposed sidewalls of the active region, and does not completely fill the groove.

[0026] Step 5: Sequentially form an inter-electrode dielectric layer and a second conductive layer on the surface of the first conductive layer, wherein the second conductive layer fills the remaining portion of the groove;

[0027] Step 6: Pattern the second conductive layer, the inter-electrode dielectric layer, and the first conductive layer to form a control gate and a floating gate;

[0028] Step 7: Form a tunneling dielectric layer on the exposed surface of the floating grid, and form a third conductive layer as a word line on the sidewall of the tunneling dielectric layer;

[0029] Step 8: Form source / drain doped regions in the semiconductor substrate on both sides of the word line and the floating gate.

[0030] Preferably, in step one, forming the active region and the isolation structure includes: sequentially forming a first mask layer and a second mask layer on the surface of the semiconductor substrate; patterning the second mask layer, the first mask layer and the semiconductor substrate to form a trench; filling the trench with an isolation medium and performing planarization treatment to expose the second mask layer to form the isolation structure.

[0031] Preferably, the first mask layer includes a base oxide layer, and the second mask layer includes a base silicon nitride layer.

[0032] Preferably, in step two, before etching the isolation structure, the second mask layer is removed.

[0033] Preferably, in step five, after forming the second conductive layer, a hard mask layer is further formed on the surface of the second conductive layer.

[0034] Preferably, in step six, the patterning process includes: first, patterning the hard mask layer so that the patterned hard mask layer remains on the second conductive layer above the groove; using the patterned hard mask layer as a mask, continuously etching the second conductive layer, the inter-electrode dielectric layer, and the first conductive layer using an integrated etching process.

[0035] Preferably, in step eight, before forming the source / drain doped regions, the method further includes: depositing a sidewall dielectric layer and etching it to form source / drain sidewalls on the sidewalls of the word lines away from the floating gate and on the sidewalls of the control gate away from the word lines.

[0036] As described above, the gate-divided flash memory and its manufacturing method of the present invention have the following beneficial effects:

[0037] The present invention provides a multi-gate flash memory and its manufacturing method, which significantly enhances the electrostatic control capability of the floating gate over the channel region by extending the floating gate downward and three-dimensionally surrounding the top and sidewalls of the active region. This effectively reduces the short-channel effect and punch-through risk caused by device size reduction. Simultaneously, the control gate extends downward and fills the remaining portion of the groove between adjacent active regions, significantly increasing the contact area between the control gate and the floating gate, thereby significantly improving the capacitive coupling rate and effectively reducing the device's operating voltage and power consumption. Furthermore, the manufacturing method of the present invention uses an integrated etching process to continuously etch the control gate and the floating gate, which not only simplifies the manufacturing process and has good compatibility with existing embedded flash memory processes, but also reduces multiple high-temperature furnace tube processes, lowering manufacturing costs and thermal budget. Ultimately, it effectively suppresses the floating gate threshold voltage shift caused by lateral diffusion of the source-drain junction, expands the operating window of the memory cell, and comprehensively improves the product yield and long-term reliability. Attached Figure Description

[0038] Figure 1 The diagram shows a cross-sectional view of the existing second-generation super flash memory (ESF2) structure;

[0039] Figure 2 The diagram shows a cross-sectional view of the existing third-generation ultra-flash memory (ESF3) structure.

[0040] Figure 3 The diagram shows a cross-sectional view of the fourth-generation ESF4 (Extra Flash Memory) structure in the prior art.

[0041] Figure 4 The diagram shows a process flow diagram of the method for forming a gated flash memory according to an embodiment of the present invention.

[0042] Figure 5 The diagram shows a cross-sectional view after the formation of the first mask layer and the second mask layer according to an embodiment of the present invention;

[0043] Figure 6 The diagram shows a cross-sectional view of the trench formed according to an embodiment of the present invention.

[0044] Figure 7 The diagram shown is a cross-sectional view of the isolation structure formed according to an embodiment of the present invention.

[0045] Figure 8 The diagram shows a cross-sectional view after removing the second mask layer according to an embodiment of the present invention.

[0046] Figure 9 The diagram shows a cross-sectional view in the Y direction after the etching of the isolation structure in an embodiment of the present invention.

[0047] Figure 10 The diagram shows a cross-sectional view in the X direction after the hard mask layer is formed according to an embodiment of the present invention.

[0048] Figure 11 The diagram shows a cross-sectional view in the Y direction after the hard mask layer is formed according to an embodiment of the present invention.

[0049] Figure 12 The diagram shows a cross-sectional view of the control grid and floating grid after patterning according to an embodiment of the present invention.

[0050] Figure 13 The diagram shows a cross-sectional view after the formation of the tunneling dielectric layer and the third conductive layer according to an embodiment of the present invention.

[0051] Figure 14 The diagram shows a cross-sectional view of the third conductive layer after planarization according to an embodiment of the present invention.

[0052] Figure 15 The diagram shown is a cross-sectional view of the word line and source / drain doped regions after forming according to an embodiment of the present invention. Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] Please refer to Figure 15 A gate-divided flash memory includes a semiconductor substrate 101 having an active region and an isolation structure 104, wherein a portion of the surface of the isolation structure 104 is lower than the surface of the active region to form a groove between adjacent active regions and expose a portion of the active region sidewalls.

[0055] In some embodiments, the semiconductor substrate 101 may be a silicon substrate, and may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates. The semiconductor substrate 101 may have a P-type doped well region or an N-type doped well region pre-formed within it, depending on the conductivity type of the device, and may even include a deep well region for providing deep electrical isolation. The isolation structure 104 is typically configured as a shallow trench isolation structure. Its main function is to provide reliable physical and electrical isolation between adjacent active regions in a high-density memory array, preventing leakage or crosstalk between adjacent memory cells. This specific recessed topography design exposes the top and part of the sidewalls of the active region in three-dimensional space, allowing the subsequently formed gate material to wrap around the active region from multiple directions. This three-dimensional wrapping structure increases the physical contact area between the gate and the channel region, enhancing the gate's electric field coupling capability and control over the channel carriers.

[0056] The coupling medium layer 105 covers the top of the active region and the exposed sidewalls of the active region.

[0057] In some embodiments, the material of the coupling dielectric layer 105 may include silicon oxide, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, or a dielectric material with a high dielectric constant, such as hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, or silicates and aluminates of these materials. The coupling dielectric layer 105 acts as a tunnel dielectric layer in a gate-based flash memory. As a channel for charge transfer, the quality of the coupling dielectric layer 105 directly affects the programming and erasing efficiency of the memory cell and its data retention capability. Using high-quality thermal silicon oxide or a high-dielectric-constant material can effectively suppress direct tunneling leakage current in the data retention state while ensuring smooth Fowler-Nordheim tunneling or hot electron injection during programming and erasing operations, thereby extending the memory's data retention lifetime.

[0058] A floating gate 106 is located on the surface of the coupling dielectric layer 105. The floating gate 106 surrounds the top of the active region and the exposed sidewalls of the active region, and does not completely fill the groove.

[0059] In some embodiments, the floating gate 106 is made of polycrystalline silicon.

[0060] In other embodiments, the material of the floating gate 106 may also include amorphous silicon, doped polycrystalline silicon, polycrystalline silicon-germanium alloy, or composite materials containing metal nanocrystals. In some advanced process nodes, the floating gate 106 may also employ a work function metal material, such as titanium nitride, tantalum nitride, tantalum carbide, tungsten, cobalt, or ruthenium, to further adjust the threshold voltage of the device and reduce the gate resistance. The structural features of the floating gate 106 surrounding the top and sidewalls of the active region form a three-dimensional enclosure configuration. The channel beneath the floating gate 106 is three-dimensionally surrounded by the floating gate 106. This configuration significantly increases the electrostatic control capability of the floating gate 106 over the channel region below, greatly reducing the increasingly severe short-channel effect and punch-through risk as memory cell sizes continue to shrink. Simultaneously, the floating gate 106 does not completely fill the recess, providing the necessary physical space for the subsequent downward extension of the control gate 108.

[0061] Interpolar dielectric layer 107 is located on the surface of floating gate 106.

[0062] In some embodiments, the inter-electrode dielectric layer 107 includes a silicon oxide-silicon nitride-silicon oxide composite layer.

[0063] In other embodiments, the inter-electrode dielectric layer 107 may also employ other multilayer stacked structures, such as a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide composite layer, or a composite layer containing a high dielectric constant material, such as a silicon oxide-hafnium oxide-silicon oxide stack. The primary function of the inter-electrode dielectric layer 107 is to provide high capacitive coupling between the floating gate 106 and the control gate 108, allowing the voltage applied to the control gate 108 to be more effectively transferred to the floating gate 106. Simultaneously, the inter-electrode dielectric layer 107 needs to possess excellent insulation properties to prevent undesirable leakage of charge stored in the floating gate 106 to the control gate 108.

[0064] A control gate 108 is located on the surface of the inter-electrode dielectric layer 107, and the control gate 108 extends downward and fills the remainder of the groove.

[0065] In some embodiments, the control gate 108 is made of polycrystalline silicon.

[0066] In other embodiments, the material of the control gate 108 may also include doped polysilicon, metal silicides such as nickel silicide, cobalt silicide, titanium silicide, or low-resistivity metallic materials such as tungsten, aluminum, copper, or alloys thereof. The control gate 108 is used to receive a bias voltage applied by an external memory controller. Through the capacitive coupling of the inter-electrode dielectric layer 107, the control gate 108 can adjust the potential of the floating gate 106, thereby enabling programming, erasing, and reading operations on the memory cells. Using a low-resistivity material can effectively reduce signal transmission delay in the word line direction, improving the overall operating speed of the memory array. The control gate 108 extends downwards and fills the remaining portion of the recess; this nested structure design significantly increases the coupling rate of the control gate 108 to the floating gate 106, thereby effectively reducing the operating voltage of the device and improving the overall energy efficiency of the device.

[0067] In some embodiments, a hard mask layer 109 is also included, which is located on top of the control gate 108 above the recess.

[0068] In some embodiments, the material of the hard mask layer 109 includes silicon nitride.

[0069] The hard mask layer 109 is mainly used as an etching barrier layer during the manufacturing process. When retained in the final device structure, it can provide physical protection for the top of the control gate 108, prevent subsequent contact hole etching processes from damaging the control gate 108, and improve the integrity of the device structure.

[0070] The character line 111 is located on the sidewall of the floating gate 106 and the control gate 108.

[0071] In some embodiments, the material of word line 111 includes polycrystalline silicon.

[0072] In other embodiments, the word line 111 may also be made of doped polysilicon, metal silicide, or a metallic material. The word line 111 acts as a select gate in the split-gate structure, controlling the switching on and off of the select transistors within the memory cell. By independently configuring the word line 111 on the sidewall of the floating gate 106, the read current of the memory cell is jointly controlled by the word line 111 and the floating gate 106. This split-gate design effectively suppresses the over-erasure problem common in traditional stacked gate structures. Even if the floating gate 106 is over-erased, causing the channel beneath it to be depleted, the channel beneath the word line 111 remains closed, thus avoiding leakage across the entire memory column and improving the accuracy of read operations and the reliability of the array.

[0073] The tunneling dielectric layer 110 is located between the word line 111 and the floating gate 106, the control gate 108 and the semiconductor substrate 101.

[0074] The tunneling dielectric layer 110 serves as the coupling and isolation medium between the word line 111 and the floating gate 106 and control gate 108, and may include high-temperature silicon oxide, free radical silicon oxide, or a high-dielectric-constant dielectric material formed by atomic layer deposition. The tunneling dielectric layer 110 needs to have a sufficiently high breakdown voltage and a low defect density to prevent high-voltage breakdown or leakage between the word line 111 and the floating gate 106 or control gate 108 during programming or erasing operations.

[0075] In some embodiments, a source drain sidewall 112 is also included, which is located on the sidewall of word line 111 away from floating gate 106 and on the sidewall of control gate 108 away from word line 111.

[0076] The source / drain sidewall 112 can be a single-layer structure or an L-type or D-type multilayer composite structure containing silicon oxide and silicon nitride. The main function of the source / drain sidewall 112 is to provide self-aligned physical masking in the subsequent source / drain ion implantation process, precisely control the lateral distance between the heavily doped region and the gate edge, thereby optimizing the short-channel performance and hot carrier injection efficiency of the device.

[0077] The source / drain doped regions 113 are located within the semiconductor substrate 101 on both sides of the word line 111 and the floating gate 106.

[0078] The conductivity type of the source / drain doped region 113 is opposite to that of the well region of the semiconductor substrate 101. For example, for an N-type memory cell, the source / drain doped region 113 may include N-type dopants such as phosphorus, arsenic, or antimony; for a P-type memory cell, the source / drain doped region 113 may include P-type dopants such as boron, boron difluoride, or indium. The source / drain doped region 113 may include a lightly doped drain region near the channel and a heavily doped region away from the channel. By optimizing the size of the source / drain sidewalls 112 and the ion implantation process parameters, the floating gate threshold voltage offset caused by lateral diffusion of the source / drain junction is effectively reduced. Compared with traditional memory cell architectures, the structure provided in this embodiment can greatly increase the operating window of the memory cell, improve the overall yield of the memory array, and enhance the reliability of the product during long-term use.

[0079] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the process flow for a method of forming a gate-divided flash memory provided in an embodiment of the present invention.

[0080] A method for manufacturing a gate-divided flash memory includes:

[0081] Step 1: Provide a semiconductor substrate 101, in which an active region and an isolation structure 104 are formed.

[0082] In some embodiments, step one, forming the active region and isolation structure 104 includes: Please refer to Figure 5A first mask layer 102 and a second mask layer 103 are sequentially formed on the surface of the semiconductor substrate 101; please refer to Figure 6 The second mask layer 103, the first mask layer 102, and the semiconductor substrate 101 are patterned to form trenches; please refer to Figure 7 The trench is filled with an isolation medium and planarized until the second mask layer 103 is exposed, forming an isolation structure 104.

[0083] In some embodiments, the first mask layer 102 includes a base oxide layer, and the second mask layer 103 includes a base silicon nitride layer.

[0084] Semiconductor manufacturing equipment can perform the above-described process steps. Specifically, the first mask layer 102 can be formed by performing a dry oxygen or wet oxygen thermal oxidation process in a high-temperature furnace tube. The first mask layer 102 mainly serves to buffer the lattice stress between the semiconductor substrate 101 and subsequent deposited layers, and to protect the surface of the semiconductor substrate 101 from contamination. The second mask layer 103 can be formed by a low-pressure chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process. The second mask layer 103 has high hardness and etching resistance, and serves as a reliable stop layer in the subsequent chemical mechanical polishing process. The patterning process includes coating the surface of the second mask layer 103 with photoresist, defining the pattern of the active region through exposure and development processes, and then using an anisotropic dry etching process containing fluorine-based or chlorine-based gases in an etching chamber to sequentially penetrate the second mask layer 103, the first mask layer 102, and penetrate deep into the semiconductor substrate 101 to form trenches with a certain depth and sidewall angle. The filling of the isolation medium can be accomplished through high-density plasma chemical vapor deposition (PDCVD), flowable PDCVD, or spin-coating processes to ensure that the high aspect ratio trenches are filled without voids. After filling, a high-temperature annealing process is typically performed to densify the isolation medium, and finally, a chemical mechanical polishing (CMP) process is used to remove excess isolation medium from the outside of the trenches, achieving global surface planarization.

[0085] Step 2: Etch part of the isolation structure 104 so that the surface of part of the isolation structure 104 is lower than the surface of the active region, so as to form a groove between adjacent active regions and expose part of the active region sidewall.

[0086] In some embodiments, step two, before etching the partial isolation structure 104, includes [refer to...]. Figure 8 Remove the second mask layer 103.

[0087] Removing the second mask layer 103 typically employs a wet etching process, such as immersing the semiconductor substrate 101 in a heated phosphoric acid solution. This solution has extremely high etching selectivity for silicon nitride, enabling complete removal of the second mask layer 103 without damaging the isolation dielectric and the first mask layer 102. Please refer to [reference needed]. Figure 9 , Figure 9 A cross-sectional structure spanning multiple active regions along the Y-direction is shown. Subsequently, semiconductor manufacturing equipment performs an etch-back process on the isolation structure 104. The etch-back process can employ a wet etching process containing dilute hydrofluoric acid or a buffered oxide etchant, or a chemical dry etching process based on the reaction of hydrogen fluoride and ammonia. By precisely controlling the etching time, solution concentration, or gas flow rate, the etch-back depth of the isolation structure 104 can be accurately controlled. This crucial step causes the top and part of the sidewalls of the active regions to protrude from the surrounding surface of the isolation structure 104, forming grooves between adjacent active regions, providing the necessary physical space and structural foundation for the subsequent formation of the three-dimensional enveloping floating gate 106.

[0088] Step 3: Form a coupling medium layer 105 on the top of the active region and the exposed sidewalls of the active region.

[0089] Before forming the coupling dielectric layer 105, semiconductor manufacturing equipment typically performs a pre-cleaning process, such as using RCA cleaning fluid to remove particles, organic matter, metal ions, residual first mask layer 102, and native oxides from the surface of the semiconductor substrate 101, exposing the semiconductor lattice surface. Subsequently, the coupling dielectric layer 105 is formed through in-situ vapor-generated thermal oxidation, rapid thermal oxidation, or plasma oxidation. These advanced oxidation processes can grow a dielectric layer with uniform thickness, density, and extremely low interface state density on the top of the active region and the exposed sidewalls. A high-quality coupling dielectric layer 105 plays a crucial role in ensuring the erase / write lifetime and data retention characteristics of the memory cells.

[0090] Step 4: A first conductive layer 106 is formed on the surface of the coupling dielectric layer 105. The first conductive layer 106 surrounds the top of the active region and the exposed sidewalls of the active region, and does not completely fill the groove.

[0091] The first conductive layer 106 can be formed by depositing polycrystalline silicon material using a low-pressure chemical vapor deposition (LPCVD) process. During deposition, silane or disilane can be introduced as a precursor gas, and phosphine or diborane can be introduced simultaneously for in-situ doping to adjust the conductivity of the first conductive layer 106. The deposition thickness is precisely calculated and controlled so that the first conductive layer 106 conformally covers the surface of the active region, but the groove space between adjacent active regions is not completely filled. Subsequently, a chemical mechanical polishing (CMP) process can be used for planarization. The planarization process can be stopped at a specific thickness by controlling the polishing time, thereby forming mutually isolated first conductive layers 106 with flat tops. At this point, the first conductive layer 106 completely covers the protruding portions of the active region from the top and sides, increasing the controllability of the channel.

[0092] Step 5: An inter-electrode dielectric layer 107 and a second conductive layer 108 are sequentially formed on the surface of the first conductive layer 106, and the second conductive layer 108 fills the remaining part of the groove.

[0093] In some embodiments, step five, after forming the second conductive layer 108, further includes forming a hard mask layer 109 on the surface of the second conductive layer 108.

[0094] Please refer to Figure 10 and Figure 11 , Figure 10 The cross-sectional structure along the X-direction, i.e., parallel to the active region direction, is shown. Figure 11 The cross-sectional structure along the Y direction, spanning multiple active regions, is shown. The inter-electrode dielectric layer 107 can be formed using a multi-step deposition process. For example, a bottom layer of silicon oxide, an intermediate layer of silicon nitride, and a top layer of silicon oxide can be deposited sequentially using low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). ALD provides atomic-level thickness control and excellent step coverage, ensuring that the inter-electrode dielectric layer 107 forms a uniform conformal coverage on the surface of the first conductive layer 106. The second conductive layer 108 can also be formed by depositing doped polycrystalline silicon or a metallic material using a chemical vapor deposition process. Since the first conductive layer 106 does not completely fill the trench, the second conductive layer 108 extends downwards during deposition and completely fills the remaining portion of the trench. This nested structure significantly increases the contact area between the second conductive layer 108 and the first conductive layer 106, thereby improving the coupling efficiency. The hard mask layer 109 can be formed by depositing silicon nitride, silicon oxynitride, or amorphous carbon material using a plasma-enhanced chemical vapor deposition (PECVD) process. The hard mask layer 109 serves as a hard mask in subsequent complex etching processes to precisely transfer the pattern of the control gate 108 and protect the underlying second conductive layer 108 from erosion by etching gases.

[0095] Step 6: Pattern the second conductive layer 108, the inter-electrode dielectric layer 107 and the first conductive layer 106 to form the control gate 108 and the floating gate 106.

[0096] In some embodiments, step six, the patterning process includes: first, patterning the hard mask layer 109 so that the patterned hard mask layer 109 is retained on the second conductive layer 108 above the groove; using the patterned hard mask layer 109 as a mask, the second conductive layer 108, the inter-electrode dielectric layer 107 and the first conductive layer 106 are continuously etched using an integrated etching process.

[0097] Please refer to Figure 12In this semiconductor manufacturing process, a photoresist pattern is formed on the surface of a hard mask layer 109 using photolithography. Then, an anisotropic dry etching process is employed in the etching chamber to pattern the hard mask layer 109. The hard mask layer 109 is precisely positioned above the groove and used as a mask for continuous, integrated etching. During etching, the balance between physical bombardment and chemical polymer deposition rates can be controlled by finely adjusting the mixing ratio of etching gases (e.g., the ratio of hydrogen bromide, chlorine, and oxygen), RF bias power, and chamber pressure. This dynamic balance ensures the perpendicularity and alignment accuracy of the control gate 108 and floating gate 106 sidewalls. This integrated etching process is simple and highly compatible with existing embedded flash memory technologies. By optimizing process steps and structural design, this method reduces four high-temperature furnace tube processes, significantly lowering manufacturing costs and production cycles, and minimizing the adverse impact of overall thermal budget on device performance.

[0098] Step 7: Form a tunneling dielectric layer 110 on the exposed surface after patterning, and form a third conductive layer as word line 111 on the sidewall of the tunneling dielectric layer 110.

[0099] Please refer to Figure 13 The tunneling dielectric layer 110 can be conformally formed on all exposed surfaces using a high-temperature oxidation process, an in-situ vapor generation process, or a chemical vapor deposition process. The high-temperature oxidation process can consume a portion of the silicon material on the sidewalls of the floating gate 106, forming a dense silicon oxide layer with excellent interface quality. The third conductive layer can be formed by depositing doped polysilicon using a chemical vapor deposition process; the deposition thickness needs to be sufficient to cover the sidewalls of the entire gate stack structure. Please refer to [reference needed]. Figure 14 Subsequently, the third conductive layer is planarized using chemical mechanical polishing or isotropic etching back to remove excess conductive material from the top of the control gate 108. Finally, the unwanted areas of the third conductive layer are removed using photolithography and anisotropic dry etching, leaving conductive material on the sidewalls of the tunneling dielectric layer 110 to form the word line 111. This word line 111 manufacturing method, similar to the sidewall formation process, enables self-alignment control of the word line 111 width, reducing the impact of photolithographic alignment deviations.

[0100] Step 8: Form source / drain doped regions 113 in the semiconductor substrate 101 on both sides of word line 111 and floating gate 106.

[0101] In some embodiments, step eight, before forming the source / drain doped region 113, further includes: depositing a sidewall dielectric layer and etching it to form source / drain sidewalls 112 on the sidewalls of word line 111 away from floating gate 106 and on the sidewalls of control gate 108 away from word line 111.

[0102] Please refer to Figure 15The formation process of the source / drain sidewalls 112 includes conformal deposition of dielectric materials and anisotropic etch-back. Before forming the source / drain sidewalls 112, the semiconductor manufacturing equipment can first perform a low-dose ion implantation process to form a lightly doped drain region within the semiconductor substrate 101 to alleviate the electric field concentration effect at the drain edge. After forming the source / drain sidewalls 112, a high-dose ion implantation process is then performed to form a heavily doped source / drain doped region 113. The implanted impurity ions can include arsenic, phosphorus, or boron, etc. After implantation, the semiconductor manufacturing equipment performs a rapid thermal annealing process, a spike annealing process, or a laser annealing process. These short-duration high-temperature treatments can effectively limit the lateral diffusion of impurity ions while activating the implanted impurities and repairing semiconductor lattice damage, reducing the risk of punch-through and providing a preferred solution for manufacturing high-density, high-performance, and high-reliability gate-divided flash memory.

[0103] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A grid-splitting flash memory, characterized in that, include: A semiconductor substrate having an active region and an isolation structure, wherein a portion of the surface of the isolation structure is lower than the surface of the active region to form a groove between adjacent active regions and expose a portion of the sidewalls of the active region. A coupling dielectric layer covers the top of the active region and the exposed sidewalls of the active region; A floating gate is located on the surface of the coupling dielectric layer, the floating gate surrounds the top of the active region and the exposed sidewalls of the active region, and does not completely fill the groove; An inter-electrode dielectric layer is located on the surface of the floating gate; A control gate is located on the surface of the inter-electrode dielectric layer, and the control gate extends downward and fills the remaining portion of the groove; The tunneling dielectric layer is located on the sidewall of the floating grid; The character line is located on the sidewall of the tunneling medium layer; The source and drain doped regions are located within the semiconductor substrate on both sides of the word line and the floating gate.

2. The gate-division flash memory according to claim 1, characterized in that: The floating gate, the control gate, and the word line are made of polycrystalline silicon.

3. The gate-division flash memory according to claim 1, characterized in that: The inter-electrode dielectric layer comprises a silicon oxide-silicon nitride-silicon oxide composite layer.

4. The gate-division flash memory according to claim 1, characterized in that: It also includes a hard mask layer located on top of the control gate above the recess.

5. The gate-division flash memory according to claim 4, characterized in that: The material of the hard mask layer includes silicon nitride.

6. The gate-divided flash memory according to claim 1, characterized in that: It also includes source-drain sidewalls, which are located on the sidewalls of the word line away from the floating grid and on the sidewalls of the control grid away from the word line.

7. A method for manufacturing a segmented gate flash memory, characterized in that, include: Step 1: Provide a semiconductor substrate, wherein an active region and an isolation structure are formed within the semiconductor substrate; Step 2: Etch a portion of the isolation structure so that the surface of a portion of the isolation structure is lower than the surface of the active region, thereby forming a groove between adjacent active regions and exposing a portion of the sidewalls of the active region; Step 3: Form a coupling dielectric layer on the top of the active region and the exposed sidewalls of the active region; Step 4: A first conductive layer is formed on the surface of the coupling dielectric layer. The first conductive layer surrounds the top of the active region and the exposed sidewalls of the active region, and does not completely fill the groove. Step 5: Sequentially form an inter-electrode dielectric layer and a second conductive layer on the surface of the first conductive layer, wherein the second conductive layer fills the remaining portion of the groove; Step 6: Pattern the second conductive layer, the inter-electrode dielectric layer, and the first conductive layer to form a control gate and a floating gate; Step 7: Form a tunneling dielectric layer on the exposed surface of the floating grid, and form a third conductive layer as a word line on the sidewall of the tunneling dielectric layer; Step 8: Form source / drain doped regions in the semiconductor substrate on both sides of the word line and the floating gate.

8. The method for manufacturing a grid-splitter flash memory according to claim 7, characterized in that: In step one, forming the active region and the isolation structure includes: sequentially forming a first mask layer and a second mask layer on the surface of the semiconductor substrate; patterning the second mask layer, the first mask layer and the semiconductor substrate to form a trench; filling the trench with an isolation medium and performing planarization treatment to expose the second mask layer to form the isolation structure.

9. The method for manufacturing a segmented flash memory according to claim 8, characterized in that: The first mask layer includes a base oxide layer, and the second mask layer includes a base silicon nitride layer.

10. The method for manufacturing a grid-splitter flash memory according to claim 8, characterized in that: In step two, before etching the isolation structure, the second mask layer is removed.

11. The method for manufacturing a grid-splitter flash memory according to claim 7, characterized in that: In step five, after forming the second conductive layer, a hard mask layer is also formed on the surface of the second conductive layer.

12. The method for manufacturing a gate-divided flash memory according to claim 11, characterized in that: In step six, the patterning process includes: first, patterning the hard mask layer so that the patterned hard mask layer remains on the second conductive layer above the groove; using the patterned hard mask layer as a mask, continuously etching the second conductive layer, the inter-electrode dielectric layer and the first conductive layer using an integrated etching process.

13. The method for manufacturing a grid-splitter flash memory according to claim 7, characterized in that: In step eight, before forming the source / drain doped regions, the method further includes: depositing a sidewall dielectric layer and etching it to form source / drain sidewalls on the sidewalls of the word lines away from the floating gate and on the sidewalls of the control gate away from the word lines.

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