A constant root mean square voltage output circuit

Abstract

The present application relates to the field of integrated circuits, in particular to a constant root mean square voltage output circuit, the main purpose is to make the output power constant under different power supply voltage, and has the advantages of high efficiency, small area. The main scheme includes root mean square voltage generating circuit (1), first sawtooth wave generating circuit (2), first comparator (3), first inverter (4), second inverter (5), low pass filter circuit (6), second sawtooth wave generating circuit (7), second comparator circuit (8), power drive circuit (9), output stage circuit (10). The circuit of the present application is simple without complex peripheral circuit, which greatly reduces the circuit cost. The power loss is mainly derived from the conduction loss and switching loss of the first PMOS tube, which is very small compared with the output power, so the output efficiency is high.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a constant root mean square voltage output circuit. Background Technology

[0002] Electronic cigarettes, electronic igniters, and other electronic products achieve atomization and ignition by heating a heating wire. If a DC power supply is used to heat the heating wire directly, the wire's power will vary depending on the power supply voltage. While using a BUCK circuit can achieve a constant power output, it requires more external circuitry, significantly increasing circuit costs. Using an LDO (Light Filter Doppler) circuit can meet power and area requirements, but the LDO's low efficiency leads to energy loss.

[0003] For example, 2020110621901 discloses a constant root mean square voltage output device and method. The circuit contains a large number of digital circuits and the digital circuits have large system errors, so the circuit needs to be adjusted in the subsequent stages. Summary of the Invention

[0004] In view of the above, the purpose of this invention is to provide a constant root mean square voltage output circuit that can keep the output power constant under different power supply voltages, and has the advantages of high efficiency and small area.

[0005] To achieve the above objectives, the present invention employs the following technical means: To achieve the above objectives, the technical solution of the present invention is as follows: a constant root mean square voltage output circuit, comprising a root mean square voltage generating circuit, a first sawtooth wave generating circuit, a first comparator circuit, a first inverter circuit, a second inverter circuit, a low-pass filter circuit, a second sawtooth wave generating circuit, a second comparator circuit, a power drive circuit, and an output stage circuit. The output terminal of the root mean square voltage generating circuit is connected to the non-inverting input terminal of the first comparator; the root mean square voltage generating circuit outputs a preset constant root mean square voltage VRMS. The output terminal of the first sawtooth wave generating circuit is connected to the inverting input terminal of the first comparator; the first sawtooth wave generating circuit outputs a periodic sawtooth wave. The first comparator circuit has its non-inverting input connected to the output of the root mean square voltage generation circuit, and its inverting input connected to the output of the first sawtooth wave generation circuit. Its output is connected to the input of the first inverter. The first comparator circuit compares the first sawtooth wave with VRMS and outputs a first PWM wave with a duty cycle of VRMS / VCC. The high level of the output PWM wave is VCC, where VCC is the power supply voltage. The first inverter has its input terminal connected to the output terminal of the first comparator, and its output terminal connected to the input terminal of the second inverter. The second inverter has its input terminal connected to the output terminal of the first inverter, and its output terminal connected to the input terminal of the low-pass filter circuit. The power supply terminal of the second inverter is connected to VRMS, and it outputs a second PWM wave with a duty cycle of VRMS / VCC. The high level of the output second PWM wave is VRMS. The low-pass filter circuit has its input terminal connected to the output terminal of the second inverter and its output terminal connected to the non-inverting input terminal of the second comparator. The low-pass filter circuit filters out the high-frequency components of the input PWM wave and outputs a DC voltage VDC = VRMS * VRMS / VCC. The output terminal of the second sawtooth wave generating circuit is connected to the inverting input terminal of the second comparator; the second sawtooth wave generating circuit outputs a periodic sawtooth wave. The second comparator circuit has its non-inverting input connected to the output of the low-pass filter circuit, its inverting input connected to the output of the second sawtooth wave generation circuit, and its output connected to the input of the power drive circuit. The second comparator circuit compares the second sawtooth wave with VDC and outputs a third PWM wave with a duty cycle of VRMS*VRMS / (VCC*VCC). The high level of the output third PWM wave is VCC. The power drive circuit has its input terminal connected to the output terminal of the second comparator and its output terminal connected to the input of the output stage; the power drive circuit improves the driving capability of the input PWM wave. The output stage circuit has its input terminal connected to the output of the power drive circuit, and its output is OUT. The input of the output stage circuit is the gate of the first PMOS transistor, and the output is the drain of the first PMOS transistor. The source of the first PMOS transistor is connected to VCC, and the drain is connected to the load RL.

[0006] Furthermore, the root mean square voltage generation circuit includes a bandgap reference circuit, an operational amplifier circuit, a first resistor R1, a second resistor R2, and a second PMOS transistor; The output terminal of the bandgap reference circuit is connected to the inverting input terminal of the operational amplifier circuit; the bandgap reference circuit outputs a bandgap reference voltage (VREF) that is insensitive to power supply voltage and temperature. The operational amplifier circuit has its non-inverting input terminal connected to one end of R1, its inverting input terminal connected to the output terminal of the bandgap reference circuit, and its output terminal connected to the gate of the second PMOS transistor. The first resistor is connected between ground and the non-inverting input of the operational amplifier; The second resistor is connected between the non-inverting input of the operational amplifier and the drain of the second PMOS transistor; The second PMOS transistor has its gate connected to the output of the operational amplifier, its source connected to the power supply voltage VCC, and its drain connected to the second resistor.

[0007] Furthermore, the output voltage VRMS of the RMS voltage generation circuit is the drain voltage of the second PMOS transistor. The RMS voltage generation circuit clamps the voltage at the positive and negative input terminals of the operational amplifier by using the virtual short of the operational amplifier, so that the voltage on resistor R1 is equal to VREF. Therefore, the output voltage VRMS = VREF*(R2+R1) / R1.

[0008] Furthermore, the frequency of the sawtooth wave output by the first sawtooth wave generating circuit is lower than the upper limit frequency of the low-pass filter circuit.

[0009] Furthermore, the average power P of the fourth PWM wave output by the output stage circuit is P = VOUT * VOUT * VRMS * VRMS / (VCC * VCC * RL), and VOUT=VCC*(RL / (RL+Ron)), because If RL >> Ron, then P = VRMS * VRMS / RL In the formula, VOUT is the potential of the high level of the fourth PWM wave output; Ron is the on-resistance of the first PMOS transistor.

[0010] Furthermore, the power P of the output fourth PWM wave is a quantity independent of VCC, and the average output power remains constant when VCC changes.

[0011] Furthermore, the frequency of the fourth PWM wave output by the output stage circuit is the same as the frequency of the sawtooth wave output by the second sawtooth wave generation circuit, and the frequency of the fourth PWM wave is adjusted by adjusting the frequency of the second sawtooth wave generation circuit.

[0012] The beneficial effects of this invention are as follows: This invention discloses a constant root mean square voltage output circuit. A first comparator compares a first sawtooth wave with VRMS and outputs a first PWM wave with a duty cycle of VRMS / VCC and a high level of VCC. After the output PWM wave is level-shifted by an inverter and low-pass filtered, it outputs a DC voltage VDC = VRMS*VRMS / VCC. Then, VDC is compared with a second sawtooth wave to output a third PWM wave with a duty cycle of VRMS*VRMS / (VCC*VCC). The third PWM wave is enhanced with driving capability and used to drive a PMOS power transistor, thereby obtaining an output signal whose average power does not change with the power supply voltage.

[0013] Because the present invention employs the above-mentioned technical means, it has the following beneficial effects: This invention provides a constant root mean square voltage output circuit. The circuit is simple and does not have complex external circuits, which greatly reduces the circuit cost.

[0014] The present invention discloses a constant root mean square voltage output circuit. The power loss mainly comes from the conduction loss and switching loss of the first PMOS transistor, which is very small relative to the output power. Therefore, the output efficiency is high.

[0015] This invention discloses a constant root-mean-square voltage output circuit. The circuit adopts an analog circuit design, without complex digital circuitry, and its principle is simple. The circuit system error mainly originates from the variation of the power transistor's on-resistance with the power supply voltage, but this is negligible compared to the load resistance. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the constant root mean square voltage output circuit of the present invention; Figure 2 This is a schematic diagram of the root mean square voltage generation circuit of the present invention; In the figure, 1 is the root mean square voltage generation circuit, 2 is the first sawtooth wave generation circuit, 3 is the first comparator circuit, 4 is the first inverter circuit, 5 is the second inverter circuit, 6 is the low-pass filter circuit, 7 is the second sawtooth wave generation circuit, 8 is the second comparator circuit, 9 is the power drive circuit, and 10 is the output stage circuit. Detailed Implementation

[0017] The embodiments of the present invention will be described in detail below. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, any modifications or equivalent substitutions made to the present invention should be covered within the scope of the claims of the present invention.

[0018] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without these specific details.

[0019] The following is combined with Figures 1 to 2 The present invention will be described in detail below. Example

[0020] like Figure 1 As shown, this embodiment provides a constant root mean square voltage output circuit, including a root mean square voltage generation circuit, a first sawtooth wave generation circuit, a first comparator circuit, a first inverter circuit, a second inverter circuit, a low-pass filter circuit, a second sawtooth wave generation circuit, a second comparator circuit, a power drive circuit, and an output stage circuit. The output terminal of the root mean square voltage generating circuit is connected to the non-inverting input terminal of the first comparator; the root mean square voltage generating circuit outputs a preset constant root mean square voltage VRMS. The output terminal of the first sawtooth wave generating circuit is connected to the inverting input terminal of the first comparator; the first sawtooth wave generating circuit outputs a periodic sawtooth wave. The first comparator circuit has its non-inverting input connected to the output of the root mean square voltage generation circuit, and its inverting input connected to the output of the first sawtooth wave generation circuit. Its output is connected to the input of the first inverter. The first comparator circuit compares the first sawtooth wave with VRMS and outputs a first PWM wave with a duty cycle of VRMS / VCC. The high level of the first PWM wave is VCC, where VCC is the power supply voltage. The first inverter has its input terminal connected to the output terminal of the first comparator, and its output terminal connected to the input terminal of the second inverter. The second inverter has its input terminal connected to the output terminal of the first inverter, and its output terminal connected to the input terminal of the low-pass filter circuit. The power supply terminal of the second inverter is connected to VRMS, and it outputs a second PWM wave with a duty cycle of VRMS / VCC. The high level of the output second PWM wave is VRMS. The low-pass filter circuit has its input terminal connected to the output terminal of the second inverter and its output terminal connected to the non-inverting input terminal of the second comparator. The low-pass filter circuit filters out the high-frequency components of the input PWM wave, and its output DC voltage VDC = VRMS*VRMS / VCC. The output terminal of the second sawtooth wave generating circuit is connected to the inverting input terminal of the second comparator; the second sawtooth wave generating circuit outputs a periodic sawtooth wave. The second comparator circuit has its non-inverting input connected to the output of the low-pass filter circuit, its inverting input connected to the output of the second sawtooth wave generation circuit, and its output connected to the input of the power drive circuit. The second comparator circuit compares the second sawtooth wave with VDC and outputs a third PWM wave with a duty cycle of VRMS*VRMS / (VCC*VCC). The high level of the output third PWM wave is VCC. The power drive circuit has its input terminal connected to the output terminal of the second comparator and its output terminal connected to the input of the output stage; the power drive circuit improves the driving capability of the input PWM wave. The output stage circuit has its input terminal connected to the output of the power drive circuit, and its output is OUT. The input of the output stage circuit is the gate of the first PMOS transistor, and the output is the drain of the first PMOS transistor. The source of the first PMOS transistor is connected to VCC, and the drain is connected to the load RL.

[0021] The working principle of this embodiment is as follows: The first comparator compares the first sawtooth wave with VRMS and outputs a first PWM wave with a duty cycle of VRMS / VCC and a high level of VCC. After the first PWM wave is level-shifted by an inverter and low-pass filtered, it outputs a DC voltage VDC = VRMS * VRMS / VCC. Then, VDC is compared with the second sawtooth wave to output a third PWM wave with a duty cycle of VRMS * VRMS / (VCC * VCC). The third PWM wave is enhanced with driving capability and used to drive the first PMOS transistor, outputting a fourth PWM wave with an average power P = VOUT * VOUT * VRMS * VRMS / (VCC * VCC * RL). Since VOUT = VCC * (RL / (RL + Ron)) and RL >> Ron, where VOUT is the high level of the fourth PWM wave and Ron is the on-resistance of the first PMOS transistor, the output average power is approximately P = VRMS * VRMS / RL, which is independent of the power supply voltage VCC and can remain basically constant.

[0022] For example, when Ron=40mΩ, RL=1Ω, the threshold voltage of the first PMOS transistor VTH=0.7V, and the power supply is 3.2V~4.2V, the change in Ron ΔRon=40mΩ*(1 / (3.2-0.7)-(1 / (4.2-0.7))=4.6mΩ, the change in output power ΔP=P*(1 / (1+0.0354)-1 / (1+0.04))=0.43%P, and the system error rate η=0.43% is almost negligible. Example

[0023] This embodiment is based on a constant root mean square voltage output circuit of Embodiment 1.

[0024] Specifically, see Figure 2 The root mean square voltage generation circuit includes a bandgap reference circuit, an operational amplifier circuit, a first resistor R1, a second resistor R2, and a second PMOS transistor; The output terminal of the bandgap reference circuit is connected to the inverting input terminal of the operational amplifier circuit; the bandgap reference circuit outputs a bandgap reference voltage (VREF) that is insensitive to power supply voltage and temperature. The operational amplifier circuit has its non-inverting input terminal connected to one end of the first resistor R1, its inverting input terminal connected to the output terminal of the bandgap reference circuit, and its output terminal connected to the gate of the second PMOS transistor. The first resistor R1 is connected between ground and the non-inverting input of the operational amplifier; The second resistor R2 is connected between the non-inverting input of the operational amplifier and the drain of the second PMOS transistor; The second PMOS transistor has its gate connected to the output of the operational amplifier, its source connected to the power supply voltage VCC, and its drain connected to the second resistor.

[0025] The RMS voltage generating circuit clamps the voltage at the positive and negative input terminals of the operational amplifier by using the virtual short of the operational amplifier, so that the voltage across the first resistor R1 is equal to VREF. Then the output RMS voltage VRMS = VREF*(R2+R1) / R1 is set by adjusting the ratio of the second resistor R2 to the first resistor R1.

[0026] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A constant root-mean-square voltage output circuit, characterized in that, It includes a root mean square voltage generation circuit (1), a first sawtooth wave generation circuit (2), a first comparator (3), a first inverter (4), a second inverter (5), a low-pass filter circuit (6), a second sawtooth wave generation circuit (7), a second comparator circuit (8), a power drive circuit (9), and an output stage circuit (10). The output terminal of the root mean square voltage generating circuit (1) is connected to the non-inverting input terminal of the first comparator (3); the root mean square voltage generating circuit outputs a preset constant root mean square voltage VRMS. The output terminal of the first sawtooth wave generating circuit is connected to the inverting input terminal of the first comparator (3); the first sawtooth wave generating circuit (2) outputs a periodic sawtooth wave, i.e., the first sawtooth wave; The output of the first comparator (3) is connected to the input of the first inverter (4); the first comparator (3) compares the first sawtooth wave with VRMS and outputs a first PWM wave with a duty cycle of VRMS / VCC, and the high level of the first PWM wave is VCC; The output terminal of the first inverter (4) is connected to the input terminal of the second inverter (5); The output terminal of the second inverter (5) is connected to the input terminal of the low-pass filter circuit (6); the power supply terminal of the second inverter is connected to VRMS, and the output duty cycle is VRMS / VCC of the second PWM wave, and the high level of the output second PWM wave is VRMS; The output terminal of the low-pass filter circuit (6) is connected to the non-inverting input terminal of the second comparator (8); the low-pass filter circuit (6) filters out the high-frequency components of the input PWM wave and outputs a DC voltage VDC = VRMS * VRMS / VCC; The output terminal of the second sawtooth wave generating circuit (7) is connected to the inverting input terminal of the second comparator (8); the second sawtooth wave generating circuit (7) outputs a periodic sawtooth wave, i.e., the second sawtooth wave; The output terminal of the second comparator (8) is connected to the input terminal of the power drive circuit (9); the second comparator (8) compares the second sawtooth wave with VDC and outputs a third PWM wave with a duty cycle of VRMS*VRMS / (VCC*VCC), and the high level of the output third PWM wave is VCC; The output terminal of the power drive circuit (9) is connected to the input of the output stage circuit (10); the power drive circuit improves the driving capability of the input PWM wave. The output stage circuit (10) outputs OUT; the input of the output stage circuit (10) is the gate of the first PMOS transistor, and the output is the drain of the first PMOS transistor. The source of the first PMOS transistor is connected to VCC, and the drain is connected to the load RL.

2. The constant root mean square voltage output circuit according to claim 1, characterized in that, The root mean square voltage generation circuit includes a bandgap reference circuit, an operational amplifier circuit, a first resistor R1, a second resistor R2, and a second PMOS transistor. The output terminal of the bandgap reference circuit is connected to the inverting input terminal of the operational amplifier circuit; the bandgap reference circuit outputs a bandgap reference voltage VREF that is insensitive to power supply voltage and temperature. The operational amplifier circuit has its non-inverting input terminal connected to one end of the first resistor R1, its inverting input terminal connected to the output terminal of the bandgap reference circuit, and its output terminal connected to the gate of the second PMOS transistor. The first resistor R1 is connected between ground and the non-inverting input of the operational amplifier; The second resistor R2 is connected between the non-inverting input of the operational amplifier and the drain of the second PMOS transistor; The second PMOS transistor has its gate connected to the output of the operational amplifier, its source connected to the power supply voltage VCC, and its drain connected to the second resistor R2.

3. The constant root mean square voltage output circuit according to claim 2, characterized in that, The output voltage VRMS of the root mean square voltage generation circuit is the drain voltage of the second PMOS transistor. The root mean square voltage generation circuit clamps the voltage at the positive and negative input terminals of the operational amplifier by using the virtual short of the operational amplifier, so that the voltage on the first resistor R1 is equal to VREF. Then the output voltage VRMS = VREF*(R2+R1) / R1. The value of VRMS is set by adjusting the ratio of the second resistor R2 to the first resistor R1.

4. The constant root mean square voltage output circuit according to claim 1, characterized in that, The frequency of the sawtooth wave output by the first sawtooth wave generating circuit is lower than the upper limit frequency of the low-pass filter circuit.

5. A constant root-mean-square voltage output circuit according to claim 1, characterized in that, The average power of the fourth PWM wave output by the output stage circuit (10) is P=VOUT*VOUT*VRMS*VRMS / (VCC*VCC*RL), and VOUT=VCC*(RL / (RL+Ron)), RL>>Ron, then P=VRMS*VRMS / RL, where VOUT is the potential of the high level of the fourth PWM wave; Ron is the on-resistance of the PMOS transistor.

6. A constant root-mean-square voltage output circuit according to claim 5, characterized in that, The power P of the fourth PWM wave output is a quantity independent of VCC; the average output power remains constant as VCC changes.

7. A constant root mean square voltage output circuit according to claim 1, characterized in that, The frequency of the fourth PWM wave output by the output stage circuit (10) is the same as the frequency of the output sawtooth wave generated by the second sawtooth wave. The frequency of the output fourth PWM wave is adjusted by adjusting the frequency of the second sawtooth wave.

8. A constant root-mean-square voltage output circuit according to any one of claims 1 to 7, characterized in that, The first comparator (3) compares the first sawtooth wave with VRMS and outputs a first PWM wave with a duty cycle of VRMS / VCC and a high level of VCC. After the output PWM wave is converted by an inverter and filtered by a low pass, it outputs a DC voltage VDC = VRMS*VRMS / VCC. Then, it compares VDC with the second sawtooth wave and outputs a third PWM wave with a duty cycle of VRMS*VRMS / (VCC*VCC). The third PWM wave is enhanced with driving capability and then used to drive the first PMOS power transistor, thereby obtaining an output signal whose average power does not change with the power supply voltage.

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