Gate drive circuit and display panel

Abstract

The embodiment of the invention provides a gate drive circuit and a display panel, the gate drive circuit comprises a plurality of cascaded gate drive sub-circuits, each gate drive sub-circuit correspondingly controls a row of sub-pixels, and each gate drive sub-circuit comprises a pull-up module, a pull-down module and an output control module. The pull-up module controls the potential of a first node according to a first level transmission signal and a clock signal; the pull-down module controls the potential of the first node according to a preset low potential and a second level transmission signal; the output control module outputs a corresponding driving signal to the corresponding sub-pixel through the output port according to the control signal, a preset low potential and the potential of the first node, and the output control module comprises a first transistor, a second transistor, a third transistor and a fourth transistor. Through the setting, the problems of high power consumption and poor cruising ability of the intelligent equipment with the high-refresh-rate display panel are at least solved.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202411796900.1, the original application being filed on December 6, 2024, and the original invention being entitled Gate driving circuit, driving method of display panel and display panel. Technical Field

[0002] This application relates to the field of display technology, specifically to a gate driving circuit and a display panel. Background Technology

[0003] Currently, high refresh rate screens are standard on mid-to-high-end smart devices. However, high resolution and high refresh rate also lead to high power consumption, resulting in high power consumption and poor battery life for smart devices with high refresh rate display panels. Summary of the Invention

[0004] Embodiments of this application provide a gate driving circuit and a display panel to at least solve the problems of high power consumption and poor battery life of smart devices with high refresh rate display panels.

[0005] On one hand, this application provides a gate driving circuit, including multiple cascaded gate driving sub-circuits, each gate driving sub-circuit controlling a row of sub-pixels. The Nth-level gate driving sub-circuit includes: a pull-up module, connected to a first-level transmission signal and a clock signal, and connected to a first node; the pull-up module is configured to control the potential of the first node according to the first-level transmission signal and the clock signal; wherein the first-level transmission signal is a scan signal output by the NKth-level gate driving sub-circuit, N > K > 0; a pull-down module, connected to a preset low potential and a second-level transmission signal, and connected to the first node; the pull-down module is configured to control the potential of the first node according to the preset low potential and the second-level transmission signal; wherein the second-level transmission signal is a scan signal output by the N+Mth-level gate driving sub-circuit, M > 0; and an output control module, connected to a control signal. The output control module is configured to output a drive signal to the pixel row corresponding to the gate drive sub-circuit through the output port according to the control signal, the preset low potential, and the potential of the first node. The output control module includes: a first transistor, including a control electrode connected to the first node, a first electrode connected to the first node, and a second electrode connected to the second node; a second transistor, including a control electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to the output port; a third transistor, including a control electrode connected to the control signal, a first electrode connected to the second node, and a second electrode connected to the preset low potential; and a fourth transistor, including a control electrode connected to the control signal, a first electrode connected to the output port, and a second electrode connected to the preset low potential.

[0006] In some embodiments, the output control module is further configured to control the output port to output a preset low potential to the pixel row corresponding to the gate driving sub-circuit when the control signal is a preset high potential, and to control the output port to output the potential of the first node to the pixel row corresponding to the gate driving sub-circuit when the control signal is a preset low potential.

[0007] In some embodiments, during a first time t1, all gate driving sub-circuits of the k to m stages are connected to the first type of control signal, and all gate driving sub-circuits of the (m+1) to n stages are connected to the first type of control signal; during a second time t2, all gate driving sub-circuits of the k to m stages are connected to the first type of control signal, and all gate driving sub-circuits of the (m+1) to n stages are connected to the second type of control signal; wherein, n > m > k, t1 > 0, t2 > 0, and one of the first type of control signal and the second type of control signal is a preset high potential and the other is a preset low potential.

[0008] In some embodiments, during a first time t1, all gate driving sub-circuits from the (n+1)th to the xth stage are connected to the first type of control signal; during a second time t2, all gate driving sub-circuits from the (n+1)th to the xth stage are connected to the first type of control signal; wherein, x > n.

[0009] In some embodiments, during a third time t3, the gate driving sub-circuits of the k to m stages are all connected to the first type of control signal, the gate driving sub-circuits of the m+1 to n stages are all connected to the second type of control signal, and the gate driving sub-circuits of the n+1 to x stages are all connected to the second type of control signal; wherein, t3 > 0.

[0010] In some embodiments, the pull-up module includes: a fifth transistor, including a first terminal connected to the fifth transistor and a control terminal connected to the first stage signal transmission, and a second terminal connected to the third node; a sixteenth transistor, including a control terminal connected to the third node, a first terminal connected to the clock signal, and a second terminal connected to the first node; wherein the fifth transistor and the sixteenth transistor are both reset transistors.

[0011] In some embodiments, the pull-down module includes: a thirteenth transistor, including a control electrode connected to the second-level signal transmission, a first electrode connected to the third node, and a second electrode connected to the preset low potential; and a fourteenth transistor, including a control electrode connected to the third-level signal transmission, a first electrode connected to the first node, and a second electrode connected to the preset low potential; wherein the thirteenth transistor is used to pull down the potential of the third node, and the fourteenth transistor is used to pull down the potential of the first node.

[0012] In some embodiments, the gate driving sub-circuit of the Nth stage further includes an inverting module; the inverting module includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; wherein the seventh transistor includes a first terminal connected to the seventh transistor and a control terminal connected to a preset high potential, and a second terminal connected to the first terminal of the eighth transistor; the eighth transistor includes a control terminal connected to a third node, a first terminal connected to the second terminal of the seventh transistor, and a second terminal connected to a preset low potential; the ninth transistor includes a control terminal connected to the first terminal of the eighth transistor, a first terminal connected to the first terminal of the seventh transistor, and a second terminal connected to a fourth node; the tenth transistor includes a control terminal connected to the third node, a first terminal connected to the fourth node, and a second terminal connected to the preset low potential; the inverting module is used to invert the potentials of the third node and the fourth node.

[0013] In some embodiments, the gate drive sub-circuit of the Nth stage further includes: a pull-down sustaining module; the pull-down sustaining module includes: an eleventh transistor, including a control electrode connected to the fourth node, a first electrode connected to the third node, and a second electrode connected to the preset low potential; and a twelfth transistor, including a control electrode connected to the fourth node, a first electrode connected to the first node, and a second electrode connected to the preset low potential.

[0014] In some embodiments, the gate drive sub-circuit of the Nth stage further includes a bootstrap capacitor; the bootstrap capacitor includes one end connected to the first pole of the twelfth transistor and the other end connected to the third node.

[0015] On the other hand, another embodiment of this application provides a display panel including the gate driving circuit described in any of the above embodiments.

[0016] The beneficial effects provided by the embodiments of this application include at least the following: This application provides a gate driving circuit and a display panel. The gate driving circuit includes multiple cascaded gate driving sub-circuits, each controlling a row of sub-pixels. Each gate driving sub-circuit includes a pull-up module, a pull-down module, and an output control module. The pull-up module controls the potential of the first node based on a first-level transmission signal and a clock signal; the pull-down module controls the potential of the first node based on a preset low potential and a second-level transmission signal; the output control module outputs a corresponding driving signal to the corresponding pixel row through an output port based on the control signal, the preset low potential, and the potential of the first node. The output control module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Through this configuration, the output control module can selectively output valid or invalid gate control signals to a specific row of pixels, thereby controlling different display areas of the same display panel to have different refresh rates. For display rows that do not require a high refresh rate, outputting an invalid gate control signal can reduce the refresh rate of the corresponding display row. This at least solves the problem of high power consumption and poor battery life in smart devices with high refresh rate display panels, thus effectively reducing the power consumption of the display panel and extending the battery life of the smart device.

[0017] Other beneficial effects of the embodiments of this application will be further explained in the following specific embodiments. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a gate driving circuit provided in some embodiments of this application; Figure 2 This is a schematic diagram of the structure of a gate driving sub-circuit provided in some embodiments of this application; Figure 3This is a schematic diagram of another gate driving sub-circuit provided in some embodiments of this application; Figure 4 This is a schematic diagram of another gate driving sub-circuit provided in some embodiments of this application; Figure 5 This is a schematic diagram of the partitioning of a display panel provided in some embodiments of this application; Figure 6 This is a timing diagram of a control signal provided in some embodiments of this application; Figure 7 This is a schematic diagram of the partitioning of another display panel provided in some embodiments of this application; Figure 8 This is a timing diagram of yet another control signal provided in some embodiments of this application; Figure 9 This is a timing diagram of yet another control signal provided in some embodiments of this application; Figure 10 A flowchart illustrating a method for driving a display panel as provided in some embodiments of this application; Figure 11 This is a schematic diagram of the structure of a display panel provided in some embodiments of this application. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0022] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0023] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the embodiments of this application.

[0024] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0025] The use of “configured to” in this application embodiment implies an open and inclusive language, which does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0026] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0027] To address the issues of high power consumption and poor battery life in smart devices with high refresh rate display panels, one embodiment of this application provides a gate driving circuit including multiple cascaded gate driving sub-circuits. For simplicity, the following signal ports and corresponding received or transmitted signals are described using the same notation; for example, the clock signal terminal and the clock signal are both represented by CK, the first node and the first node potential are both represented by G(N), and the output port and the output driving signal are both represented by G(N)-AA.

[0028] Figure 1 This is a schematic diagram of a gate drive circuit provided in some embodiments of this application. (Refer to...) Figure 1As shown, this application embodiment provides a gate driving circuit GM, which includes multiple cascaded gate driving sub-circuits GA and a frequency division control line CL that transmits control signals Ctr to the multiple gate driving sub-circuits GA. The multiple gate driving sub-circuits GA are electrically connected to multiple clock lines CKL1~CKL8. The multiple gate driving sub-circuits GA are configured to output a scan signal Nscan to the corresponding pixel row as a gate driving signal, and simultaneously output to the input terminal STV of the corresponding gate driving sub-circuit as an input signal or output to the pull-down signal control terminal PD of the corresponding gate driving sub-circuit as a pull-down control signal. For example Figure 1 As shown, the scan signal Nscan 1 output by the first-stage gate driver sub-circuit is the input signal of the fifth-stage gate driver sub-circuit GA, and the scan signal Nscan 5 output by the fifth-stage gate driver sub-circuit GA is the pull-down control signal of the first-stage gate driver sub-circuit. Figure 1 The input signal of the Nth stage gate driver sub-circuit shown is the scan signal output by the (N-4)th stage gate driver sub-circuit. Therefore, the input signal of the first 4 stages of gate driver sub-circuits is the frame start signal stv.

[0029] It should be noted that, Figure 1 The single frequency divider control line CL shown is connected to multiple gate driver sub-circuits GA, which is an exemplary illustration. In practical applications, since the control signal Ctr connected to different gate driver sub-circuits has different potentials, each gate driver sub-circuit can be connected to an independent frequency divider control line CL to obtain an independent control signal Ctr, thereby controlling the refresh rate of each row of pixels. Alternatively, the display screen can be divided into zones according to different refresh rates. For example, rows 1 to 100 share the same frequency divider control line CL1, rows 101 to 1100 share the same frequency divider control line CL2, and rows 1101 to 1200 share the same frequency divider control line CL3. Connecting each gate driver sub-circuit to an independent frequency divider control line CL allows for more flexible control of the refresh rate of each row of pixels, while sharing a single frequency divider control line CL across zones effectively saves area in the non-display area of ​​the panel.

[0030] Figure 2 This is a schematic diagram of the structure of a gate driving sub-circuit provided in some embodiments of this application. (Refer to...) Figure 2 As shown, the Nth-level gate driver sub-circuit GA is used as an example for illustrative purposes. The gate driver sub-circuit GA includes a pull-up module 1211, a pull-down module 1212, and an output control module 1213.

[0031] The pull-up module 1211 is connected to the first-stage transmission signal G(NK) and the CK clock signal, and is connected to the first node G(N). The pull-up module 1211 is configured to control the potential of the first node according to the first-stage transmission signal G(NK) and the preset high potential CK. The first-stage transmission signal G(NK) comes from the NK-th stage gate driver sub-circuit, where N > K > 0.

[0032] The pull-down module 1212 is connected to a preset low potential VSS and a second-level transmission signal G(N+M), and is connected to the first node G(N). The pull-down module 1212 is configured to control the potential of the first node G(N) according to the preset low potential VSS and the second-level transmission signal G(N+M); wherein, the second-level transmission signal G(N+M) comes from the N+Mth level gate driver sub-circuit, and M>0.

[0033] The output control module 1213 receives the control signal Ctr and the preset low potential VSS, and connects to the first node G(N) and the output port G(N)-AA. The output control module 1213 is configured to output the corresponding driving signal to the corresponding sub-pixel through the output port G(N)-AA according to the control signal Ctr, the preset low potential VSS and the potential G(N) of the first node.

[0034] Through the above settings, the output control module 1213 can selectively output valid or invalid gate control signals to one or more rows of sub-pixels, thereby controlling different display areas of the same display panel to have different refresh rates. This at least solves the problem of high power consumption and poor battery life in smart devices with high refresh rate display panels. Specifically, when the control signal Ctr is high, the output port G(N)-AA outputs a preset low potential VSS to the pixel row corresponding to the gate drive sub-circuit. When the control signal Ctr is low, the output port G(N)-AA outputs the potential G(N) of the first node to the pixel row corresponding to the gate drive sub-circuit. This allows different display areas of the same display panel to have different refresh rates. For display rows that do not require a high refresh rate, an invalid gate control signal can be output to reduce the refresh rate of the corresponding display row, thereby effectively reducing the power consumption of the display panel and extending the battery life of the smart device.

[0035] It should be noted that the implementation of each unit and control switch in the gate drive circuit can be a single transistor or a combination of multiple transistors, a capacitor, or a combination of a transistor and a capacitor. In all embodiments of this application, the transistors used can be thin-film transistors (TFTs), metal-oxide-semiconductor (MOSs), or other devices with similar characteristics; this application does not limit the specific type of transistor used.

[0036] For example, the transistor can be a TFT. TFTs can be fabricated using a-Si technology, oxide semiconductor technology, low-temperature polysilicon (LTPS) technology, or high-temperature polysilicon (HTPS) technology. The embodiments of this application do not limit this.

[0037] The embodiments of this application do not limit the type of transistor. The transistor can be an N-type transistor, a P-type transistor, an enhancement-mode transistor, or a depletion-mode transistor. In the embodiments of this application, all transistors are N-type transistors as an example for illustrative explanation. An N-type transistor is turned on under a high-level voltage signal and turned off under a low-level voltage signal; that is, the operating voltage of an N-type transistor is a high-level voltage, and the turn-off voltage is a low-level voltage.

[0038] In the embodiments of this application, the gate of the transistor is the control electrode. To distinguish the two electrodes of the transistor other than the gate, one electrode is directly described as the first electrode, and the other as the second electrode. In this case, the first electrode of the transistor can be either the source or the drain, and the second electrode can be either the source or the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable.

[0039] The capacitor in this embodiment can be a capacitor device manufactured separately through a process, such as by fabricating dedicated capacitor electrodes. The individual capacitor electrodes (first and second plates) can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. The capacitor can also be the parasitic capacitance between transistors, or implemented through the transistor itself and other devices or circuits, or by utilizing the parasitic capacitance between circuit lines themselves.

[0040] Each of the aforementioned transistors may further include at least one switching transistor connected in parallel with each transistor. The embodiments in this application are merely illustrative examples of pixel driving circuits and gate driving circuits; other structures with the same function as pixel driving circuits and gate driving circuits will not be described in detail, but should all fall within the protection scope of this application.

[0041] In the embodiments of this application, "first node," "second node," etc., do not refer to actual existing components, but rather to the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0042] Figure 3 This is a schematic diagram of another gate driver sub-circuit provided in some embodiments of this application. (Refer to...) Figure 3 As shown, in some embodiments, the output control module 1213 is further configured to control the output port G(N)-AA to output a preset low potential to the pixel row corresponding to the gate driving sub-circuit GA when the control signal Ctr is a preset high potential, and to control the output port G(N)-AA to output the potential G(N) of the first node to the pixel row corresponding to the gate driving sub-circuit GA when the control signal Ctr is a preset low potential.

[0043] Continue to refer to Figure 3 As shown, in some embodiments, the output control module 1213 includes: a first transistor T1, including a control electrode connected to a first node G(N), a first electrode connected to the first node G(N), and a second electrode connected to a second node A; a second transistor T2, including a control electrode connected to the second node A, a first electrode connected to the first node G(N), and a second electrode connected to the output port G(N); a third transistor T3, including a control electrode connected to a control signal Ctr, a first electrode connected to the second node A, and a second electrode connected to a preset low potential VSS; and a fourth transistor T4, including a control electrode connected to a control signal Ctr, a first electrode connected to the output port G(N)-AA, and a second electrode connected to a preset low potential VSS.

[0044] The gate driving sub-circuit provided in this embodiment is equivalent to determining whether a valid G(N) signal is output before the gate control signal G(N) is output to the corresponding sub-pixel of area AA through the output control module 1213. The control signal Ctr is connected to the gate driving sub-circuit GA through the frequency divider signal line CL. The frequency divider control line CL can be connected to the timing controller TCON or the system on-chip SIC. By setting the control signal Ctr of one or more rows, it is possible to control whether the gate control signal input to the corresponding sub-pixel of area AA is a valid G(N) signal.

[0045] Continue to refer to Figure 3 As shown, when the Ctr signal input to the gate drive sub-circuit of a certain row of sub-pixels is low, the third transistor T3 and the fourth transistor T4 are turned off. The low potential VSS cannot be transmitted to the output port G(N)-AA through the third transistor T3 or the fourth transistor T4. The potential G(N) of the first node can be transmitted to the output port G(N)-AA. That is, the G(N)-AA signal received by the corresponding sub-pixel is consistent with the potential G(N) of the first node, and the sub-pixel performs data signal refresh.

[0046] When the Ctr signal input to the gate drive sub-circuit of a certain row of sub-pixels is high, the third transistor T3 and the fourth transistor T4 are turned on. The low potential VSS can be transmitted to the output port G(N)-AA through the third transistor T3 or the fourth transistor T4. The potential G(N) of the first node cannot be transmitted to the output port G(N)-AA normally. That is, the G(N)-AA signal received by the corresponding sub-pixel is a continuous low level, and the sub-pixel does not perform data signal refresh.

[0047] It should be noted that the pull-up and pull-down modules can be implemented using conventional GOA (Gate-driver on array) circuits, such as 7T2C, 9T2C, or 13T2C, and can be selected according to actual needs. This application does not limit this.

[0048] Figure 4 This is a schematic diagram of another gate driver sub-circuit provided in some embodiments of this application. (Refer to...) Figure 4 As shown, the gate drive sub-circuit GA of the Nth stage includes a pull-up module 1211, a pull-down module 1212, an output control module 1213, an inverting module 1214, a pull-down sustaining module 1215, and two reset transistors T6 and T15.

[0049] The pull-up module 1211 includes a fifth transistor T5 and a sixteenth transistor T16. The control electrode of the fifth transistor T5 is connected to the first terminal and the first-stage transmission signal G(N-4), and the second terminal is connected to the third node Q(N). The control electrode of the sixteenth transistor T16 is connected to the third node Q(N), the first terminal is connected to the clock signal CKN, and the second terminal is connected to the first node G(N). The pull-up module 1211 is used to turn on the sixteenth transistor T16 when the potential of the second node Q(N) is high, and to output a high potential to the first node G(N) when the clock signal CKN is high.

[0050] The pull-down module 1212 includes a thirteenth transistor T13 and a fourteenth transistor T14. The control electrode of the thirteenth transistor T13 is connected to the second-stage transmission signal G(N+6), its first electrode is connected to the third node Q(N), and its second electrode is connected to a preset low potential VSS. The control electrode of the fourteenth transistor T14 is connected to the third-stage transmission signal G(N+4), its first electrode is connected to the first node G(N), and its second electrode is connected to the preset low potential VSS. The thirteenth transistor T13 is used to pull down the potential of the third node Q(N), and the fourteenth transistor T14 is used to pull down the potential of the first node G(N).

[0051] The inverting module 1214 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The control electrode of the seventh transistor T7 is connected to its first terminal and a preset high potential VGH, and its second terminal is connected to the first terminal of the eighth transistor T8. The control electrode of the eighth transistor T8 is connected to the third node Q(N), its first terminal is connected to the second terminal of the seventh transistor T7, and its second terminal is connected to a preset low potential VSS. The control electrode of the ninth transistor T9 is connected to the first terminal of the eighth transistor T8, its first terminal is connected to the first terminal of the seventh transistor T7, and its second terminal is connected to the fourth node P(N). The control electrode of the tenth transistor T10 is connected to the third node Q(N), its first terminal is connected to the fourth node P(N), and its second terminal is connected to the preset low potential VSS. The inverting module 1214 is used to invert the potentials of the fourth node P(N) and the third node Q(N).

[0052] The pull-down sustaining module 1215 includes an eleventh transistor T11 and a twelfth transistor T12. The control electrode of the eleventh transistor T11 is connected to the fourth node P(N), the first electrode is connected to the third node Q(N), and the second electrode is connected to a preset low potential VSS. The control electrode of the twelfth transistor T12 is connected to the fourth node P(N), the first electrode is connected to one end of the bootstrap capacitor C, and the second electrode is connected to the preset low potential VSS. The pull-down sustaining module 1215 is used to maintain the stability of the third node Q(N) and the voltage. The two ends of the bootstrap capacitor C are connected to the third node Q(N) and the first node G(N) respectively, and are used to couple the voltage between the third node Q(N) and the first node G(N).

[0053] The sixth transistor T6 and the fifteenth transistor T15 are reset transistors. By connecting a reset signal, the potentials of the third node Q(N) and the first node G(N) can be reset with one key.

[0054] In some embodiments, during a first time t1, all gate driving sub-circuits of the k to m stages are connected to the first type of control signal, and all gate driving sub-circuits of the (m+1) to n stages are connected to the first type of control signal; during a second time t2, all gate driving sub-circuits of the k to m stages are connected to the first type of control signal, and all gate driving sub-circuits of the (m+1) to n stages are connected to the second type of control signal; wherein, n > m > k, t1 > 0, t2 > 0, and one of the first type of control signal and the second type of control signal is a preset high potential and the other is a preset low potential.

[0055] Figure 5 This is a schematic diagram of the partitioning of a display panel provided in some embodiments of this application. Figure 6 This is a timing diagram of a control signal provided in some embodiments of this application. (Refer to...) Figure 5 and Figure 6As shown, the display area (AA) of the display panel can be divided into two display zones with different refresh rates. For example, rows 1 to 100 are dynamic display areas with a refresh rate of 120Hz, and rows 101 to 1200 are static display areas with a refresh rate of 60Hz. The gate driver sub-circuits of rows 1 to 100 are connected to the first control signal Ctr1, and the gate driver sub-circuits of rows 101 to 1200 are connected to the second control signal Ctr2. During the first time interval t1, the first control signal Ctr 1 is low, and the gate driver sub-circuits of rows 1 to 100 output valid G(N)-AA. The second control signal Ctr 2 is low, and the gate driver sub-circuits of rows 101 to 1200 output valid G(N)-AA. During the second time interval t2, the first control signal Ctr 1 is low, and the gate driver sub-circuits of rows 1 to 100 output valid G(N)-AA. The second control signal Ctr 2 is high, and the gate driver sub-circuits of rows 101 to 1200 output a preset low potential, and no data refresh is performed.

[0056] In some embodiments, the first to 100th rows of subpixels can be used as static display areas with a refresh rate of 30Hz, and the 101st to 1200th rows of subpixels can be used as dynamic display areas with a refresh rate of 100Hz. The specific partitions and corresponding refresh rates can be set according to the actual application scenario, and this application embodiment does not limit them.

[0057] In some embodiments, during a first time t1, all gate driving sub-circuits from the (n+1)th to the xth stage are connected to a first type of control signal; during a second time t2, all gate driving sub-circuits from the (n+1)th to the xth stage are connected to a first type of control signal; wherein, x > n.

[0058] Figure 7 This is a schematic diagram of another display panel partition provided in some embodiments of this application. Figure 8 This is a timing diagram of yet another control signal provided in some embodiments of this application. (Refer to...) Figure 7 and Figure 8As shown, the display area (AA) of the display panel can be divided into three display zones with different refresh rates. For example, rows 1 to 100 are dynamic display zones with a refresh rate of 120Hz, rows 101 to 1100 are static display zones with a refresh rate of 60Hz, and rows 1101 to 1200 are dynamic display zones with a refresh rate of 120Hz. The gate driver sub-circuits of levels 1 to 100 are connected to the first control signal Ctr 1, levels 101 to 1100 are connected to the second control signal Ctr 2, and levels 1101 to 1200 are connected to the third control signal Ctr 3. Within the first time interval t1, the first control signal Ctr1 is low, and the gate driver sub-circuits of levels 1 to 100 output valid G(N)-AA; the second control signal Ctr2 is low, and the gate driver sub-circuits of levels 101 to 1100 output valid G(N)-AA; the third control signal Ctr3 is low, and the gate driver sub-circuits of levels 1101 to 1200 output valid G(N)-AA; within the second time interval t2, the first control signal Ctr1 is low, and the gate driver sub-circuits of levels 1 to 100 output valid G(N)-AA; the second control signal Ctr2 is high, and the gate driver sub-circuits of levels 101 to 1200 output a preset low potential and do not perform data refresh; the third control signal Ctr1 is low, and the gate driver sub-circuits of levels 1 to 100 output valid G(N)-AA.

[0059] Figure 8 In the timing diagram shown, the refresh rate of sub-pixels in rows 1 to 100 is the same as the refresh rate of rows 1101 to 1200. The specific timing control of the control signals can be... Figure 8 Conversely, for example, rows 1 to 100 are static display areas with a refresh rate of 60Hz, rows 101 to 1100 are dynamic display areas with a refresh rate of 120Hz, and rows 1101 to 1200 are static display areas with a refresh rate of 60Hz. The corresponding first control signal Ctr 1 is low in the first time t1 and high in the second time t2. The second control signal Ctr 2 is low in both the first time t1 and the second time t2. The third control signal Ctr 3 is low in the first time t1 and high in the second time t2.

[0060] In some embodiments, during a third time t3, the gate driving sub-circuits of stages k to m are all connected to a first type of control signal, the gate driving sub-circuits of stages m+1 to n are all connected to a second type of control signal, and the gate driving sub-circuits of stages n+1 to x are all connected to the second type of control signal; wherein, t3 > 0.

[0061] Figure 9This is a timing diagram of yet another control signal provided in some embodiments of this application. (Refer to...) Figure 9 As shown, the display panel can be divided into three zones, each with a different refresh rate. Gate driver sub-circuits from levels 1 to 100 are connected to the first control signal Ctr 1, levels 101 to 1100 are connected to the second control signal Ctr 2, and levels 1101 to 1200 are connected to the third control signal Ctr 3. During the first time interval t1, the second time interval t2, and the third time interval t3, the first control signal Ctr 1 is low, and levels 1 to 100 always output valid G(N)-AA. The second control signal Ctr 2 is low during the first time interval t1, and levels 101 to 1100 output valid G(N)-AA. During the second time interval t2 and the third time interval t3, it is high, and levels 101 to 1200 output a preset low potential, without performing data refresh. The third control signal Ctr 3 is low during the first time t1, and the gate driver sub-circuits of levels 1101 to 1200 output valid G(N)-AA; it is high during the second time t2, and the gate driver sub-circuits of levels 1101 to 1200 output a preset low potential, and no data refresh is performed; it is low during the third time t3, and the gate driver sub-circuits of levels 1101 to 1200 output valid G(N)-AA.

[0062] Figure 10 This is a flowchart illustrating a display panel driving method provided in some embodiments of this application. (Refer to...) Figure 10 As shown, another embodiment of this application also provides a method for driving a display panel, which is implemented by the gate driving circuit in any of the above embodiments. The content already described will not be repeated here.

[0063] The above driving methods include: In step S1001, the gate driving sub-circuit generates the potential of the first node based on the first-stage transmission signal, the second-stage transmission signal, the clock signal, and the preset low potential. Step S1002: Based on the potential of the first node and the control signal, output a driving signal to the pixel row corresponding to the gate driving sub-circuit.

[0064] In some embodiments, step S1002 can be implemented by the following steps: S11, when the control signal is at a preset high potential, outputs a preset low potential to the pixel row corresponding to the gate driver sub-circuit.

[0065] In some embodiments, step S1002 can be implemented by the following steps: S21, when the control signal is at a preset low potential, output the potential of the first node to the pixel row corresponding to the gate driver sub-circuit.

[0066] In some embodiments, step S1002 can be implemented by the following steps: Within the first time t1, a first type of control signal is input to the gate driving sub-circuit of the k to m level, and a first type of control signal is input to the gate driving sub-circuit of the m+1 to n level, so as to output the first type of driving signal to the pixel row of the k to n level. During the second time t2, a first type of control signal is input to the gate driving sub-circuit of the k to m level to output a first type of driving signal to the pixel row of the k to m level; the second type of control signal is input to the gate driving sub-circuit of the (m+1) to n level to output a second type of driving signal to the pixel row of the (m+1) to n level. Where n > m > k, t1 > 0, t2 > 0, one of the first type of control signal and the second type of control signal is a preset high potential, and the other is a preset low potential.

[0067] In some embodiments, during a first time t1, the first type of control signal is input to the gate driving sub-circuit of the (n+1)th to (x)th levels to output the first type of driving signal to the (n+1)th to (x)th pixel rows; during a second time t2, the first type of control signal is input to the gate driving sub-circuit of the (n+1)th to (x)th levels to output the first type of driving signal to the (n+1)th to (x)th pixel rows; wherein, x > n.

[0068] In some embodiments, during a third time t3, a first type of control signal is input to the gate driving sub-circuit of the k to m levels to output a first type of driving signal to the k to m pixel rows; a second type of control signal is input to the gate driving sub-circuit of the (m+1) to n levels to output a second type of driving signal to the (m+1) to n pixel rows; and a second type of control signal is input to the gate driving sub-circuit of the (n+1) to x levels to output a second type of driving signal to the (n+1) to x pixel rows; wherein, t3 > 0.

[0069] Using the above method, based on the potential of the first node and the control signal, a drive signal is output to the pixel row corresponding to the gate drive sub-circuit. This effectively controls whether the signal output by each stage of the gate drive sub-circuit is a valid scan signal, enabling zoned control of the display panel and reducing the refresh rate of some display areas. This at least solves the problem of high power consumption and poor battery life of smart devices with high refresh rate display panels. By controlling different display areas of the same display panel to have different refresh rates, and by outputting an invalid gate control signal for display rows that do not require a high refresh rate, the refresh rate of the corresponding display row can be reduced, thereby effectively reducing the power consumption of the display panel and extending the battery life of the smart device.

[0070] Figure 11 This is a schematic diagram of the structure of a display panel provided in some embodiments of this application. (Refer to...) Figure 11 As shown, another embodiment of this application also provides a display panel 100, including the gate driving circuit GM described in any of the above embodiments. The display panel 100 includes an effective display area AA and a non-display area NA located around AA. The gate driving circuit GM is disposed in the non-display area NA, and the gate driving circuit GM receives a clock signal and a control signal from the timing controller TCON.

[0071] Another embodiment of this application provides a non-transitory computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described display panel driving method. This non-transitory computer-readable storage medium possesses all the beneficial effects of the above-described display panel driving method, which will not be elaborated upon further herein.

[0072] Computer-readable storage media can be, for example, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof, without particular limitation herein. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0073] In some embodiments of this application, a computer-readable storage medium may be any tangible medium that contains or stores a program that may be used or combined with an instruction execution system, apparatus, or device.

[0074] Computer program code for performing operations of some embodiments of this application can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0075] This application uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0076] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A gate driving circuit, characterized in that, It includes multiple cascaded gate driving sub-circuits, each gate driving sub-circuit controlling a row of sub-pixels, and the Nth level gate driving sub-circuit includes: A pull-up module is connected to the first-stage transmission signal and the clock signal, and is connected to the first node. The pull-up module is configured to control the potential of the first node according to the first-stage transmission signal and the clock signal. The first-stage transmission signal is the scan signal output by the gate driver sub-circuit of the NKth stage, where N > K > 0. A pull-down module is connected to a preset low potential and a second-level transmission signal, and is connected to the first node. The pull-down module is configured to control the potential of the first node according to the preset low potential and the second-level transmission signal; wherein, the second-level transmission signal is a scan signal output by the gate driver sub-circuit of the (N+M)th stage, where M > 0; and An output control module is connected to a control signal and the preset low potential, and is connected to the first node and the output port. The output control module is configured to output a drive signal to the pixel row corresponding to the gate drive sub-circuit through the output port according to the control signal, the preset low potential and the potential of the first node. The output control module includes: The first transistor includes a control electrode connected to the first node, a first electrode connected to the first node, and a second electrode connected to the second node; The second transistor includes a control electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to the output port; The third transistor includes a control electrode connected to the control signal, a first electrode connected to the second node, and a second electrode connected to the preset low potential; and The fourth transistor includes a control electrode connected to the control signal, a first electrode connected to the output port, and a second electrode connected to the preset low potential.

2. The gate driving circuit according to claim 1, characterized in that, The output control module is also configured to: When the control signal is at a preset high potential, the output port is controlled to output a preset low potential to the pixel row corresponding to the gate driving sub-circuit; and when the control signal is at a preset low potential, the output port is controlled to output the potential of the first node to the pixel row corresponding to the gate driving sub-circuit.

3. The gate driving circuit according to claim 2, characterized in that, Within the first time interval t1, all gate driving sub-circuits from level k to level m are connected to the first type of control signal, and all gate driving sub-circuits from level m+1 to level n are connected to the first type of control signal; During the second time t2, the gate driving sub-circuits of the kth to mth stages are all connected to the first type of control signal, and the gate driving sub-circuits of the (m+1)th to nth stages are all connected to the second type of control signal; Where n > m > k, t1 > 0, t2 > 0, and one of the control signals of the first type and the control signal of the second type is a preset high potential and the other is a preset low potential.

4. The gate driving circuit according to claim 3, characterized in that, Within the first time t1, the gate driving sub-circuits from the (n+1)th to the xth stage are all connected to the control signal of the first type; During the second time t2, the gate driving sub-circuits of the n+1 to xth stages are all connected to the control signal of the first type; Where x > n.

5. The gate driving circuit according to claim 4, characterized in that, During the third time t3, the gate driving sub-circuits of the kth to mth stages are all connected to the first type of control signal, the gate driving sub-circuits of the m+1th to nth stages are all connected to the second type of control signal, and the gate driving sub-circuits of the n+1th to xth stages are all connected to the second type of control signal. Where t3 > 0.

6. The gate driving circuit according to claim 1, characterized in that, The pull-up module includes: The fifth transistor includes a first terminal connected to the fifth transistor and a control terminal connected to the first stage for transmitting signals, and a second terminal connected to the third node; The sixteenth transistor includes a control electrode connected to the third node, a first electrode connected to the clock signal, and a second electrode connected to the first node; Both the fifth transistor and the sixteenth transistor are reset transistors.

7. The gate driving circuit according to claim 1, characterized in that, The drop-down module includes: The thirteenth transistor includes a control electrode connected to the second stage of signal transmission, a first electrode connected to the third node, and a second electrode connected to the preset low potential. The fourteenth transistor includes a control electrode connected to the third stage of signal transmission, a first electrode connected to the first node, and a second electrode connected to the preset low potential. The thirteenth transistor is used to pull down the potential of the third node, and the fourteenth transistor is used to pull down the potential of the first node.

8. The gate driving circuit according to claim 1, characterized in that, The gate drive sub-circuit of the Nth stage further includes: an inverting module; the inverting module includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The seventh transistor includes: a first terminal connected to the seventh transistor and a control terminal with a preset high potential, and a second terminal connected to the first terminal of the eighth transistor; The eighth transistor includes: a control electrode connected to the third node, a first electrode connected to the second electrode of the seventh transistor, and a second electrode connected to a preset low potential; The ninth transistor includes: a control electrode connected to the first electrode of the eighth transistor, a first electrode connected to the first electrode of the seventh transistor, and a second electrode connected to the fourth node; The tenth transistor includes: a control electrode connected to the third node, a first electrode connected to the fourth node, and a second electrode connected to the preset low potential; The inverting module is used to invert the potentials of the third node and the fourth node.

9. The gate driving circuit according to claim 1, characterized in that, The gate driver sub-circuit of the Nth stage further includes: a pull-down sustaining module; the pull-down sustaining module includes: The eleventh transistor includes a control electrode connected to the fourth node, a first electrode connected to the third node, and a second electrode connected to the preset low potential; The twelfth transistor includes a control electrode connected to the fourth node, a first electrode connected to the first node, and a second electrode connected to the preset low potential.

10. The gate driving circuit according to claim 9, characterized in that, The gate driver sub-circuit of the Nth stage further includes: a bootstrap capacitor; the bootstrap capacitor includes: One end of the first electrode of the twelfth transistor is connected, and the other end of the third node is connected.

11. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 10.

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