Display panel

Abstract

This invention discloses a display panel comprising an array substrate and a black matrix. The array substrate includes a first substrate, pixel units, data lines, and shielding electrode lines. The shielding electrode lines include a first shielding line and a second shielding line. The orthographic projection of the first shielding line onto the first substrate covers the orthographic projection of the data lines onto the first substrate. The orthographic projection of the black matrix onto the first substrate covers a first driving region. The orthographic projection of the second shielding line and the gate of the thin-film transistor onto the first substrate covers a second driving region. When the array substrate and the color filter substrate are assembled, if the black matrix shifts, the area not covered by the black matrix (the second driving region) is covered by the second shielding line and the gate. Furthermore, a small voltage difference exists between the second shielding line and the common electrode line, allowing the liquid crystal molecules in this area to maintain their original state under the influence of the electric field force, preventing deflection due to the deflection of surrounding liquid crystals. This helps avoid light leakage.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] Existing liquid crystal display panels generally include an array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. Multiple thin-film transistors (TFTs) are disposed on the array substrate, and a common electrode layer and a black matrix for shielding the TFTs are disposed on the color filter substrate. To increase transmittance, the black matrix is ​​typically designed so that its orthogonal projection onto the array substrate is close to the gate edge of the TFT. However, with this design, the black matrix is ​​prone to shifting when the array substrate and color filter substrate are assembled, resulting in some areas of the driving circuit region of the array substrate not being shielded by the black matrix, causing light leakage. Summary of the Invention

[0003] The present invention provides a display panel that can solve the technical problem that the black matrix is ​​easily misaligned when the array substrate and the color filter substrate are assembled in the existing display panel, resulting in some areas of the driving circuit area of ​​the array substrate not being covered by the black matrix and causing light leakage.

[0004] To solve the above problems, the technical solution provided by the present invention is as follows:

[0005] This invention provides a display panel, comprising an array substrate disposed opposite to each other and a black matrix disposed opposite to the array substrate;

[0006] The array substrate includes a first substrate, a plurality of pixel units located on the first substrate, and data lines located on both sides of the pixel units. Each pixel unit includes a pixel electrode region and a driving circuit region located on one side of the pixel electrode region. The driving circuit region is provided with a thin film transistor. The driving circuit region includes a first driving region and a second driving region located on the side of the first driving region away from the pixel electrode region.

[0007] The array substrate further includes shielding electrode lines, which include a first shielding line arranged parallel to the data line and a second shielding line disposed between two adjacent first shielding lines; wherein, the orthographic projection of the first shielding line on the first substrate covers the orthographic projection of the data line on the first substrate, the orthographic projection of the black matrix on the first substrate covers the first driving region, and the orthographic projection of the second shielding line and the gate of the thin film transistor on the first substrate covers the second driving region.

[0008] According to the display panel provided by the present invention, the second driving area includes a blank area located between the first shielding line and the gate, and the orthogonal projection of the second shielding line on the first substrate at least covers the blank area.

[0009] According to the display panel provided by the present invention, there is an overlap between the orthogonal projection of the second shielding line on the first substrate and the orthogonal projection of the gate on the first substrate.

[0010] According to the display panel provided by the present invention, the thin-film transistor further includes an active layer, wherein the orthographic projection of the active layer on the first substrate is located within the orthographic projection of the gate on the first substrate; wherein the orthographic projection of the active layer on the first substrate does not overlap with the orthographic projection of the second shielding line on the first substrate.

[0011] According to the display panel provided by the present invention, the array substrate includes a pixel electrode disposed on the same layer as the shielding electrode line, the pixel electrode is located in the pixel electrode region, the drain of the thin film transistor is located in the first driving region, and the pixel electrode is electrically connected to the drain in the first driving region through a via; wherein, there is a gap between the first shielding line and the via.

[0012] According to the display panel provided by the present invention, the edge of the second shielding line near the pixel electrode region is the first edge, the edge of the gate near the pixel electrode region is the second edge, and the edge of the source of the thin film transistor away from the pixel electrode region is the third edge; wherein, the first edge is located between the second edge and the third edge.

[0013] According to the display panel provided by the present invention, the second shielding line includes a first shielding portion and a second shielding portion connected to each other, wherein the first shielding portion is located on the side of the active layer close to the first shielding line, and the second shielding portion is located on the side of the active layer away from the pixel electrode region.

[0014] According to the display panel provided by the present invention, the array substrate includes:

[0015] A first metal layer is disposed on the first substrate and includes the gate and scan line;

[0016] A gate insulating layer covers the first metal layer and the first substrate;

[0017] A second metal layer is disposed on the gate insulating layer and includes the data line;

[0018] A first insulating layer covers the second metal layer and the gate insulating layer;

[0019] A color resist layer is disposed on the first insulating layer;

[0020] A second insulating layer covers the color resist layer and the first insulating layer; and

[0021] A pixel electrode layer is disposed on the second insulating layer and includes pixel electrodes and the shielding electrode lines disposed at intervals.

[0022] According to the display panel provided by the present invention, the display panel further includes a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate; wherein, the color filter substrate includes:

[0023] A second substrate, wherein the black matrix is ​​disposed on the side of the second substrate near the array substrate; and

[0024] A common electrode line is disposed on the side of the second substrate and the black matrix near the array substrate;

[0025] The orthogonal projection of the common electrode line onto the array substrate covers the driving circuit area and the pixel electrode area.

[0026] According to the display panel provided by the present invention, the voltage difference between the common electrode line and the shielding electrode line is in the range of 0 volts to 3 volts.

[0027] Beneficial Effects: In the display panel provided by this invention, by setting the shielding electrode line into two parts, namely a first shielding line and a second shielding line, the orthographic projection of the first shielding line on the first substrate covers the orthographic projection of the data line on the first substrate, the orthographic projection of the second shielding line and the gate of the thin-film transistor on the first substrate covers the second driving area of ​​the driving circuit region, and the orthographic projection of the black matrix on the first substrate covers the first driving area. That is, the first shielding line is used to shield the data line, the second shielding line and the gate are used to shield the second driving area, and the black matrix is ​​used to shield the first driving area. Thus, when the array substrate and the color filter substrate are assembled, if the black matrix is ​​offset, the part of the area not covered by the black matrix (the second driving area) is covered by the second shielding line and the gate. Since there is a small voltage difference between the second shielding line and the common electrode line, an electric field is formed between the second shielding line and the common electrode line. This allows the liquid crystal molecules in this area to maintain their original state under the action of the electric field force, without being deflected by the surrounding liquid crystal deflection, which helps to avoid light leakage. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention;

[0030] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the display panel along section line A-A'.

[0031] Figure 3 A schematic diagram showing the positional relationship between the shielding electrode lines, the black matrix, and the gate of a display panel provided in an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of the planar structure of the shielding electrode lines of the display panel provided in an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of the array arrangement of multiple shielding electrode lines provided in an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] 1. Array substrate; 2. Color filter substrate; 3. Liquid crystal layer; 31. Liquid crystal molecules;

[0036] 11. Pixel unit; 11a. Pixel electrode area; 11b. Driving circuit area; 111b. First driving area; 112b. Second driving area; 1121b. Blank area; 111. Pixel electrode; 12. Data line; 13. Scan line; 14. Masking electrode line; 141. First masking line; 142. Second masking line; 1421. First masking portion; 1422. Second masking portion; 15. Thin film transistor; 151. Gate; 152. Source; 153. Drain; 154. Active layer; 16. Via;

[0037] 101. First substrate; 102. First metal layer; 103. Gate insulating layer; 104. Second metal layer; 105. First insulating layer; 106. Color resist layer; 107. Second insulating layer; 108. Pixel electrode layer;

[0038] 201, Second substrate; 202, Black matrix; 203, Common electrode line. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0040] In the description of this invention, it should be understood that the terms "length," "width," "thickness," "upper," "lower," etc., indicating orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] In this invention, unless otherwise expressly specified and limited, the first feature "above" or "below" the second feature may include direct contact between the first and second features, or contact between the first and second features not in direct contact but through another feature between them.

[0042] The display panels provided in the embodiments of the present invention will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0043] Please see Figures 1-3 As shown, an embodiment of the present invention provides a display panel, the display panel including an array substrate 1 disposed opposite to the array substrate 1 and a black matrix 202 disposed opposite to the array substrate 1.

[0044] Specifically, the display panel further includes a color filter substrate 2 disposed opposite to the array substrate 1, and a liquid crystal layer 3 disposed between the array substrate 1 and the color filter substrate 2. The liquid crystal layer 3 includes a plurality of liquid crystal molecules 31. A voltage difference exists between the array substrate 1 and the color filter substrate 2 to drive the liquid crystal molecules 31 to deflect, thereby achieving display. The color filter substrate 2 includes a second substrate 201 and a common electrode line 203. The black matrix 202 is disposed on the side of the second substrate 201 closest to the array substrate 1. The common electrode line 203 is disposed on the side of the second substrate 201 and the black matrix 202 closest to the array substrate 1.

[0045] The array substrate 1 includes a first substrate 101, a plurality of pixel units 11 located on the first substrate 101, and data lines 12 located on both sides of the pixel units 11. Each pixel unit 11 includes a pixel electrode region 11a and a driving circuit region 11b located on one side of the pixel electrode region 11a. The driving circuit region 11b is provided with a thin film transistor 15. The driving circuit region 11b includes a first driving region 111b and a second driving region 112b located on the side of the first driving region 111b away from the pixel electrode region 11a.

[0046] Specifically, the array substrate 1 further includes multiple scan lines 13 disposed on the first substrate 101, and multiple data lines 12. The multiple scan lines 13 and multiple data lines 12 intersect to define the pixel unit 11. The pixel electrode region 11a is a light-transmitting region, and the driving circuit region 11b is a light-blocking region. The black matrix 202 is made of a light-shielding material and is disposed corresponding to the driving circuit region 11b.

[0047] In this invention, the array substrate 1 further includes shielding electrode lines 14, which include a first shielding line 141 disposed parallel to the data line 12 and a second shielding line 142 disposed between two adjacent first shielding lines 141. The orthographic projection of the first shielding line 141 on the first substrate 101 covers the orthographic projection of the data line 12 on the first substrate 101, the orthographic projection of the black matrix 202 on the first substrate 101 covers the first driving region 111b, and the orthographic projections of the second shielding line 142 and the gate 151 of the thin-film transistor 15 on the first substrate 101 cover the second driving region 112b.

[0048] Understandably, in related technologies, the orthogonal projection of the common electrode line 203 onto the array substrate 1 covers the driving circuit region 11b and the pixel electrode region 11a, and the liquid crystal layer 3 fills the areas of the array substrate 1 and the color filter substrate 2 except for the encapsulation area. Simply put, the liquid crystal layer 3 is disposed across the entire surface, the common electrode line 203 is disposed across the entire surface, and the black matrix 202 covers the entire driving circuit region 11b. However, when the array substrate 1 and the color filter substrate 2 are assembled, due to assembly accuracy limitations, the black matrix 202 is prone to shifting. For example, the black matrix 202 may shift towards the side closer to the pixel electrode region 11a, causing a portion of the driving circuit region 11b away from the pixel electrode region 11a to be exposed by the black matrix 202, thus revealing the gate 151. Furthermore, due to the voltage difference between the common electrode line 203 and the gate 151, the liquid crystal molecules 31 located between the common electrode line 203 and the gate 151 are deflected. Consequently, the liquid crystal molecules 31 located at the gap between the gate 151 and the data line 12 (i.e., the liquid crystal molecules 31 located between the common electrode line 203 and the gate 151) are also deflected. Since the gap between the gate 151 and the data line 12 is neither covered by the black matrix 202 nor blocked by the gate 151, light leakage ultimately occurs at this location.

[0049] For example, during normal display, the voltage of the gate 151 is 30 volts to turn on the thin-film transistor 15, and the voltage of the common electrode line 203 is 6 volts. The data voltage on the data line 12 is transmitted to the pixel electrode 111 located in the pixel electrode region 11a, and the voltage of the pixel electrode 111 is 12 volts. Therefore, there is a voltage difference of 6 volts between the pixel electrode 111 and the common electrode line 203, causing the liquid crystal molecules 31 at this location to deflect. However, when the black matrix 202 shifts, there is also a voltage difference of 24 volts between the common electrode line 203 and the gate 151, causing the liquid crystal molecules 31 at this location to deflect as well. Both voltage differences together cause light leakage at this location.

[0050] In view of this, the present invention sets the existing shielding electrode line 14 into two parts, namely the first shielding line 141 and the second shielding line 142. The first shielding line 141 is used to shield the data line 12, the second shielding line 142 and the gate 151 of the thin film transistor 15 are used together to cover the second driving region 112b, and the black matrix 202 is used to cover the first driving region 111b. That is, the black matrix 202, the second shielding line 142 and the gate 151 together cover the driving circuit region 11b.

[0051] When the array substrate 1 and the color filter substrate 2 are assembled, if the black matrix 202 is offset, the area not covered by the black matrix 202 (the second driving area 112b) is covered by the second shielding line 142 and the gate 151. There is a small pressure difference between the second shielding line 142 and the common electrode line 203 (i.e., the gap between the gate 151 and the data line 12). This pressure difference causes an electric field to be formed between the second shielding line 142 and the common electrode line 203. The liquid crystal molecules 31 at this location remain in their original state under the action of this electric field force, and will not be deflected due to the deflection of the surrounding liquid crystal (i.e., the liquid crystal molecules 31 between the common electrode line 203 and the gate 151). Thus, the liquid crystal molecules 31 at the gap between the gate 151 and the data line 12 do not deflect and remain in a vertical state. Even if the black matrix 202 is not covered here and the gate 151 is not shielding, light leakage can be avoided.

[0052] For example, during normal display, the voltage of the gate 151 is 30 volts to turn on the thin-film transistor 15, the voltage of the common electrode line 203 is 6 volts, the data voltage on the data line 12 is transmitted to the pixel electrode 111, and the voltage of the pixel electrode 111 is 12 volts. There is a voltage difference between the pixel electrode 111 and the common electrode line 203, driving the liquid crystal molecules 31 to deflect. A small voltage difference exists between the second shielding line 142 and the common electrode line 203. When the black matrix 202 shifts, the liquid crystal molecules 31 at this point maintain their current state due to the electric field force, without deflection, remaining in a normally black state and preventing light leakage.

[0053] It should be noted that the first driving region 111b and the second driving region 112b in this invention are used to divide the driving circuit region 11b for the convenience of describing the relative positions of the black matrix 202 and the second masking line 142. However, it should be understood that since the array substrate 1 and the color filter substrate 2 are fabricated separately and then assembled, the offset of the black matrix 202 occurs after the fabrication of the array substrate 1. In order to avoid the offset area of ​​the black matrix 202 not being completely covered, the second driving region 112b should be at least the offset area of ​​the black matrix 202 during the fabrication of the array substrate 1.

[0054] Specifically, in this embodiment of the invention, the orthographic projection of the second shielding line 142 on the first substrate 101 overlaps with the orthographic projection of the black matrix 202 on the first substrate 101, so that the black matrix 202 and the second shielding line 142 can shield the driving circuit area 11b.

[0055] Specifically, in this embodiment of the invention, the first shielding line 141 and the second shielding line 142 are connected to the same shielding signal. Optionally, the second shielding line 142 extends from the first shielding line 141 to the driving circuit region 11b, and one of the first shielding line 141 and the second shielding line 142 is connected to the shielding signal, which is transmitted to the other; or, the first shielding line 141 and the second shielding line 142 are disconnected, in which case the first shielding line 141 and the second shielding line 142 are respectively connected to the same shielding signal.

[0056] In one embodiment, the orthogonal projection of the second shielding line 142 on the first substrate 101 covers the second driving region 112b, that is, the second shielding line 142 shields the entire second driving region 112b.

[0057] In another embodiment, the orthogonal projection of the second shielding line 142 onto the first substrate 101 covers a portion of the second driving region 112b, and the orthogonal projection of the gate 151 onto the first substrate 101 also covers a portion of the second driving region 112b. Since the gate 151 is typically made of a metallic material and has inherent light-shielding properties, the second shielding line 142 is only required for the area of ​​the second driving region 112b not covered by the gate 151, which helps to save materials.

[0058] Specifically, the second driving region 112b includes a blank region 1121b located between the first shielding line 141 and the gate 151, and the orthographic projection of the second shielding line 142 on the first substrate 101 at least covers the blank region 1121b. This arrangement is because a voltage difference exists between the common electrode line 203 and the gate 151, which not only causes the liquid crystal molecules 31 at the position directly opposite the gate 151 to deflect, resulting in light leakage, but also causes the liquid crystal molecules 31 located near the gate 151 to deflect due to inertia. In particular, the area in the second driving region 112b not covered by the gate 151 will also experience light leakage due to inertia, causing the liquid crystal molecules 31 at the location of the blank region 1121b to deflect. In view of this, this application covers the blank area 1121b with the second shielding line 142, so that there is a small voltage difference between the second shielding line 142 and the common electrode line 203 to form an electric field. This allows the liquid crystal molecules 31 in the blank area 1121b to maintain their original state under the action of the electric field force, without being affected by the liquid crystal molecules 31 that are deflected on their sides. As a result, they do not deflect and remain upright, thus keeping the blank area 1121b in a normally black state, which can solve the light leakage problem.

[0059] Specifically, the voltage difference between the common electrode line 203 and the shielding electrode line 14 ranges from 0 volts to 3 volts. Preferably, the voltage difference between the common electrode line 203 and the shielding electrode line 14 ranges from 0 volts to 1 volt. By adjusting the voltage difference between the common electrode line 203 and the shielding electrode line 14 and controlling this voltage difference within a very small range, the liquid crystal molecules 31 can be controlled to deflect at a very small angle, ensuring that the liquid crystal molecules 31 are neither allowed to emit light nor are allowed to remain upright.

[0060] Specifically, the common electrode line 203 and the shielding electrode line 14 each have two different signal interfaces, which are connected to different signals.

[0061] It should be noted that the blank area 1121b in this invention does not refer to an area without any film layer, but rather to the area in the second driving area 112b that is not covered by the gate 151. The gate 151 is not provided in the blank area 1121b.

[0062] In this embodiment of the invention, to ensure that the second shielding line 142 can completely cover the blank area 1121b, the orthographic projection of the second shielding line 142 on the first substrate 101 overlaps with the orthographic projection of the gate 151 on the first substrate 101. Further, in this embodiment, the thin-film transistor 15 includes an active layer 154, the orthographic projection of the active layer 154 on the first substrate 101 being located within the orthographic projection of the gate 151 on the first substrate 101; wherein the orthographic projection of the active layer 154 on the first substrate 101 does not overlap with the orthographic projection of the second shielding line 142 on the first substrate 101. This arrangement is because, since the second shielding line 142 is made of a metallic material, if it overlaps with the active layer 154, an electron flow will occur between the second shielding line 142 and the active layer 154, leading to leakage. Therefore, to avoid display defects, the active layer 154 and the second shielding line 142 should not overlap in the vertical direction.

[0063] Optionally, the edge profile of the second masking line 142 near the active layer 154 is the same as the edge profile of the active layer 154.

[0064] Furthermore, the pixel electrode 111 is disposed on the same layer as the shielding electrode line 14, the drain 153 of the thin film transistor 15 is located in the first driving region 111b, and the pixel electrode 111 is electrically connected to the drain 153 in the first driving region 111b through a via 16; wherein, there is a gap between the first shielding line 141 and the via 16.

[0065] It should be noted that, since the pixel electrode 111 and the masking electrode line 14 are arranged on the same layer and input different signals respectively, in order to avoid short circuits caused by contact between the two, which would lead to signal disorder and affect normal display, in this embodiment of the invention, it is necessary to control the interval between the second masking line 142 and the pixel electrode 111.

[0066] Further, in this embodiment of the invention, the edge of the second masking line 142 near the pixel electrode region 11a is the first edge E1, the edge of the gate 151 near the pixel electrode region 11a is the second edge E2, and the edge of the source 152 of the thin-film transistor 15 away from the pixel electrode region 11a is the third edge E3; wherein, the first edge E1 is located between the second edge E2 and the third edge E3, that is, the second masking line 142 does not extend beyond the second edge E2 to avoid contact with the pixel electrode 111, and the second masking line 142 extends beyond the third edge E3 to ensure that the second masking line 142 is large enough to completely cover the offset area of ​​the black matrix 202.

[0067] Furthermore, in this embodiment of the invention, the edge of the gate 151 away from the pixel electrode region 11a is the fourth edge E4. The distance between the first edge E1 and the fourth edge E4 is greater than 8 micrometers. Since the offset distance of the black matrix 202 is generally less than 8 micrometers when the color filter substrate 2 and the array substrate 1 are paired, the present invention controls the distance between the first edge E1 and the fourth edge E4 to be greater than 8 micrometers, which is beneficial to ensure complete coverage of the offset area of ​​the black matrix 202 and avoid light leakage.

[0068] Please see Figure 4 and Figure 5 In this embodiment of the invention, the second masking line 142 includes a first masking portion 1421 and a second masking portion 1422 connected together. The first masking portion 1421 is located on the side of the active layer 154 close to the first masking line 141, and the second masking portion is located on the side of the active layer 154 away from the pixel electrode region 11a, such that the first masking portion 1421 of the two second masking lines 142 located on opposite sides of the pixel unit 11 is connected through the second masking portion 1422.

[0069] In the embodiments of the present invention, please refer again. Figure 2The array substrate 1 further includes a first metal layer 102, a gate insulating layer 103, a second metal layer 104, a first insulating layer 105, a color resist layer 106, a second insulating layer 107, and a pixel electrode layer 108. The first metal layer 102 is disposed on the first substrate 101 and includes the gate 151 and scan lines 13. The gate insulating layer 103 covers the first metal layer 102 and the first substrate 101. The second metal layer 104 is disposed on the gate insulating layer 103 and includes the data lines 12. The first insulating layer 105 covers the second metal layer 104 and the gate insulating layer 103. The color resist layer 106 is disposed on the first insulating layer 105. The second insulating layer 107 covers the color resist layer 106 and the first insulating layer 105; the pixel electrode layer 108 is disposed on the second insulating layer 107 and includes pixel electrodes 111 spaced apart and shielding electrode lines 14.

[0070] Accordingly, embodiments of the present invention also provide a display device. This display device includes the display panel described above. The display device provided in the embodiments of the present invention can be at least one of a smartphone, tablet computer, mobile phone, video phone, e-book reader, laptop, netbook, workstation, server, personal digital assistant, portable media player, MP3 player, mobile medical device, camera, game console, digital camera, car navigation system, electronic billboard, ATM, smart bracelet, smartwatch, virtual reality device, or wearable device. The display panel has been described in detail in the above embodiments; therefore, further details about the display panel are not provided in the embodiments of the present invention.

[0071] Beneficial Effects: In the display panel provided in this embodiment of the invention, by setting the shielding electrode line into two parts, namely a first shielding line and a second shielding line, the orthographic projection of the first shielding line on the first substrate covers the orthographic projection of the data line on the first substrate, the orthographic projection of the second shielding line and the gate of the thin-film transistor on the first substrate covers the second driving area of ​​the driving circuit region, and the orthographic projection of the black matrix on the first substrate covers the first driving area. That is, the first shielding line is used to shield the data line, the second shielding line and the gate are used to shield the second driving area, and the black matrix is ​​used to shield the first driving area. Thus, when the array substrate and the color filter substrate are assembled, if the black matrix is ​​offset, the part of the area not covered by the black matrix (the second driving area) is covered by the second shielding line and the gate. Since there is a small voltage difference between the second shielding line and the common electrode line, an electric field is formed between the second shielding line and the common electrode line. This allows the liquid crystal molecules in this area to maintain their original state under the action of the electric field force, without being deflected by the surrounding liquid crystal deflection, which helps to avoid light leakage.

[0072] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0073] The above provides a detailed description of a display panel provided in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, Includes an array substrate disposed opposite to each other and a black matrix disposed opposite to the array substrate; The array substrate includes a first substrate, a plurality of pixel units located on the first substrate, and data lines located on both sides of the pixel units. Each pixel unit includes a pixel electrode region and a driving circuit region located on one side of the pixel electrode region. The driving circuit region is provided with a thin film transistor. The driving circuit region includes a first driving region and a second driving region located on the side of the first driving region away from the pixel electrode region. The array substrate further includes shielding electrode lines, which include a first shielding line arranged parallel to the data line and a second shielding line disposed between two adjacent first shielding lines; wherein, the orthographic projection of the first shielding line on the first substrate covers the orthographic projection of the data line on the first substrate, the orthographic projection of the black matrix on the first substrate covers the first driving region, the orthographic projection of the second shielding line on the first substrate and the orthographic projection of the gate of the thin film transistor on the first substrate together cover the second driving region, the second driving region includes a blank area located between the first shielding line and the gate, the orthographic projection of the second shielding line on the first substrate at least covers the blank area, and there is an overlap between the orthographic projection of the second shielding line on the first substrate and the orthographic projection of the gate on the first substrate.

2. The display panel according to claim 1, characterized in that, The thin-film transistor further includes an active layer, the orthographic projection of the active layer on the first substrate being located within the orthographic projection of the gate on the first substrate; wherein the orthographic projection of the active layer on the first substrate does not overlap with the orthographic projection of the second shielding line on the first substrate.

3. The display panel according to claim 2, characterized in that, The array substrate includes a pixel electrode disposed on the same layer as the shielding electrode line, the pixel electrode being located in the pixel electrode region, the drain of the thin-film transistor being located in the first driving region, and the pixel electrode being electrically connected to the drain in the first driving region through a via; wherein, there is a gap between the first shielding line and the via.

4. The display panel according to claim 3, characterized in that, The edge of the second shielding line closest to the pixel electrode region is the first edge, the edge of the gate closest to the pixel electrode region is the second edge, and the edge of the source of the thin-film transistor furthest from the pixel electrode region is the third edge; wherein the first edge is located between the second edge and the third edge.

5. The display panel according to claim 2, characterized in that, The second masking line includes a first masking portion and a second masking portion connected together. The first masking portion is located on the side of the active layer closer to the first masking line, and the second masking portion is located on the side of the active layer away from the pixel electrode region.

6. The display panel according to claim 1, characterized in that, The array substrate includes: A first metal layer is disposed on the first substrate and includes the gate and scan line; A gate insulating layer covers the first metal layer and the first substrate; A second metal layer is disposed on the gate insulating layer and includes the data line; A first insulating layer covers the second metal layer and the gate insulating layer; A color resist layer is disposed on the first insulating layer; A second insulating layer covers the color resist layer and the first insulating layer; and A pixel electrode layer is disposed on the second insulating layer and includes pixel electrodes and the shielding electrode lines disposed at intervals.

7. The display panel according to claim 6, characterized in that, The display panel further includes a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate; wherein, the color filter substrate includes: A second substrate, wherein the black matrix is ​​disposed on the side of the second substrate near the array substrate; and A common electrode line is disposed on the side of the second substrate and the black matrix near the array substrate; The orthogonal projection of the common electrode line onto the array substrate covers the driving circuit area and the pixel electrode area.

8. The display panel according to claim 7, characterized in that, The voltage difference between the common electrode line and the shielding electrode line ranges from 0 volts to 3 volts.

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