Gate drive circuit and display panel

Abstract

The present application discloses a gate driving circuit and a display panel. The gate driving circuit includes a plurality of gate driving units, wherein one gate driving unit includes a stage transmission signal selection module, a pull-up control module, a pulse number reduction module, a first inversion module, a first output stage and a second output stage, and can output a second gate control signal with a larger number of pulses, and can also output a first gate control signal with a smaller number of pulses.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] With the continuous updating of pixel circuits, gate driving circuits also need to be improved to provide various gate control signals required by the pixel circuits.

[0003] However, in the current gate driving circuit, the pulses of various gate control signals that can be provided by a gate driving unit are subject to many restrictions in terms of time, quantity, etc., and cannot meet the driving requirements of the corresponding pixel circuit. Summary of the invention

[0004] The present application provides a gate driving circuit and a display panel to alleviate the technical problem that the pulses of various gate control signals that can be provided by the same gate driving unit cannot meet the requirements of the pixel circuit in terms of time, quantity, etc.

[0005] In a first aspect, the present application provides a gate driving circuit, which includes a plurality of cascaded gate driving units, wherein one gate driving unit includes a level transmission signal selection module, a pull-up control module, a pulse number reduction module, a first inversion module, a first output stage and a second output stage, wherein the level transmission signal selection module is electrically connected between the first wiring and the first node; the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; the pulse number reduction module is electrically connected between the second node and the third node, and the control end of the pulse number reduction module is electrically connected to the reset line; the first inversion module is connected between the second node and the fourth node; the first output stage outputs a first gate control signal according to the potential of the third node and the potential of the fourth node; the second output stage outputs a second gate control signal according to the potential of the second node, and the number of pulses of the second gate control signal in one frame is greater than the number of pulses of the first gate control signal in one frame; wherein at least one of the level transmission signal selection module, the first inversion module and the second output stage includes three transistors of the same channel type.

[0006] In some embodiments, at least one of the stage transfer signal selection module, the first inversion module and the second output stage includes a first transistor, a second transistor and a third transistor, one of the source or the drain of the first transistor is electrically connected to the low potential line, the gate of the first transistor is electrically connected to the first wiring, and the first transistor is a P-channel thin film transistor; the gate of the second transistor is electrically connected to the gate of the first transistor, one of the source or the drain of the second transistor is electrically connected to the high potential line, the other of the source or the drain of the second transistor is electrically connected to the first node, and the second transistor is a P-channel thin film transistor; the gate of the third transistor is electrically connected to the other of the source or the drain of the first transistor, one of the source or the drain of the third transistor is electrically connected to the low potential line, the other of the source or the drain of the third transistor is electrically connected to the first node, and the third transistor is a P-channel thin film transistor.

[0007] In some embodiments, the ratio of the channel width of the first transistor to the channel length of the first transistor is greater than 1.5:1; the ratio of the channel width of the second transistor to the channel length of the second transistor is in the range of 0.5:1 to 3:1; the ratio of the channel width of the third transistor to the channel length of the third transistor is in the range of 0.5:1 to 3:1.

[0008] In some embodiments, the pulse number reduction module includes a fourth transistor, one of the source or the drain of the fourth transistor is electrically connected to the second node, the other of the source or the drain of the fourth transistor is electrically connected to the third node, and the gate of the fourth transistor is electrically connected to the reset line; wherein the fourth transistor is a P-channel thin film transistor.

[0009] In some embodiments, a ratio of a channel width of the fourth transistor to a channel length of the fourth transistor is greater than or equal to 0.5 and less than or equal to 1.5.

[0010] In some embodiments, the pulse number reduction module further includes a first capacitor, one end of the first capacitor is electrically connected to the gate of the fourth transistor, and the other end of the first capacitor is electrically connected to the other of the source or the drain of the fourth transistor.

[0011] In some embodiments, the first output stage includes a pull-up transistor and a second capacitor, the gate of the pull-up transistor is electrically connected to one of the source or drain of the fourth transistor, one of the source or drain of the pull-up transistor is electrically connected to the second clock line, and the other of the source or drain of the pull-up transistor outputs a first gate control signal; one end of the second capacitor is electrically connected to the gate of the pull-up transistor, and the other end of the second capacitor is electrically connected to the other of the source or drain of the pull-up transistor; wherein the ratio of the capacity of the first capacitor to that of the second capacitor is greater than or equal to 0.5.

[0012] In some of the embodiments, the output end of the second output stage is electrically connected to the second gate control line, the second gate control line is used to transmit a second gate control signal, and the second gate control signal has a first positive pulse and a second positive pulse in sequence in one frame; the output end of the first output stage is electrically connected to the first gate control line, the first gate control line is used to transmit the first gate control signal, and the first gate control signal has a first negative pulse in one frame.

[0013] In some of the embodiments, in one frame, the duration of the second positive pulse is longer than the duration of the first negative pulse, and the duration of the first negative pulse is within the duration of the second positive pulse.

[0014] In some embodiments, the control end of the pull-up control module is electrically connected to the first clock line, and the first clock line is used to transmit the first clock signal; the first output stage is electrically connected to the second clock line, and the second clock line is used to transmit the second clock signal, and the phase difference between the first clock signal and the second clock signal is 180°; a falling edge of the second clock signal, the falling edge of the second positive pulse, and the rising edge of the first negative pulse are all located in the duration of a positive pulse of the first clock signal.

[0015] In the second aspect, the present application provides a display panel, which includes a pixel circuit and a gate driving circuit in at least one of the above-mentioned embodiments, the pixel circuit includes a write transistor for controlling the input of a data signal and a compensation transistor for controlling the input of the data signal to the gate of the driving transistor; the output end of the first output stage is electrically connected to the gate of the write transistor, and the output end of the second output stage is electrically connected to the gate of the compensation transistor.

[0016] In some embodiments, the first gate control signal is an N-th level negative pulse scanning signal, and the second gate control signal is an N-th level positive pulse scanning signal; the control end of the pulse number reduction module is connected to the NX-th level positive pulse scanning signal, where N is an integer greater than or equal to 1, and X is an integer greater than or equal to 2.

[0017] In some of the embodiments, the pixel circuit further includes a first initialization transistor for initializing the gate potential of the driving transistor, and the gate of the first initialization transistor is connected to the NX-th level positive pulse scanning signal.

[0018] In some implementations, the level transmission signal selection module receives a start control signal or a NY-th level positive pulse scanning signal, where Y is an integer greater than or equal to 1.

[0019] The gate driving circuit and display panel provided in the present application can output a second gate control signal with a larger number of pulses through a level transmission signal selection module, a pull-up control module and a second output stage, and can also select the second gate control signal as a level transmission signal between different gate driving units; and can also output a first gate control signal with a smaller number of pulses through a level transmission signal selection module, a pull-up control module, a pulse number reduction module, a first inversion module and a first output stage, which can meet the needs of the corresponding pixel circuit for the time, number and other aspects of the gate control signal pulses in one frame, thereby being able to drive the pixel circuit to achieve quality display.

[0020] Furthermore, the gate drive circuit and display panel provided by the present application, by constructing a level transmission signal selection module, a first inversion module, and at least one of the second output stages including three transistors of the same channel type, can construct a level transmission signal selection module with an inversion effect with a smaller number of transistors of the same channel type, thereby simplifying the manufacturing process and improving the dynamic performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0022] Figure 1 Schematic diagram of the structure of a gate drive circuit in the related art.

[0023] Figure 2 for Figure 1 The timing diagram of the gate drive circuit shown.

[0024] Figure 3 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application.

[0025] Figure 4 for Figure 3 The timing diagram of the gate drive circuit shown.

[0026] Figure 5 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the first stage of the process.

[0027] Figure 6 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the second stage of the status.

[0028] Figure 7 for Figure 3 The gate drive circuit shown in Figure 4Schematic diagram of the third stage of the status.

[0029] Figure 8 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the fourth stage of the status.

[0030] Fig. 9 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the fifth stage of the status.

[0031] Fig.10 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the sixth stage of the status.

[0032] Fig.11 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the seventh stage of the state.

[0033] Fig.12 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the eighth stage of the state.

[0034] Fig.13 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the ninth stage of the process.

[0035] Fig.14 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the status of the tenth stage.

[0036] Fig.15 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the status of the eleventh stage.

[0037] Fig.16 for Figure 3 A schematic diagram of the structure of cascading between different gate driving units in the gate driving circuit shown.

[0038] Fig.17 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0039] Fig.18 for Fig.17 A schematic structural diagram of a pixel circuit in a display panel is shown.

[0040] Fig.19 for Fig.18 Timing diagram of the pixel circuit shown. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0043] See also Figure 1 , Figure 2 , Figure 1 Schematic diagram of the structure of a gate drive circuit in the related art. Figure 2 for Figure 1 The timing diagram of the gate driving circuit shown in FIG. Although this gate driving circuit can output a gate control signal (Nout) with a positive pulse and a gate control signal (Pout) with a negative pulse at the same time, its disadvantage is that there is only one positive pulse of the gate control signal (Nout) and one negative pulse of the gate control signal (Pout) in one frame and they can only be output at the same time, which cannot meet the driving requirements of the corresponding pixel circuit.

[0044] In view of this, this embodiment provides a gate driving circuit, see Figures 1 to 19 ,like Figure 3 As shown, the gate driving circuit includes multiple cascaded gate driving units, one of which includes a stage transmission signal selection module 10, a pull-up control module 20, a pulse number reduction module 30, a first inversion module 50, a first output stage and at least one of a second output stage 70.

[0045] The stage-transmission signal selection module 10 is electrically connected between the first wiring and the first node O.

[0046] The pull-up control module 20 controls the potential of the second node K according to the potential of the first node O and the potential of the first clock signal.

[0047] The pulse number reduction module 30 is electrically connected between the second node K and the third node Q, and a control terminal of the pulse number reduction module 30 is electrically connected to the reset line.

[0048] The first inversion module 50 is connected between the second node K and the fourth node P.

[0049] The first output stage outputs a first gate control signal according to the potential of the third node Q and the potential of the fourth node P.

[0050] The second output stage 70 outputs a second gate control signal according to the potential of the second node K, and the number of pulses of the second gate control signal in one frame is greater than the number of pulses of the first gate control signal in one frame.

[0051] Wherein, at least one of the stage transmission signal selection module 10, the first inversion module 50 and the second output stage 70 includes three transistors of the same channel type.

[0052] It can be understood that the gate driving circuit provided in this embodiment can output a second gate control signal with a larger number of pulses through the level transmission signal selection module 10, the pull-up control module 20 and the second output stage 70, and can also select the second gate control signal as the level transmission signal between different gate driving units; and can output a first gate control signal with a smaller number of pulses through the level transmission signal selection module 10, the pull-up control module 20, the pulse number reduction module 30, the first inversion module 50 and the first output stage, which can meet the needs of the corresponding pixel circuit for the pulses of the gate control signal in time, quantity, etc. in one frame, thereby being able to drive the pixel circuit to achieve image quality display.

[0053] Furthermore, the gate drive circuit and display panel provided in this embodiment, by constructing at least one of the stage transmission signal selection module 10, the first inversion module 50 and the second output stage 70 including three transistors of the same channel type, can construct the stage transmission signal selection module 10, the first inversion module 50 and the second output stage 70 with inversion effect with a smaller number of transistors of the same channel type, thereby simplifying the manufacturing process and improving the dynamic performance.

[0054] Among them, the input end of the level transmission signal selection module 10 is electrically connected to the starting control line or the NYth level positive pulse scanning line, wherein N is an integer greater than or equal to 1, and Y is an integer greater than or equal to 1.

[0055] The input end of the pull-up control module 20 is electrically connected to the output end of the stage transmission signal selection module 10 , and the control end of the pull-up control module 20 is electrically connected to the first clock line.

[0056] The input end of the pulse number reduction module 30 is electrically connected to the output end of the pull-up control module 20 , and the control end of the pulse number reduction module 30 is electrically connected to the reset line.

[0057] The control end of the pull-up module 40 is electrically connected to the output end of the pulse number reduction module 30, the input end of the pull-up module 40 is electrically connected to the second clock line, and the output end of the pull-up module 40 is electrically connected to the Nth level negative pulse scanning line. The input end of the first inversion module 50 is electrically connected to the output end of the pull-up control module 20.

[0058] The control end of the pull-down module 60 is electrically connected to the output end of the first inverting module 50 , the input end of the pull-down module 60 is electrically connected to the high potential line, and the output end of the pull-down module 60 is electrically connected to the Nth level negative pulse scanning line.

[0059] The input end of the second output stage 70 is electrically connected to the input end of the pull-up control module 20, and the output end of the second output stage 70 is electrically connected to the Nth level positive pulse scanning line, and the number of positive pulses output by the Nth level positive pulse scanning line in one frame is greater than the number of negative pulses output by the Nth level negative pulse scanning line in one frame.

[0060] In one embodiment, the first output stage includes a pull-up module 40 and a pull-down module 60 .

[0061] It should be noted that the first wiring can be a starting control line or a NY-th level positive pulse scanning line; when NY is less than or equal to 0, the first wiring is a starting control line. The N-th level positive pulse scanning line, i.e., the second gate control line, is used to transmit the N-th level positive pulse scanning signal Nout [N], i.e., the second gate control signal. The N-th level negative pulse scanning line, i.e., the first gate control line, is used to transmit the N-th level negative pulse scanning signal Pout [N], i.e., the first gate control signal.

[0062] In one embodiment, the pulse number reduction module 30 includes a fourth transistor T11, one of the source or the drain of the fourth transistor T11 is electrically connected to the output end of the pull-up control module 20, the other of the source or the drain of the fourth transistor T11 is electrically connected to the control end of the pull-up module 40, and the gate of the fourth transistor T11 is electrically connected to the reset line; wherein the fourth transistor T11 is a P-channel thin film transistor; the reset line is the NXth level positive pulse scanning line, and X is an integer greater than or equal to 2.

[0063] It should be noted that the output end of the pull-up control module 20 is the second node K. The control end of the pull-up module 40 is the third node Q. The other of the source or the drain of the fourth transistor T11 is the node W. The pulse number reduction module 30 is used to reduce the double pulses appearing at the second node K in one frame to a single pulse appearing at the third node Q in one frame; specifically, the first pulse appearing at the second node K in one frame is eliminated, while the second pulse appearing in the same frame is retained.

[0064] In one embodiment, a ratio of a channel width of the fourth transistor T11 to a channel length of the fourth transistor T11 is greater than or equal to 0.5 and less than or equal to 1.5.

[0065] It should be noted that this embodiment is conducive to ensuring the output stability of the Nth level negative pulse scanning signal Pout [N], and avoids the coupling pull-down phenomenon before the negative pulse arrives.

[0066] In one embodiment, the pulse number reduction module 30 further includes a first capacitor C2, one end of the first capacitor C2 is electrically connected to the gate of the fourth transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the source or the drain of the fourth transistor T11.

[0067] It should be noted that this embodiment is beneficial to further improve the output stability of the Nth stage negative pulse scanning signal Pout [N].

[0068] In one embodiment, the pull-up module 40 includes a pull-up transistor T6 and a second capacitor C1, the gate of the pull-up transistor T6 is electrically connected to one of the source or drain of the fourth transistor T11, one of the source or drain of the pull-up transistor T6 is electrically connected to the second clock line, and the other of the source or drain of the pull-up transistor T6 is electrically connected to the Nth level negative pulse scan line; one end of the second capacitor C1 is electrically connected to the gate of the pull-up transistor T6, and the other end of the second capacitor C1 is electrically connected to the other of the source or drain of the pull-up transistor T6; wherein, the ratio of the capacity of the first capacitor C2 to the second capacitor C1 is greater than or equal to 0.5.

[0069] It should be noted that the design of the capacitance ratio of the first capacitor C2 to the second capacitor C1 in this embodiment is conducive to further ensuring the output stability of the Nth level negative pulse scanning signal Pout [N] and avoiding the coupling pull-down phenomenon before the negative pulse arrives.

[0070] Specifically, the capacity of the first capacitor C2 may be greater than or equal to 50 fF. The capacity of the second capacitor C1 may be greater than or equal to 100 fF.

[0071] The ratio of the channel width of the pull-up transistor T6 to the channel length of the pull-up transistor T6 is greater than 30:1, which is conducive to further ensuring the output stability of the Nth level negative pulse scanning signal Pout [N]. The pull-up transistor T6 can be a P-channel thin film transistor.

[0072] In one embodiment, at least one of the stage transmission signal selection module 10, the first inversion module 50 and the second output stage 70 includes a first transistor T14, a second transistor T12 and a third transistor T13, one of the source or the drain of the first transistor T14 is electrically connected to the low potential line, the gate of the first transistor T14 is electrically connected to the start control line or the NY-th stage positive pulse scanning line, and the first transistor T14 is a P-channel thin film transistor; the gate of the second transistor T12 is electrically connected to the gate of the first transistor T14, one of the source or the drain of the second transistor T12 is electrically connected to the high potential line, and the second transistor T12 is a P-channel thin film transistor; the gate of the third transistor T13 is electrically connected to the other of the source or the drain of the first transistor T14, one of the source or the drain of the third transistor T13 is electrically connected to the low potential line, the other of the source or the drain of the third transistor T13 is electrically connected to the other of the source or the drain of the second transistor T12, and the third transistor T13 is a P-channel thin film transistor.

[0073] It should be noted that the level transmission signal selection module 10 in this embodiment not only has an objective inverting effect, that is, the potentials of the input signal and the output signal are opposite at the same time, but also plays a role in making the Nth level positive pulse scanning signal Nout [N] serve as the level transmission signal between the gate driving units. Otherwise, the level transmission cannot be achieved between the gate driving units, which will cause the gate driving circuit to be unable to normally provide the corresponding scanning signal.

[0074] Among them, the ratio of the channel width of the first transistor T14 to the channel length of the first transistor T14 is greater than 1.5:1; the ratio of the channel width of the second transistor T12 to the channel length of the second transistor T12 is in the range of 0.5:1 to 3:1; the ratio of the channel width of the third transistor T13 to the channel length of the third transistor T13 is in the range of 0.5:1 to 3:1. In this way, the role played by the stage transmission signal selection module 10 in the present application can be more accurately realized.

[0075] The high potential line is used to transmit a high potential signal VGH, which can control the N-channel thin film transistor to be turned on or the P-channel thin film transistor to be turned off. The low potential line is used to transmit a low potential signal VGL, which can control the P-channel thin film transistor to be turned on or the N-channel thin film transistor to be turned off.

[0076] In one embodiment, the pull-up control module 20 includes a pull-up control transistor T2, one of the source or the drain of the pull-up control transistor T2 is electrically connected to the output end of the stage transmission signal selection module 10, the other of the source or the drain of the pull-up control transistor T2 is electrically connected to the input end of the pulse number reduction module 30, and the gate of the pull-up control transistor T2 is electrically connected to the first clock line.

[0077] It should be noted that the pull-up control transistor T2 may be a P-channel thin film transistor. The ratio of the channel width of the pull-up control transistor T2 to the channel length of the pull-up control transistor T2 is in the range of 0.5:1 to 3:1.

[0078] In one embodiment, the first inversion module 50 or the stage transmission signal selection module 10 may also include a transistor T3 and a transistor T1, one of the source or the drain of the transistor T3 is electrically connected to the high potential line, the other of the source or the drain of the transistor T3 is electrically connected to one of the source or the drain of the transistor T1 and the control end of the pull-down module 60, the other of the source or the drain of the transistor T1 is electrically connected to the low potential line, and the output end of the pull-up control module 20 is electrically connected to the gate of the transistor T3, the first gate of the transistor T1 and the second gate of the transistor T1.

[0079] It should be noted that the transistor T3 is a P-channel thin film transistor, and the transistor T1 is a dual-gate N-channel thin film transistor, so that the dynamic performance of the transistors T3 and T1 can be improved, and thus the dynamic performance of the first inverter module 50 can be improved.

[0080] The ratio of the channel width of the transistor T3 to the channel length of the transistor T3 is in the range of 0.5:1 to 3:1. The ratio of the channel width of the transistor T1 to the channel length of the transistor T1 is greater than or equal to 2:1.

[0081] In one embodiment, the pull-down module 60 includes a pull-down transistor T7, one of the source or the drain of the pull-down transistor T7 is electrically connected to the high potential line, the other of the source or the drain of the pull-down transistor T7 is electrically connected to the Nth level negative pulse scan line, and the gate of the pull-down transistor T7 is electrically connected to the output end of the first inversion module 50, i.e., the fourth node P.

[0082] It should be noted that the pull-down transistor T7 can be a P-channel thin film transistor. Under the joint action of the pull-down module 60 and the pull-up module 40, the required Nth level negative pulse scanning signal Pout [N] can be modulated.

[0083] The ratio of the channel width of the pull-down transistor T7 to the channel length of the pull-down transistor T7 is greater than or equal to 30:1.

[0084] In one embodiment, the second output stage 70 or the stage transmission signal selection module 10 may also include a transistor T9 and a transistor T10, one of the source or the drain of the transistor T9 is electrically connected to the high potential line, the other of the source or the drain of the transistor T9 is electrically connected to one of the source or the drain of the transistor T10 and the Nth stage positive pulse scanning line, the other of the source or the drain of the transistor T10 is electrically connected to the low potential line, and the output end of the pull-up control module 20 is electrically connected to the gate of the transistor T9, the first gate of the transistor T10 and the second gate of the transistor T10.

[0085] It should be noted that the transistor T9 is a P-channel thin film transistor and the transistor T10 is a dual-gate N-channel thin film transistor, which can improve the dynamic performance of the transistors T9 and T10, and further improve the dynamic performance of the second output stage 70.

[0086] The ratio of the channel width of the transistor T9 to the channel length of the transistor T9 is greater than or equal to 30:1. The ratio of the channel width of the transistor T10 to the channel length of the transistor T10 is greater than or equal to 30:1.

[0087] In one embodiment, the N-th level gate driving unit further includes an anti-leakage module 80, one end of the anti-leakage module 80 is electrically connected to the output end of the pulse number reduction module 30, the other end of the anti-leakage module 80 is electrically connected to the control end of the pull-up module 40, and the control end of the anti-leakage module 80 is electrically connected to the low potential line.

[0088] It should be noted that the anti-leakage module 80 can be used to prevent the charge of the third node Q from flowing to the node W, which is beneficial to maintaining the potential stability of the third node Q.

[0089] In one embodiment, the anti-leakage module 80 includes an anti-leakage transistor T8, one of the source or the drain of the anti-leakage transistor T8 is electrically connected to the output end of the pulse number reduction module 30, the other of the source or the drain of the anti-leakage transistor T8 is electrically connected to the control end of the pull-up module 40, and the gate of the anti-leakage transistor T8 is electrically connected to the low potential line.

[0090] It should be noted that the leakage protection transistor T8 can be a P-channel thin film transistor; it can also be an N-channel thin film transistor. In this case, the gate of the leakage protection transistor T8 needs to be electrically connected to the high potential line.

[0091] The ratio of the channel width of the anti-leakage transistor T8 to the channel length of the anti-leakage transistor T8 is in the range of 0.5:1 to 3:1.

[0092] In one embodiment, the N-th level gate driving unit also includes a feedback module 90, which includes a transistor T4 and a transistor T5, one of the source or the drain of the transistor T4 is electrically connected to the output end of the pull-up control module 20, the gate of the transistor T4 is electrically connected to the second clock line, the other of the source or the drain of the transistor T4 is electrically connected to one of the source or the drain of the transistor T5, the other of the source or the drain of the transistor T5 is electrically connected to the high potential line, and the gate of the transistor T5 is electrically connected to the output end of the first inversion module 50.

[0093] The ratio of the channel width of the transistor T4 to the channel length of the transistor T4 is in the range of 0.5:1 to 3:1. The ratio of the channel width of the transistor T5 to the channel length of the transistor T5 is in the range of 0.5:1 to 3:1.

[0094] It should be noted that the feedback module 90 can maintain the second node K at a high potential based on the potential of the fourth node P and the potential of the second clock line. That is, when the fourth node P is at a low potential and the second clock signal CK is at a low potential, the high potential line can control the potential of the second node K to the potential of the high potential signal VGH.

[0095] It should be noted that the Nth level positive pulse scan line is used to transmit the Nth level positive pulse scan signal Nout [N]. The Nth level negative pulse scan line is used to transmit the Nth level negative pulse scan signal Pout [N]. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The NYth level positive pulse scan line is used to transmit the NYth level positive pulse scan signal Nout [NY]. The NXth level positive pulse scan line is used to transmit the NXth level positive pulse scan signal Nout [NX]. The reset line is used to transmit the reset signal RST.

[0096] The working process of the gate driving unit in one frame may include the following: Figure 4 The following stages are shown:

[0097] Stage 1 S1: Figure 4 , Figure 5 As shown, the start control signal STV, the reset signal RST, and the second clock signal CK are all at a low potential, the first clock signal XCK is at a high potential, the first node O, the second node K, and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse scanning signal Nout [N] is at a low potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0098] Stage 2 S2: Figure 4 , Figure 6 As shown, the start control signal STV, the reset signal RST, and the first clock signal XCK are all at a low potential, the second clock signal CK is at a high potential, the first node O, the second node K, and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse scanning signal Nout [N] is at a low potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0099] Stage 3 S3: Figure 4 , Figure 7 As shown, the start control signal STV and the first clock signal XCK are both at a low potential, the reset signal RST and the second clock signal CK are both at a high potential, the first node O, the second node K and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse scanning signal Nout [N] is at a low potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0100] Stage 4 S4: Figure 4 , Figure 8 As shown, the start control signal STV and the second clock signal CK are both at a low potential, the reset signal RST and the first clock signal XCK are both at a high potential, the first node O, the second node K and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse scanning signal Nout [N] is at a low potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0101] Stage 5 S5: Figure 4 , Fig. 9 As shown, the reset signal RST and the second clock signal CK are both at a low potential, the start control signal STV and the first clock signal XCK are both at a high potential, the second node K and the third node Q are both at a high potential, the first node O and the fourth node P are both at a low potential, the Nth level positive pulse scanning signal Nout [N] is at a low potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0102] Stage 6 S6: Figure 4 , Fig.10 As shown, the first clock signal XCK is at a low potential, the reset signal RST, the start control signal STV, and the second clock signal CK are all at a high potential, the second node K and the first node O are both at a low potential, the third node Q and the fourth node P are both at a high potential, the Nth level positive pulse scanning signal Nout [N] is at a high potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0103] Stage 7 S7: Figure 4 , Fig.11As shown, the start control signal STV and the second clock signal CK are both at a low potential, the reset signal RST and the first clock signal XCK are both at a high potential, the second node K is at a low potential, the first node O, the third node Q, and the fourth node P are all at a high potential, the Nth level positive pulse scanning signal Nout [N] is at a high potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0104] Stage 8 S8: Figure 4 , Fig.12 As shown, the reset signal RST, the start control signal STV, and the first clock signal XCK are all at a low potential, the second clock signal CK is at a high potential, the fourth node P is at a low potential, the third node Q and the second node K are both at a high potential, the Nth level positive pulse scanning signal Nout [N] is at a low potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0105] Stage 9 S9: Figure 4 , Fig.13 As shown, the reset signal RST and the second clock signal CK are both at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the first node O and the fourth node P are at a low potential, the third node Q and the second node K are both at a high potential, the Nth level positive pulse scanning signal Nout [N] is at a low potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0106] Stage 10: Figure 4 , Fig.14 As shown, the reset signal RST and the first clock signal XCK are both at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the first node O, the third node Q, and the second node K are at a low potential, the fourth node P is at a high potential, the Nth level positive pulse scanning signal Nout [N] is at a high potential, and the Nth level negative pulse scanning signal Pout [N] is at a high potential.

[0107] Stage 11 S11: Figure 4 , Fig.15 As shown, the start control signal STV, the reset signal RST, and the second clock signal CK are all at a low potential, the first clock signal XCK is at a high potential, the third node Q and the second node K are at a low potential, the first node O and the fourth node P are at a high potential, the Nth level positive pulse scanning signal Nout [N] is at a high potential, and the Nth level negative pulse scanning signal Pout [N] is at a low potential.

[0108] It should be noted that Figures 5 to 15 The "cross" in the indicates that the transistor it covers is in the off state. Figures 5 to 15 The dashed arrow in the figure shows the direction of current flow.

[0109] since Figure 4 It can be seen that the N-th level positive pulse scanning signal Nout [N] has a first positive pulse and a second positive pulse in sequence in one frame; the N-th level negative pulse scanning signal Pout [N] has a first negative pulse in one frame.

[0110] In one frame, a duration of the second positive pulse is longer than a duration of the first negative pulse, and a duration of the first negative pulse is within a duration of the second positive pulse.

[0111] Specifically, the falling edge of the second positive pulse and the rising edge of the first negative pulse are at the same time.

[0112] In one embodiment, the phase difference between the first clock signal XCK and the second clock signal CK is 180°; a falling edge of the second clock signal CK, a falling edge of the second positive pulse, and a rising edge of the first negative pulse are all located within the duration of a positive pulse of the first clock signal XCK.

[0113] Fig.16 for Figure 3 The schematic diagram of the structure of the cascade connection between different gate driving units in the gate driving circuit shown in the figure, wherein the first gate driving unit 101, the second gate driving unit 102, the third gate driving unit 103, the fourth gate driving unit 104, the fifth gate driving unit 105, the sixth gate driving unit 106, etc. are arranged in sequence from top to bottom. The first clock line is electrically connected to each gate driving unit, and the second clock line is also electrically connected to each gate driving unit.

[0114] Among them, P1 to P6 can be respectively a first-level negative pulse scanning line for transmitting a first-level negative pulse scanning signal, a second-level negative pulse scanning line for transmitting a second-level negative pulse scanning signal, a third-level negative pulse scanning line for transmitting a third-level negative pulse scanning signal, a fourth-level negative pulse scanning line for transmitting a fourth-level negative pulse scanning signal, a fifth-level negative pulse scanning line for transmitting a fifth-level negative pulse scanning signal, and a sixth-level negative pulse scanning line for transmitting a sixth-level negative pulse scanning signal. N1 to N6 can be respectively a first-level positive pulse scanning line for transmitting a first-level positive pulse scanning signal, a second-level positive pulse scanning line for transmitting a second-level positive pulse scanning signal, a third-level positive pulse scanning line for transmitting a third-level positive pulse scanning signal, a fourth-level positive pulse scanning line for transmitting a fourth-level positive pulse scanning signal, a fifth-level positive pulse scanning line for transmitting a fifth-level positive pulse scanning signal, and a sixth-level positive pulse scanning line for transmitting a sixth-level positive pulse scanning signal.

[0115] The input end of the intermediate signal selection module 10 of the first gate drive unit 101 is electrically connected to the start control line to access the start control signal STV. The input ends of the intermediate signal selection modules 10 of other gate drive units are sequentially connected to the positive pulse scanning line of the gate drive unit of the previous level, for example, N1 is connected to the input end of the intermediate signal selection module 10 of the second gate drive unit 102, N2 is connected to the input end of the intermediate signal selection module 10 of the third gate drive unit 103, N3 is connected to the input end of the intermediate signal selection module 10 of the fourth gate drive unit 104, N4 is connected to the input end of the intermediate signal selection module 10 of the fifth gate drive unit 105, N5 is connected to the input end of the intermediate signal selection module 10 of the sixth gate drive unit 106, and the like can be deduced in turn. Among them, Y can also be 2, 3, 4, 5, 6, etc., and Y equals 1 as an example for explanation here.

[0116] The control end of the pulse number reduction module 30 in the fifth gate driving unit 105 is connected to N1, and the control end of the pulse number reduction module 30 in the sixth gate driving unit 106 is connected to N2, and the others can be deduced in the same manner. Among them, X can also be 3, 4, 5, 6, 7, etc., and X is taken as 4 as an example for explanation.

[0117] Among them, each output end of the first gate driving unit 101 to the fourth gate driving unit 104 is not used to drive the corresponding pixel circuit for display, but is connected to a dummy pixel (Dummy) or is suspended. Each output end of the fifth gate driving unit 105 is electrically connected to the pixel circuit (Pixel) of the first row, and each output end of the sixth gate driving unit 106 is electrically connected to the pixel circuit (Pixel) of the second row, and the others can be deduced in this way.

[0118] Fig.17 The above figure is a schematic diagram of the structure of the display panel in the traditional technology. On the left side (non-display area or border area) of the display area (AA area), gate driving circuits for providing the light-emitting control signal EM, the scanning signal Nscan1, and the scanning signal Pscan are arranged respectively. On the right side (non-display area or border area) of the display area (AA area), gate driving circuits for providing the scanning signal Pscan, the scanning signal Nscan2, and the scanning signal Pscan2 are arranged respectively.

[0119] Among them, each scanning signal Pscan drives a row of pixel circuits. The working modes of the scanning signals Nscan1 and Nscan2 are also the same as those of the scanning signal Pscan, but one scanning signal Nscan1 / scanning signal Nscan2 needs to drive two rows of pixel circuits. In the actual working process, in order to achieve a narrower border, the gate driving circuit for outputting the scanning signal Nscan1 and the gate driving circuit for outputting the scanning signal Nscan2 are both set to single-sided driving. However, this will cause the driving capability of the two gate driving circuits to deteriorate and the power consumption will also increase.

[0120] In view of this, this embodiment will Figure 3 The gate drive circuit shown is set up as Fig.17 The bilateral drive shown in the figure below is to set a Figure 3 The gate drive circuit in the display is used to input the corresponding scan signals from both ends of each scan line at the same time. This not only improves the driving capability of the positive pulse scan signal (Nscan), but also reduces power consumption and the space occupied by the border, which is conducive to the development of narrower border solutions.

[0121] In one of the embodiments, the present embodiment provides a display panel, which includes the gate driving circuit and the pixel circuit in at least one of the above embodiments, and a row of pixel circuits is electrically connected to the Nth level positive pulse scanning line and the Nth level negative pulse scanning line.

[0122] It can be understood that since the display panel provided in this embodiment includes the gate driving circuit in at least one of the above-mentioned embodiments, it can also output a second gate control signal with a larger number of pulses through the level transmission signal selection module 10, the pull-up control module 20 and the second output stage 70, and the second gate control signal can also be selected as the level transmission signal between different gate driving units; and the first gate control signal with a smaller number of pulses can be output through the level transmission signal selection module 10, the pull-up control module 20, the pulse number reduction module 30, the first inversion module 50 and the first output stage, which can meet the needs of the corresponding pixel circuit for the pulses of the gate control signal in time, quantity, etc. in one frame, thereby driving the pixel circuit to achieve image quality display.

[0123] Furthermore, the gate drive circuit and display panel provided in this embodiment, by constructing at least one of the stage transmission signal selection module 10, the first inversion module 50 and the second output stage 70 including three transistors of the same channel type, can construct the stage transmission signal selection module 10, the first inversion module 50 and the second output stage 70 with inversion effect with a smaller number of transistors of the same channel type, thereby simplifying the manufacturing process and improving the dynamic performance.

[0124] Fig.18 for Fig.17 The schematic diagram of the structure of the pixel circuit in the display panel shown in FIG. 1 shows that, Figure 3 The gate drive circuit shown can be Fig.18 The pixel circuit shown provides corresponding scan signals Nscan[n], Nscan[nX] and Pscan1.

[0125] Fig.18 The pixel circuit shown may include at least one of a write transistor T2P, a drive transistor T1P, a first light emission control transistor T5P, a second light emission control transistor T6P, a first initialization transistor T4P, a first initialization transistor T4P, a third initialization transistor T8P, a compensation transistor T3P, a light emitting device D1, a storage capacitor Cst, and a bootstrap capacitor Cboost.

[0126] The first power line is electrically connected to the first electrode of the first light-emitting control transistor T5P and one end of the storage capacitor Cst, the second electrode of the first light-emitting control transistor T5P is electrically connected to the first electrode of the driving transistor T1P and the first electrode of the writing transistor T2P, the second electrode of the driving transistor T1P is electrically connected to the first electrode of the compensation transistor T3P and the first electrode of the second light-emitting control transistor T6P, the second electrode of the second light-emitting control transistor T6P is electrically connected to the first electrode of the first initialization transistor T4P and the anode of the light-emitting device D1, and the cathode of the light-emitting device D1 is electrically connected to the second power line. The light-emitting control line is electrically connected to the gate of the first light-emitting control transistor T5P and the gate of the second light-emitting control transistor T6P. The second electrode of the writing transistor T2P is electrically connected to the data line, and the gate of the writing transistor T2P is electrically connected to the first scanning line and one end of the bootstrap capacitor Cboost. The second electrode of the first initialization transistor T4P is electrically connected to the second initialization line, and the gate of the first initialization transistor T4P is electrically connected to the second scanning line. The second electrode of the compensation transistor T3P is electrically connected to the gate of the driving transistor T1P, and the gate of the compensation transistor T3P is electrically connected to the third scan line. The gate of the driving transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor Cboost, and the first electrode of the first initialization transistor T4P. The second electrode of the first initialization transistor T4P is electrically connected to the first initialization line, and the gate of the first initialization transistor T4P is electrically connected to the fourth scan line. The first electrode of the third initialization transistor T8P is electrically connected to the first electrode of the driving transistor T1P, the second electrode of the third initialization transistor T8P is electrically connected to the third initialization line, and the gate of the third initialization transistor T8P shares the second scan line with the gate of the first initialization transistor T4P.

[0127] It should be noted that the second initialization line may also be replaced by the first initialization line, which can reduce one wiring required for the pixel circuit and is beneficial to increase the density of the pixel circuit in the display panel.

[0128] The first electrode may be one of the source electrode and the drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. For example, when the first electrode is the source electrode, the second electrode is the drain electrode; or when the first electrode is the drain electrode, the second electrode is the source electrode.

[0129] Wherein, the first power line is used to transmit a positive power signal VDD, the second power line is used to transmit a negative power signal VSS, and the potential of the positive power signal VDD is higher than the potential of the negative power signal VSS. The data line is used to transmit a data signal Data. The light control line is used to transmit a light control signal EM. The first initialization line is used to transmit a first initialization signal Vi1. The second initialization line is used to transmit a second initialization signal. The third initialization line is used to transmit a third initialization signal Vi3. The first scan line is used to transmit a scan signal Pscan1. The second scan line is used to transmit a scan signal Pscan2. The third scan line is used to transmit a scan signal Nscan [n]. The fourth scan line is used to transmit a scan signal Nscan [nX].

[0130] Fig.18 The working sequence of the pixel circuit in one frame is as follows: Fig.19 As shown, under the common drive of the scanning signal Pscan1, the scanning signal Pscan2, the scanning signal Nscan [nX], the scanning signal Nscan [n] and the light emitting control signal EM, Fig.18 The pixel circuit shown can perform normal display.

[0131] Among them, the scanning signal Pscan1, the scanning signal Nscan [nX], and the scanning signal Nscan [n] can be Figure 3 The gate drive circuit shown is provided. The scanning signal Pscan1 is the same as the Nth level negative pulse scanning signal Pout [N], the scanning signal Nscan [n] is the same as the Nth level positive pulse scanning signal Nout [N], and the scanning signal Nscan [nX] is the same as the NXth level positive pulse scanning signal Nout [NX].

[0132] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0133] The gate drive circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit comprises a plurality of cascaded gate driving units, wherein one of the gate driving units comprises: a level transmission signal selection module, the level transmission signal selection module being electrically connected between the first wiring and the first node; A pull-up control module, wherein the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; a pulse number reduction module, the pulse number reduction module being electrically connected between the second node and the third node, and a control end of the pulse number reduction module being electrically connected to a reset line; A first inverting module, wherein the first inverting module is connected between the second node and a fourth node; a first output stage, the first output stage outputting a first gate control signal according to the potential of the third node and the potential of the fourth node; and a second output stage, wherein the second output stage outputs a second gate control signal according to the potential of the second node, wherein the number of pulses of the second gate control signal in one frame is greater than the number of pulses of the first gate control signal in one frame; Wherein, at least one of the stage transmission signal selection module, the first inversion module and the second output stage includes three transistors of the same channel type.

2. The gate driving circuit according to claim 1, characterized in that: At least one of the stage transmission signal selection module, the first inversion module and the second output stage comprises: a first transistor, wherein one of a source or a drain of the first transistor is electrically connected to a low potential line, a gate of the first transistor is electrically connected to the first wiring, and the first transistor is a P-channel thin film transistor; a second transistor, wherein a gate of the second transistor is electrically connected to a gate of the first transistor, one of a source or a drain of the second transistor is electrically connected to a high potential line, the other of the source or the drain of the second transistor is electrically connected to the first node, and the second transistor is a P-channel thin film transistor; and A third transistor, wherein the gate of the third transistor is electrically connected to the other of the source or the drain of the first transistor, one of the source or the drain of the third transistor is electrically connected to the low potential line, the other of the source or the drain of the third transistor is electrically connected to the first node, and the third transistor is a P-channel thin film transistor.

3. The gate driving circuit according to claim 2, characterized in that: The ratio of the channel width of the first transistor to the channel length of the first transistor is greater than 1.5:1; the ratio of the channel width of the second transistor to the channel length of the second transistor is in the range of 0.5:1 to 3:1; the ratio of the channel width of the third transistor to the channel length of the third transistor is in the range of 0.5:1 to 3:

1.

4. The gate driving circuit according to claim 1, characterized in that: The pulse number reduction module includes a fourth transistor, one of a source or a drain of the fourth transistor is electrically connected to the second node, the other of the source or the drain of the fourth transistor is electrically connected to the third node, and a gate of the fourth transistor is electrically connected to the reset line.

5. The gate driving circuit according to claim 4, characterized in that: A ratio of a channel width of the fourth transistor to a channel length of the fourth transistor is greater than or equal to 0.5 and less than or equal to 1.

5.

6. The gate driving circuit according to claim 4, characterized in that: The pulse number reduction module further includes a first capacitor, one end of which is electrically connected to the gate of the fourth transistor, and the other end of which is electrically connected to the other of the source or the drain of the fourth transistor.

7. The gate driving circuit according to claim 6, characterized in that: The first output stage comprises: a pull-up transistor, a gate of the pull-up transistor being electrically connected to the third node, one of a source or a drain of the pull-up transistor being electrically connected to a second clock line, and the other of the source or the drain of the pull-up transistor outputting the first gate control signal; and a second capacitor, one end of the second capacitor being electrically connected to the gate of the pull-up transistor, and the other end of the second capacitor being electrically connected to the other of the source or the drain of the pull-up transistor; Wherein, a ratio of the capacitance of the first capacitor to that of the second capacitor is greater than or equal to 0.

5.

8. The gate drive circuit according to any one of claims 1 to 7, characterized in that: The output end of the second output stage is electrically connected to a second gate control line, the second gate control line is used to transmit the second gate control signal, and the second gate control signal sequentially has a first positive pulse and a second positive pulse in one frame; The output end of the first output stage is electrically connected to a first gate control line, and the first gate control line is used to transmit the first gate control signal. The first gate control signal has a first negative pulse in one frame.

9. The gate driving circuit according to claim 8, characterized in that: In one frame, a duration of the second positive pulse is longer than a duration of the first negative pulse, and a duration of the first negative pulse is within a duration of the second positive pulse.

10. The gate driving circuit according to claim 9, characterized in that: The control end of the pull-up control module is electrically connected to a first clock line, and the first clock line is used to transmit a first clock signal; the first output stage is electrically connected to a second clock line, and the second clock line is used to transmit a second clock signal, and the phase difference between the first clock signal and the second clock signal is 180°; A falling edge of the second clock signal, a falling edge of the second positive pulse, and a rising edge of the first negative pulse are all located in a duration of a positive pulse of the first clock signal.

11. A display panel, characterized in that: The display panel comprises: a pixel circuit including a write transistor for controlling input of a data signal and a compensation transistor for controlling input of the data signal to a gate of a drive transistor; and According to the gate drive circuit as described in any one of claims 1 to 10, the output end of the first output stage is electrically connected to the gate of the write transistor, and the output end of the second output stage is electrically connected to the gate of the compensation transistor.

12. The display panel according to claim 11, characterized in that: The first gate control signal is an Nth level negative pulse scanning signal, and the second gate control signal is an Nth level positive pulse scanning signal; the control end of the pulse number reduction module is connected to the NXth level positive pulse scanning signal, wherein N is an integer greater than or equal to 1, and X is an integer greater than or equal to 2.

13. The display panel according to claim 12, characterized in that: The pixel circuit further includes a first initialization transistor for initializing the gate potential of the driving transistor, and the gate of the first initialization transistor is connected to the NX-th level positive pulse scanning signal.

14. The display panel according to claim 12, characterized in that: The level transmission signal selection module receives a start control signal or a NY-th level positive pulse scanning signal, wherein Y is an integer greater than or equal to 1.

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