Shift register unit, drive control circuit, display device, and drive method
By designing input, reset, and output circuits within the shift register unit, the duration of the control signal is ensured, thus resolving the issue of unstable node levels, improving output stability, and reducing area footprint.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2022-05-26
- Publication Date
- 2026-07-07
AI Technical Summary
The existing shift register unit output is unstable, causing display abnormalities, especially the node level is unstable during the output stage, which leads to unstable signals at the drive output end.
By designing the input circuit, reset circuit, first control circuit, and output circuit in the shift register unit, it is ensured that the effective level duration of the first control signal is greater than the effective level duration of the drive output signal, thereby increasing the conduction time of the first control circuit to stabilize the level of the second node and reduce the dependence on the capacitor.
This improves the output stability of the shift register unit, eliminates the need for additional large capacitors to maintain stable node levels, and reduces the footprint.
Smart Images
Figure CN117461072B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to shift register units, drive control circuits, display devices, and driving methods. Background Technology
[0002] With the rapid development of display technology, display devices are increasingly moving towards higher integration and lower cost. Among these technologies, GOA (Gate Driver on Array) integrates TFT (Thin Film Transistor) driving control circuitry onto the array substrate of the display device to drive the display. This driving control circuit typically consists of multiple cascaded shift register units. However, unstable output from these shift register units can lead to display abnormalities. Summary of the Invention
[0003] The shift register unit provided in this embodiment includes:
[0004] The input circuit is configured to provide an input signal to the first node in response to a first clock signal;
[0005] The reset circuit is configured to provide a first reference signal to the second node in response to a second clock signal;
[0006] A first control circuit is configured to provide the second clock signal to the second node in response to a first control signal;
[0007] The output circuit is configured to provide a third clock signal to the drive output terminal in response to a signal from the first node, and to provide a second reference signal to the drive output terminal in response to a signal from the second node.
[0008] Wherein, the duration of the effective level of the first control signal is greater than the duration of the effective level of the signal at the drive output terminal.
[0009] In some examples, the duration of the effective level of the first control signal is approximately twice the duration of the effective level of the signal at the drive output terminal.
[0010] In some examples, the first control circuit includes a first transistor;
[0011] The control electrode of the first transistor is configured to receive the first control signal, the first electrode of the first transistor is configured to receive the second clock signal, and the second electrode of the first transistor is coupled to the second node.
[0012] In some examples, the input circuitry includes a second transistor;
[0013] The control electrode of the second transistor is configured to receive the first clock signal, the first electrode of the second transistor is configured to receive the input signal, and the second electrode of the second transistor is coupled to the first node.
[0014] In some examples, the input circuit further includes a third transistor; the second terminal of the second transistor is coupled to the first node via the third transistor;
[0015] The control electrode of the third transistor is configured to receive the first clock signal, the first electrode of the third transistor is coupled to the second electrode of the second transistor, and the second electrode of the third transistor is coupled to the first node.
[0016] In some examples, the shift register unit further includes: a first noise reduction circuit;
[0017] The first noise reduction circuit is configured to provide the third clock signal to the first pole of the third transistor in response to the signal at the drive output terminal.
[0018] In some examples, the first noise reduction circuit includes: a fourth transistor;
[0019] The control electrode of the fourth transistor is coupled to the drive output terminal, the first electrode of the fourth transistor is configured to receive the third clock signal, and the second electrode of the fourth transistor is coupled to the first electrode of the third transistor.
[0020] In some examples, the first control circuit is coupled to the first terminal of the third transistor, and the signal at the first terminal of the third transistor is the first control signal.
[0021] In some examples, the first control circuit is coupled to the first node, and the signal of the first node is the first control signal.
[0022] In some examples, the output circuit includes a fifth transistor, a sixth transistor, and a first capacitor;
[0023] The control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is configured to receive the third clock signal, and the second electrode of the fifth transistor is coupled to the drive output terminal.
[0024] The control electrode of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is configured to receive the second reference signal, and the second electrode of the sixth transistor is coupled to the drive output terminal.
[0025] The first electrode plate of the first capacitor is coupled to the first node, and the second electrode plate of the first capacitor is coupled to the drive output terminal.
[0026] In some examples, the output circuit further includes a second capacitor;
[0027] The first electrode plate of the second capacitor is coupled to the second node, and the second electrode plate of the second capacitor is configured to receive the second reference signal.
[0028] In some examples, the shift register unit further includes: a second control circuit;
[0029] The second control circuit is configured to provide the second reference signal to the first node in response to a signal from the second node.
[0030] In some examples, the second control circuit includes a seventh transistor;
[0031] The control electrode of the seventh transistor is coupled to the second node, the first electrode of the seventh transistor is configured to receive the second reference signal, and the second electrode of the seventh transistor is coupled to the first node.
[0032] In some examples, the second control circuit further includes an eighth transistor; the second terminal of the seventh transistor is coupled to the first node through the eighth transistor;
[0033] The control electrode of the eighth transistor is coupled to the second node, the first electrode of the eighth transistor is coupled to the second electrode of the seventh transistor, and the second electrode of the eighth transistor is coupled to the first node.
[0034] In some examples, the shift register unit further includes: a second noise reduction circuit;
[0035] The second noise reduction circuit is configured to provide the first reference signal to the first electrode of the eighth transistor in response to the signal of the first node.
[0036] In some examples, the second noise reduction circuit includes: a ninth transistor;
[0037] The control electrode of the ninth transistor is coupled to the first node, the first electrode of the ninth transistor is configured to receive the first reference signal, and the second electrode of the ninth transistor is coupled to the first electrode of the eighth transistor.
[0038] In some examples, the reset circuit includes a tenth transistor;
[0039] The control electrode of the tenth transistor is configured to receive the second clock signal, the first electrode of the tenth transistor is configured to receive the first reference signal, and the second electrode of the tenth transistor is coupled to the second node.
[0040] The drive control circuit provided in this disclosure includes a plurality of cascaded shift register units as described above;
[0041] The input signal for the first-stage shift register unit is provided by the frame trigger signal terminal;
[0042] In two adjacent shift register units, the input signal of the next shift register unit is provided by the drive output terminal of the previous shift register unit.
[0043] The display device provided in this disclosure includes the drive control circuit described above.
[0044] The driving method for the shift register unit described above, provided in this embodiment, includes:
[0045] During the input phase, the input circuit responds to the first clock signal and provides the input signal to the first node; the first control circuit responds to the first control signal and provides the second clock signal to the second node; the output circuit responds to the signal from the first node and provides the third clock signal to the drive output terminal.
[0046] During the output phase, the first control circuit responds to the first control signal and provides the second clock signal to the second node; the output circuit responds to the signal from the first node and provides the third clock signal to the drive output terminal.
[0047] During the reset phase, the reset circuit responds to the second clock signal and provides the first reference signal to the second node; the output circuit responds to the signal of the second node and provides the second reference signal to the drive output terminal. Attached Figure Description
[0048] Figure 1 These are schematic diagrams of some structures of shift registers in related technologies;
[0049] Figure 2 Here are some signal timing diagrams for shift registers in related technologies;
[0050] Figure 3 Some structural schematic diagrams of shift registers provided in embodiments of this disclosure;
[0051] Figure 4 Other schematic diagrams of the shift register provided in the embodiments of this disclosure;
[0052] Figure 5Some signal timing diagrams of the shift register provided in the embodiments of this disclosure;
[0053] Figure 6 Some flowcharts of the driving method provided in the embodiments of this disclosure;
[0054] Figure 7 Further schematic diagrams of the shift register provided in embodiments of this disclosure;
[0055] Figure 8 Further schematic diagrams of the shift register provided in embodiments of this disclosure;
[0056] Figure 9 Further schematic diagrams of the shift register provided in embodiments of this disclosure;
[0057] Figure 10 Further schematic diagrams of the shift register provided in embodiments of this disclosure;
[0058] Figure 11 Further schematic diagrams of the shift register provided in embodiments of this disclosure;
[0059] Figure 12a Further schematic diagrams of the shift register provided in embodiments of this disclosure;
[0060] Figure 12b Further structural schematic diagrams of the shift register unit provided in the embodiments of this disclosure;
[0061] Figure 13 Other signal timing diagrams for the shift register provided in embodiments of this disclosure;
[0062] Figure 14a Further schematic diagrams of the shift register provided in embodiments of this disclosure;
[0063] Figure 14b Further structural schematic diagrams of the shift register unit provided in the embodiments of this disclosure;
[0064] Figure 15 Further signal timing diagrams of shift registers provided for embodiments of this disclosure;
[0065] Figure 16 Some structural schematic diagrams of the drive control circuit provided in the embodiments of this disclosure. Detailed Implementation
[0066] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0067] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.
[0068] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
[0069] like Figure 1 As shown, the shift register unit may include transistors M01 to M010 and capacitors C01 to C02. The corresponding signal timing diagram is as follows. Figure 2 As shown in the diagram. Here, GCK1~GCK3 represent clock signals, GIP represents input signals, n01 represents the signal of node N01, n02 represents the signal of node N02, and gso represents the signal of the drive output terminal GSO.
[0070] During the input phase T01, clock signal GCK1 is low, transistors M01 and M02 are turned on, providing the low-level input signal GIP to node N01, which in turn turns on transistors M05 and M09. The turned-on M09 provides the low-level signal VGL to node N03. The turned-on transistor M05 provides the high-level clock signal GCK2 to the drive output GSO, making the output signal gso high and turning off transistor M03. Clock signal GCK3 is high, and transistor M010 is turned off. Input signal GIP is low, transistor M04 is turned on, providing the high-level signal VGH to node N02, which in turn turns off transistor M06.
[0071] In the output phase T02, clock signal GCK1 is high, and transistors M01 and M02 are off. Clock signal GCK3 is high, and transistor M010 is off. Input signal GIP is high, and transistor M04 is off. Therefore, nodes N01 and N02 are both floating. Capacitor C01 keeps node N01 low, controlling transistors M05 and M09 to conduct. The conducting transistor M05 provides the low level of clock signal GCK2 to the drive output GSO, making the output signal gso low. Due to the bootstrap effect of capacitor C01, the level of node N01 can be further pulled low, controlling transistor M05 to conduct as fully as possible, providing the low level of clock signal GCK2 to the drive output GSO, making the output signal gso low, and controlling transistor M03 to conduct. The conducting transistor M03 provides the low level of signal gso to node N04. Because capacitor C02 can keep node N02 at a high level, it can control transistor M06 to be turned off.
[0072] However, in the aforementioned shift register unit, since the gate of transistor M04 receives the input signal GIP, transistor M04 can only conduct during the input phase t01, and cannot conduct during the other phases. Especially in the output phase t02, node N02 does not receive a high-level input signal; instead, it is held high by capacitor C02. However, due to leakage current in transistor M010, the high level held high by capacitor C02 at node N02 can be pulled low (e.g., ...). Figure 2 In the diagram, the solid line in signal n01 represents the actual voltage level of node N02 during stage t02, while the dashed line represents the ideal voltage level of node N02 during stage t02. This results in instability in the signal gso output from the drive output terminal GSO (e.g., ...). Figure 2 In the diagram, the solid line represents the actual level of signal gso during the t02 phase, while the dashed line represents the ideal level of signal gso during the t02 phase.
[0073] Although capacitor C02 is included in the aforementioned shift register unit, in practical applications, the voltage drop across capacitor C02 can only be achieved through voltage division. 02 / (c 02 +c gd(M06) +c N02(others)This voltage divider is used to maintain the stability of node N02. The larger the voltage divider, the more stable node N02. To prevent node N02 from being pulled low, capacitor C02 can be set to a relatively large value. However, for example, when the channel width of transistor M06 is 400µm, and the capacitance of capacitor C02 is 500fF, node N02 still experiences a voltage drop of about 1V. Figure 2 As shown, during the output stage T02, affected by the output transition, node N02 will drop from 7V to 4.9V. As capacitor C02 increases, the downward adjustment of node N02 decreases, but the level of node N02 still cannot reach 7V. Therefore, even if capacitor C02 is set relatively large, it is not possible to completely prevent node N02 from being pulled low, and it will also result in a large space occupied by the shift register unit.
[0074] To address the aforementioned issues, embodiments of this disclosure provide a shift register unit that can improve node stability.
[0075] In the embodiments disclosed herein, such as Figure 3 As shown, the shift register unit may include: an input circuit 10, a reset circuit 20, a first control circuit 30, and an output circuit 40. The input circuit 10 is configured to provide an input signal GIP to a first node N1 in response to a first clock signal CK1. The reset circuit 20 is configured to provide a first reference signal VREF1 to a second node N2 in response to a second clock signal CK2. The first control circuit 30 is configured to provide a second clock signal CK2 to the second node N2 in response to a first control signal CS1. The output circuit 40 is configured to provide a third clock signal CK3 to the drive output terminal GSO in response to a signal from the first node N1, and to provide a second reference signal VREF2 to the drive output terminal GSO in response to a signal from the second node N2. Furthermore, the duration of the effective level of the first control signal CS1 is greater than the duration of the effective level of the signal at the drive output terminal GSO.
[0076] The shift register unit provided in this embodiment increases the conduction time of the first control circuit by making the duration of the effective level of the first control signal greater than the duration of the effective level of the signal driving the output terminal. This increases the duration for which the second clock signal is provided to the second node, thereby stabilizing the level of the second node through the input signal. This eliminates the need for a large additional capacitor to achieve level stability of the second node, improving output stability and reducing the footprint.
[0077] In some embodiments of this disclosure, such as Figure 4As shown, the first control circuit 30 includes a first transistor M1. The control electrode of the first transistor M1 is configured to receive a first control signal CS1, the first electrode of the first transistor M1 is configured to receive a second clock signal CK2, and the second electrode of the first transistor M1 is coupled to a second node N2.
[0078] For example, the first transistor M1 is turned on under the control of the effective level of the first control signal CS1 and turned off under the control of the ineffective level of the first control signal CS1. For instance, if the first transistor M1 is a P-type transistor, then the effective level of the first control signal CS1 is low and the ineffective level is high. Alternatively, if the first transistor M1 is an N-type transistor, then the effective level of the first control signal CS1 is high and the ineffective level is low. In practical applications, the specific implementation of the first transistor can be determined according to the needs of the actual application, and is not limited here.
[0079] In some embodiments of this disclosure, such as Figure 4 As shown, the input circuit 10 may include a second transistor M2. The control electrode of the second transistor M2 is configured to receive a first clock signal CK1, the first electrode of the second transistor M2 is configured to receive an input signal GIP, and the second electrode of the second transistor M2 is coupled to a first node N1.
[0080] For example, the second transistor M2 is turned on under the control of the active level of the first clock signal CK1 and turned off under the control of the inactive level of the first clock signal CK1. For instance, if the second transistor M2 is a P-type transistor, then the active level of the first clock signal CK1 is low and the inactive level is high. Alternatively, if the second transistor M2 is an N-type transistor, then the active level of the first clock signal CK1 is high and the inactive level is low. In practical applications, the specific implementation of the second transistor can be determined according to the needs of the actual application, and is not limited here.
[0081] In some embodiments of this disclosure, such as Figure 4 As shown, the output circuit 40 includes a fifth transistor M5, a sixth transistor M6, and a first capacitor C1. The control electrode of the fifth transistor M5 is coupled to the first node N1, the first electrode of the fifth transistor M5 is configured to receive the third clock signal CK3, and the second electrode of the fifth transistor M5 is coupled to the drive output terminal GSO. The control electrode of the sixth transistor M6 is coupled to the second node N2, the first electrode of the sixth transistor M6 is configured to receive the second reference signal VREF2, and the second electrode of the sixth transistor M6 is coupled to the drive output terminal GSO. The first electrode plate of the first capacitor C1 is coupled to the first node N1, and the second electrode plate of the first capacitor C1 is coupled to the drive output terminal GSO.
[0082] For example, the fifth transistor M5 is turned on under the control of the effective level of the signal at the first node N1, and turned off under the control of the ineffective level of the signal at the first node N1. For instance, if the fifth transistor M5 is a P-type transistor, then the effective level of the signal at the first node N1 is low, and the ineffective level is high. Alternatively, if the fifth transistor M5 is an N-type transistor, then the effective level of the signal at the first node N1 is high, and the ineffective level is low. In practical applications, the specific implementation of the fifth transistor can be determined according to the needs of the actual application, and is not limited here.
[0083] For example, the sixth transistor M6 is turned on under the control of the effective level of the signal at the second node N2, and turned off under the control of the ineffective level of the signal at the second node N2. For instance, if the sixth transistor M6 is a P-type transistor, then the effective level of the signal at the second node N2 is low, and the ineffective level is high. Alternatively, if the sixth transistor M6 is an N-type transistor, then the effective level of the signal at the second node N2 is high, and the ineffective level is low. In practical applications, the specific implementation of the sixth transistor can be determined according to the needs of the actual application, and is not limited here.
[0084] In some embodiments of this disclosure, such as Figure 4 As shown, the shift register unit further includes a second control circuit 50. The second control circuit 50 is configured to provide a second reference signal VREF2 to the first node N1 in response to a signal from the second node N2. Exemplarily, the second control circuit 50 includes a seventh transistor M7. The control electrode of the seventh transistor M7 is coupled to the second node N2, the first electrode of the seventh transistor M7 is configured to receive the second reference signal VREF2, and the second electrode of the seventh transistor M7 is coupled to the first node N1.
[0085] For example, the seventh transistor M7 is turned on under the control of the effective level of the signal at the second node N2, and turned off under the control of the ineffective level of the signal at the second node N2. For instance, if the seventh transistor M7 is a P-type transistor, then the effective level of the signal at the second node N2 is low, and the ineffective level is high. Alternatively, if the seventh transistor M7 is an N-type transistor, then the effective level of the signal at the second node N2 is high, and the ineffective level is low. In practical applications, the specific implementation of the seventh transistor can be determined according to the needs of the actual application, and is not limited here.
[0086] In some embodiments of this disclosure, such as Figure 4 As shown, the reset circuit 20 includes a tenth transistor M10. The control terminal of the tenth transistor M10 is configured to receive a second clock signal CK2, the first terminal of the tenth transistor M10 is configured to receive a first reference signal VREF1, and the second terminal of the tenth transistor M10 is coupled to a second node N2.
[0087] For example, the tenth transistor M10 is turned on under the control of the active level of the second clock signal CK2 and turned off under the control of the inactive level of the second clock signal CK2. For instance, if the tenth transistor M10 is a P-type transistor, then the active level of the second clock signal CK2 is low and the inactive level is high. Alternatively, if the tenth transistor M10 is an N-type transistor, then the active level of the second clock signal CK2 is high and the inactive level is low. In practical applications, the specific implementation of the tenth transistor can be determined according to the needs of the actual application, and is not limited here.
[0088] In some embodiments of this disclosure, Figure 4 The signal timing diagram corresponding to the shift register unit shown can be as follows: Figure 5 As shown in the diagram. Here, GIP represents the input signal, CK1 represents the first clock signal, CK2 represents the second clock signal, CK3 represents the third clock signal, n1 represents the signal of the first node N1, n2 represents the signal of the second node N2, gso represents the signal driving the output terminal GSO, and CS1 represents the first control signal. When the effective level is low, the duration ts2 of the low level of the first control signal CS1 is greater than the duration ts1 of the low level of the signal gso driving the output terminal GSO. For example, the duration ts2 of the low level of the first control signal CS1 can be approximately twice the duration ts1 of the low level of the signal gso driving the output terminal GSO. Alternatively, when the effective level is high, the duration ts2 of the high level of the first control signal CS1 is greater than the duration ts1 of the high level of the signal gso driving the output terminal GSO. For example, the duration ts2 of the high level of the first control signal CS1 can be approximately twice the duration ts1 of the high level of the signal gso driving the output terminal GSO. In practical applications, the determination can be made based on the specific needs of the application, and no restrictions are imposed here.
[0089] It should be noted that in actual processes, due to limitations in process conditions or other factors, the above-mentioned equality relationships may not be exactly the same and may have some deviations. Therefore, as long as the above-mentioned equality relationships roughly meet the above conditions, they are all within the protection scope of this disclosure. For example, the above-mentioned equality relationships can be the kind of equality that is allowed within the allowable error range.
[0090] In practical implementation, the control electrode of the aforementioned transistor can be used as the upper electrode. Furthermore, depending on the direction of signal flow, the first electrode of the aforementioned transistor can be used as its source and the second electrode as its drain; or, the first electrode can be used as its drain and the second electrode as its source, without making a specific distinction here.
[0091] It should be noted that the transistors mentioned in the above embodiments of this disclosure can be TFTs or metal-oxide-semiconductor field-effect transistors (MOS), and are not limited thereto.
[0092] To simplify the preparation process, in specific implementations, as described in the embodiments of this disclosure, Figure 4 As shown, all transistors can be P-type transistors. Of course, all transistors can also be N-type transistors; this is not a limitation here.
[0093] The above are merely examples illustrating the specific structure of the shift register unit provided in the embodiments of this disclosure. In specific implementations, the specific structure of each circuit is not limited to the structure provided in the embodiments of this disclosure, and may also be other structures known to those skilled in the art, which are not limited here.
[0094] This disclosure also provides a method for driving a shift register unit, such as... Figure 6 As shown, it may include the following steps:
[0095] S10, Input phase: The input circuit responds to the first clock signal and provides the input signal to the first node; the first control circuit responds to the first control signal and provides the second clock signal to the second node; the output circuit responds to the signal of the first node and provides the third clock signal to the drive output terminal.
[0096] S20, Output stage: The first control circuit responds to the first control signal and provides the second clock signal to the second node; the output circuit responds to the signal of the first node and provides the third clock signal to the drive output terminal.
[0097] S30, Reset Phase: The reset circuit responds to the second clock signal and provides the first reference signal to the second node; the output circuit responds to the signal of the second node and provides the second reference signal to the drive output terminal.
[0098] The driving method provided in this disclosure increases the conduction time of the first control circuit by making the duration of the effective level of the first control signal greater than the duration of the effective level of the signal at the drive output terminal. This increases the duration for which the second clock signal is provided to the second node, thereby stabilizing the level of the second node through the input signal. This eliminates the need for a large additional capacitor to achieve level stability of the second node. Consequently, it not only improves output stability but also reduces the footprint.
[0099] In some embodiments of this disclosure, when the shift register unit further includes a second control circuit, during the reset phase, the second control circuit may provide a second reference signal to the first node in response to a signal from the second node.
[0100] The following is based on Figure 4 Taking the shift register unit shown as an example, combined with Figure 5 The signal timing diagram shown describes the operation of the shift register unit provided in the embodiments of this disclosure.
[0101] Specifically, select such as Figure 5 The signal timing diagram shown includes input phase T1, output phase T2, and reset phase T3. It should be noted that... Figure 5 The signal timing diagram shown only represents the operation of a single shift register unit within one frame. The operation of this shift register unit in other frames is basically the same as that in this frame, and will not be described in detail here.
[0102] During input phase T1, the first clock signal CK1 is low, the second transistor M2 is turned on, providing the low-level input signal GIP to the first node N1, which in turn turns on the fifth transistor M5. The turned-on fifth transistor M5 provides the high-level third clock signal CK3 to the drive output terminal GSO, making the output signal gso high. The second clock signal CK2 is high, and the tenth transistor M10 is turned off. The first control signal CS1 is low, the first transistor M1 is turned on, and the high-level second reference signal VREF2 is provided to the second node N2, which turns off the sixth transistor M6 and the seventh transistor M7.
[0103] During output phase T2, the first clock signal CK1 is high, and the second transistor M2 is off. The second clock signal CK2 is high, and the tenth transistor M10 is off. The first control signal CS1 is low, and the first transistor M1 is on, providing the high-level second reference signal VREF2 to the second node N2, controlling the sixth transistor M6 and the seventh transistor M7 to be off. Therefore, the first node N1 is in a floating state. Due to the function of the first capacitor C1, the first node N1 can be kept low, controlling the fifth transistor M5 to be on. The on fifth transistor M5 provides the low level of the third clock signal CK3 to the drive output terminal GSO, making the signal gso output by the drive output terminal GSO low. Due to the bootstrap effect of the first capacitor C1, the level of the first node N1 can be further pulled low, controlling the fifth transistor M5 to be on as fully as possible, so as to provide the low level of the third clock signal CK3 to the drive output terminal GSO, making the signal gso output by the drive output terminal GSO low.
[0104] During the reset phase T3, the first clock signal CK1 is high, and the second transistor M2 is off. The first control signal CS1 is high, and the first transistor M1 is off. The second clock signal CK2 is low, and the tenth transistor M10 is on, providing the low-level first reference signal VREF1 to the second node N2, controlling the sixth transistor M6 and the seventh transistor M7 to turn on. The on-state seventh transistor M7 provides the high-level second reference signal VREF2 to the first node N1, controlling the fifth transistor M5 to turn off. The on-state sixth transistor M6 provides the high-level second reference signal VREF2 to the drive output terminal GSO, making the signal gso output by the drive output terminal GSO high.
[0105] It should be noted that by controlling the first transistor M1 to be turned on in both the input phase T1 and the output phase T2 via the first control signal CS1, a high-level second reference signal VREF2 can be provided to the second node N2 in both phases, preventing the second node N2 from floating in these two phases. This allows the second node N2 to be stable in the output phase (e.g., stable at 7V). Furthermore, since the high-level second reference signal VREF2 is provided to the second node N2 in both the input phase T1 and the output phase T2, a capacitor is not needed at the control electrode of the sixth transistor M6, which further reduces the space occupied by the shift register unit. For example, when no capacitor is provided at the control electrode of the sixth transistor M6, the width of the channel region of the sixth transistor M6 can be greater than 50µm or 100µm, thus achieving stable output of the shift register unit.
[0106] This disclosure provides other structural diagrams of shift register units, such as... Figure 7 As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.
[0107] In some embodiments of this disclosure, such as Figure 7 As shown, the output circuit 40 further includes a second capacitor C2. The first electrode plate of the second capacitor C2 is coupled to the second node N2, and the second electrode plate of the second capacitor C2 is configured to receive the second reference signal VREF2. This further stabilizes the level of the second node N2 through the second capacitor C2.
[0108] It should be noted that, Figure 7 The signal timing diagram corresponding to the shift register unit shown can be seen as follows: Figure 5 As shown. And, Figure 7 The shift register unit shown is combined with Figure 5 The signal timing shown can be used to describe the operation of the shift register unit as described above, and will not be repeated here.
[0109] It should be noted that the signal stability of the second node N2 can be further improved by setting the second capacitor C2. In practical applications, the width of the channel region of the sixth transistor M6 can be less than 400um, and the capacitance value of the DARPE capacitor can be as low as 50fF to 200fF to ensure stable output of the shift register unit.
[0110] This disclosure provides further structural diagrams of shift register units, such as... Figure 8 As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.
[0111] In some embodiments of this disclosure, such as Figure 8 As shown, the input circuit 10 also includes a third transistor M3; the second terminal of the second transistor M2 is coupled to the first node N1 through the third transistor M3. The control terminal of the third transistor M3 is configured to receive the first clock signal CK1, the first terminal of the third transistor M3 is coupled to the second terminal of the second transistor M2, and the second terminal of the third transistor M3 is coupled to the first node N1.
[0112] For example, the third transistor M3 is turned on under the control of the effective level of the first clock signal CK1 and turned off under the control of the ineffective level of the first clock signal CK1. For instance, if the third transistor M3 is a P-type transistor, then the effective level of the first clock signal CK1 is low and the ineffective level is high. Alternatively, if the third transistor M3 is an N-type transistor, then the effective level of the first clock signal CK1 is high and the ineffective level is low. In practical applications, the specific implementation of the third transistor can be determined according to the needs of the actual application, and is not limited here.
[0113] It should be noted that, Figure 8 The signal timing diagram corresponding to the shift register unit shown can be seen as follows: Figure 5 As shown. Furthermore, the third transistor M3 is turned on during the input phase T1 under the control of the first clock signal CK1, thus enabling it to supply the low-level input signal GIP to the first node N1 in conjunction with the turned-on second transistor M2. The third transistor M3 is turned off during the output phase T2 and the reset phase T3 under the control of the first clock signal CK1. Furthermore, Figure 8 The shift register unit shown is combined with Figure 5 The process of performing other tasks based on the signal timing shown can be referred to the working process of the shift register unit described above, and will not be repeated here.
[0114] It should be noted that by setting two transistors in the input circuit 10, the influence of the leakage current of the first node N1 on the signal of the first node N1 can be reduced, thereby improving the signal stability of the first node N1.
[0115] This disclosure provides further structural diagrams of shift register units, such as... Figure 9 As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.
[0116] In some embodiments of this disclosure, such as Figure 9 As shown, the shift register unit further includes a first noise reduction circuit 60. The first noise reduction circuit 60 is configured to provide a third clock signal CK3 to the first terminal of the third transistor M3 in response to a signal from the drive output terminal GSO. Exemplarily, the first noise reduction circuit 60 includes a fourth transistor M4. The control terminal of the fourth transistor M4 is coupled to the drive output terminal GSO, the first terminal of the fourth transistor M4 is configured to receive the third clock signal CK3, and the second terminal of the fourth transistor M4 is coupled to the first terminal of the third transistor M3.
[0117] For example, the fourth transistor M4 is turned on under the control of the effective level of the signal driving the output terminal GSO, and turned off under the control of the ineffective level of the signal driving the output terminal GSO. For instance, if the fourth transistor M4 is a P-type transistor, then the effective level of the signal driving the output terminal GSO is low, and the ineffective level is high. Alternatively, if the fourth transistor M4 is an N-type transistor, then the effective level of the signal driving the output terminal GSO is high, and the ineffective level is low. In practical applications, the specific implementation of the fourth transistor can be determined according to the needs of the actual application, and is not limited here.
[0118] In some embodiments of this disclosure, when the shift register unit further includes a first noise reduction circuit, during the output stage, the first noise reduction circuit can respond to the signal driving the output terminal and provide a third clock signal to the first pole of the third transistor.
[0119] It should be noted that, Figure 9 The signal timing diagram corresponding to the shift register unit shown can be seen as follows: Figure 5 As shown. Furthermore, in output phase T2, the fourth transistor M4 is turned on under the control of the signal gso driving the output terminal GSO, providing the low level of the third clock signal CK3 to the first terminal of the third transistor M3. In input phase T1 and reset phase T3, the fourth transistor M4 is turned off under the control of the signal gso driving the output terminal GSO. Furthermore, Figure 9 The shift register unit shown is combined with Figure 5The process of performing other tasks based on the signal timing shown can be referred to the working process of the shift register unit described above, and will not be repeated here.
[0120] It should be noted that by setting the first noise reduction circuit 60, the low level of the third clock signal CK3 can be provided to the first pole of the third transistor M3 in the output stage. This can further reduce the influence of the leakage current of the first node N1 on the signal of the first node N1 and further improve the signal stability of the first node N1.
[0121] This disclosure provides further structural diagrams of shift register units, such as... Figure 10 As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.
[0122] In some embodiments of this disclosure, such as Figure 10 As shown, the second control circuit 50 may further include: an eighth transistor M8; the second terminal of the seventh transistor M7 is coupled to the first node N1 through the eighth transistor M8. The control terminal of the eighth transistor M8 is coupled to the second node N2, the first terminal of the eighth transistor M8 is coupled to the second terminal of the seventh transistor M7, and the second terminal of the eighth transistor M8 is coupled to the first node N1.
[0123] For example, the eighth transistor M8 is turned on under the control of the effective level of the signal at the second node N2, and turned off under the control of the ineffective level of the signal at the second node N2. For instance, if the eighth transistor M8 is a P-type transistor, then the effective level of the signal at the second node N2 is low, and the ineffective level is high. Alternatively, if the eighth transistor M8 is an N-type transistor, then the effective level of the signal at the second node N2 is high, and the ineffective level is low. In practical applications, the specific implementation of the eighth transistor can be determined according to the needs of the actual application, and is not limited here.
[0124] It should be noted that, Figure 10 The signal timing diagram corresponding to the shift register unit shown can be seen as follows: Figure 5 As shown. Furthermore, the eighth transistor M8 is turned on during the reset phase T3 under the level control of the second node N2, and in conjunction with the turned-on seventh transistor M7, provides the high-level second reference signal VREF2 to the first node N1. The eighth transistor M8 is turned off during the input phase T1 and the output phase T2 under the level control of the second node N2. Furthermore, Figure 10 The shift register unit shown is combined with Figure 5 The process of performing other tasks based on the signal timing shown can be referred to the working process 6 of the shift register unit above, and will not be repeated here.
[0125] It should be noted that by setting the eighth transistor M8, the influence of the leakage current of the first node N1 on the signal of the first node N1 can be reduced, thereby further improving the signal stability of the first node N1.
[0126] This disclosure provides further structural diagrams of shift register units, such as... Figure 11 As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.
[0127] In some embodiments of this disclosure, such as Figure 11 As shown, the shift register unit further includes a second noise reduction circuit 70; wherein the second noise reduction circuit 70 is configured to provide a first reference signal VREF1 to the first terminal of the eighth transistor M8 in response to a signal from the first node N1. Exemplarily, the second noise reduction circuit 70 includes a ninth transistor M9; wherein the control terminal of the ninth transistor M9 is coupled to the first node N1, the first terminal of the ninth transistor M9 is configured to receive the first reference signal VREF1, and the second terminal of the ninth transistor M9 is coupled to the first terminal of the eighth transistor M8.
[0128] For example, the ninth transistor M9 is turned on under the control of the effective level of the signal at the first node N1, and turned off under the control of the ineffective level of the signal at the first node N1. For instance, if the ninth transistor M9 is a P-type transistor, then the effective level of the signal at the first node N1 is low, and the ineffective level is high. Alternatively, if the ninth transistor M9 is an N-type transistor, then the effective level of the signal at the first node N1 is high, and the ineffective level is low. In practical applications, the specific implementation of the ninth transistor can be determined according to the needs of the actual application, and is not limited here.
[0129] In some embodiments of this disclosure, when the shift register unit further includes a second noise reduction circuit, during the input phase, the second noise reduction circuit can provide a first reference signal to the first terminal of the eighth transistor in response to the signal of the first node. And, during the output phase, the second noise reduction circuit can provide the first reference signal to the first terminal of the eighth transistor in response to the signal of the first node.
[0130] It should be noted that, Figure 11 The signal timing diagram corresponding to the shift register unit shown can be seen as follows: Figure 5 As shown. Furthermore, the ninth transistor M9 is turned on under the level control of the first node N1 during input phase T1 and output phase T2, providing the low-level first reference signal VREF1 to the first terminal of the eighth transistor M8. The ninth transistor M9 is turned off under the level control of the first node N1 during reset phase T3. Furthermore, Figure 11 The shift register unit shown is combined with Figure 5 The process of performing other tasks based on the signal timing shown can be referred to the working process of the shift register unit described above, and will not be repeated here.
[0131] It should be noted that by setting the ninth transistor M9, the impact of the leakage current of the first node N1 on the signal of the first node N1 can be further reduced, thereby further improving the signal stability of the first node N1.
[0132] This disclosure provides further structural diagrams of shift register units, such as... Figure 12a As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.
[0133] In some embodiments of this disclosure, such as Figure 12a As shown, the first control circuit 30 is coupled to the first terminal of the third transistor M3, and the signal at the first terminal of the third transistor M3 is the first control signal CS1. Specifically, the control terminal of the first transistor M1 is coupled to the first terminal of the third transistor M3.
[0134] For example, Figure 12a The signal timing diagram corresponding to the shift register unit shown is as follows: Figure 13 As shown. m1 represents the signal at the control electrode of the first transistor M1. Furthermore, Figure 12a The shift register unit shown is combined with Figure 13 The process of performing other tasks based on the signal timing shown can be referred to the working process of the shift register unit described above, and will not be repeated here.
[0135] It should be noted that, through the signal control of the first terminal of the third transistor M3, the first transistor M1 is turned on in both the input stage T1 and the output stage T2, so that the high-level second reference signal VREF2 can be provided to the second node N2 in both stages, avoiding the second node N2 from floating in these two stages, thus allowing the second node N2 to be stable in the output stage (for example, it can be stable at 7V).
[0136] In some examples, since the high-level second reference signal VREF2 is provided to the second node N2 in both the input phase T1 and the output phase T2, the second capacitor C2 may not be necessary. Figure 12b As shown. This can further reduce the space occupied by the shift register unit. For example, when the second capacitor C2 is not set at the control electrode of the sixth transistor M6, the width of the channel region of the sixth transistor M6 can be greater than 50um or 100um, which can achieve stable output of the shift register unit.
[0137] This disclosure provides further structural diagrams of shift register units, such as... Figure 14a As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.
[0138] In some embodiments of this disclosure, such as Figure 14a As shown, the first control circuit 30 is coupled to the first node N1, and the signal of the first node N1 is the first control signal CS1. Specifically, the control electrode of the first transistor M1 is coupled to the first node N1.
[0139] For example, Figure 14a The signal timing diagram corresponding to the shift register unit shown is as follows: Figure 15 As shown. m1 represents the signal at the control electrode of the first transistor M1. Furthermore, Figure 14a The shift register unit shown is combined with Figure 15 The process of performing other tasks based on the signal timing shown can be referred to the working process of the shift register unit described above, and will not be repeated here.
[0140] It should be noted that by controlling the first transistor M1 to be turned on in both the input stage T1 and the output stage T2 through the signal of the first node N1, the high-level second reference signal VREF2 can be provided to the second node N2 in both stages, avoiding the second node N2 from floating in these two stages. This allows the second node N2 to be stable in the output stage (for example, it can be stable at 7V).
[0141] In some examples, since the high-level second reference signal VREF2 is provided to the second node N2 in both the input phase T1 and the output phase T2, the second capacitor C2 may not be necessary. Figure 14b As shown. This can further reduce the space occupied by the shift register unit. For example, when the second capacitor C2 is not set at the control electrode of the sixth transistor M6, the width of the channel region of the sixth transistor M6 can be greater than 50um or 100um, which can achieve stable output of the shift register unit.
[0142] This disclosure also provides some drive control circuits, such as Figure 16 As shown, the drive control circuit includes multiple cascaded shift register units SR(1), SR(2), SR(3)...SR(N-1), SR(N) (a total of N shift register units). The input signal GIP of the first-stage shift register unit SR(1) is provided by the frame trigger signal STV. Furthermore, in adjacent shift register units, the input signal GIP of the next-stage shift register unit is provided by the drive output GSO of the previous-stage shift register unit.
[0143] Specifically, the specific structure of each shift register unit in the aforementioned drive control circuit is the same as that of the shift register unit described in this disclosure in both function and structure, and the repetitions will not be repeated. This drive control circuit can be configured in a liquid crystal display panel or in an electroluminescent display panel, and is not limited thereto.
[0144] Specifically, in the drive control circuit provided in the embodiments of this disclosure, the first reference signal VREF1 of each shift register unit is provided by the same first DC signal terminal, and the second reference signal VREF2 of each shift register unit is provided by the same second DC signal terminal.
[0145] Specifically, in the drive control circuit provided in the embodiments of this disclosure, such as Figure 16 As shown, the first clock signal CK1 of the 3k-2 level shift register unit, the second clock signal CK2 of the 3k-1 level shift register unit, and the third clock signal CK3 of the 3k level shift register unit are all provided by the same clock input, namely the first clock input ck1. The second clock signal CK2 of the 3k-2 level shift register unit, the third clock signal CK3 of the 3k-1 level shift register unit, and the first clock signal CK1 of the 3k level shift register unit are all provided by the same clock input, namely the second clock input ck2. The third clock signal CK3 of the 3k-2 level shift register unit, the first clock signal CK1 of the 3k-1 level shift register unit, and the second clock signal CK2 of the 3k level shift register unit are all provided by the same clock input, namely the third clock input ck3. Here, k is a positive integer.
[0146] This disclosure also provides a display device, including the drive control circuit described above. The principle by which this display device solves the problem is similar to that of the aforementioned drive control circuit; therefore, the implementation of this display device can refer to the implementation of the aforementioned drive control circuit, and repeated details will not be described here.
[0147] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0148] In specific implementations, the display device may include multiple pixel units, multiple gate lines and data lines, and each pixel unit may include multiple sub-pixels, such as red sub-pixels, green sub-pixels and blue sub-pixels. The display device provided in the embodiments of this disclosure may be an organic light-emitting display device or a liquid crystal display device, and is not limited thereto.
[0149] In this embodiment, multiple gate lines are also correspondingly provided with driving control circuits; one gate line is coupled to the driving output terminal of a first-level shift register unit in the driving control circuit. For example, when the display device provided in this embodiment is a liquid crystal display device, the TFT in the sub-pixel can be coupled to the gate line, and the driving control circuit can be used as a gate driving circuit. This gate driving circuit, coupled to the gate line, is used to provide a gate scan signal to the TFT in the sub-pixel. It should be noted that the TFT in the sub-pixel can be an N-type transistor or a P-type transistor, and this is not limited thereto.
[0150] In some embodiments of this disclosure, when the display device provided in the embodiments of this disclosure is an organic light-emitting display device, the display device further includes multiple light-emitting control signal lines; each of the multiple light-emitting control signal lines is correspondingly provided with a driving control circuit; one light-emitting control signal line is coupled to the driving output terminal of a first-stage shift register unit in the driving control circuit. Additionally, multiple gate lines are also correspondingly provided with driving control circuits; one gate line is coupled to the driving output terminal of a first-stage shift register unit in the driving control circuit. For example, in an organic light-emitting display device, multiple organic light-emitting diodes (OLEDs) and pixel circuits connected to each OLED are generally provided. Generally, the pixel circuit includes a light-emitting control transistor for controlling the light emission of the OLEDs and a scan control transistor for controlling the input of data signals.
[0151] In a specific implementation, the light-emitting control transistor can be coupled to the light-emitting control signal line, and the scan control transistor can be coupled to the gate line. The organic light-emitting display device may include the driving control circuit described in the embodiments of this disclosure. The driving control circuit can serve as a light-emitting driving circuit, and is coupled to the light-emitting control transistor to provide a light-emitting control signal for the light-emitting control transistor. Alternatively, the driving control circuit can also serve as a gate driving circuit, and is coupled to the gate line to provide a gate scan signal for the scan control transistor.
[0152] Of course, the organic light-emitting display device may also include two of the driving control circuits provided in the embodiments of this disclosure. One of the driving control circuits may serve as a light-emitting driving circuit, coupled to the light-emitting control transistor, and used to provide the light-emitting control signal of the light-emitting control transistor; while the other driving control circuit may serve as a gate driving circuit, coupled to the gate line, and used to provide the gate scanning signal of the scan control transistor. This is not limited here.
[0153] The shift register unit, drive control circuit, display device, and drive method provided in this disclosure increase the conduction time of the first control circuit by making the duration of the effective level of the first control signal greater than the duration of the effective level of the signal at the drive output terminal. This increases the duration for which the second clock signal is provided to the second node, thereby stabilizing the level of the second node through the input signal. This eliminates the need for a large additional capacitor to achieve level stability of the second node, improving output stability and reducing the footprint.
[0154] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0155] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.
Claims
1. A shift register unit, comprising: The input circuit is configured to provide an input signal to the first node in response to a first clock signal; The reset circuit is configured to provide a first reference signal to the second node in response to a second clock signal; A first control circuit is configured to provide the second clock signal to the second node in response to a first control signal; The output circuit is configured to provide a third clock signal to the drive output terminal in response to a signal from the first node, and to provide a second reference signal to the drive output terminal in response to a signal from the second node. Wherein, the duration of the effective level of the first control signal is greater than the duration of the effective level of the signal at the drive output terminal; The input circuit includes a second transistor; the control electrode of the second transistor is configured to receive the first clock signal, the first electrode of the second transistor is configured to receive the input signal, and the second electrode of the second transistor is coupled to the first node. The input circuit further includes a third transistor; the second terminal of the second transistor is coupled to the first node through the third transistor; the control terminal of the third transistor is configured to receive the first clock signal, the first terminal of the third transistor is coupled to the second terminal of the second transistor, and the second terminal of the third transistor is coupled to the first node; The shift register unit further includes a first noise reduction circuit, which is configured to provide the third clock signal to the first pole of the third transistor in response to a signal at the drive output terminal.
2. The shift register unit as described in claim 1, wherein, The duration of the effective level of the first control signal is approximately twice the duration of the effective level of the signal at the drive output terminal.
3. The shift register unit as described in claim 1, wherein, The first control circuit includes a first transistor; The control electrode of the first transistor is configured to receive the first control signal, the first electrode of the first transistor is configured to receive the second clock signal, and the second electrode of the first transistor is coupled to the second node.
4. The shift register unit as described in claim 1, wherein, The first noise reduction circuit includes: a fourth transistor; The control electrode of the fourth transistor is coupled to the drive output terminal, the first electrode of the fourth transistor is configured to receive the third clock signal, and the second electrode of the fourth transistor is coupled to the first electrode of the third transistor.
5. The shift register unit as described in claim 1, wherein, The first control circuit is coupled to the first terminal of the third transistor, and the signal at the first terminal of the third transistor is the first control signal.
6. The shift register unit as described in any one of claims 1-5, wherein, The first control circuit is coupled to the first node, and the signal of the first node is the first control signal.
7. The shift register unit as described in any one of claims 1-5, wherein, The output circuit includes: a fifth transistor, a sixth transistor, and a first capacitor; The control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is configured to receive the third clock signal, and the second electrode of the fifth transistor is coupled to the drive output terminal. The control electrode of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is configured to receive the second reference signal, and the second electrode of the sixth transistor is coupled to the drive output terminal. The first electrode plate of the first capacitor is coupled to the first node, and the second electrode plate of the first capacitor is coupled to the drive output terminal.
8. The shift register unit as described in claim 7, wherein, The output circuit also includes: a second capacitor; The first electrode plate of the second capacitor is coupled to the second node, and the second electrode plate of the second capacitor is configured to receive the second reference signal.
9. The shift register unit as described in any one of claims 1-5, wherein, The shift register unit further includes: a second control circuit; The second control circuit is configured to provide the second reference signal to the first node in response to a signal from the second node.
10. The shift register unit as claimed in claim 9, wherein, The second control circuit includes: a seventh transistor; The control electrode of the seventh transistor is coupled to the second node, the first electrode of the seventh transistor is configured to receive the second reference signal, and the second electrode of the seventh transistor is coupled to the first node.
11. The shift register unit as claimed in claim 10, wherein, The second control circuit further includes: an eighth transistor; the second terminal of the seventh transistor is coupled to the first node through the eighth transistor; The control electrode of the eighth transistor is coupled to the second node, the first electrode of the eighth transistor is coupled to the second electrode of the seventh transistor, and the second electrode of the eighth transistor is coupled to the first node.
12. The shift register unit as claimed in claim 11, wherein, The shift register unit further includes: a second noise reduction circuit; The second noise reduction circuit is configured to provide the first reference signal to the first electrode of the eighth transistor in response to the signal of the first node.
13. The shift register unit as claimed in claim 12, wherein, The second noise reduction circuit includes: a ninth transistor; The control electrode of the ninth transistor is coupled to the first node, the first electrode of the ninth transistor is configured to receive the first reference signal, and the second electrode of the ninth transistor is coupled to the first electrode of the eighth transistor.
14. The shift register unit as described in any one of claims 1-5, wherein, The reset circuit includes a tenth transistor; The control electrode of the tenth transistor is configured to receive the second clock signal, the first electrode of the tenth transistor is configured to receive the first reference signal, and the second electrode of the tenth transistor is coupled to the second node.
15. A drive control circuit comprising a plurality of cascaded shift register units as described in any one of claims 1-14; The input signal for the first-stage shift register unit is provided by the frame trigger signal terminal; In two adjacent shift register units, the input signal of the next shift register unit is provided by the drive output terminal of the previous shift register unit.
16. A display device comprising the drive control circuit as described in claim 15.
17. A driving method for a shift register unit as described in any one of claims 1-14, comprising: During the input phase, the input circuit responds to the first clock signal and provides the input signal to the first node; The first control circuit responds to the first control signal and provides the second clock signal to the second node; The output circuit responds to the signal of the first node and provides the third clock signal to the drive output terminal; During the output phase, the first control circuit responds to the first control signal and provides the second clock signal to the second node; The output circuit responds to the signal of the first node and provides a third clock signal to the drive output terminal; the first noise reduction circuit responds to the signal of the drive output terminal and provides the third clock signal to the first terminal of the third transistor. During the reset phase, the reset circuit responds to the second clock signal and provides the first reference signal to the second node; The output circuit responds to the signal of the second node by providing a second reference signal to the drive output terminal.