Pixel circuit, driving method thereof and display device
By employing a specific transistor combination and signal-controlled pixel circuit structure in AMOLED technology, the problem of threshold voltage uniformity in driving thin-film transistors has been solved, resulting in better display effects and narrow bezel design, while reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2022-05-26
- Publication Date
- 2026-06-09
AI Technical Summary
The problem of threshold voltage uniformity in driving thin-film transistors in existing AMOLED technology has not been effectively solved, resulting in image retention, abnormal brightness in the first frame, and low grayscale flicker when switching between different driving frequencies.
A pixel circuit structure is adopted, including a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, first and second light-emitting control transistors, a light-emitting device, and a capacitor. Through a specific signal control and capacitor storage mechanism, the threshold voltage compensation and simultaneous reset of the driving transistor are realized, which simplifies the transistor setup and reduces the number of GOA and reset signals.
It improves the display effect, avoids problems such as image retention, abnormal brightness of the first frame, and low grayscale flicker, while supporting narrow bezel design and reducing power consumption.
Smart Images
Figure CN117461075B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, its driving method, and a display device. Background Technology
[0002] With the development of Active Matrix Organic Light Emitting Diode (AMOLED) technology, people's demands for its image quality are also increasing. In the pursuit of higher image quality, problems such as the uniformity of the threshold voltage of the driver thin film transistor (DTFT) caused by the manufacturing process, DTFT hysteresis leading to image retention, abnormal brightness in the first frame, and low grayscale flicker when switching between different driving frequencies urgently need to be solved. Summary of the Invention
[0003] This disclosure provides a pixel circuit, its driving method, and a display device for improving the display effect of the display device.
[0004] In a first aspect, embodiments of this disclosure provide a pixel circuit, comprising: a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a light-emitting device, and a first capacitor; wherein:
[0005] The first reset transistor is coupled between the first electrode of the light-emitting device and the first initialization signal terminal, and its gate is coupled to the first light-emitting control terminal;
[0006] The second electrode of the light-emitting device is coupled to the first power supply terminal;
[0007] The compensation transistor is coupled between the gate and the first electrode of the driving transistor, and the gate is coupled to the first scan control terminal.
[0008] The data writing transistor is coupled between the second terminal of the driving transistor and the data signal terminal, and its gate is coupled to the second scan control terminal.
[0009] The first light-emitting control transistor is coupled between the second power supply terminal and the second terminal of the driving transistor, and its gate is coupled to the first light-emitting control terminal.
[0010] The second light-emitting control transistor is coupled between the first terminal of the driving transistor and the first terminal of the light-emitting device, and its gate is coupled to the second light-emitting control terminal;
[0011] The first capacitor is coupled between the second power supply terminal and the gate of the driving transistor;
[0012] The first light-emitting control transistor and the second light-emitting control transistor are of the same type and are opposite in type to the first reset transistor; the first light-emitting control terminal is used to receive the first light-emitting control signal, and the second light-emitting control terminal is used to receive the second light-emitting control signal. The first light-emitting control signal and the second light-emitting control signal are provided by different output terminals of the same light-emitting driving unit, and the second light-emitting control signal is earlier than the first light-emitting control signal.
[0013] In one possible implementation, a second reset transistor is further included, which is coupled between the first terminal of the driving transistor and the second initialization signal terminal, and its gate is coupled to the initialization control terminal.
[0014] In one possible implementation, the second reset transistor and the data write transistor are of the same type; the second scan control terminal is used to receive the first scan control signal, and the initialization control terminal is used to receive the second scan control signal. The first scan control signal and the second scan control signal are provided by different stage output terminals of the same gate drive unit, and the second scan control signal is earlier than the first scan control signal.
[0015] In one possible implementation, the first initialization signal terminal and the second initialization signal terminal may be the same signal terminal or different signal terminals.
[0016] In one possible implementation, a second capacitor is further included, coupled between the second power supply terminal and the second electrode of the driving transistor.
[0017] In one possible implementation, the capacitance value of the second capacitor is less than the capacitance value of the first capacitor.
[0018] In one possible implementation, the first light-emitting control transistor, the second light-emitting control transistor, the driving transistor, and the data writing transistor are all P-type transistors; the compensation transistor and the first reset transistor are both N-type transistors.
[0019] In one possible implementation, the active layers of the compensation transistor and the first reset transistor are made of metal-oxide-semiconductor materials, and the active layers of the driving transistor, the data writing transistor, the first light-emitting control transistor, and the second light-emitting control transistor are made of low-temperature polycrystalline silicon materials.
[0020] Secondly, embodiments of this disclosure also provide a display device, which includes the pixel circuitry described in any of the preceding claims.
[0021] Thirdly, embodiments of this disclosure also provide a method for driving a pixel circuit as described in any of the preceding claims, comprising:
[0022] Based on the current refresh rate of the display device and the reference refresh rate, the current display frame of the display device is divided into one write frame and N hold frames, where N is an integer greater than 1; wherein, the write frame includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage set sequentially;
[0023] In the first stage, the first light-emitting control transistor, the driving transistor, and the compensation transistor are turned on, and the potentials of the first terminal, gate, and second terminal of the driving transistor are reset through the second power supply terminal;
[0024] In the second stage, the first reset transistor, the compensation transistor, and the second light-emitting control transistor are turned on to reset the potentials of the first electrode, gate, and second electrode of the driving transistor, and the potential of the first electrode of the light-emitting device is reset through the first initialization signal terminal;
[0025] In the third stage, the first light-emitting control transistor and the driving transistor are turned on, and the potentials of the first and second terminals of the driving transistor are reset.
[0026] In the fourth stage, the first reset transistor, the compensation transistor, the driving transistor, and the data writing transistor are turned on to reset the potential of the first electrode of the light-emitting device, and the data signal provided by the data signal terminal is loaded to the second electrode of the driving transistor. The threshold voltage of the driving transistor and the data signal are written into the gate of the driving transistor through the compensation transistor and stored in the first capacitor.
[0027] In the fifth stage, the first reset transistor and the second light-emitting control transistor are turned on, and the potential of the first terminal of the driving transistor is reset through the first initialization signal terminal.
[0028] In one possible implementation, the holding frame includes a sixth stage and a seventh stage set sequentially;
[0029] In the sixth stage, the second light-emitting control transistor and the first light-emitting control transistor are turned off sequentially, and the first reset transistor is turned on, thereby resetting the potential of the first electrode of the light-emitting device through the first initialization signal terminal;
[0030] In the seventh stage, the first reset transistor and the second light-emitting control transistor are turned on, and the potential of the second terminal of the driving transistor is reset through the first power supply terminal.
[0031] In one possible implementation, the first stage and the second stage are considered as a repeating unit, and the write frame includes M repeating units set sequentially, where M is a positive integer greater than 1.
[0032] In one possible implementation, the M repeating units include two repeating units, namely a first repeating unit and a second repeating unit, wherein the duration of the second light emission control signal in the first repeating unit is greater than the duration of the second repeating unit.
[0033] In one possible implementation, the pixel circuit further includes a second reset transistor, the write frame further includes an eighth stage located between the third stage and the fourth stage, and the method further includes:
[0034] During the time period between the eighth stage and the fourth stage, the signals loaded on the first light-emitting control terminal, the second light-emitting control terminal, the first scan control terminal, and the second scan control terminal are kept in a regulated state, and the potential of the gate of the driving transistor is kept the same as the control signal provided by the second initialization signal terminal coupled to the second reset transistor.
[0035] In one possible implementation, the pixel circuit further includes a second capacitor coupled between the second power supply terminal and the second electrode of the driving transistor, and the method further includes:
[0036] In the fourth stage, the data signal is loaded onto the second terminal of the driving transistor and stored in the second capacitor;
[0037] The second capacitor continues to charge the second terminal of the driving transistor. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the structure of one type of pixel circuit used in related technologies;
[0039] Figure 2 for Figure 1 The pixel circuit shown is one of the timing diagrams used in this circuit.
[0040] Figure 3 This is a schematic diagram of the structure of one type of pixel circuit used in related technologies;
[0041] Figure 4 for Figure 3 The pixel circuit shown is one of the timing diagrams used in this circuit.
[0042] Figure 5 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present disclosure;
[0043] Figure 6 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present disclosure;
[0044] Figure 7 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present disclosure;
[0045] Figure 8 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present disclosure;
[0046] Figure 9 for Figure 5 The pixel circuit shown is one of the timing diagrams for the write frame.
[0047] Figure 10 for Figure 5 The pixel circuit shown is one of the timing diagrams for the holding frame.
[0048] Figure 11 for Figure 5 The pixel circuit shown is one of the timing diagrams for the write frame.
[0049] Figure 12 for Figure 5 The pixel circuit shown is one of the timing diagrams for the write frame.
[0050] Figure 13 for Figure 6 The pixel circuit shown is one of the timing diagrams for the write frame.
[0051] Figure 14 A flowchart illustrating a method for driving a pixel circuit according to an embodiment of this disclosure;
[0052] Figure 15 A flowchart illustrating a method for driving a pixel circuit according to an embodiment of this disclosure;
[0053] Figure 16 This is a flowchart illustrating a method for driving a pixel circuit according to an embodiment of the present disclosure. Detailed Implementation
[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. As used in this disclosure, the words “comprising” or “including” and similar terms mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.
[0056] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
[0057] In related technologies, the following are commonly used: Figure 1 The pixel circuit shown, and Figure 2 The timing diagram shown indicates that M3 represents the DTFT, L represents the light-emitting device, n01, n02, and n03 represent the nodes where each transistor is coupled to the corresponding terminal of the DTFT, M1 and M2 are N-type transistors, M3, M4, M5, M6, and M7 are P-type transistors, M1 and M2 are metal-oxide-semiconductor transistors, and M3 to M7 are low-temperature polysilicon transistors. The threshold voltage of the DTFT is compensated to ensure its uniformity and improve the low-frequency flicker problem. This is still combined with... Figure 1 and Figure 2 As shown, in stage 01, node n01 is reset; in stage 02, data signals are written to compensate for the threshold voltage of the DTFT; in stage 03, the anode of the light-emitting device L (corresponding to...) is... Figure 1 The n04 node is reset; in stage 04, the light-emitting device L emits light. For Figure 1 The specific working process of the pixel circuit shown can be found in the relevant technical implementations, and will not be described in detail here.
[0058] exist Figure 1 In the pixel circuit shown, NR and NG are driven by the same Gate on Array (GOA) circuit, PG and PR are driven by the same GOA circuit, and V1 and V2 can use the same or different signals. Thus, this pixel circuit requires three GOA circuits and one or two reset signals. This pixel circuit can compensate for the threshold voltage of the DTFT. Since M1 and M2 are metal-oxide transistors, anode reset can be performed during the hold frame, thus avoiding low-frequency flicker. However, some issues still exist, such as low-grayscale flicker (i.e., frequency-switching flicker) when switching between different driving frequencies, and problems caused by DTFT hysteresis.
[0059] Therefore, in related technologies, the following can be adopted: Figure 3The pixel circuit shown, combined with Figure 4 The timing diagram shown aims to improve the aforementioned problems. The pixel circuit includes eight transistors: m1, m2, m3, m4, m5, m6, m7, and m8. m3 represents the DTFT, and n1, n2, and n3 represent the nodes where each transistor is coupled to the corresponding electrode of the DTFT. m1 and m2 are metal-oxide-semiconductor transistors, and m3 to m8 are low-temperature polysilicon transistors. In stage ①, n1, n2, and n3 are high-level reset and emit light; in stage ②, n1 is low-level reset, and the DTFT has a large Vgs; in stage ③, n1, n2, and n3 are low-level reset; in stage ④, DATA is written, and the DTFT threshold voltage is compensated; in stage ⑤, the anode (corresponding to…)… Figure 3 In stage ⑥, the light emission control signal em is adjusted using pulse width modulation (PWM). In stage ⑦, the anode is reset, and n3 is reset to a high level. Using this in conjunction with the n3 low-level reset in stage ⑤ can improve frequency switching flicker. Because when using… Figure 4 The timing diagram shown controls Figure 3 During the pixel circuit process shown, nodes n1, n2, and n3 can all be reset, nodes n1, n2, and n3 can be reset alternately using high and low levels, and the Vgs voltage of the DTFT can be increased, thereby further improving the hysteresis problem of the DTFT and ensuring the display effect.
[0060] However, in Figure 3 and Figure 4 In this design, the pixel circuit is essentially an 8T1C structure, requiring five GOAs and three reset signals. Therefore, compared to... Figure 1 The pixel circuitry shown requires more transistors and more GOA and reset signals, which is detrimental to increasing pixel density (Pixels Per Inch, PPI), narrowing bezels, and reducing GOA power consumption.
[0061] Therefore, embodiments of this disclosure provide a pixel circuit, a driving method thereof, and a display device for improving the display effect of the display device.
[0062] like Figure 5 As shown, this disclosure provides a pixel circuit, which includes:
[0063] The system comprises a first reset transistor T1, a compensation transistor T2, a drive transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a light-emitting device 10, and a first capacitor C1; wherein:
[0064] The first reset transistor T1 is coupled between the first electrode of the light-emitting device 10 and the first initialization signal terminal Vinit1, and its gate is coupled to the first light-emitting control terminal EM(n+x);
[0065] The second electrode of the light-emitting device 10 is coupled to the first power supply terminal VSS;
[0066] The compensation transistor T2 is coupled between the gate and the first terminal of the driving transistor T3, and the gate is coupled to the first scan control terminal N_Gate.
[0067] The data writing transistor T4 is coupled between the second terminal of the driving transistor T3 and the data signal terminal Data, and its gate is coupled to the second scan control terminal P_Gate.
[0068] The first light-emitting control transistor T5 is coupled between the second power supply terminal VDD and the second terminal of the driving transistor T3, and its gate is coupled to the first light-emitting control terminal EM(n+x).
[0069] The second light-emitting control transistor T6 is coupled between the first terminal of the driving transistor T3 and the first terminal of the light-emitting device 10, and its gate is coupled to the second light-emitting control terminal EM(n);
[0070] The first capacitor C1 is coupled between the second power supply terminal VDD and the gate of the driving transistor T3;
[0071] The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are of the same type and are opposite in type to the first reset transistor T1; the first light-emitting control terminal EM(n+x) is used to receive the first light-emitting control signal, and the second light-emitting control terminal EM(n) is used to receive the second light-emitting control signal. The first light-emitting control signal and the second light-emitting control signal are provided by different output terminals of the same light-emitting driving unit, and the second light-emitting control signal is earlier than the first light-emitting control signal.
[0072] Still combined Figure 5 As shown, the pixel circuit provided in this embodiment may include six transistors: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, and a second light-emitting control transistor T6. Compared to... Figure 1 and Figure 3In the pixel circuit shown, the number of transistors in the pixel circuit is reduced, which is beneficial for narrow bezel design. Specifically, the first reset transistor T1 is coupled between the first electrode of the light-emitting device 10 and the first initialization signal terminal Vinit1, and its gate is coupled to the first light-emitting control terminal EM(n+x). Thus, when the first reset transistor T1 is turned on, the first initialization signal terminal Vinit1 can be used to control the first electrode of the light-emitting device 10 (i.e.,...) Figure 5 The N4 node in the light-emitting device 10 is reset, achieving anode reset when the first electrode of the light-emitting device 10 is anode, thereby improving frequency switching flicker. The second electrode of the light-emitting device 10 is coupled to the first power supply terminal VSS, which can be a low-potential power supply terminal, providing a constant low-potential signal. The compensation transistor T2 is coupled between the gate and the first electrode of the driving transistor T3, and the gate is coupled to the first scan control terminal N_Gate. The data writing transistor T4 is coupled between the second electrode of the driving transistor T3 and the data signal terminal Data, and the gate is coupled to the second scan control terminal P_Gate. When the compensation transistor T2, the driving transistor T3, and the data writing transistor T4 are all turned on, the threshold voltage of the driving transistor T3 and the data signal provided by the data signal terminal Data can be written into the first capacitor C1, thereby achieving compensation for the threshold voltage of the driving transistor T3.
[0073] Still combined Figure 5 As shown, the first light-emitting control transistor T5 is coupled between the second power supply terminal VDD and the second terminal of the driving transistor T3, and its gate is coupled to the first light-emitting control terminal EM(n+x). The second power supply terminal VDD can be a high-potential power supply terminal, providing a constant high-potential signal. The second light-emitting control transistor T6 is coupled between the first terminal of the driving transistor T3 and the first terminal of the light-emitting device 10, and its gate is coupled to the second light-emitting control terminal EM(n). The first capacitor C1 is coupled between the second power supply terminal VDD and the gate of the driving transistor T3. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are of the same type, and are opposite in type to the first reset transistor T1. In one exemplary embodiment, both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are P-type transistors, and the first reset transistor T1 is an N-type transistor. The first light-emitting control terminal EM(n+x) receives the first light-emitting control signal, and the second light-emitting control terminal EM(n) receives the second light-emitting control signal. The first and second light-emitting control signals are provided by different output terminals of the same light-emitting driving unit, and the second light-emitting control signal is given earlier than the first light-emitting control signal. In this way, the entire pixel circuit requires two light-emitting driving units and two gate driving units coupled to the first scan control terminal N_Gate and the second scan control terminal P_Gate, respectively, and only requires a reset signal provided by the first initialization signal terminal Vinit1.
[0074] In the specific implementation process, the following methods are adopted: Figure 5 The pixel circuit shown can not only compensate for the threshold voltage of the driving transistor T3, but also simultaneously reset each pole of the driving transistor T3 and alternately reset it. This simplifies the structure of the pixel circuit, reduces the number of transistors, ensures the narrow bezel design, improves the hysteresis problem of the driving transistor T3, avoids problems such as image retention, abnormal brightness of the first frame, and low grayscale flicker when switching between different driving frequencies, and improves the display effect of the display device.
[0075] In one exemplary embodiment, such as Figure 6 As shown, the pixel circuit also includes a second reset transistor T7, which is coupled between the first terminal of the driving transistor T3 and the second initialization signal terminal, and its gate is coupled to the initialization control terminal P_Gate(ny).
[0076] Still combined Figure 6 As shown, the pixel circuit also includes a second reset transistor T7, which is coupled between the first terminal of the driving transistor T3 and the second initialization signal terminal Vinit2, and its gate is connected to the initialization control terminal P_Gate(ny). In this way, when the second reset transistor T7 is turned on, the first terminal of the driving transistor T3 can be reset through the second initialization signal terminal Vinit2, thus improving the hysteresis problem of the driving transistor T3.
[0077] In this embodiment of the disclosure, the second reset transistor T7 and the data write transistor T4 are of the same type; the second scan control terminal P_Gate is used to receive the first scan control signal, and the initialization control terminal P_Gate(ny) is used to receive the second scan control signal. The first scan control signal and the second scan control signal are provided by different output terminals of the same gate drive unit, and the second scan control signal is earlier than the first scan control signal.
[0078] In specific implementation, the second reset transistor T7 and the data write transistor T4 are of the same type. In one exemplary embodiment, they are still combined with... Figure 6As shown, the second reset transistor T7 and the data write transistor T4 can both be P-type transistors. The second scan control terminal P_Gate is used to receive the first scan control signal, and the initialization control terminal P_Gate(ny) is used to receive the second scan control signal. The first scan control signal and the second scan control signal are provided by different output terminals of the same gate driving unit, and the second scan control signal is earlier than the first scan control signal. The first initialization signal terminal Vinit1 and the second initialization signal terminal can be the same signal terminal or different signal terminals. In this way, the entire pixel circuit requires two light-emitting driving units and two gate driving units, and at most requires two types of reset signals provided by the first initialization signal terminal Vinit1 and the second initialization signal terminal. Therefore, using... Figure 6 The pixel circuit shown can not only compensate for the threshold voltage of the driving transistor T3, but also simultaneously reset each pole of the driving transistor T3 and alternately reset it. This simplifies the structure of the pixel circuit, reduces the number of transistors, ensures the narrow bezel design, improves the hysteresis problem of the driving transistor T3, avoids problems such as image retention, abnormal brightness of the first frame, and low grayscale flicker when switching between different driving frequencies, and improves the display effect of the display device.
[0079] In this embodiment of the disclosure, a second capacitor C2 is further included, which is coupled between the second power supply terminal VDD and the second terminal of the driving transistor T3.
[0080] In one exemplary embodiment, such as Figure 7 As shown, the pixel circuit also includes a second capacitor C2 coupled between the second power supply terminal VDD and the second terminal of the driving transistor T3. The capacitance value of the second capacitor C2 is less than the capacitance value of the first capacitor C1.
[0081] In one exemplary embodiment, such as Figure 8 As shown, the pixel circuit also includes a second capacitor C2 coupled between the second power supply terminal VDD and the second terminal of the driving transistor T3. The capacitance value of the second capacitor C2 is less than the capacitance value of the first capacitor C1.
[0082] It should be noted that, in Figure 7 and Figure 8 In the corresponding exemplary embodiment, the capacitance value of the second capacitor C2 is greater than 10fF. This allows the second capacitor C2 to charge the N2 node via the data writing transistor T4, thus ensuring the performance of the pixel circuit. The capacitance value of the second capacitor C2 can be set to be less than the capacitance value of the first capacitor C1, thereby ensuring sufficient layout space for the pixel circuit.
[0083] Still combined Figure 7 and Figure 8In high-frequency conditions, when the data writing transistor T4, the driving transistor T3, and the compensation transistor T2 are all turned on, the N2 node can be charged through the data signal terminal Data and stored in the second capacitor C2. Subsequently, when the data writing transistor T4 is turned off and the compensation transistor T2 is still turned on, the threshold voltage compensation of the N1 node can continue through the second capacitor C2 and the N2 node.
[0084] In this embodiment, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the driving transistor T3, and the data writing transistor T4 are all P-type transistors; the compensation transistor T2 and the first reset transistor T1 are both N-type transistors.
[0085] In the specific implementation process, it is still combined with Figures 5 to 8 As shown, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the driving transistor T3, and the data writing transistor T4 are all P-type transistors, while the compensation transistor T2 and the first reset transistor T1 are both N-type transistors. Therefore, the first light-emitting control transistor T5 will only conduct when the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x) is low; the second light-emitting control transistor T6 will only conduct when the second light-emitting control signal provided by the second light-emitting control terminal EM(n) is low; the data writing transistor T4 will only conduct when the first scan control signal provided by the second scan control terminal P_Gate is low; the compensation transistor T2 will only conduct when the second scan control signal provided by the first scan control terminal N_Gate is high; and the first reset transistor T1 will only conduct when the second scan control signal provided by the initialization control terminal P_Gate(ny) is high. In practical applications, corresponding signals can be loaded onto the first light emission control terminal EM(n+x), the second light emission control terminal EM(n), the first scan control terminal N_Gate, the second scan control terminal P_Gate, and the initialization control terminal P_Gate(ny) respectively to control the conduction and cutoff of the corresponding transistors, thereby improving the control effect of the pixel circuit.
[0086] In this embodiment of the disclosure, the active layer of the compensation transistor T2 and the first reset transistor T1 is a metal oxide semiconductor material, and the active layer of the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 is a low-temperature polycrystalline silicon material.
[0087] In the specific implementation process, it is still combined with Figures 5 to 8As shown, the active layers of the compensation transistor T2 and the first reset transistor T1 are made of metal-oxide-semiconductor (MOS) material, while the active layers of the driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, and second light-emitting control transistor T6 are made of low-temperature polycrystalline silicon (LTPS). Accordingly, the compensation transistor T2 and the first reset transistor T1 can be N-type transistors with MOS materials as their active layers, resulting in lower leakage currents. The driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, and second light-emitting control transistor T6 can be P-type transistors (i.e., LTPS transistors) with LTPS materials as their active layers, allowing them to have higher mobility, and enabling them to be made thinner, smaller, and with lower power consumption. In this way, the pixel circuit provided in this embodiment is essentially a low-temperature poly-silicon+oxide (LTPO) pixel circuit that combines the two transistor fabrication processes of LTPS transistor and oxide transistor, thereby ensuring that the gate leakage current of the driving transistor T3 is small and the power consumption is low.
[0088] It should be noted that the light-emitting device 10 in this embodiment can be an electroluminescent diode, such as at least one of organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), and micro light-emitting diodes / mini light-emitting diodes, and is not limited herein. The light-emitting device 10 may include an anode, a light-emitting layer, and a cathode stacked together. Further, the light-emitting layer may include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the light-emitting device 10 can be designed according to the requirements of the actual application environment, and is not limited here.
[0089] The first and second terminals of the aforementioned transistors can be interchanged depending on their type and the signal at the signal terminal. For example, the first terminal can be the source and the second terminal the drain, or vice versa; no limitation is made here. The transistors can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs); no limitation is made here. Of course, the specific type of each transistor can be set according to the actual application requirements; no limitation is made here.
[0090] The above are merely illustrative examples illustrating the specific structure of the pixel circuit provided in the embodiments of this disclosure. In specific implementations, the specific structure of the pixel circuit is not limited to the structure provided in the embodiments of this disclosure, but may also be other structures known to those skilled in the art. These are all within the protection scope of this invention, and are not specifically limited here.
[0091] The following is based on Figure 5 The pixel circuit structure shown and Figure 9 and Figure 10 The timing diagram shown, in which, Figure 9 for Figure 5 The shown pixel circuit corresponds to one type of timing diagram of the write frame. Figure 10 for Figure 5 The timing diagram shown illustrates one possible holding frame for the pixel circuit, explaining the operation of the pixel circuit provided in this embodiment. The potential signal provided by the first power supply terminal VSS is low, and the potential signal provided by the second power supply terminal VDD is high. Furthermore, based on the current refresh rate and the reference refresh rate of the display device, the current display frame can be divided into one write frame and N holding frames, where N is an integer greater than 1. For example, if the current refresh rate is 40Hz and the reference refresh rate is 120Hz (three times the current refresh rate), the current display frame can be divided into one write frame and two holding frames. Alternatively, if the current refresh rate is 60Hz and the reference refresh rate is 120Hz (twice the current refresh rate), the current display frame can be divided into one write frame and one holding frame. Of course, the current display frame can be divided according to actual application needs, and this is not limited here. One write frame includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, and a fifth stage t5 set sequentially. It should be noted that the embodiments disclosed herein are for better explanation of the pixel circuit provided herein and do not limit the specific implementation of this disclosure. In this case, "0" represents a low level and "1" represents a high level.
[0092] In the first stage t1, EM(n+x)=0, EM(n)=1, N_Gate=1, P_Gate=1;
[0093] In the first stage t1, the first light-emitting control transistor T5 is turned on under the control of the low level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the compensation transistor T2 is turned on under the control of the high level provided by the first scan control terminal N_Gate. Furthermore, when the driving transistor T3 is turned on, N1, N2, and N3 are reset to a high level by the second power supply terminal VDD. The implementation process of this first stage t1 is roughly the same as that of stage ① described above. In addition, the second light-emitting control transistor T6 is turned off under the control of the high level of the second light-emitting control signal provided by the second light-emitting control terminal EM(n), and the light-emitting device 10 does not emit light.
[0094] In the second stage t2, EM(n+x)=1, EM(n)=0, N_Gate=1, P_Gate=1;
[0095] In the second stage t2, the first reset transistor T1 is turned on under the control of a high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), the compensation transistor T2 is turned on under the control of a high level of the first scan control terminal N_Gate, and the second light-emitting control transistor T6 is turned on under the control of a low level of the second light-emitting control signal provided by the second light-emitting control terminal EM(n). The first light-emitting control transistor T5 is turned off under the control of a high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x). In this second stage t2, N4 is reset to the potential of the signal provided by the first initialization signal terminal Vinit1, the light-emitting device 10 does not emit light, and N1, N2, and N3 are reset to a low level. The implementation process of this second stage t2 is roughly the same as that of the aforementioned stage ③.
[0096] In the third stage t3, EM(n+x)=0, EM(n)=1, N_Gate=0, P_Gate=1;
[0097] In the third stage t3, the first light-emitting control transistor T5 is turned on under the control of a low level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), the driving transistor T3 is turned on under the control of a low level of N1, N2 and N3 are reset to a high level, the compensation transistor T2 is turned off under the control of a low level provided by the first scan control terminal N_Gate, and N1 remains at a low level. At this time, the driving transistor T3 has a larger Vgs, thereby improving the hysteresis problem of the driving transistor T3. In addition, the second light-emitting control transistor T6 is turned off under the control of a high level of the second light-emitting control signal provided by the second light-emitting control terminal EM(n), and the light-emitting device 10 does not emit light. The implementation process of this third stage t3 is roughly the same as that of the aforementioned stage ②.
[0098] In the fourth stage t4, EM(n+x) = 1, EM(n) = 1, N_Gate = 1, P_Gate = 0;
[0099] In the fourth stage t4, the first light-emitting control transistor T5 is turned off under the control of the high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the second light-emitting control transistor T6 is turned off under the control of the high level of the second light-emitting control signal provided by the second light-emitting control terminal EM(n), so the light-emitting device 10 does not emit light. The first reset transistor T1 is turned on under the control of the high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the first terminal (i.e., N4) of the light-emitting device 10 is reset to the potential of the signal provided by the first initialization signal terminal Vinit1. The compensation transistor T2 is turned on under the control of the high level provided by the first scan control terminal N_Gate, the data writing transistor T4 is turned on under the control of the low level of the second scan control terminal P_Gate, and the driving transistor T3 is turned on under the control of the low level of N1. The data signal provided by the data signal terminal Data is loaded onto the second terminal (i.e., N2) of the driving transistor T3, and the threshold voltage of the driving transistor T3 and the data signal are written into the gate (i.e., N1) of the driving transistor T3 through the compensation transistor T2 and stored in the first capacitor C1. This achieves compensation for the threshold voltage of the driving transistor T3 and improves uniformity. The implementation process of this fourth stage t4 is roughly the same as the aforementioned stage ④.
[0100] In the fifth stage t5, EM(n+x)=1, EM(n)=0, N_Gate=0, P_Gate=1.
[0101] In the fifth stage t5, the first reset transistor T1 is turned on under the control of a high level of the first light emission control signal provided by the first light emission control terminal EM(n+x), the second light emission control transistor T6 is turned on under the control of a low level of the second light emission control terminal EM(n), and the first light emission control transistor T5 is turned off under the control of a high level of the first light emission control signal provided by the first light emission control terminal EM(n+x). The first terminal (i.e., N3) of the driving transistor T3 is reset to the potential of the signal provided by the first initialization signal terminal Vinit1. Correspondingly, N3 is reset to a low level, and the light-emitting device 10 does not emit light. The implementation process of this fifth stage t5 is roughly the same as that of the aforementioned stage ⑤. Moreover, the entire reset process does not pass through the driving transistor T3. Therefore, regardless of which image is written, N3 can be reset to a low level, thereby ensuring the performance of the pixel circuit.
[0102] In addition, the hold frame includes a sixth stage and a seventh stage set sequentially;
[0103] In the sixth stage t6, EM(n) and EM(n+x) are set to high one after the other, N_Gate = 0, P_Gate = 1;
[0104] In the sixth stage t6, EM(n) and EM(n+x) are successively set high. Correspondingly, the second light-emitting control transistor T6, under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM(n), and the first light-emitting control transistor T5, under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), are successively cut off. Moreover, the first reset transistor T1 is turned on under the control of the high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x). Correspondingly, the first electrode (i.e., N4) of the light-emitting device 10 is reset to the potential of the signal provided by the first initialization signal terminal Vinit1, completing the anode reset. The light-emitting device 10 does not emit light. At this time, the duty cycle of the light-emitting stage can be controlled by controlling the duration of the light-emitting control signal being high, thereby achieving flexible adjustment of the brightness of the holding frame. Moreover, the implementation process of the sixth stage t6 is roughly the same as that of the aforementioned stage ⑥.
[0105] In the seventh stage t7, EM(n+x)=1, EM(n)=0, N_Gate=0, P_Gate=1;
[0106] In the seventh stage, the second light-emitting control transistor T6 is turned on under the low-level control of the second light-emitting control signal provided by the second light-emitting control terminal EM(n), and the first light-emitting control transistor T5 is turned off under the high-level control of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), so the light-emitting device 10 does not emit light. The first reset transistor T1 is turned on under the high-level control of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the first terminal (i.e., N4) of the light-emitting device 10 is reset to the potential of the signal provided by the first initialization signal terminal Vinit1, and the first terminal (i.e., N3) of the driving transistor T3 is reset to a low level. Moreover, the implementation process of the seventh stage is roughly the same as that of the aforementioned seventh stage.
[0107] It should be noted that in stages t6 and t7, except for the light emission control signal which needs to be output, the control signals provided by the first scan control terminal N_Gate and the second scan control terminal P_Gate remain in a regulated state. The control signal provided by the first scan control terminal N_Gate is a constant low-potential signal, and the first scan control signal provided by the second scan control terminal P_Gate is a constant high-potential signal. In one exemplary embodiment, for Figure 5If the display driver chip coupled to the pixel circuit cannot achieve different outputs for the write frame and the hold frame, the signal output of the light emission control terminal can be kept the same as that of the write frame. The first scan control terminal N_Gate and the second scan control terminal P_Gate can still be kept at low and high levels respectively, which can still satisfy the functions of the sixth stage t6 and the seventh stage t7. This will not be described in detail here.
[0108] In one exemplary embodiment, the terminals of the driving transistor T3 can be refreshed repeatedly. Figure 11 Taking the timing diagram shown as an example, N1, N2, and N3 can be repeatedly refreshed with high and low levels. Figure 11 The diagram illustrates a scenario where the first stage t1 and the second stage t2 are considered as a repeating unit, and the written frame includes two repeating units set sequentially. Of course, multiple repeating units can be set according to actual application needs, and other stages can also be repeated; these will not be detailed here. This improves the afterimage problem.
[0109] In this embodiment of the disclosure, the duty cycle of the light-emitting stage can be changed by adjusting the width of the high level of the light-emitting control signal, thereby achieving brightness adjustment by the pixel circuit. In one exemplary embodiment, adjustment can be achieved by shifting the rising edge of the light-emitting control signal forward. Figure 12 Taking the timing diagram shown as an example, the write frame includes two repeating units, namely a first repeating unit and a second repeating unit set sequentially. The duration of the second emission control signal in the first repeating unit is longer than that in the second repeating unit; the duration of the first emission control signal in the first repeating unit is longer than that in the second repeating unit. In this way, the duty cycle of the emission stage can be adjusted.
[0110] In one exemplary embodiment, Figure 6 The pixel circuit shown can also be used Figure 13 The timing diagram shown includes an eighth stage t8 located between the third stage t3 and the fourth stage t4. During the time period between the eighth stage t8 and the fourth stage t4, the signals loaded on the first light emission control terminal EM(n+x), the second light emission control terminal EM(n), the first scan control terminal N_Gate, and the second scan control terminal P_Gate are kept in a regulated state, and the potential of the gate of the driving transistor T3 is kept the same as the control signal provided by the second initialization signal terminal coupled to the second reset transistor T7. In this way, there is no signal transition during the time period between the eighth stage t8 and the fourth stage t4, and the potential of node N1 remains at Vinit1. Moreover, separating the voltage of the reset node N1 from the voltage of the reset anode improves the control capability of the pixel circuit.
[0111] In this embodiment, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the driving transistor T3, and the data writing transistor T4 are all P-type transistors; the compensation transistor T2 and the first reset transistor T1 are both N-type transistors.
[0112] In this embodiment, the active layers of the compensation transistor T2 and the first reset transistor T1 are made of metal-oxide-semiconductor (MOS) material, while the active layers of the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are made of low-temperature polycrystalline silicon (LTPS). The transistors with MOS active layers have lower leakage current, while the transistors with LPS active layers have higher mobility, which can accelerate charging speed. Thus, the pixel circuit provided in this embodiment combines the advantages of these two types of transistors, contributing to the development of high-resolution, low-power, and high-quality display products.
[0113] Based on the same disclosed concept, embodiments of this disclosure also provide a display device, which includes any of the pixel circuits described above.
[0114] Since the principle by which this display device solves the problem is similar to that of the aforementioned pixel circuit, the implementation of this display device can be found in the implementation of the aforementioned pixel circuit, and the repetitions will not be repeated.
[0115] In specific implementations, the display device provided in the embodiments of this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0116] Based on the same publicly disclosed concept, such as Figure 14 As shown, this disclosure also provides a driving method for the above-described pixel circuit, the driving method comprising:
[0117] S101: Based on the current refresh rate of the display device and the reference refresh rate, the current display frame of the display device is divided into one write frame and N hold frames, where N is an integer greater than 1; wherein, the write frame includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage set sequentially;
[0118] S102: In the first stage, the first light-emitting control transistor, the driving transistor and the compensation transistor are turned on, and the potentials of the first terminal, gate and second terminal of the driving transistor are reset through the second power supply terminal;
[0119] S103: In the second stage, the first reset transistor, the compensation transistor, and the second light-emitting control transistor are turned on to reset the potentials of the first electrode, gate, and second electrode of the driving transistor, and the potential of the first electrode of the light-emitting device is reset through the first initialization signal terminal;
[0120] S104: In the third stage, the first light-emitting control transistor and the driving transistor are turned on, and the potentials of the first and second terminals of the driving transistor are reset;
[0121] S105: In the fourth stage, the first reset transistor, the compensation transistor, the driving transistor and the data writing transistor are turned on to reset the potential of the first electrode of the light-emitting device, and the data signal provided by the data signal terminal is loaded to the second electrode of the driving transistor. The threshold voltage of the driving transistor and the data signal are written to the gate of the driving transistor through the compensation transistor and stored in the first capacitor.
[0122] S106: In the fifth stage, the first reset transistor and the second light-emitting control transistor are turned on, and the potential of the first terminal of the driving transistor is reset through the first initialization signal terminal.
[0123] In one exemplary embodiment, the specific implementation process of steps S101 to S106 can be referred to the aforementioned method. Figure 5 The pixel circuit shown and Figure 9 The descriptions of the corresponding parts of the timing diagram shown are not repeated here.
[0124] In the embodiments disclosed herein, such as Figure 15 As shown, the holding frame includes a sixth stage and a seventh stage set sequentially, and the method further includes:
[0125] S201: In the sixth stage, the second light-emitting control transistor and the first light-emitting control transistor are controlled to be turned off one after the other, and the first reset transistor is turned on, so as to reset the potential of the first electrode of the light-emitting device through the first initialization signal terminal;
[0126] S202: In the seventh stage, the first reset transistor and the second light-emitting control transistor are turned on, and the potential of the second terminal of the driving transistor is reset through the first power supply terminal.
[0127] In one exemplary embodiment, the specific implementation process of steps S201 to S202 can be referred to the aforementioned method. Figure 5 The pixel circuit shown and Figure 10The descriptions of the corresponding parts of the timing diagram shown are not repeated here.
[0128] In this embodiment of the disclosure, the first stage and the second stage are considered as a repeating unit, and the write frame includes M repeating units arranged sequentially, where M is a positive integer greater than 1.
[0129] In this embodiment, the M repeating units include two repeating units, namely a first repeating unit and a second repeating unit. The duration of the second light emission control signal in the first repeating unit is greater than the duration of its duration in the second repeating unit. For the specific implementation process of this part, please refer to the aforementioned method. Figure 5 The pixel circuit shown and Figure 12 The descriptions of the corresponding parts of the timing diagram shown are not repeated here.
[0130] In this embodiment of the disclosure, the pixel circuit further includes a second reset transistor, the write frame further includes an eighth stage located between the third stage and the fourth stage, and the method further includes:
[0131] During the time interval between the eighth stage and the fourth stage, the signals loaded on the first light-emitting control terminal, the second light-emitting control terminal, the first scan control terminal, and the second scan control terminal are kept in a regulated state, and the potential of the gate of the driving transistor and the control signal provided by the second initialization signal terminal coupled to the second reset transistor are kept the same. For the specific implementation process of this part, please refer to the aforementioned method. Figure 6 The pixel circuit shown can also be used Figure 13 The descriptions of the corresponding parts of the timing diagram shown are not repeated here.
[0132] In the embodiments disclosed herein, such as Figure 16 As shown, the pixel circuit further includes a second capacitor coupled between the second power supply terminal and the second electrode of the driving transistor, and the method further includes:
[0133] S301: In the fourth stage, the data signal is loaded onto the second terminal of the driving transistor and stored in the second capacitor;
[0134] S302: The second terminal of the driving transistor continues to be charged through the second capacitor.
[0135] For the specific implementation process of steps S301 to S302, please refer to the description of the relevant parts in the aforementioned pixel circuit, which will not be repeated here.
[0136] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0137] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.
Claims
1. A pixel circuit, wherein, include: The system comprises a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a light-emitting device, and a first capacitor; wherein: The first reset transistor is coupled between the first electrode of the light-emitting device and the first initialization signal terminal, and its gate is coupled to the first light-emitting control terminal; The second electrode of the light-emitting device is coupled to the first power supply terminal; The compensation transistor is coupled between the gate and the first electrode of the driving transistor, and the gate is coupled to the first scan control terminal. The data writing transistor is coupled between the second terminal of the driving transistor and the data signal terminal, and its gate is coupled to the second scan control terminal. The first light-emitting control transistor is coupled between the second power supply terminal and the second terminal of the driving transistor, and its gate is coupled to the first light-emitting control terminal. The second light-emitting control transistor is coupled between the first terminal of the driving transistor and the first terminal of the light-emitting device, and its gate is coupled to the second light-emitting control terminal; The first capacitor is coupled between the second power supply terminal and the gate of the driving transistor; Wherein, the first light-emitting control transistor and the second light-emitting control transistor are of the same type and are both P-type transistors, and are of the opposite type to the first reset transistor, which is an N-type transistor; the first light-emitting control terminal is used to receive the first light-emitting control signal, and the second light-emitting control terminal is used to receive the second light-emitting control signal. The first light-emitting control signal and the second light-emitting control signal are provided by different output terminals of the same light-emitting driving unit, and the second light-emitting control signal is earlier than the first light-emitting control signal. The pixel circuit is configured as follows: Based on the current refresh rate of the display device and the reference refresh rate, the current display frame of the display device is divided into one write frame and N hold frames, where N is an integer greater than 1; wherein, the write frame includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage set sequentially; In the first stage, the first light-emitting control transistor, the driving transistor, and the compensation transistor are turned on, and the potentials of the first terminal, gate, and second terminal of the driving transistor are reset through the second power supply terminal; In the second stage, the first reset transistor, the compensation transistor, and the second light-emitting control transistor are turned on to reset the potentials of the first electrode, gate, and second electrode of the driving transistor, and the potential of the first electrode of the light-emitting device is reset through the first initialization signal terminal; In the third stage, the first light-emitting control transistor and the driving transistor are turned on, and the potentials of the first and second terminals of the driving transistor are reset. In the fourth stage, the first reset transistor, the compensation transistor, the driving transistor, and the data writing transistor are turned on to reset the potential of the first electrode of the light-emitting device, and the data signal provided by the data signal terminal is loaded to the second electrode of the driving transistor. The threshold voltage of the driving transistor and the data signal are written into the gate of the driving transistor through the compensation transistor and stored in the first capacitor. In the fifth stage, the first reset transistor and the second light-emitting control transistor are turned on, and the potential of the first terminal of the driving transistor is reset through the first initialization signal terminal.
2. The pixel circuit as described in claim 1, wherein, It also includes a second reset transistor, which is coupled between the first terminal of the driving transistor and the second initialization signal terminal, and its gate is coupled to the initialization control terminal.
3. The pixel circuit as described in claim 2, wherein, The second reset transistor and the data write transistor are of the same type; the second scan control terminal is used to receive the first scan control signal, and the initialization control terminal is used to receive the second scan control signal. The first scan control signal and the second scan control signal are provided by different output terminals of the same gate drive unit, and the second scan control signal is earlier than the first scan control signal.
4. The pixel circuit as described in claim 3, wherein, The first initialization signal terminal and the second initialization signal terminal may be the same signal terminal or different signal terminals.
5. The pixel circuit according to any one of claims 1-4, wherein, Also includes: A second capacitor is coupled between the second power supply terminal and the second electrode of the driving transistor.
6. The pixel circuit as described in claim 5, wherein, The capacitance of the second capacitor is less than that of the first capacitor.
7. The pixel circuit according to any one of claims 1-4, wherein, The first light-emitting control transistor, the second light-emitting control transistor, the driving transistor, and the data writing transistor are all P-type transistors; the compensation transistor and the first reset transistor are both N-type transistors.
8. The pixel circuit as described in claim 7, wherein, The active layers of the compensation transistor and the first reset transistor are made of metal oxide semiconductor material, while the active layers of the driving transistor, the data writing transistor, the first light-emitting control transistor, and the second light-emitting control transistor are made of low-temperature polycrystalline silicon material.
9. A display device, wherein, Includes the pixel circuit as described in any one of claims 1-8.
10. A driving method for a pixel circuit as described in any one of claims 1-8, wherein, include: Based on the current refresh rate of the display device and the reference refresh rate, the current display frame of the display device is divided into one write frame and N hold frames, where N is an integer greater than 1; wherein, the write frame includes a first stage, a second stage, a third stage, a fourth stage and a fifth stage set sequentially; In the first stage, the first light-emitting control transistor, the driving transistor, and the compensation transistor are turned on, and the potentials of the first terminal, gate, and second terminal of the driving transistor are reset through the second power supply terminal; In the second stage, the first reset transistor, the compensation transistor, and the second light-emitting control transistor are turned on to reset the potentials of the first electrode, gate, and second electrode of the driving transistor, and the potential of the first electrode of the light-emitting device is reset through the first initialization signal terminal; In the third stage, the first light-emitting control transistor and the driving transistor are turned on, and the potentials of the first and second terminals of the driving transistor are reset. In the fourth stage, the first reset transistor, the compensation transistor, the driving transistor, and the data writing transistor are turned on to reset the potential of the first electrode of the light-emitting device, and the data signal provided by the data signal terminal is loaded to the second electrode of the driving transistor. The threshold voltage of the driving transistor and the data signal are written into the gate of the driving transistor through the compensation transistor and stored in the first capacitor. In the fifth stage, the first reset transistor and the second light-emitting control transistor are turned on, and the potential of the first terminal of the driving transistor is reset through the first initialization signal terminal.
11. The method of claim 10, wherein, The holding frame includes a sixth stage and a seventh stage set sequentially, and the method further includes: In the sixth stage, the second light-emitting control transistor and the first light-emitting control transistor are turned off sequentially, and the first reset transistor is turned on, thereby resetting the potential of the first electrode of the light-emitting device through the first initialization signal terminal; In the seventh stage, the first reset transistor and the second light-emitting control transistor are turned on, and the potential of the second terminal of the driving transistor is reset through the first power supply terminal.
12. The method of claim 10, wherein, The first stage and the second stage are considered as a repeating unit, and the write frame includes M repeating units set sequentially, where M is a positive integer greater than 1.
13. The method of claim 12, wherein, The M repeating units include two repeating units, namely a first repeating unit and a second repeating unit. The duration of the second light emission control signal in the first repeating unit is longer than the duration of the second repeating unit.
14. The method according to any one of claims 10-13, wherein, The pixel circuit further includes a second reset transistor, and the write frame further includes an eighth stage located between the third stage and the fourth stage, and the method further includes: During the time period between the eighth stage and the fourth stage, the signals loaded on the first light-emitting control terminal, the second light-emitting control terminal, the first scan control terminal, and the second scan control terminal are kept in a regulated state, and the potential of the gate of the driving transistor is kept the same as the control signal provided by the second initialization signal terminal coupled to the second reset transistor.
15. The method of claim 14, wherein, The pixel circuit further includes a second capacitor coupled between the second power supply terminal and the second electrode of the driving transistor, and the method further includes: In the fourth stage, the data signal is loaded onto the second terminal of the driving transistor and stored in the second capacitor; The second capacitor continues to charge the second terminal of the driving transistor.