Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor having high moisture-resistant reliability while achieving miniaturization and increased capacity. A multilayer ceramic capacitor (1) comprises: a multilayer body (10) that includes an inner layer part (100) in which internal electrode layers (30) and internal dielectric layers (20i) are layered, and that has two main surfaces (TS1, TS2) facing each other in the lamination direction (T), two lateral surfaces (WS1, WS2) facing each other in the width direction intersecting the lamination direction (T), and two end surfaces facing each other in the length direction intersecting the lamination direction (T) and the width direction (W); and external electrodes (40) that are respectively disposed on the two end surfaces and are connected to internal electrode layers. In side margin parts (WG) positioned on both sides of the inner layer part (100) in the width direction (W), the content of elemental rare earth in an outer region (WGo) is lower than the content of elemental rare earth in an inner region (WGi).

Description

Multilayer ceramic capacitor

[0001] This invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, multilayer ceramic capacitors, which include a laminated structure with an inner layer in which an internal dielectric layer and an internal electrode layer are alternately stacked, and external electrodes electrically connected to the internal electrodes, have been used as an electronic component in a wide range of fields, including communications, IoT, automotive, and medical.

[0003] In particular, in recent years, multilayer ceramic capacitors are sometimes installed in equipment that protects people's safety, and as the demand for further miniaturization, increased capacitance, and improved quality increases, moisture resistance reliability in multilayer ceramic capacitors has become an important factor that can lead to equipment failure. Patent Document 1 discloses a multilayer ceramic capacitor in which the capacitance section is large relative to the chip size, thereby improving reliability while achieving miniaturization and increased capacitance.

[0004] Japanese Patent Application Publication No. 10-050545

[0005] However, conventional multilayer ceramic capacitors have a problem in that if moisture penetrates from the outside, the moisture can easily reach the inner layers where the internal electrode layers and internal dielectric layers are stacked alternately, making it difficult to guarantee high moisture resistance reliability.

[0006] The present invention aims to provide a multilayer ceramic capacitor that achieves miniaturization and high capacitance while possessing high moisture resistance reliability.

[0007] The inventors of the present invention have discovered that moisture resistance reliability can be improved by adjusting the content of rare earth elements in a predetermined region of a multilayer ceramic capacitor, and have completed the present invention.

[0008] In other words, the present invention relates to a multilayer ceramic capacitor comprising: an inner layer in which an internal electrode layer and an internal dielectric layer are stacked, having two main surfaces opposite to each other in the stacking direction, two side surfaces opposite to each other in the width direction intersecting the stacking direction, and two end surfaces opposite to each other in the length direction intersecting the stacking direction and the width direction; and external electrodes arranged on each of the two end surfaces and connected to the internal electrode layer, wherein in the side margin portions located on both sides of the width direction of the inner layer and forming the side surfaces, the content of rare earth elements in the outer region located on the side surface side of the laminate is lower than the content of rare earth elements in the inner region located on the inner layer side of the laminate.

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that prevents moisture from penetrating into the inner layer and has high moisture resistance reliability.

[0010] This is a perspective view showing a multilayer ceramic capacitor according to this embodiment. This is a cross-sectional view (LT section) of the multilayer ceramic capacitor shown in Figure 1, taken along line II-II. This is a cross-sectional view (WT section) of the multilayer ceramic capacitor shown in Figure 1, taken along line III-III. This is a cross-sectional view (LW section) of the multilayer ceramic capacitor shown in Figure 3, taken along line IV-IV. This is a diagram showing two internal electrode patterns formed on a dielectric sheet. This is a diagram illustrating the process of forming the multilayer ceramic capacitor shown in Figure 1. This is a diagram illustrating the process of forming the multilayer ceramic capacitor shown in Figure 1.

[0011] The following describes embodiments of the multilayer ceramic capacitor of the present invention, but the present invention is not limited thereto. Furthermore, the drawings may be schematically simplified to illustrate the content of the invention, and the ratios of dimensions of the depicted components or between components may not match the ratios of those dimensions described in the specification. Also, components described in the specification may be omitted in the drawings, or their quantities may be omitted.

[0012] (Multilayer Ceramic Capacitor) Figure 1 is a perspective view showing a multilayer ceramic capacitor, Figure 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line II-II, and Figure 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line III-III. Figure 4 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 3 along line IV-IV. The multilayer ceramic capacitor 1 shown in Figures 1 to 4 comprises a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0013] Figures 1 to 4 show the XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10. Accordingly, the cross section shown in Figure 2 is also called the LT cross section, the cross section shown in Figure 3 is also called the WT cross section, and the cross section shown in Figure 4 is also called the LW cross section.

[0014] Furthermore, the length direction L, width direction W, and stacking direction T are not necessarily orthogonal to each other; they may intersect.

[0015] The laminate 10 has a substantially rectangular parallelepiped shape and includes a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W, and a first end surface LS1 and a second end surface LS2 facing the length direction L. The surface of each face may have irregularities or be rough.

[0016] When there is no need to distinguish between the first main surface TS1 and the second main surface TS2, they are collectively referred to as the main surface TS; when there is no need to distinguish between the first side surface WS1 and the second side surface WS2, they are collectively referred to as the side surface WS; and when there is no need to distinguish between the first end surface LS1 and the second end surface LS2, they are collectively referred to as the end surface LS.

[0017] It is preferable that the edges and corners of the laminate 10 are rounded. The edges are the parts where two faces of the laminate 10 intersect, and the corners are the parts where three faces of the laminate 10 intersect.

[0018] As shown in Figures 2 and 3, the laminate 10 has a plurality of internal dielectric layers 20 and a plurality of internal electrode layers 30 stacked in the stacking direction T. The laminate 10 also has an inner layer portion 100 and a first outer layer portion 201 and a second outer layer portion 202 arranged to sandwich the inner layer portion 100 in the stacking direction T.

[0019] The inner layer 100 includes a plurality of internal dielectric layers 20i and a plurality of internal electrode layers 30. The inner layer 100 is a region sandwiched between the internal electrode layers 30 located at both ends in the stacking direction T, where the internal dielectric layers 20i and internal electrode layers 30 are stacked alternately. The inner layer 100 is a portion in which the plurality of internal electrode layers 30 are arranged facing each other via the internal dielectric layers 20i, generating capacitance and functioning substantially as a capacitor.

[0020] The first outer layer 201 is located on the side of the first main surface TS1 of the laminate 10, and the second outer layer 202 is located on the side of the second main surface TS2 of the laminate 10. More specifically, the first outer layer 201 is located between the internal electrode layer 30 closest to the first main surface TS1 and the first main surface TS1, and the second outer layer 202 is located between the internal electrode layer 30 closest to the second main surface TS2 and the second main surface TS2. The first outer layer 201 and the second outer layer 202 are formed of a dielectric layer 20o and do not include the internal electrode layers 30.

[0021] For example, the material for the dielectric layer 20 is BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ A dielectric ceramic containing the above as the main component can be used. In addition, the material of the dielectric layer 20 may have, for example, Mn compounds, Ni compounds, Fe compounds, Cr compounds, Co compounds, Mg compounds, Si compounds, Al compounds, V compounds, or rare earth compounds added as minor components.

[0022] The thickness of the dielectric layer 20 is not particularly limited, but is preferably 0.3 μm to 5.0 μm, and more preferably 0.3 μm to 2.0 μm. The number of dielectric layers 20 is not particularly limited, but is preferably 100 to 2000. This number of dielectric layers 20 is the total number of internal dielectric layers 20i in the inner layer portion 100 and dielectric layers 20o in the outer layer portion 200.

[0023] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10.

[0024] The first internal electrode layer 31 includes a facing portion 311 and a leading portion 312, and the second internal electrode layer 32 includes a facing portion 321 and a leading portion 322.

[0025] The opposing portion 311 of the first internal electrode layer 31 and the opposing portion 321 of the second internal electrode layer 32 face each other via the internal dielectric layer 20i in the stacking direction T of the laminate 10. The shapes of the opposing portions 311 and 321 are not particularly limited and may be, for example, substantially rectangular. The opposing portions 311 and 321 are parts that generate capacitance and function substantially as capacitors.

[0026] The lead-out portion 312 of the first internal electrode layer 31 extends from the opposing portion 311 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The lead-out portion 322 of the second internal electrode layer 32 extends from the opposing portion 321 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2.

[0027] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end face LS2 of the laminate 10, i.e., the second external electrode 42. Also, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end face LS1 of the laminate 10, i.e., the first external electrode 41.

[0028] The first internal electrode layer 31 and the second internal electrode layer 32 may contain, for example, at least one of the following as a main component or as a component other than the main component: a metal such as Ni, Cu, Ag, Pd, or Au, or an Ag-Pd alloy. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may also contain dielectric particles of the same composition system as the ceramic contained in the internal dielectric layer 20i as a component other than the main component. In this specification, the main component metal refers to the metal component with the highest weight %. A metal layer such as Sn may be arranged around the first internal electrode layer 31 and the second internal electrode layer 32.

[0029] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 0.30 μm or more and 0.40 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 10 or more and 1000 or less.

[0030] Furthermore, a method for measuring the thickness of the internal dielectric layer 20i and the internal electrode layer 30 is, for example, to observe the LT cross-section near the center in the width direction of the laminate exposed by polishing using a scanning electron microscope. In addition, each value may be the average of measurements taken at multiple locations in the length direction, or further, the average of measurements taken at multiple locations in the lamination direction.

[0031] As shown in Figure 3, the laminate 10 has an electrode-facing portion W30 on which the internal electrode layer 30 faces in the width direction W, and a first side margin portion WG1 and a second side margin portion WG2 arranged to sandwich the electrode-facing portion W30. The electrode-facing portion W30 is composed of an inner layer portion 100 on which the internal electrode layer 30 and the internal dielectric layer 20i are laminated, and two outer layer portions 200 arranged to sandwich the inner layer portion 100 from the lamination direction T. That is, the first side margin portion WG1 and the second side margin portion WG2 are arranged to sandwich the inner layer portion 100 and the two outer layer portions 200 from the width direction W.

[0032] The first side margin portion WG1 is located between the electrode facing portion W30 and the first side surface WS1, and the second side margin portion WG2 is located between the electrode facing portion W30 and the second side surface WS2. More specifically, the first side margin portion WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side margin portion WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side margin portion WG1 and the second side margin portion WG2 do not include the internal electrode layer and include only the dielectric. The first side margin portion WG1 and the second side margin portion WG2 are also called side gaps or W gaps. In cases where there is no need to distinguish between the first side margin section WG1 and the second side margin section WG2, they will be described collectively as the side margin section WG.

[0033] The side margin section WG is BaTiO ３ It can be made from a dielectric ceramic material with as its main component. Furthermore, the side margin portion WG may consist of two layers, or three or more layers.

[0034] As shown in Figure 3, the side margin portion WG includes an inner region WGi and an outer region WGo arranged in the width direction W. The inner region WGi can be the region located closest to the innermost layer portion 100 when the side margin portion is divided into five equal parts in the width direction W. The inner region WGi can be the region located closest to the side WS when the side margin portion is divided into five equal parts in the width direction W.

[0035] The inner region WGi is BaTiO ３ It can be made from a dielectric ceramic material mainly composed of SiO. The inner region WGi may contain glass. The glass is SiO ２ It can be the main component, but is not limited to this.

[0036] The inner region WGi contains rare earth elements such as dysprosium (Dy), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lanthanum (La) as additive components. The thickness of the inner region WGi in the width direction W is 1 μm or more and 7 μm or less.

[0037] The outer region WGo can be composed of a dielectric ceramic material having BaTiO ３ as a main component. The inner region WGi contains glass. The glass can have SiO ２ as a main component, but is not limited thereto.

[0038] The outer region WGo contains rare earth elements such as dysprosium (Dy) and lanthanum (La) as additive components. The thickness of the outer region WGo in the width direction W is 1 μm or more and 7 μm or less.

[0039] As described later, the side margin portion WG can be formed by attaching side surface covering portions SC for forming the side margin portion WG to both side surfaces of the laminated body chip 10T composed of the inner layer portion 100 and the outer layer portion 200 in the width direction W.

[0040] As shown in FIG. 2, the laminate 10 has, in the length direction L, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end margin portion LG1, and a second end margin portion LG2. The first end margin portion LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second end margin portion LG2 is located between the electrode facing portion L30 and the second end face LS2. More specifically, the first end margin portion LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end margin portion LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2.

[0041] The first end margin portion LG1 includes the first internal electrode layer 31 and the dielectric layer 20, and does not include the second internal electrode layer 32. Therefore, a dielectric layer 20z having a thickness corresponding to the thickness of the second internal electrode layer 32 can be disposed to eliminate a step at an end on the first end face LS1 side of the second internal electrode layer 32. The second end margin portion LG2 includes the second internal electrode layer 32 and the dielectric layer 20, and does not include the first internal electrode layer 31. Therefore, a dielectric layer 20z having a thickness corresponding to the thickness of the first internal electrode layer 31 can be disposed to eliminate a step at an end on the second end face LS2 side of the first internal electrode layer 31. Note that the dielectric layer 20z does not necessarily need to be disposed, and the laminate 10 may be formed without disposing the dielectric layer 20z.

[0042] The first end margin portion LG1 is a portion that functions as a lead-out electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end margin portion LG2 is a portion that functions as a lead-out electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end margin portion LG1 and the second end margin portion LG2 are also referred to as an L gap.

[0043] In the electrode facing portion L30, the facing portion 311 of the first internal electrode layer 31 and the facing portion 321 of the second internal electrode layer 32 described above are located. Further, in the first end margin portion LG1, the lead-out portion 312 of the first internal electrode layer 31 described above is located, and in the second end margin portion LG2, the lead-out portion 322 of the second internal electrode layer 32 described above is located.

[0044] As a method for measuring the thickness of each part of the laminate 10, for example, one method is to observe the LT cross section near the center in the width direction of the laminate exposed by polishing, or the WT cross section near the center in the length direction of the laminate exposed by polishing, using a scanning electron microscope. In addition, each value may be the average of measurements taken at multiple locations in the length direction or width direction. Similarly, as a method for measuring the length of each part of the laminate 10, for example, one method is to observe the LT cross section near the center in the width direction of the laminate exposed by polishing, using a scanning electron microscope. In addition, each value may be the average of measurements taken at multiple locations in the lamination direction. Similarly, as a method for measuring the width of each part of the laminate 10, for example, one method is to observe the WT cross section near the center in the length direction of the laminate exposed by polishing, using a scanning electron microscope. In addition, each value may be the average of measurements taken at multiple locations in the lamination direction.

[0045] The external electrode 40 includes a first external electrode 41 and a second external electrode 42.

[0046] The first external electrode 41 is positioned on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2. Alternatively, the first external electrode 41 may extend from the first end face LS1 to a part of the first side surface WS1 and a part of the second side surface WS2.

[0047] The second external electrode 42 is positioned on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2. The second external electrode 42 may also extend from the second end face LS2 to a part of the first side surface WS1 and a part of the second side surface WS2.

[0048] The first external electrode 41 has a base electrode layer 415 and a plating layer 416, and the second external electrode 42 has a base electrode layer 425 and a plating layer 426. The first external electrode 41 may consist only of the plating layer 416, and the second external electrode 42 may consist only of the plating layer 426.

[0049] The base electrode layers 415 and 425 may be fired layers containing metal and glass. Examples of glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, or Li. Borosilicate glass can be used as a specific example. The metal mainly contains Cu. Alternatively, the metal may mainly contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, or may be included as a component other than the main component.

[0050] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate using a dip method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, there may be multiple fired layers.

[0051] Alternatively, the base electrode layers 415 and 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-described firing layer, or it may be formed directly on the laminate without forming a firing layer.

[0052] The resin layer is a layer obtained by coating a laminate with a conductive paste containing conductive particles and a thermosetting resin using a coating method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, the resin layer may consist of multiple layers.

[0053] The thickness of each layer of the base electrode layers 415 and 425, which are a fired layer or a resin layer, is not particularly limited and may be 1 μm or more and 10 μm or less.

[0054] Alternatively, the base electrode layers 415 and 425 may be thin films of 1 μm or less in thickness, formed by a thin film formation method such as sputtering or vapor deposition, and in which metal particles are deposited.

[0055] The plating layer 416 covers at least a portion of the underlying electrode layer 415, and the plating layer 426 covers at least a portion of the underlying electrode layer 425. The plating layers 416 and 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.

[0056] The plating layers 416 and 426 may each be formed from multiple layers. Preferably, they are a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the underlying electrode layer from being corroded by the solder when mounting ceramic electronic components, and the Sn plating layer improves the wettability of the solder when mounting ceramic electronic components, making mounting easier. The plating layers 416 and 426 can also be a three-layer structure by stacking Sn plating, Ni plating and Sn plating, respectively. The outermost layer may be Au plating.

[0057] The thickness of each plating layer 416, 426 is not particularly limited and may be 1 μm or more and 10 μm or less.

[0058] (Rare Earth Element Content) In the side margin region WG, the rare earth element content in the outer region WGo is lower than that in the inner region WGi.

[0059] In this way, by making the rare earth element content of the outer region WGo lower than that of the inner region WGi, it is possible to promote the densification of the outer region WGo. This suppresses the penetration of moisture from the outer region WGo, and ensures moisture resistance reliability.

[0060] In the inner region WGi, the content of rare earth elements is preferably 0.3 mol% to 7.0 mol% per 100 mol of Ti, and in the outer region WGO, the content of rare earth elements is preferably 0.1 mol% to 6.5 mol% per 100 mol of Ti.

[0061] The inner region WGi and the outer region WGO may contain additives such as Al, Mg, Mn, Ni, V, etc., but their inclusion is not necessarily required.

[0062] Preferably, the molar ratio A of the rare earth element to Ti at both ends of the width direction W of the internal dielectric layer 20i constituting the inner layer 100, and the molar ratio B of the rare earth element to Ti in the inner region WGi of the side margin WG, are in a relationship of 0.9 ≤ molar ratio A / molar ratio B ≤ 1.1.

[0063] In this way, by adjusting the molar ratio A of rare earth elements to Ti at both ends of the width direction W of the internal dielectric layer 20i and the molar ratio B of rare earth elements to Ti in the inner region WGi of the side margin WG to satisfy the relationship 0.9 ≤ molar ratio A / molar ratio B ≤ 1.1, the diffusion of rare earth elements from the inner layer 100 to the inner region WGi can be suppressed. This makes it possible to suppress changes in the properties of the inner layer 100 caused by the outflow of rare earth elements into the side margin WG, and to suppress the decrease in high-temperature load reliability due to grain growth in the outer region WGo.

[0064] Preferably, the molar ratio B of rare earth elements to Ti in the inner region WGi of the side margin portion WG and the molar ratio C of rare earth elements to Ti in the outer region WGo of the side margin portion WG are in a relationship of 0.389 ≤ molar ratio C / molar ratio B ≤ 0.922.

[0065] In this way, by adjusting the molar ratio B of rare earth elements to Ti in the inner region WGi and the molar ratio C of rare earth elements to Ti in the outer region WGo so that the relationship 0.389 ≤ molar ratio C / molar ratio B ≤ 0.922 is satisfied, it is possible to maintain the rare earth concentration in the inner region WGi at approximately the same level as the internal dielectric layer 20i of the inner layer 100 while promoting grain densification in the outer region WGo. This makes it possible to maintain high-temperature load reliability while ensuring moisture resistance reliability.

[0066] If the molar ratio C / molar ratio B is less than 0.389, the concentration difference between the rare earth elements in the inner region WGi and the center of the inner dielectric layer 20i tends to be relatively large, potentially leading to a large difference in rare earth element concentrations between the center of the inner dielectric layer 20i and the W-direction edge of the inner dielectric layer 20i. In this state, grain growth is more likely to occur at the W-direction edge of the inner dielectric layer 20i than at the center of the inner dielectric layer 20i, potentially degrading high-temperature load reliability. On the other hand, if the molar ratio C / molar ratio B exceeds 0.922, it becomes difficult to form dense grains in the outer region WGo, and moisture resistance reliability decreases due to pore formation.

[0067] (Si content) The side margin portion WG contains Si, and it is preferable that the Si content of the outer region WGo is higher than the Si content of the inner region WGi.

[0068] In the outer region WGo, the Si content is preferably 1.1 mol% to 7.0 mol% per 100 mol of Ti, and in the inner region WGi, the Si content is preferably 1.0 mol% to 4.0 mol% per 100 mol of Ti, and the molar ratio E of Si to Ti in the outer region WGo and the molar ratio D of Si to Ti in the inner region WGi are preferably adjusted to satisfy the relationship 1.103 ≤ molar ratio E / molar ratio D ≤ 1.770.

[0069] In this way, by adjusting the Si content in the outer region WGo and the inner region WGi, it is possible to obtain high moisture resistance reliability.

[0070] The inner region WGi preferably contains ceramic grains and glass containing Si, with Dy contained between and within the ceramic grains, and Si contained between the ceramic grains. By including Dy and Si in the inner region WGi in this way, it is possible to obtain high humidity resistance reliability and high high temperature load reliability.

[0071] The inner region WGi preferably contains Dy near the surface of the ceramic grain. By including Dy in the inner region WGi in this way, it is possible to obtain higher high-temperature load reliability.

[0072] (Manufacturing Method) An example of the manufacturing method for the multilayer ceramic capacitor 1 described above will be explained. First, a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and conductive paste contain a binder and a solvent. Known materials can be used as the binder and solvent.

[0073] Next, an internal electrode pattern is formed on the dielectric sheet by printing a conductive paste onto the dielectric sheet, for example, in a predetermined pattern. Screen printing or gravure printing can be used as methods for forming the internal electrode pattern.

[0074] In mass production, a dielectric sheet with two internal electrode patterns as shown in Figure 5 can be prepared. The coated portions 30N to which conductive paste is applied are spaced apart in the length direction L, and ceramic paste is applied between adjacent coated portions 30N to form height adjustment portions 20N. The height adjustment portions 20N are applied to approximately the same thickness as the thickness of the conductive paste in the coated portions 30N, canceling out the steps on the dielectric sheet caused by the application of the conductive paste and making the surface of the dielectric sheet to which the conductive paste is applied smooth. As shown in Figure 5, the two internal electrode layer patterns are printed offset in the length direction L, and as will be described later, by alternately stacking the dielectric sheets of the two internal electrode patterns in the stacking direction T and cutting along the cutting lines x and y in the stacking direction T, an inner layer portion 100 can be formed.

[0075] The coated portion 30N to which conductive paste is applied forms the first internal electrode layer 31 and the second internal electrode layer 32 of the inner layer 100 in the laminated body 10 after firing, the height adjustment portion 20N forms the dielectric layer 20z of the inner layer 100, and the dielectric sheet forms the internal dielectric layer 20i of the inner layer 100.

[0076] To form the outer layer 200, a predetermined number of dielectric sheets for the second outer layer 202, which do not have the internal electrode pattern printed on them, are stacked. On top of that, dielectric sheets for the inner layer 100, which have two internal electrode patterns printed on them, are stacked alternately. Then, a predetermined number of dielectric sheets for the first outer layer 201, which do not have the internal electrode pattern printed on them, are stacked. This creates a laminated sheet.

[0077] Next, the laminated sheets are pressed in the lamination direction using means such as a hydrostatic press to produce a laminated block. Then, the laminated block is cut to a predetermined size in the lamination direction T along the cutting lines x and y shown in Figure 5 to cut out the laminated chip 10T.

[0078] As shown in Figure 6, the laminated chip 10T is formed in a substantially rectangular parallelepiped shape by alternately stacking multiple material sheets on the surface of a ceramic green sheet 120 for lamination, which will become the dielectric layer 20, with a conductive pattern 131 that will become the first internal electrode layer 31 printed on it and a conductive pattern 132 that will become the second internal electrode layer 32 printed on it.

[0079] On one of the pair of end faces 10Ta of the laminated chip 10T, a conductive pattern 131 is exposed, and a conductive pattern 132 is exposed on the other end face.

[0080] Furthermore, on the side surface 10Tp3 of the laminated chip 10T, all ends in the width direction W of the laminated conductive patterns 131 and 132 are aligned along the lamination direction T.

[0081] Similarly, on the side surface 10Tp4 of the laminated chip 10T, all ends in the width direction W of the laminated conductive patterns 131 and 132 are aligned along the lamination direction T.

[0082] Side covering portions SC are attached to the side surfaces 10Tp3 and 10Tp4 of the laminated chip 10T to form a first side margin portion WG1 and a second side margin portion WG2, respectively, so as to cover them.

[0083] The side covering portion SC is composed of an inner side covering portion SCi and an outer side covering portion SCo. The inner region WGi may include the inner side covering portion SCi, and the outer region WGo may include the outer side covering portion SCo.

[0084] The ceramic slurry for forming the side coating portion SC is prepared using a perovskite-type compound containing Ba and Ti as the dielectric ceramic material. The dielectric powder obtained from this dielectric ceramic material is then mixed with a binder resin, an organic solvent, a plasticizer, and a dispersant in predetermined proportions as additives.

[0085] In preparing the ceramic slurry for the inner side coating SCi, a compound containing a rare earth element, such as Dy, is mixed with the ceramic slurry and stirred. The compound containing the rare earth element is blended so that Dy is between 0.3 mol% and 7.0 mol% per 100 mol of Ti, and is prepared to have a predetermined relationship with the Dy content in the outer side coating SCo. Si can also be added to the ceramic slurry. The Si content is blended so that it is between 1.0 mol% and 4.0 mol% per 100 mol of Ti, and is prepared to have a predetermined relationship with the Si content in the outer side coating SCo.

[0086] By applying and drying the created ceramic slurry that will become the outer side coating SCi, a ceramic green sheet that will become the outer side coating SCi is obtained.

[0087] Similarly, in the preparation of the ceramic slurry for the outer side coating SCo, a compound containing a rare earth element, such as Dy, is mixed and stirred into the ceramic slurry. The compound containing the rare earth element is blended so that Dy is between 0.1 mol% and 6.5 mol% per 100 mol of Ti, and is prepared to have a predetermined relationship with the Dy content in the inner side coating SCi. Si can also be added to the ceramic slurry. The Si content is blended so that it is between 1.1 mol% and 7.0 mol% per 100 mol of Ti, and is prepared to have a predetermined relationship with the Si content in the inner side coating SCi.

[0088] A ceramic green sheet with an outer side coating (SCo) is obtained by applying a ceramic slurry, which forms the outer side coating (SCo), to the surface of a resin film and drying it.

[0089] As described above, a ceramic green sheet that will become the side covering portion SC is obtained. In this embodiment, the side covering portion SC is formed of two layers, with the inner region WGi being formed by the inner side covering portion SCi and the outer region WGo being formed by the outer side covering portion SCo. However, the sheet thickness ratio between the inner side covering portion SCi and the outer side covering portion SCo can be adjusted as appropriate. Depending on the sheet thickness ratio between the inner side covering portion SCi and the outer side covering portion SCo, the inner region WGi may be formed from the inner side covering portion SCi alone, or it may be formed from multiple sheets, such as the inner side covering portion SCi and the outer side covering portion SCo. Similarly, depending on the sheet thickness ratio between the inner side covering portion SCi and the outer side covering portion SCo, the outer region WGo may be formed from the outer side covering portion SCo alone, or it may be formed from multiple sheets, such as the inner side covering portion SCi and the outer side covering portion SCo.

[0090] Although the above describes a method for forming a ceramic green sheet that forms a two-layer side covering SC, it is possible to create a ceramic green sheet with three or more layers of side coverings by further overlapping the side coverings.

[0091] Next, the ceramic green sheet that will become the inner side coating SCi of the peeled side coating SC is placed facing the side 10Tp3 of the laminate chip 10T and punched out to attach the side coating SC. The same procedure is followed to attach the side coating SC to the side 10Tp4.

[0092] As a result of the above, an unfired laminated chip 10T with a side coating SC is formed, as shown in Figure 7. Next, this laminated chip 10T is fired to produce the laminate 10. The firing temperature depends on the dielectric and internal electrode materials, but is preferably between 900°C and 1400°C.

[0093] Next, the conductive paste for the base electrode layer 415 is applied to the first end face LS1 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. Similarly, the conductive paste for the base electrode layer 425 is applied to the second end face LS2 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. After that, the base electrode layers 415 and 425, which are fired layers, are formed by firing these conductive pastes. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0094] As described above, the base electrode layers 415 and 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and firing it, or the base electrode layers 415 and 425, which are thin films, may be formed by a thin film formation method such as sputtering or vapor deposition.

[0095] Subsequently, a plating layer 416 is formed on the surface of the base electrode layer 415 to form the first external electrode 41, and a plating layer 426 is formed on the surface of the base electrode layer 425 to form the second external electrode 42. Through these steps, the multilayer ceramic capacitor 1 described above is obtained.

[0096] (Evaluation Tests) The following evaluation tests were conducted to confirm the effects of the multilayer ceramic capacitor according to the present invention. Note that the present invention is not limited to these experimental examples.

[0097] (Test Method) Dimensions of the multilayer ceramic capacitor of the test specimen: L-direction dimension × W-direction dimension × T-direction dimension: 1.0 mm × 0.5 mm × 0.5 mm, side margin thickness: 18 μm

[0098] 1. Humidity Resistance Test 1) The test specimens were mounted on a circuit board and a humidity resistance test was conducted. The humidity resistance test was performed by applying 6.3V to the circuit board on which the test specimens were mounted for 500 hours at a humidity of 85% and a temperature of 85°C.

[0099] 2) The insulation resistance IR of the test samples from 1) was measured under a condition of 6.3V. Test samples in which IR (insulation resistance) × Cap (capacitance) was less than 10Ω·F were counted as having poor moisture resistance, and the defect rate for all test samples (n=72) was calculated.

[0100] 2. High-Temperature Load Reliability Test: Test samples were subjected to a voltage of 6.3V at 85°C, and those whose IR (insulation resistance) after 1000 hours fell below the standard IR × Cap (less than 10Ω·F) were counted as having high-temperature load reliability defects. The defect rate for all test samples (n=72) was then calculated.

[0101] 3. Measurement of Dy and Si Content 1) The WT surface was polished at the center of the length L, and Dy, Si, and Ti were detected by EDX (TEM). 2) The field of view used for detection of the inner region was defined as a region with a length of 0.4 μm in the stacking direction T and a length of 0.4 μm in the width direction W centered on a virtual line extending in the stacking direction T at a position 1 / 10 of the width W dimension of the side margin from the edge of the width direction W of the internal electrode layer. 3) Elemental concentrations were measured using the intensity of color in each region, and the content of Dy and Si was measured when the Ti content was set to 100, and the molar ratio of Dy and Si to Ti was calculated.

[0102] (Judgment Criteria) ◎: Both the failure rate for moisture resistance and the failure rate for high-temperature load reliability are 0. ○: The failure rate for moisture resistance is 0.04 or less, and the failure rate for high-temperature load reliability is 0.04 or less. ×: The failure rate for moisture resistance exceeds 0.04, and the failure rate for high-temperature load reliability exceeds 0.04. A judgment result of "◎" or "〇" was considered a pass.

[0103]

[0104] As shown in Table 1, good results were confirmed in terms of humidity resistance reliability and high-temperature load reliability in Experimental Examples 1 to 7. In particular, in Experimental Examples 2 to 7, where the molar ratio B of rare earth elements to Ti in the inner region and the molar ratio C of rare earth elements to Ti in the outer region were in the relationship 0.389 ≤ molar ratio C / molar ratio B ≤ 0.922, excellent humidity resistance reliability and high-temperature load reliability were confirmed.

[0105] In experimental examples 2 to 7, the molar ratio Ro of Si to Ti in the outer region WGo and the molar ratio Ri of Si to Ti in the inner region WGi are in a relationship of 1.103 ≤ molar ratio Ro / molar ratio Ri ≤ 1.770.

[0106] Although embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from the spirit of the invention.

[0107] 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 20i Internal dielectric layer 20o Dielectric layer 20z Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 Opposing portion 312 Lead-out portion 32 Second internal electrode layer 321 Opposing portion 322 Lead-out portion 40 External electrode 41 First external electrode 415 Base electrode layer 416 Plating layer 42 Second external electrode 425 Base electrode layer 426 Plating layer 100 Inner layer 200 Outer layer 201 First outer layer 202 Second outer layer L30 Electrode opposing portion LG1 First end margin portion LG2 Second end margin portion W30 Electrode opposing portion WG Side margin portion WGi Inner region WGo Outer region WG1 First side margin WG2 Second side margin L Length direction T Lamination direction W Width direction TS Main surface TS1 First main surface TS2 Second main surface WS Side surface WS1 First side surface WS2 Second side surface LS End surface LS1 First end surface LS2 Second end surface

Claims

1. A multilayer ceramic capacitor comprising: an inner layer in which an internal electrode layer and an internal dielectric layer are stacked, having two main surfaces opposite to each other in the stacking direction, two side surfaces opposite to each other in the width direction intersecting the stacking direction, and two end surfaces opposite to each other in the length direction intersecting the stacking direction and the width direction; and external electrodes disposed on each of the two end surfaces and connected to the internal electrode layer, wherein in the side margin portions located on both sides of the width direction of the inner layer and forming the side surfaces, the content of rare earth elements in the outer region located on the side surface side of the laminate is lower than the content of rare earth elements in the inner region located on the inner layer side of the laminate.

2. The multilayer ceramic capacitor according to claim 1, wherein the molar ratio A of the rare earth element to Ti at both ends in the width direction of the internal dielectric layer and the molar ratio B of the rare earth element to Ti in the inner region of the side margin are in a relationship of 0.9 ≤ molar ratio A / molar ratio B ≤ 1.

1.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the molar ratio B of the rare earth element to Ti in the inner region of the side margin and the molar ratio C of the rare earth element to Ti in the outer region of the side margin are in a relationship of 0.389 ≤ molar ratio C / molar ratio B ≤ 0.

922.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein the rare earth element is Dy.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein the inner region of the side margin portion comprises ceramic grains and glass containing Si, and contains Dy between and within the ceramic grains, and contains Si between the ceramic grains.

6. The multilayer ceramic capacitor according to claim 5, wherein the inner region of the side margin portion contains Dy near the surface of the ceramic grain.

7. The multilayer ceramic capacitor according to claim 1 or 2, wherein the side margin portion contains Si, and the Si content of the outer region of the side margin portion is higher than the Si content of the inner region of the side margin portion.

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