Gate drive circuit and display device

Abstract

The application provides a gate drive circuit and a display device. The gate drive circuit comprises a plurality of cascaded shift registers. Each shift register comprises a scan output end and a pull-down module. The scan output end is electrically connected to a scan signal line. The pull-down module is configured to transmit the voltage of a power supply node to the scan output end when the pull-down module is turned on. The power supply node in the shift register located in an odd row is electrically connected to a first detection signal line. The power supply node in the shift register located in an even row is electrically connected to a second detection signal line. When the gate drive circuit is in a driving state, the first detection signal line and the second detection signal line are used to transmit a first voltage to the corresponding scan signal line when the pull-down module is turned on. When the gate drive circuit is in a detection state, the pull-down module is turned on. The first detection signal line and the second detection signal line transmit a second voltage to the corresponding scan signal line. The second voltage is greater than the first voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate drive circuit and display device. BACKGROUND

[0002] In the related art, a plurality of scan lines are provided in a display panel, and the scan lines are used to provide scan signals. Due to the use of a DLS architecture, short circuit is prone to occur between two adjacent scan lines, and it is difficult to detect the short circuit after the short circuit occurs. SUMMARY

[0003] Embodiments of the present application provide a gate drive circuit and display device to solve the technical problem that it is difficult to detect short circuit between two adjacent scan lines.

[0004] To solve the above problems, the technical solutions provided by the present application are as follows:

[0005] In a first aspect, the embodiments of the present application provide a gate drive circuit, comprising a plurality of cascaded shift registers, each of the shift registers comprising a scan output end and a pull-down module, the scan output end being electrically connected to a scan signal line, and the pull-down module being configured to transmit a voltage of a power supply node to the scan output end when the pull-down module is turned on.

[0006] The power supply node in the shift register located in an odd-numbered row is electrically connected to a first detection signal line, and the power supply node in the shift register located in an even-numbered row is electrically connected to a second detection signal line.

[0007] When the gate drive circuit is in a driving state, the first detection signal line and the second detection signal line are used to transmit a first voltage to the corresponding scan signal line when the pull-down module is turned on; when the gate drive circuit is in a detection state, the pull-down module is turned on, and the first detection signal line and the second detection signal line transmit a second voltage to the corresponding scan signal line, the second voltage being greater than the first voltage, and if the resistance between the first detection signal line and the second detection signal line is detected to be lower than that in the driving state, it is determined that the gate drive circuit has a short circuit.

[0008] In an embodiment, the output end of each pull-down module is electrically connected to the scan output end, the control end of each pull-down module is electrically connected to the scan output end in the next stage shift register, and the input end of each pull-down module is electrically connected to the power supply node.

[0009] In an embodiment, the gate drive circuit further comprises a first clock signal line and a second clock signal line, and each shift register further comprises:

[0010] a pull-up module, an output end of the pull-up module being electrically connected to the scan output end;

[0011] an input end of the pull-up module in the shift register in the odd-numbered row being electrically connected to the first clock signal line, and an input end of the pull-up module in the shift register in the even-numbered row being electrically connected to the second clock signal line;

[0012] wherein, when the gate drive circuit is in the detection state, the first clock signal line and the second clock signal line are used to transmit a third voltage to the corresponding scan signal line when the pull-up module is turned on, the third voltage being greater than the first voltage.

[0013] In an embodiment, the shift register further comprises:

[0014] a pull-up control module, an output end of the pull-up control module being electrically connected to a control end of the pull-up module;

[0015] wherein, an input end of the pull-up control module and the control end of the pull-up control module in each shift register are electrically connected to the scan output end of the previous shift register.

[0016] In an embodiment, the shift register further comprises:

[0017] a pull-down control module, an output end of the pull-down control module being electrically connected to the control end of the pull-up module, an input end of the pull-down control module being electrically connected to the power supply node, and a control end of each pull-down control module being electrically connected to the scan output end in the next shift register.

[0018] In an embodiment, the pull-down module comprises a pull-down transistor, an output end of the pull-down transistor being electrically connected to the scan output end, and in a plurality of shift registers, an input end of the pull-down transistor in the shift register in the odd-numbered row being electrically connected to the first detection signal line, and an input end of the pull-down transistor in the shift register in the even-numbered row being electrically connected to the second detection signal line.

[0019] the pull-up module comprises a pull-up transistor, an output end of the pull-up transistor being electrically connected to the scan output end, and in a plurality of shift registers, an input end of the pull-up transistor in the shift register in the odd-numbered row being electrically connected to the first clock signal line, and an input end of the pull-up transistor in the shift register in the even-numbered row being electrically connected to the second clock signal line.

[0020] The pull-up control module comprises a pull-up control transistor, an output end of the pull-up control transistor is electrically connected to a control end of the pull-up transistor, and an input end of the pull-up control transistor in each shift register and the control end of the pull-up control transistor are electrically connected to the scan output end of the previous stage shift register.

[0021] The pull-down control module comprises a pull-down control transistor, an output end of the pull-down control transistor is electrically connected to the control end of the pull-up transistor, and an input end of the pull-down control transistor is electrically connected to the power supply node.

[0022] In each shift register, the control end of the pull-down transistor and the control end of the pull-down control transistor are electrically connected to the scan output end in the next stage shift register.

[0023] In an embodiment, the gate drive circuit further comprises a storage module for maintaining the voltage of the control end of the pull-up transistor, and the storage module comprises:

[0024] a first storage capacitor, one end of the first storage capacitor is electrically connected to the control end of the pull-up transistor, and the other end of the first storage capacitor is electrically connected to the input end of the pull-up transistor;

[0025] a second storage capacitor, one end of the second storage capacitor is electrically connected to the control end of the pull-up transistor, and the other end of the second storage capacitor is electrically connected to the scan output end.

[0026] In a third aspect, the embodiment of the present application further provides a gate drive circuit, comprising a plurality of cascaded shift registers, each of the shift registers comprising:

[0027] a scan output end, the scan output end in each shift register is electrically connected to a scan signal line;

[0028] a pull-down transistor, an output end of the pull-down transistor is electrically connected to the scan output end, and a control end of the pull-down transistor is electrically connected to the scan output end in the next stage shift register;

[0029] a pull-up transistor, an output end of the pull-up transistor is electrically connected to the scan output end;

[0030] a pull-up control transistor, an output end of the pull-up control transistor is electrically connected to a control end of the pull-up transistor, an input end of the pull-up control transistor in each shift register and the control end of the pull-up control transistor are electrically connected to the scan output end of the previous stage shift register;

[0031] A pull-down control transistor, wherein the output terminal of the pull-down control transistor is electrically connected to the control terminal of the pull-up transistor, the input terminal of the pull-down control transistor is electrically connected to the input terminal of the pull-down transistor, and the control terminal of the pull-down control transistor is electrically connected to the scan output terminal in the next stage shift register;

[0032] The input terminal of the pull-down transistor in the shift register located in the odd-numbered row is electrically connected to the first detection signal line, and the input terminal of the pull-down transistor in the shift register located in the even-numbered row is electrically connected to the second detection signal line.

[0033] The input of the pull-up transistor in the shift register located in the odd-numbered row is electrically connected to the first clock signal line, and the input of the pull-up transistor in the shift register located in the even-numbered row is electrically connected to the second clock signal line.

[0034] In one embodiment, the gate driving circuit further includes a first storage capacitor and a second storage capacitor. One end of the first storage capacitor is electrically connected to the control terminal of the pull-up transistor, and the other end of the first storage capacitor is electrically connected to the input terminal of the pull-up transistor. One end of the second storage capacitor is electrically connected to the control terminal of the pull-up transistor, and the other end of the second storage capacitor is electrically connected to the scan output terminal.

[0035] Thirdly, embodiments of the present invention also provide a display device, including the gate driving circuit as described in any of the preceding embodiments.

[0036] The beneficial effects of the present invention are as follows: by setting the first detection signal line and the second detection signal line, the pull-down modules in the shift registers of odd-numbered rows and even-numbered rows are respectively connected to the first detection signal line and the second detection signal line, so that during detection, the magnitude of the resistance between the first detection signal line and the second detection signal line can be detected to determine whether a short circuit has occurred between adjacent scan lines. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Appendix Figure 1 This is a schematic diagram of the module structure of a shift register in a gate driving circuit according to an embodiment of the present invention;

[0039] Appendix Figure 2A circuit structure schematic diagram of a shift register of a gate drive circuit according to an embodiment of the present application;

[0040] The application further provides a gate drive circuit. Figure 3 A circuit structure schematic diagram of a gate drive circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0042] Embodiments of the present application provide a gate drive circuit to solve the technical problem that it is difficult to detect short circuit of adjacent two scan lines.

[0043] As shown in FIG. 1, a gate drive circuit is used to provide a scan signal for a display panel. The gate drive circuit comprises a first detection signal line VSS, a second detection signal line VSS', and a plurality of cascaded shift registers. Each shift register is electrically connected to a scan signal line to output the scan signal to the scan signal line. The first detection signal line VSS and the second detection signal line VSS' have a first voltage and a second voltage, and the second voltage is greater than the first voltage. Figure 1 The shift register comprises a scan output end G and a pull-down module 10. The scan output end G is electrically connected to the scan signal line, and the pull-down module 10 is electrically connected to the scan output end G and a power supply node N respectively. When the pull-down module 10 is turned on, the pull-down module 10 transmits the voltage of the power supply node N to the scan output end G.

[0044] The plurality of shift registers are arranged in multiple rows. The power supply node N in the shift register in an odd-numbered row is electrically connected to the first detection signal line VSS, and the power supply node N in the shift register in an even-numbered row is electrically connected to the second detection signal line VSS'.

[0045] The output end of each pull-down module 10 is electrically connected to the scan output end G, the control end of each pull-down module 10 is electrically connected to the scan output end G in the next stage shift register, and the input end of each pull-down module 10 is electrically connected to the power supply node N.

[0046]

[0047] ​When the gate drive circuit is in the driving state, the first detection signal line VSS and the second detection signal line VSS' have the first voltage. After the pull-down module 10 is turned on, it transmits the first voltage to the scan signal line of the corresponding row. It can be understood that when the gate drive circuit is in the driving state, in order to turn off the multiple shift registers one after another, in two adjacent shift registers, the first voltage output by the pull-down module 10 of the next shift register will turn off the pull-down module 10 of the previous shift register. That is, the first voltage is the voltage that turns off the pull-down module 10.

[0048] When the gate drive circuit is in the detection state, the first detection signal line VSS and the second detection signal line VSS' have the second voltage that turns on the pull-down module 10. The pull-down module 10 is in the on state and transmits the second voltage to the scan signal line of the corresponding row. It is understood that since the input terminal of the pull-down module 10 is electrically connected to the corresponding detection signal line, and the output terminal of the pull-down module 10 is electrically connected to the corresponding scan signal line through the scan output terminal G, when adjacent scan lines are short-circuited, the first detection signal line VSS and the second detection signal line VSS' will be electrically connected, and the resistance between the first detection signal line VSS and the second detection signal line VSS' will decrease significantly compared to the driving state. Therefore, by detecting the resistance between the first detection signal line VSS and the second detection signal line VSS', it can be determined whether a scan line is short-circuited.

[0049] In this embodiment, by setting the first detection signal line VSS and the second detection signal line VSS', the pull-down module 10 in the shift register of the odd row and the even row is connected to the first detection signal line VSS and the second detection signal line VSS' respectively. This allows the detection to determine whether a short circuit has occurred between adjacent scan lines by detecting the resistance between the first detection signal line VSS and the second detection signal line VSS'.

[0050] like Figure 2 , Figure 3 As shown, in one embodiment, the gate drive circuit further includes a first clock signal line XCK and a second clock signal line CK. Each shift register also includes a pull-up module 20, the output of which is electrically connected to the scan output terminal G.

[0051] The input end of the pull-up module 20 in the shift register in the odd-numbered row is electrically connected to the first clock signal line XCK, and the input end of the pull-up module 20 in the shift register in the even-numbered row is electrically connected to the second clock signal line CK.

[0052] When the gate drive circuit is in the driving state, the first clock signal line XCK and the second clock signal line CK provide a scanning voltage for the display of the display panel, and when the gate drive circuit is in the detection state, the first clock signal line XCK and the second clock signal line CK are used to provide a third voltage, the pull-up module 20 is turned on, and the third voltage is transmitted to the corresponding scanning signal line. In order to make the pull-down module 10 and the pull-up module 20 in all shift registers open during detection, the third voltage is a voltage that makes the pull-up module 20 and the pull-down module 10 open. In some embodiments, the second voltage is equal to the third voltage, and both are greater than the first voltage.

[0053] In some embodiments, the shift register further comprises a pull-up control module 30, and the output end of the pull-up control module 30 is electrically connected to the control end of the pull-up module 20. The input end of the pull-up control module 30 in each shift register and the control end of the pull-up control module 30 are electrically connected to the scanning output end G of the upper-level shift register, so as to be opened under the action of the signal output by the scanning output end G of the upper-level shift register, thereby enabling the multiple shift registers to open level by level.

[0054] In some embodiments, the shift register further comprises a pull-down control module 40, and the output end of the pull-down control module 40 is electrically connected to the control end of the pull-up module 20, and the input end of the pull-down control module 40 is electrically connected to the power supply node N. The control end of each pull-down control module 40 is electrically connected to the scanning output end G in the next-level shift register, so as to be opened under the signal output by the scanning output end G of the next-level shift register, thereby outputting the signal of the power supply node N to the scanning output end G of the current-level shift register.

[0055] Now, a specific circuit of the gate drive circuit in the above-mentioned embodiment is described. In the present embodiment, the gate drive circuit comprises a plurality of cascaded shift registers, and each shift register comprises a pull-down module 10, a pull-up module 20, a pull-up control module 30, a pull-down control module 40, a first detection signal line VSS, a second detection signal line VSS', a first clock signal line XCK, and a second clock signal line CK.

[0056] The first detection signal line VSS and the second detection signal line VSS' have a first voltage when the gate drive circuit normally drives the display panel, and have a second voltage when detection is performed, the second voltage being greater than the first voltage.

[0057] The first clock signal line XCK and the second clock signal line CK provide a scanning voltage for display of the display panel when the gate drive circuit is in the driving state, and are used to provide a third voltage when the gate drive circuit is in the detection state, the third voltage being a voltage for opening the pull-up module 20 and the pull-down module 10.

[0058] The pull-down module 10 includes a pull-down transistor T31, the pull-up module 20 includes a pull-up transistor T21, the pull-up control module 30 includes a pull-up control transistor T11, and the pull-down control module 40 includes a pull-down control transistor T41.

[0059] The plurality of cascaded shift registers are arranged in a plurality of rows, and each row of the shift registers is electrically connected to a scanning signal line through a scanning output end G. An output end of the pull-down transistor T31 is electrically connected to the scanning output end G, and in the plurality of shift registers, an input end of the pull-down transistor T31 in the shift register in an odd-numbered row is electrically connected to a first detection signal line VSS, and an input end of the pull-down transistor T31 in the shift register in an even-numbered row is electrically connected to a second detection signal line VSS'.

[0060] An output end of the pull-up transistor T21 is electrically connected to the scanning output end G, and in the plurality of shift registers, an input end of the pull-up transistor T21 in the shift register in an odd-numbered row is electrically connected to the first clock signal line XCK, and an input end of the pull-up transistor T21 in the shift register in an even-numbered row is electrically connected to the second clock signal line CK.

[0061] An output end of the pull-up control transistor T11 is electrically connected to a control end of the pull-up transistor T21, and an input end of the pull-up control transistor T11 and the control end of the pull-up control transistor T11 in each shift register are electrically connected to the scanning output end G of a previous stage shift register.

[0062] An output terminal of the pull-down control transistor T41 is electrically connected to the control terminal of the pull-up transistor T21, and an input terminal of the pull-down control transistor T41 is electrically connected to the power supply node N. In each of the shift registers, the control terminal of the pull-down transistor T31 and the control terminal of the pull-down control transistor T41 are electrically connected to the scan output terminal G in the next stage of the shift register.

[0063] During detection, the first detection signal line VSS and the second detection signal line VSS' have the second voltage, and the first clock signal line XCK and the second clock signal line CK have the third voltage. The second voltage and the third voltage are voltages that turn on the pull-up transistor T21, the pull-up control transistor T11, the pull-down transistor T31, and the pull-down control transistor T41. Since the input terminal of the pull-down transistor T31 is electrically connected to the corresponding detection signal line, and the output terminal of the pull-down transistor T31 is electrically connected to the corresponding scan signal line through the scan output terminal G, when the adjacent scan lines are short-circuited, the first detection signal line VSS and the second detection signal line VSS' will be electrically connected, and the resistance between the first detection signal line VSS and the second detection signal line VSS' will be greatly reduced. Thus, whether the scan lines are short-circuited can be determined by detecting the resistance between the first detection signal line VSS and the second detection signal line VSS'.

[0064] In some embodiments, the pull-down transistor T31, the pull-up transistor T21, the pull-up control transistor T11, and the pull-down control transistor T41 are all N-type transistors, and the second voltage and the third voltage are high levels.

[0065] In some embodiments, the gate drive circuit further includes a storage module 50 for maintaining the voltage of the control terminal of the pull-up transistor T21. The storage module 50 includes a first storage capacitor Cgs and a second storage capacitor Cgd. One end of the first storage capacitor Cgs is electrically connected to the control terminal of the pull-up transistor T21, and the other end of the first storage capacitor Cgs is electrically connected to the input terminal of the pull-up transistor T21. One end of the second storage capacitor Cgd is electrically connected to the control terminal of the pull-up transistor T21, and the other end of the second storage capacitor Cgd is electrically connected to the scan output terminal G. It can be understood that when the control terminal of the pull-up transistor T21 receives a voltage signal, the first storage capacitor Cgs and the second storage capacitor Cgd will be charged to store the voltage of the control terminal of the pull-up transistor T21.

[0066] The embodiment of the present application further provides a display device. The display device comprises a display panel and the gate drive circuit according to any one of the above embodiments, and the gate drive circuit is used for providing a driving signal for the display panel.

[0067] In summary, although the present application has been disclosed with the preferred embodiments as above, the above preferred embodiments are not used to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application is defined by the scope of the claims.

Claims

1. A gate drive circuit characterized by comprising: The gate drive circuit comprises a first detection signal line, a second detection signal line, a first clock signal line, a second clock signal line and a plurality of cascaded shift registers, each of the shift registers comprises a scan output end, a pull-up control module, a pull-up module and a pull-down module, the scan output end is electrically connected to a scan signal line, and the pull-down module is configured to transmit a voltage of a power supply node to the scan output end when the pull-down module is turned on. The power supply node in the shift register located in an odd-numbered row is electrically connected to the first detection signal line, and the power supply node in the shift register located in an even-numbered row is electrically connected to the second detection signal line. An output end of each of the pull-down modules is electrically connected to the scan output end, a control end of each of the pull-down modules is electrically connected to the scan output end in a next-stage shift register, and an input end of each of the pull-down modules is electrically connected to the power supply node. An output end of the pull-up module is electrically connected to the scan output end, an input end of the pull-up module in the shift register located in the odd-numbered row is electrically connected to the first clock signal line, and an input end of the pull-up module in the shift register located in the even-numbered row is electrically connected to the second clock signal line. An output end of the pull-up control module is electrically connected to a control end of the pull-up module, an input end of the pull-up control module in each of the shift registers and the control end of the pull-up control module are electrically connected to the scan output end of a previous-stage shift register. When the gate drive circuit is in a driving state, the first detection signal line and the second detection signal line are used to transmit a first voltage to the corresponding scan signal line when the pull-down module is turned on. When the gate drive circuit is in a detection state, the pull-down module is turned on, the first detection signal line and the second detection signal line transmit a second voltage to the corresponding scan signal line, the second voltage is greater than the first voltage, and if it is detected that the resistance between the first detection signal line and the second detection signal line is reduced compared with that in the driving state, it is determined that a short circuit occurs in the gate drive circuit. When the gate drive circuit is in the detection state, the first clock signal line and the second clock signal line are used to transmit a third voltage to the corresponding scan signal line when the pull-up module is turned on, and the third voltage is greater than the first voltage.

2. The gate drive circuit according to claim 1, characterized by The shift register further comprises: a pull-down control module, an output end of the pull-down control module is electrically connected to a control end of the pull-up module, an input end of the pull-down control module is electrically connected to the power supply node, and a control end of each of the pull-down control modules is electrically connected to the scan output end in a next-stage shift register.

3. The gate drive circuit according to claim 2, characterized in that: The pull-down module comprises a pull-down transistor, an output end of the pull-down transistor is electrically connected to the scan output end, in a plurality of the shift registers, an input end of the pull-down transistor in the shift register located in an odd row is electrically connected to the first detection signal line, and an input end of the pull-down transistor in the shift register located in an even row is electrically connected to the second detection signal line; The pull-up module comprises a pull-up transistor, an output end of the pull-up transistor is electrically connected to the scan output end, in a plurality of the shift registers, an input end of the pull-up transistor in the shift register located in an odd row is electrically connected to the first clock signal line, and an input end of the pull-up transistor in the shift register located in an even row is electrically connected to the second clock signal line; The pull-up control module comprises a pull-up control transistor, an output end of the pull-up control transistor is electrically connected to a control end of the pull-up transistor, and an input end and the control end of the pull-up control transistor in each shift register are electrically connected to the scan output end of a previous stage shift register; The pull-down control module comprises a pull-down control transistor, an output end of the pull-down control transistor is electrically connected to the control end of the pull-up transistor, and an input end of the pull-down control transistor is electrically connected to the power supply node; In each shift register, the control end of the pull-down transistor and the control end of the pull-down control transistor are electrically connected to the scan output end in a next stage shift register.

4. The gate drive circuit according to claim 3, characterized by The gate drive circuit further comprises a storage module for maintaining the voltage of the control end of the pull-up transistor, and the storage module comprises: A first storage capacitor, one end of the first storage capacitor is electrically connected to the control end of the pull-up transistor, and the other end of the first storage capacitor is electrically connected to the input end of the pull-up transistor; A second storage capacitor, one end of the second storage capacitor is electrically connected to the control end of the pull-up transistor, and the other end of the second storage capacitor is electrically connected to the scan output end.

5. A gate drive circuit characterized by comprising: The gate drive circuit further comprises a storage module for maintaining the voltage of the control end of the pull-up transistor, and the storage module comprises: A first storage capacitor, one end of the first storage capacitor is electrically connected to the control end of the pull-up transistor, and the other end of the first storage capacitor is electrically connected to the input end of the pull-up transistor; A second storage capacitor, one end of the second storage capacitor is electrically connected to the control end of the pull-up transistor, and the other end of the second storage capacitor is electrically connected to the scan output end. The gate drive circuit further comprises a storage module for maintaining the voltage of the control end of the pull-up transistor, and the storage module comprises: A first storage capacitor, one end of the first storage capacitor is electrically connected to the control end of the pull-up transistor, and the other end of the first storage capacitor is electrically connected to the input end of the pull-up transistor; A second storage capacitor, one end of the second storage capacitor is electrically connected to the control end of the pull-up transistor, and the other end of the second storage capacitor is electrically connected to the scan output end. a pull-down control transistor, an output end of the pull-down control transistor being electrically connected to a control end of the pull-up transistor, an input end of the pull-down control transistor being electrically connected to an input end of the pull-down transistor, and a control end of the pull-down control transistor being electrically connected to the scan output end in the next stage of the shift register; wherein the input end of the pull-down transistor in the shift register in the odd-numbered row is electrically connected to the first detection signal line, and the input end of the pull-down transistor in the shift register in the even-numbered row is electrically connected to the second detection signal line; the input end of the pull-up transistor in the shift register in the odd-numbered row is electrically connected to the first clock signal line, and the input end of the pull-up transistor in the shift register in the even-numbered row is electrically connected to the second clock signal line; when the gate drive circuit is in a driving state, the first detection signal line and the second detection signal line are used to transmit a first voltage to the corresponding scan signal line when the pull-down transistor is turned on; when the gate drive circuit is in a detection state, the pull-down transistor is turned on, the first detection signal line and the second detection signal line transmit a second voltage to the corresponding scan signal line, the second voltage is greater than the first voltage, and if it is detected that the resistance between the first detection signal line and the second detection signal line is reduced compared with the driving state, it is determined that the gate drive circuit has a short circuit; when the gate drive circuit is in the detection state, the first clock signal line and the second clock signal line are used to transmit a third voltage to the corresponding scan signal line when the pull-up transistor is turned on, the third voltage being greater than the first voltage.

6. The gate drive circuit according to claim 5, characterized in that The gate drive circuit further comprises a first storage capacitor and a second storage capacitor, one end of the first storage capacitor being electrically connected to the control end of the pull-up transistor, the other end of the first storage capacitor being electrically connected to the input end of the pull-up transistor, one end of the second storage capacitor being electrically connected to the control end of the pull-up transistor, and the other end of the second storage capacitor being electrically connected to the scan output end.

7. A display device, characterized by comprising: The gate drive circuit comprises any one of claims 1-6.

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