Pixel compensation circuit, pixel compensation method and display panel

Abstract

The application provides a pixel compensation circuit, a pixel compensation method and a display panel, and relates to the technical field of display. The application solves the problem that the current pixel compensation circuit needs multiple array substrate row driving circuits, which is not conducive to product narrow frame design. The pixel compensation circuit comprises a compensation transistor, a driving transistor, a reset transistor, a first switch transistor and a second switch transistor, a first capacitor, a second capacitor and a light emitting device. Compared with the current pixel compensation circuit, the application does not need to use multiple array substrate row driving circuits to realize the compensation function. The scanning signal line used in the application is less, which is conducive to the narrow frame design of the display product.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel compensation circuit, a pixel compensation method, and a display panel. Background Technology

[0002] Unlike liquid crystals, which are voltage-driven, organic light-emitting diodes (OLEDs) and micro / mini light-emitting diodes (Micro / MiniLEDs) are current-driven devices. The current during the display stage is determined by the driving transistor: Ipixel = K(VGS - Vth). 2 In this formula, the coefficient k is related to the mobility and the size of the thin-film transistor (TFT), VGS is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. It can be seen from the formula that if there are differences in the threshold voltage of the driving transistor, especially in the low grayscale range (when VGS is small), the pixel current will be different, ultimately leading to differences in brightness.

[0003] To compensate for differences in the threshold voltage of driving transistors, various compensation methods have emerged. Currently, the mainstream compensation methods are external compensation and internal compensation. External compensation offers a wide range of threshold voltage compensation for driving transistors, but the driving system is complex and costly. Internal compensation offers a relatively simple driving system and low cost, but its threshold voltage compensation range for driving transistors is limited, thus requiring high stability from the driving transistors.

[0004] Internally compensated pixel circuits (nTnC) are generally more complex than externally compensated pixel circuits (3T1C), thus requiring more horizontal scanning signals and multiple array substrate row driver (Gate Driver On Array, GOA) circuits, which increases the product bezel width and is detrimental to the product's appearance. Summary of the Invention

[0005] This application provides a pixel compensation circuit, pixel compensation method, and display panel that can compensate driving transistors and uses fewer scan signal lines compared to current pixel compensation circuits, making it easier to display products with narrow bezels.

[0006] On one hand, this application provides a pixel compensation circuit, including a compensation transistor, a driving transistor, a reset transistor, a first switching transistor and a second switching transistor, a first capacitor, a second capacitor, and a light-emitting device;

[0007] The gate of the compensation transistor is electrically connected to the current stage scan signal line, the source of the compensation transistor is electrically connected to the first node, and the drain of the compensation transistor is electrically connected to the data line. The current stage scan signal line is used to provide a scan signal, and the data line is used to provide a data signal.

[0008] The gate of the driving transistor is electrically connected to the first node, the source of the driving transistor is electrically connected to the drain of the first switching transistor, the drain of the driving transistor is electrically connected to the positive terminal of the light-emitting device, and the negative terminal of the light-emitting device is electrically connected to the negative terminal of the power supply.

[0009] The gate of the reset transistor is electrically connected to the compensation control line, the source of the reset transistor is electrically connected to the first node, and the drain of the reset transistor is electrically connected to the second voltage terminal.

[0010] The gate of the first switching transistor is electrically connected to the control signal line, the source of the first switching transistor is electrically connected to the positive terminal of the power supply, and the drain of the first switching transistor is electrically connected to the source of the driving transistor.

[0011] The gate of the second switching transistor is electrically connected to the reset signal line, the source of the second switching transistor is electrically connected to the first voltage terminal, and the drain of the second switching transistor is electrically connected to the connection point between the drain of the driving transistor and the positive terminal of the light-emitting device, forming a second node at the connection point.

[0012] One end of the first capacitor is electrically connected to the positive terminal of the power supply, and the other end of the first capacitor is electrically connected to the second node;

[0013] One end of the second capacitor is electrically connected to the first node, and the other end of the second capacitor is electrically connected to the second node.

[0014] In one possible implementation of this application, the current-level scan signal line, the compensation control line, the reset signal line, and the control signal line are combined to correspond sequentially to the reset stage, the detection stage, the data writing stage, and the light emission stage.

[0015] In one possible implementation of this application, during the reset phase, both the control signal line and the current stage scan signal line are at a low level, while both the compensation control line and the reset signal line are at a high level.

[0016] In one possible implementation of this application, during the reset phase, both the reset transistor and the second switching transistor are in the ON state, while both the compensation transistor and the first switching transistor are in the OFF state.

[0017] In one possible implementation of this application, during the detection phase, both the control signal line and the compensation control line are at a high level, while both the reset signal line and the current stage scan signal line are at a low level.

[0018] In one possible implementation of this application, during the detection phase, both the first switching transistor and the reset transistor are in the ON state, while both the second switching transistor and the compensation transistor are in the OFF state.

[0019] In one possible implementation of this application, during the data writing phase, the control signal line, the reset signal line, and the compensation control line are all at a low level, while the current level scan signal line changes to a high level line by line.

[0020] In one possible implementation of this application, during the data writing phase, the compensation transistor is in the on state, while the reset transistor, the first switching transistor, and the second switching transistor are all in the off state.

[0021] In one possible implementation of this application, during the light emission stage, the control signal line is at a high level, while the compensation control line, the reset signal line, and the current stage scan signal line are all at a low level.

[0022] In one possible implementation of this application, during the light-emitting stage, the first switching transistor is in the on state, while the reset transistor, the second switching transistor, and the compensation transistor are all in the off state.

[0023] On the other hand, this application provides a pixel driving method, the method comprising:

[0024] Provide the pixel compensation circuit as described in claim 1;

[0025] Upon entering the reset phase, both the control signal line and the current stage scan signal line provide a low level, while both the compensation control line and the reset signal line provide a high level. The reset transistor and the second switching transistor are both in the on state, while the compensation transistor and the first switching transistor are both in the off state. The potential reset of the first node is the second voltage provided by the second voltage terminal, and the potential reset of the second node is the first voltage provided by the first voltage terminal.

[0026] Upon entering the detection phase, both the control signal line and the compensation control line are provided with a high level, while both the reset signal line and the current stage scan signal line are provided with a low level. The first switching transistor and the reset transistor are both in the on state, while the second switching transistor and the compensation transistor are both in the off state. The voltage change of the second node is the third voltage V3, where V3 = V2 - Vth, and V2 is the second voltage V2, and Vth is the threshold voltage of the driving transistor.

[0027] Upon entering the data writing stage, the control signal line, reset signal line, and compensation control line all provide a low level. The current stage scan signal line changes to a high level line by line, the compensation transistor is in the on state, and the reset transistor, the first switching transistor, and the second switching transistor are all in the off state. The first node writes the data signal, and the voltage change of the second node is the fourth voltage V4, which is V3 + (Data - V2) * [Cst / (Cst + C1)] = V2 - Vth + (Data - V2) * [Cst / (Cst + C1)], where Data is the data signal input by the data line Vdata.

[0028] Upon entering the light-emitting stage, the control signal line provides a high level, while the compensation control line, reset signal line, and current stage scan signal line all provide a low level. The first switching transistor and the driving transistor are in the on state, while the reset transistor, the second switching transistor, and the compensation transistor are all in the off state. The source-drain voltage of the driving transistor is T2_Vgs = (Data-V2)*[Cst / (Cst+C1)]+Vth, and the light-emitting device emits light.

[0029] On the other hand, this application also provides a display panel, which includes the pixel compensation circuit as described or employs the pixel compensation method as described.

[0030] The pixel compensation circuit proposed in this application includes a compensation transistor, a driving transistor, a reset transistor, a first switching transistor and a second switching transistor, a first capacitor, a second capacitor, and a light-emitting device. By combining control signal lines, compensation control lines, reset signal lines, current stage scan signal lines, and a set timing control method, the threshold voltage in the driving transistor can be compensated. Compared with the current pixel compensation circuit, this application does not require a multi-channel array substrate row driving circuit to achieve the compensation function. The number of scan signal lines used in this application is less, which is conducive to the narrow bezel design of display products. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0033] Figure 2 This is a timing diagram of a pixel compensation circuit provided in an embodiment of this application;

[0034] Figure 3This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0035] Figure 4 This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0036] Figure 5 This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0037] Figure 6 This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0038] Figure 7 This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0039] Figure 8 This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0040] Figure 9 This is a circuit diagram of a pixel compensation circuit provided in an embodiment of this application;

[0041] Figure 10 This is a timing diagram of a pixel compensation circuit provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0044] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0045] This application provides a pixel compensation circuit, a pixel compensation method, and a display panel, which will be described in detail below.

[0046] like Figure 1 As shown in the schematic diagram, this embodiment of the pixel compensation circuit includes a compensation transistor T1, a driving transistor T2, a reset transistor T3, a first switching transistor T4 and a second switching transistor T5, a first capacitor Cs, a second capacitor Cst, and a light-emitting device LED. The compensation transistor T1 is used to compensate for the threshold voltage in the driving transistor T2, the driving transistor T2 is used to drive the LED to emit light, the reset transistor T3 is used to control the reset of the pixel compensation circuit, the first switching transistor T4 is used to control the LED to emit light, and the second switching transistor T5 is used to control the writing of data signals into the pixel compensation circuit.

[0047] The gate of the compensation transistor T1 is electrically connected to the current stage scan signal line SPAM(n), the source of the compensation transistor T1 is electrically connected to the first node G, and the drain of the compensation transistor T1 is electrically connected to the data line Vdata. The current stage scan signal line SPAM is used to provide the scan signal, and the data line Vdata is used to provide the data signal.

[0048] Among them, the current level scan signal line SPAM(n) represents the row scan signal of the nth row of pixel units output by the Gate side of the driving circuit, and the previous level scan signal SPAM(n-1) represents the row scan signal of the (n-1)th row of pixel units output by the Gate side of the driving circuit.

[0049] The gate of the driving transistor T2 is electrically connected to the first node G, the source of the driving transistor T2 is electrically connected to the drain of the first switching transistor T4, the drain of the driving transistor T2 is electrically connected to the positive terminal of the light-emitting device LED, and the negative terminal of the light-emitting device LED is electrically connected to the negative terminal of the power supply VSS.

[0050] The gate of the reset transistor T3 is electrically connected to the compensation control line Comp(n), the source of the reset transistor T3 is electrically connected to the first node G, and the drain of the reset transistor T3 is electrically connected to the second voltage terminal V2.

[0051] The gate of the first switching transistor T4 is electrically connected to the control signal line EM, the source of the first switching transistor T4 is electrically connected to the positive power supply VDD, and the drain of the first switching transistor T4 is electrically connected to the source of the driving transistor T2.

[0052] The gate of the second switching transistor T5 is electrically connected to the reset signal line Res, the source of the second switching transistor T5 is electrically connected to the first voltage terminal V1, and the drain of the second switching transistor T5 is electrically connected to the connection point between the drain of the driving transistor T2 and the positive terminal of the light-emitting device LED, forming a second node S at the connection point.

[0053] One end of the first capacitor Cs is electrically connected to the positive terminal VDD of the power supply, and the other end of the first capacitor Cs is electrically connected to the second node S.

[0054] One end of the second capacitor Cst is electrically connected to the first node G, and the other end of the second capacitor Cst is electrically connected to the second node S.

[0055] In this embodiment, the compensation transistor T1, driving transistor T2, reset transistor T3, first switching transistor T4, and second switching transistor T5 can all be N-channel thin film transistors (TFTs), N-channel amorphous silicon transistors (a-Si), N-channel low-temperature polysilicon transistors (N-LTPS), or N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), or P-channel thin film transistors, P-channel low-temperature polysilicon transistors (P-LTPS), P-channel metal-oxide-semiconductor field-effect transistors, etc. This embodiment does not impose specific limitations on these.

[0056] In this embodiment, the driving transistor T2 serves as the driving transistor in the pixel compensation circuit for driving the LED light-emitting device. The pixel compensation circuit proposed in this application can compensate for the threshold voltage of the driving transistor (i.e., driving transistor T2). In this embodiment, the current stage scan signal line SPAM(n), compensation control line Comp(n), reset signal line Res, and control signal line EM are all controlled by an external timing controller.

[0057] In the pixel compensation circuit of this application, such as Figure 2 As shown, the current stage scan signal line SPAM(n), compensation control line Comp(n), reset signal line Res, and control signal line EM are combined to correspond to the reset stage, detection stage, data writing stage, and light emission stage, respectively.

[0058] The following section provides a detailed analysis of the potential changes during the reset, detection, data writing, and light emission phases, as well as how to compensate for the threshold voltage of the driving transistor.

[0059] During the reset phase, the control signal line EM and the current stage scan signal line SPAM(n) are both low, while the compensation control line Comp(n) and the reset signal line Res are both high.

[0060] At this stage, such as Figure 3 As shown, reset transistor T3 and second switching transistor T5 are both in the on state, while compensation transistor T1 and first switching transistor T4 are both in the off state.

[0061] At this time, the potential reset of the first node G is the second voltage V2 provided by the second voltage terminal V2, and the potential reset of the second node S is the first voltage V1 provided by the first voltage terminal V1. Since the first switching transistor T4 and the driving transistor T2 are both in the off state, the light-emitting device LED does not emit light at this time.

[0062] During the detection phase, the control signal line EM and the compensation control line Comp(n) are both at a high level, while the reset signal line Res and the current stage scan signal line SPAM(n) are both at a low level.

[0063] At this stage, such as Figure 4 As shown, the first switching transistor T4 and the reset transistor T3 are both in the on state, while the second switching transistor T5 and the compensation transistor T1 are both in the off state.

[0064] At this time, the positive voltage VDD of the power supply begins to discharge until the gate-source voltage of the driving transistor T2 changes to the threshold voltage Vth of the driving transistor T2. The driving transistor T2 is then turned off. At this time, the voltage change of the second node S is the third voltage V3. The third voltage V3 = V2 - Vth, which contains the threshold voltage Vth information of the driving transistor T2. Since the driving transistor T2 is in the off state, the light-emitting device LED does not emit light.

[0065] During the data writing phase, the control signal line EM, the reset signal line Res, and the compensation control line Comp(n) are all at low level, while the current stage scan signal line SPAM(n) changes to high level line by line.

[0066] At this stage, such as Figure 5 As shown, the compensation transistor T1 corresponding to the current stage scan signal line SPAM(n) is in the on state, while the reset transistor T3, the first switching transistor T4, and the second switching transistor T5 are all in the off state.

[0067] At this time, the first node G writes the data signal Vdata. Since the voltage change of the second node S during the detection phase is V3, the data signal Vdata is coupled to the second node S through the first capacitor Cs. The voltage change of the second node S is the fourth voltage V4. The fourth voltage V4 = V3 + (Data - V2) * [Cst / (Cst + C1)] = V2 - Vth + (Data - V2) * [Cst / (Cst + C1)]. Therefore, the source-drain voltage T2_Vgs of the driving transistor T2 at this time is (Data - V2) * [Cst / (Cst + C1)] + Vth. That is, the voltage of the second node S at this moment contains the threshold voltage Vth information of the driving transistor T2. Since the driving transistor T2 and the third switching transistor T4 are still in the off state, the light-emitting device LED does not emit light.

[0068] During the light emission stage, the control signal line EM is at a high level, while the compensation control line Comp(n), the reset signal line Res, and the current stage scan signal line SPAM(n) are all at a low level.

[0069] At this stage, such as Figure 6 As shown, the first switching transistor T4 is in the on state, while the reset transistor T3, the second switching transistor T5, and the compensation transistor T1 are all in the off state.

[0070] At this time, both the first switching transistor T4 and the driving transistor T2 are turned on. Since the source-drain voltage T2_Vgs of the driving transistor T2 is (Data-V2)*[Cst / (Cst+C1)]+Vth during the data writing stage, which includes the threshold voltage Vth of the driving transistor T2, the current flowing through the light-emitting device LED is independent of the threshold voltage Vth according to the TFT saturation current formula, thus compensating for the threshold voltage of the driving transistor. At the same time, the light-emitting device LED emits light.

[0071] The pixel compensation circuit described above can maintain the current change within 5% of the threshold voltage Vth offset ΔVth within the range of -mV to +nV.

[0072] In summary, the pixel compensation circuit proposed in this application, using a set of GOA structures and simple timing control, can compensate the threshold voltage in the driving transistor (i.e., driving transistor T2 in this application), thereby improving the uniformity and accuracy of the light emission of the LED. Furthermore, compared with current pixel compensation circuits, this application uses fewer scanning signal lines, which is conducive to narrow bezels in display products.

[0073] In another embodiment of this application, a pixel compensation circuit is also provided, such as Figure 7 As shown, the pixel compensation circuit proposed in this embodiment is... Figure 1 Based on the pixel compensation circuit, the position of the first capacitor Cs is replaced between the second node S and the negative power supply VSS. That is, in this embodiment, one end of the first capacitor Cs is electrically connected to the second node S, and the other end of the first capacitor Cs is electrically connected to the negative power supply VSS.

[0074] In this embodiment, the pixel compensation circuit employs the same reset phase, detection phase, data writing phase, and light emission phase as described above to compensate for the threshold voltage of the driving transistor T2.

[0075] In another embodiment of this application, a pixel compensation circuit is also provided, such as Figure 8 As shown, the pixel compensation circuit proposed in this embodiment is... Figure 1 Based on the pixel compensation circuit, the drain of the reset transistor T3 is electrically connected to the negative power supply VSS. That is, in this embodiment, the gate of the reset transistor T3 is electrically connected to the compensation control line Comp(n), the source of the reset transistor T3 is electrically connected to the first node G, and the drain of the reset transistor T3 is electrically connected to the negative power supply VSS. The VSS signal provided by the negative power supply VSS is used as the reset signal of the first node G and the compensation stage voltage.

[0076] In this embodiment, the pixel compensation circuit employs the same reset phase, detection phase, data writing phase, and light emission phase as described above to compensate for the threshold voltage of the driving transistor T2.

[0077] The pixel compensation circuit proposed in this embodiment can reduce the number of signals and save layout space.

[0078] In another embodiment of this application, a pixel compensation circuit is also provided, such as Figure 9 As shown, the pixel compensation circuit proposed in this embodiment is... Figure 1 Based on the pixel compensation circuit, the position of the first capacitor Cs is replaced between the second node S and the negative power supply VSS. That is, in this embodiment, one end of the first capacitor Cs is electrically connected to the second node S, and the other end of the first capacitor Cs is electrically connected to the negative power supply VSS.

[0079] The pixel compensation circuit proposed in this embodiment is still... Figure 1 Based on the pixel compensation circuit in the original, delete Figure 1 The pixel compensation circuit shown has a first switching transistor T4; specifically, the gate of the driving transistor T2 is electrically connected to the first node G, the source of the driving transistor T2 is electrically connected to the positive terminal of the power supply VDD, and the drain of the driving transistor T2 is electrically connected to the positive terminal of the light-emitting device LED; and an alternating current (AC) signal is used to replace the positive terminal of the power supply VDD.

[0080] In this embodiment, the pixel compensation circuit adopts the following... Figure 10 The timing control method described herein achieves compensation for the threshold voltage of the driving transistor T2.

[0081] The pixel compensation circuit proposed in this embodiment can reduce circuit noise and reduce power consumption at the display panel.

[0082] In another embodiment of this application, a pixel compensation method is also provided, such as... Figure 1 and Figure 2 As shown, pixel compensation methods include 101 to 105:

[0083] 101. Provide such as Figure 1 The pixel compensation circuit shown in the figure;

[0084] The pixel compensation circuit includes a compensation transistor T1, a driving transistor T2, a reset transistor T3, a first switching transistor T4 and a second switching transistor T5, a first capacitor Cs, a second capacitor Cst, and a light-emitting device LED.

[0085] 102. Upon entering the reset phase, the control signal line EM and the current stage scan signal line SPAM(n) are both provided with a low level, the compensation control line Comp(n) and the reset signal line Res are both provided with a high level, the reset transistor T3 and the second switching transistor T5 are both in the on state, the compensation transistor T1 and the first switching transistor T4 are both in the off state, the potential reset of the first node G is the second voltage V2 provided by the second voltage terminal V2, and the potential reset of the second node S is the first voltage V1 provided by the first voltage terminal V1.

[0086] 103. Upon entering the detection phase, both the control signal line EM and the compensation control line Comp(n) are at a high level, while both the reset signal line Res and the current stage scan signal line SPAM(n) are at a low level. The first switching transistor T4 and the reset transistor T3 are both in the on state, while the second switching transistor T5 and the compensation transistor T1 are both in the off state. The voltage change at the second node S is the third voltage V3, where V3 = V2 - Vth, and V2 is the second voltage V2, and Vth is the threshold voltage of the driving transistor T2.

[0087] 104. Upon entering the data writing stage, the control signal line EM, the reset signal line Res, and the compensation control line Comp(n) all provide a low level. The current stage scan signal line SPAM(n) changes to a high level line by line. The compensation transistor T1 is in the on state, while the reset transistor T3, the first switch transistor T4, and the second switch transistor T5 are all in the off state. The first node G writes the data signal Vdata, and the voltage change of the second node S is the fourth voltage V4. The fourth voltage V4 = V3 + (Data - V2) * [Cst / (Cst + C1)] = V2 - Vth + (Data - V2) * [Cst / (Cst + C1)], where Data is the data signal input to the data line Vdata.

[0088] 105. Upon entering the light-emitting stage, the control signal line EM provides a high level, while the compensation control line Comp(n), the reset signal line Res, and the current stage scan signal line SPAM(n) all provide a low level. The first switching transistor T4 and the driving transistor T2 are in the on state, while the reset transistor T3, the second switching transistor T5, and the compensation transistor T1 are all in the off state. The source-drain voltage of the driving transistor T2 is T2_Vgs = (Data-V2)*[Cst / (Cst+C1)]+Vth, and the light-emitting device LED emits light.

[0089] In another embodiment of this application, this application provides a display panel, which includes the pixel compensation circuit as described above or employs the pixel compensation method as described above.

[0090] The pixel compensation circuit, pixel compensation method, and display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A pixel compensation circuit, characterized in that, It includes a compensation transistor, a driving transistor, a reset transistor, a first switching transistor and a second switching transistor, a first capacitor, a second capacitor, and a light-emitting device; The gate of the compensation transistor is electrically connected to the current stage scan signal line, the source of the compensation transistor is electrically connected to the first node, and the drain of the compensation transistor is electrically connected to the data line. The current stage scan signal line is used to provide a scan signal, and the data line is used to provide a data signal. The gate of the driving transistor is electrically connected to the first node, the source of the driving transistor is electrically connected to the drain of the first switching transistor, the drain of the driving transistor is electrically connected to the positive terminal of the light-emitting device, and the negative terminal of the light-emitting device is electrically connected to the negative terminal of the power supply. The gate of the reset transistor is electrically connected to the compensation control line, the source of the reset transistor is electrically connected to the first node, and the drain of the reset transistor is electrically connected to the second voltage terminal. The gate of the first switching transistor is electrically connected to the control signal line, the source of the first switching transistor is electrically connected to the positive terminal of the power supply, and the drain of the first switching transistor is electrically connected to the source of the driving transistor. The gate of the second switching transistor is electrically connected to the reset signal line, the source of the second switching transistor is electrically connected to the first voltage terminal, and the drain of the second switching transistor is electrically connected to the connection point between the drain of the driving transistor and the positive terminal of the light-emitting device, forming a second node at the connection point. One end of the first capacitor is electrically connected to the positive terminal of the power supply, and the other end of the first capacitor is electrically connected to the second node; One end of the second capacitor is electrically connected to the first node, and the other end of the second capacitor is electrically connected to the second node; The current-level scan signal line, the compensation control line, the reset signal line, and the control signal line are combined to correspond to the reset stage, the detection stage, the data writing stage, and the light emission stage, respectively. During the reset stage, the control signal line and the current-level scan signal line are both at a low level, while the compensation control line and the reset signal line are both at a high level.

2. The pixel compensation circuit as described in claim 1, characterized in that, During the reset phase, both the reset transistor and the second switching transistor are in the ON state, while both the compensation transistor and the first switching transistor are in the OFF state.

3. The pixel compensation circuit as described in claim 2, characterized in that, During the detection phase, both the control signal line and the compensation control line are at a high level, while both the reset signal line and the current stage scan signal line are at a low level.

4. The pixel compensation circuit as described in claim 3, characterized in that, During the detection phase, both the first switching transistor and the reset transistor are in the ON state, while both the second switching transistor and the compensation transistor are in the OFF state.

5. The pixel compensation circuit as described in claim 4, characterized in that, During the data writing phase, the control signal line, the reset signal line, and the compensation control line are all at a low level, while the current level scan signal line changes to a high level line by line.

6. The pixel compensation circuit as described in claim 5, characterized in that, During the data writing phase, the compensation transistor is in the ON state, while the reset transistor, the first switching transistor, and the second switching transistor are all in the OFF state.

7. The pixel compensation circuit as described in claim 6, characterized in that, During the light emission stage, the control signal line is at a high level, while the compensation control line, the reset signal line, and the current stage scan signal line are all at a low level.

8. The pixel compensation circuit as described in claim 7, characterized in that, During the light-emitting phase, the first switching transistor is in the on state, while the reset transistor, the second switching transistor, and the compensation transistor are all in the off state.

9. A pixel compensation method, characterized in that, The method includes: Provide a pixel compensation circuit as described in any one of claims 1 to 8; Upon entering the reset phase, both the control signal line and the current stage scan signal line provide a low level, while both the compensation control line and the reset signal line provide a high level. The reset transistor and the second switching transistor are both in the on state, while the compensation transistor and the first switching transistor are both in the off state. The potential reset of the first node is the second voltage provided by the second voltage terminal, and the potential reset of the second node is the first voltage provided by the first voltage terminal. Upon entering the detection phase, both the control signal line and the compensation control line are provided with a high level, while both the reset signal line and the current stage scan signal line are provided with a low level. The first switching transistor and the reset transistor are both in the on state, while the second switching transistor and the compensation transistor are both in the off state. The voltage change of the second node is the third voltage V3, where V3 = V2 - Vth, and V2 is the second voltage V2, and Vth is the threshold voltage of the driving transistor. Upon entering the data writing stage, the control signal line, reset signal line, and compensation control line all provide a low level. The current stage scan signal line changes to a high level line by line, the compensation transistor is in the on state, and the reset transistor, the first switching transistor, and the second switching transistor are all in the off state. The first node writes the data signal, and the voltage change of the second node is the fourth voltage V4, which is V3 + (Data - V2) * [Cst / (Cst + C1)] = V2 - Vth + (Data - V2) * [Cst / (Cst + C1)], where Data is the data signal input by the data line Vdata. Upon entering the light-emitting stage, the control signal line provides a high level, while the compensation control line, reset signal line, and current stage scan signal line all provide a low level. The first switching transistor and the driving transistor are in the on state, while the reset transistor, the second switching transistor, and the compensation transistor are all in the off state. The source-drain voltage of the driving transistor is T2_Vgs=(Data-V2)*[Cst / (Cst+C1)]+Vth, and the light-emitting device emits light.

10. A display panel, characterized in that, The display panel includes a pixel compensation circuit as described in any one of claims 1 to 8 or employs a pixel compensation method as described in claim 9.

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