Gate drive circuit and display device

Abstract

The application discloses a gate driving circuit and a display device. The gate driving circuit comprises a signal generating unit and a plurality of mutually independent gate driving units. The signal generating unit provides a plurality of input selection signals to a plurality of selection signal lines. Each gate driving unit is connected to N selection signal lines corresponding to the gate driving unit to receive N input selection signals corresponding to the gate driving unit. Each input terminal of each gate driving unit is disconnected from each output terminal of a gate driving unit other than the gate driving unit. N is an integer greater than or equal to 1. In each row scanning stage, N input selection signals corresponding to the row scanning stage among the plurality of input selection signals are in a preset level state, so that the gate driving unit receiving the N input selection signals provides a gate driving signal in an effective level state to a corresponding row of pixel units. Each gate driving unit is controlled only by the input selection signal generated by the signal unit, which facilitates independent operation to save power consumption.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a gate driving circuit and a display device. Background Technology

[0002] A display device is a tool that transmits display data to a display panel via a transmission device and then reflects it to the human eye. Examples of display devices include liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting diode (OLED) displays, and electrophoretic displays (EPDs).

[0003] Taking a thin-film transistor (TFT) liquid crystal display device as an example, it includes a liquid crystal display panel and a driving circuit. The liquid crystal display panel includes multiple scan lines and multiple data lines, and two adjacent scan lines and two adjacent data lines intersect to form a pixel unit. Each pixel unit includes at least one thin-film transistor. The driving circuit includes a gate drive circuit and a source drive circuit.

[0004] The gate drive circuit sends a gate drive signal Gn to the scan line through a pull-up transistor electrically connected to the scan line, sequentially turning on the TFTs of each row. Then, the source drive circuit simultaneously charges the pixel units of an entire row to their respective required voltages to display different gray levels. However, this results in significant power consumption waste when displaying a static image or an image that only requires partial changes.

[0005] In existing technologies, power consumption is typically reduced by using low-voltage charging and thicker wires to lower wire resistance. For display devices supporting touch functionality, intra-frame touch driving (long-H, Long Horizontal) can also be used, adding a pause function to further reduce power consumption. However, low-voltage charging may lead to incomplete charging, reducing display quality; large wire widths reduce usable space and increase inter-line capacitance; and when selecting a Long-H driver circuit, special attention must be paid to maintaining the Q-point level, which is often impossible to balance in parameter design.

[0006] Therefore, there is an urgent need for a new gate driving circuit and display device. Summary of the Invention

[0007] In view of the above problems, the purpose of this application is to provide a gate driving circuit and a display device. Each gate driving unit is individually controlled by an input selection signal generated by a signal unit, thereby making each gate driving unit independent and facilitating energy saving.

[0008] According to one aspect of this application, a gate driving circuit is provided, comprising: a signal generating unit providing a plurality of input selection signals to corresponding plurality of selection signal lines; and a plurality of independent gate driving units, each gate driving unit being connected to a corresponding N selection signal lines to receive N input selection signals corresponding to that gate driving unit, and each input terminal of each gate driving unit being disconnected from each output terminal of the gate driving units other than that gate driving unit, where N is an integer greater than or equal to 1, and during each row scanning phase, the N input selection signals corresponding to that row scanning phase are at a preset level state, so that the gate driving unit receiving the N input selection signals provides a gate driving signal at an effective level state to the corresponding pixel unit row.

[0009] Optionally, the plurality of input selection signals are configured by the signal generating unit to such that, for different row scanning stages, the N selection signal lines corresponding to the N input selection signals configured to a preset level state are not completely the same, and the N selection signal lines connected to different gate driving units are not completely the same, so that the plurality of gate driving units can provide the gate driving signal with an effective level state to the corresponding pixel unit row in the corresponding row scanning stage.

[0010] Optionally, N is an integer greater than or equal to 2, and at least one of the selection signal lines is simultaneously connected to multiple of the gate drive units.

[0011] Optionally, each of the gate driving units includes N-input AND gate logic, and the gate driving unit provides the gate driving signal with a valid level state to the corresponding pixel unit row if and only if all N input selection signals received by the gate driving unit are at a preset level state.

[0012] Optionally, the gate drive signal includes: an input module connected to the corresponding N selection signal lines, used to adjust the voltage of the first node and provide a control signal according to the corresponding N input selection signals; an output module connected to the input module at the first node, used to output the gate drive signal at an effective level to the output terminal of the gate drive unit according to the voltage of the first node; and a pull-down module connected to the input module and the output terminal of the gate drive unit, used to pull the gate drive signal down to a low level voltage according to the control signal.

[0013] Optionally, the input module includes: a first switching element, a second switching element, and a third switching element. The first path terminal, the control terminal, the first path terminal, and the control terminal of the second switching element are respectively connected to N selection signal lines corresponding to the gate driving unit to receive the corresponding N input selection signals. The control terminal of the third switching element is connected to the second path terminal of the first switching element, and the second path terminal of the third switching element is connected to the second path terminal of the second switching element. The first path terminal of the third switching element is the first node, and the voltage of the second path terminal of the first switching element is used as the control signal.

[0014] Optionally, the pull-down module includes: a fourth switching element, wherein the control terminal of the fourth switching element receives the control signal, the second path terminal is connected to a low-level voltage, and the first path terminal is a second node; a fifth switching element, wherein the control terminal of the fifth switching element is connected to the first path terminal of the fourth switching element, the first path terminal is connected to the first node, and the second path terminal is connected to the low-level voltage; a sixth switching element, wherein the control terminal of the sixth switching element is connected to the first path terminal of the fourth switching element, the first path terminal is connected to the output terminal of the gate drive circuit, and the second path terminal is connected to the low-level voltage; and a seventh switching element, wherein the control terminal and the second path terminal of the seventh switching element receive a high-level voltage, and the first path terminal is connected to the first path terminal of the fourth switching element.

[0015] Optionally, the size of the fourth switching element is larger than the size of the seventh switching element, the size of the third switching element is larger than the size of the fifth switching element, and the size of the sixth switching element is at least larger than the size of the fourth switching element and the size of the fifth switching element.

[0016] Optionally, the output module includes: an eighth switching element, wherein a first path terminal of the eighth switching element receives a high-level voltage, a second path terminal is connected to the output terminal of the gate driving unit, and a control terminal is connected to the first node; and a capacitor, wherein a first terminal of the capacitor is connected to the control terminal of the eighth switching element, and a second terminal is connected to the second path terminal of the eighth switching element.

[0017] According to another aspect of this application, a display device is provided, comprising: a display panel including pixel units arranged in an array; a source driving circuit connected to the display panel and connected to the corresponding pixel units via data lines to output a data signal containing display image information; and a gate driving circuit as described in any of the preceding claims, connected to each pixel unit row via a plurality of scan lines to output a corresponding gate driving signal to the corresponding pixel unit row via each scan line.

[0018] According to the gate driving circuit and display device of this application, the signal generating unit provides different combinations of input selection signals to different gate driving units through multiple selection signal lines. A valid gate driving signal is provided to the corresponding pixel unit row only when N selection signal lines in the same input selection signal combination meet a preset level state. This enables individual control of each gate driving unit and its corresponding pixel unit row. Since the gate driving units are not cascaded, charging can be applied only to changing positions during display device operation, thus saving power. Furthermore, because the output level is provided by either a high-level voltage or a low-level voltage, the voltage source is more stable, and the signal transmission is less affected.

[0019] Furthermore, for display devices that support touch display functionality, especially in (long-H, Long Horizontal) mode, since the first node does not need to be kept at a high level, the operating time of the touch unit can be inserted at any position between two adjacent display stages, which makes the design of touch display logic easier. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 This is a schematic structural block diagram of a display device according to an embodiment of the present application;

[0022] Figure 2 Show Figure 1 A schematic block diagram of the gate drive circuit shown.

[0023] Figure 3 Show Figure 2 The circuit structure diagram of the gate driving unit shown is shown.

[0024] Figure 4 Show Figure 3 The input and output waveforms of the gate drive unit are shown. Detailed Implementation

[0025] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0026] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0027] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0028] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0029] In this application, the transistor includes a first pass terminal, a second pass terminal, and a control terminal. When the transistor is in the on state, current flows from the first pass terminal to the second pass terminal. The first pass terminal, the second pass terminal, and the control terminal of the P-type transistor are the source, the drain, and the gate, respectively, and the first pass terminal, the second pass terminal, and the control terminal of the N-type transistor are the drain, the source, and the gate, respectively.

[0030] This application provides a display device, taking a liquid crystal display panel as an example. Figure 1 A schematic structural block diagram of a display device according to an embodiment of this application is shown. Figure 1 As shown, the display device 1 includes a display panel, a deflection drive circuit 100, a source drive circuit 200, and a timing control circuit 300.

[0031] The display panel includes pixel units arranged in an array for displaying images. Each pixel unit includes a thin-film transistor T and multiple pixel capacitors (not shown) formed between a pixel electrode and a common electrode. The source driving circuit 200 is connected to the corresponding pixel unit via a data line S to output a data signal containing information about the displayed image; the gate driving circuit 100 is connected to each row of pixel units via a scan line G to output a gate driving signal synchronized with the data signal to the corresponding row of pixel units via each scan line G; the timing control circuit 300 is used to control the source driving circuit 200 and the gate driving circuit 100.

[0032] Furthermore, Figure 2 Show Figure 1 The diagram shows a schematic block diagram of the gate drive circuit. Figure 2 As shown, the gate driving circuit 100 of this embodiment includes multiple gate-independent driving units 110, multiple selection signal lines 120, and a signal generation unit 130. The signal generation unit 130 provides multiple input selection signals to the corresponding multiple selection signal lines 120. Each gate driving unit 110 is connected to the corresponding N selection signal lines 120 to receive N input selection signals (N is an integer greater than or equal to 1) corresponding to that gate driving unit. Each gate driving unit 120 receives different combinations of input selection signals (i.e., the N input selection signal lines connected to any two gate driving units 120 are at least partially different), and each input terminal of each gate driving unit 120 is disconnected from the output terminals of the other gate driving units, thereby making each gate driving unit 120 independent.

[0033] During each row scanning phase, the gate driving unit provides a gate driving signal to the pixel cell row according to the corresponding N input selection signals. Furthermore, the gate driving unit 120 provides a gate driving signal with an effective level state to the corresponding pixel cell row only when all N input selection signals are at a preset level, so that the corresponding pixel cell row displays an image according to the data signal.

[0034] Accordingly, in the embodiments of this application, corresponding to different row scanning stages, the signal generation unit 130 is configured to provide N input selection signals with preset level states to N not completely identical selection signal lines. This is so that the gate driving unit 120 provides input selection signals with preset level states to the corresponding row scanning stage, thereby enabling the gate driving unit to provide gate driving signals with valid level states to the corresponding pixel unit row.

[0035] The signal generation unit provides different combinations of input selection signals to different gate driving units through multiple selection signal lines. A valid gate driving signal is provided to the corresponding pixel unit row only if N selection signal lines in the same input selection signal combination meet a preset level state. This enables individual control of each gate driving unit and its corresponding pixel unit row. Since the gate driving units are not cascaded, charging can be applied only to changing positions during display device operation, thus saving power consumption.

[0036] In this embodiment, each gate driving unit 110 includes N-input AND gate logic, and controls the output of the gate driving unit through the AND gate logic, such that the gate driving unit provides a valid level state to the corresponding pixel unit row if and only if all N input selection signals received by the gate driving unit are in a preset level state. Figure 3 This diagram illustrates the circuit structure of a gate driving unit according to an embodiment of this application. Figure 3 As shown, each gate drive unit 110 includes an input module 111, a pull-down module 112, and an output module 113. The input module 111 is connected to N corresponding signal lines and is used to adjust the voltage of the first node and provide control signals according to the N corresponding input selection signals. The output module 113 is connected to the input module 111 at the first node and is used to output a gate drive signal Gn at an effective level according to the voltage of the first node. The pull-down module 112 is connected to the input module 111 and the output terminal of the gate drive unit 110 and is used to pull the gate drive signal Gn down to a low level voltage according to the control signal.

[0037] Furthermore, taking as an example each gate drive unit is connected to 4 select signal lines to receive 4 input select signals (i.e., N equals 4), and a high level is used as the effective level state of the gate drive signal.

[0038] The input module 111 further includes a first switching element T1, a second switching element T2, and a third switching element T3. Specifically, the first path terminal of the first switching element T1 is connected to the first selection signal line and receives the first input selection signal IN1; the control terminal of the first switching element T1 is connected to the second selection signal line and receives the second input selection signal IN2; the first path terminal of the second switching element T2 is connected to the third selection signal line and receives the third input selection signal IN3, and the control terminal of the second switching element T2 is connected to the fourth selection signal line and receives the fourth input selection signal IN4; the control terminal of the third switching element T3 is connected to the second path terminal of the first switching element T1, the first path terminal of the third switching element T3 is the first node Q, and the second path terminal of the third switching element T3 is connected to the second path terminal of the second switching element T2. Furthermore, in this embodiment, the voltage at the second path terminal of the first switching element T1 is also used as the control signal.

[0039] The pull-down module 112 includes a fourth switch element T4, a fifth switch element T5, a sixth switch element T6, and a seventh switch element T7. Specifically, the control terminal of the fourth switching element T4 is connected to the second path terminal of the first switching element T1 to receive a control signal. The second path terminal of the fourth switching element T4 is connected to a low-level voltage, and the first path terminal of the fourth switching element T4 is the second node QB. The control terminal of the fifth switching element T5 is connected to the first path terminal (i.e., the second node QB) of the fourth switching element T4. The first path terminal of the fifth switching element T5 is connected to the first path terminal (i.e., the first node Q) of the third switching element T3. The second path terminal of the fifth switching element is connected to a low-level voltage. The control terminal of the sixth switching element T6 is connected to the first path terminal (i.e., the second node QB) of the fourth switching element T4. The first path terminal of the sixth switching element T6 is connected to the output terminal of the gate driving unit 110. The second terminal of the sixth switching element T6 is connected to a low-level voltage VGL. The control terminal and the second path terminal of the seventh switching element T7 receive a high-level voltage VGH. The first path terminal of the seventh switching element T7 is connected to the first path terminal (i.e., the second node QB) of the fourth switching element T4. Furthermore, the size (channel width-to-length ratio) of the fourth switching element T4 is larger than that of the seventh switching element T7, and the size (channel width-to-length ratio) of the third switching element T3 is larger than that of the fifth switching element T5. In some embodiments, for example, the size of the fourth switching element T4 is three times the size of the seventh switching element T7, and the size of the third switching element T3 is three times the size of the fifth switching element T5. Additionally, the sixth switching element T6 also needs to be large, at least larger than the sizes of the fourth and fifth switching elements. In some embodiments, for example, the size of the sixth switching element is larger than the sizes of the other switching elements to provide a greater current capacity.

[0040] Output module 113 includes an eighth switching element T8 and a capacitor C1. The first terminal of the eighth switching element T8 is connected to a high-level voltage VGH, the second terminal of the eighth switching element T8 is connected to the output terminal of the gate drive unit 110, and the control terminal of the eighth switching element T8 is connected to the first terminal (i.e., the first node Q) of the third switching element T3. The first terminal of capacitor C1 is connected to the control terminal of the eighth switching element T8, and the second terminal of capacitor C1 is connected to the second terminal of the eighth switching element T8. In this embodiment, capacitor C1 is an independent component; however, it should be understood that in some embodiments, the parasitic capacitance of the eighth switching element T8 can also be used as capacitor C1.

[0041] In this embodiment, the first to eighth switching elements are all implemented using N-type transistors. However, it should be understood that in some other embodiments, the first to eighth switching elements may also be implemented using, for example, P-type transistors or other switching elements. The working principle of this application will be specifically described below using an N-type transistor as an example.

[0042] The gate driving unit in this application embodiment includes two operating states:

[0043] In the first operating state, all of the first to fourth input selection signals are at a high level (i.e., the first to fourth input selection signals meet the preset level).

[0044] The first switching element T1 and the second switching element T2 are turned on. The voltage at the second terminal of T1 and the second terminal of T2 are raised, and correspondingly, the third switching element T3 and the fourth switching element T4 are turned on. Although the high-level voltage VGH can continuously turn on the seventh switching element T7, the fourth switching element T4 is larger than the seventh switching element T7, so the voltage of the second node QB is still pulled down by the low-level voltage VGL, and the sixth transistor T6 cannot be turned on. The voltage at the first path terminal (i.e., the first node Q) of the third transistor T3 is pulled up, thereby turning on the eighth switching element T8. The gate drive signal Gn output from the output terminal of the gate drive unit 110 is gradually pulled up by the high-level voltage VGH. Furthermore, due to the bootstrap effect of the capacitor C1, as the gate drive signal Gn increases, the voltage of the first node Q is further pulled up, and the eighth switching element T8 is turned on more fully, thereby further pulling up the voltage of the gate drive signal Gn to reach the high-level voltage VGH.

[0045] In the second operating state, at least one of the first to fourth input selection signals is at a low level (i.e., the four input selection signals do not meet the preset level state).

[0046] For example, consider a scenario where the first input selection signal is low and the other input selection signals are high. The first switching element T1 and the second switching element T2 are turned on, and the voltage at the second path terminal of the first switching element T1 is gradually pulled low; the voltage at the second path terminal of the second switching element T2 is gradually pulled high. The third switching element T3 and the fourth switching element T4 cannot be turned on. The seventh switching element T7, controlled by the high-level voltage VGH, is always turned on, gradually pulling up the voltage of the second node QB, causing the fifth switching element T5 and the sixth switching element T6 to gradually turn on. As the fifth switching element T5 gradually turns on, the voltage of the first node Q is gradually pulled low by the low-level voltage VGL. The eighth switching element T8 cannot be turned on. And as the sixth switching element T6 gradually turns on, the voltage at the output terminal Gn is gradually pulled low to the low-level voltage VGL. Therefore, in the second operating state, the level of the second node QB gradually increases, while the first node Q cannot maintain a high level, and the voltage at the output terminal Gn is pulled low to the low-level voltage VGL by the low-level power supply terminal. (Since other input selection signal combinations that do not meet the preset level state operate on similar principles, they will not be explained one by one here.)

[0047] Furthermore, in the embodiments of this application, a four-input AND gate logic is formed using three switching elements. The gate driving unit outputs the effective level of the gate driving signal only when all four input selection signals are high. Then, according to the calculation formula for permutations and combinations:

[0048]

[0049] When i = 15, there are 1820 possible combinations of input selection signals; when i = 16, there are 1820 possible combinations of input selection signals. By adjusting the number of signal lines, the number of combinations of input selection signals can be made greater than or equal to the number of scan lines to accommodate different scan line numbers of different display devices.

[0050] Therefore, in the embodiments of this application, the signal generating unit provides different combinations of input selection signals to different gate driving units through multiple selection signal lines. A valid gate driving signal is provided to the corresponding pixel unit row only if N selection signal lines in the same input selection signal combination meet a preset level state. This enables individual control of each gate driving unit and its corresponding pixel unit row. Since the gate driving units are not cascaded, charging can be applied only to changing positions during display device operation, thus saving power. Simultaneously, because the output level is provided by either a high-level voltage VGH or a low-level voltage VGL, the voltage source is more stable, and the signal transmission is less affected.

[0051] Furthermore, for display devices that support touch display functionality, especially in intra-frame touch driving (long-H) mode, since the first node does not need to be kept at a high level, the working time of the touch unit can be inserted at any position between two adjacent display stages, which makes the design of touch display logic easier.

[0052] However, it should be understood that this application should not be limited thereto. For example, in some embodiments, the first terminal of the first switching element and / or the second switching element can be connected to the control terminal to reduce the number of input ports of the input module 111, but correspondingly, more signal lines are required to provide different combinations of input selection signals. In a preferred embodiment, N is preferably an integer greater than or equal to 2. Accordingly, at least one selection signal line can be multiplexed in different gate driving units (i.e., at least one selection signal line is connected to multiple gate driving units at the same time) to reduce the number of required selection signal lines and facilitate the miniaturization of the gate driving circuit.

[0053] Figure 4 Show Figure 3 The input and output waveforms of the gate drive unit are shown below. Figure 4 As shown, when IN1, IN2, IN3, and IN4 are all high, the output Gn of the gate drive unit is high. However, when at least one of IN1, IN2, IN3, and IN4 is low, the output Gn of the gate drive unit cannot maintain a high level, and because the sixth switching element T6 is relatively large, Gn is quickly pulled down to a low level. This allows for individual control of each gate drive unit and its corresponding pixel row. Since the gate drive units are not cascaded, charging can be applied only to changing positions during display device operation, thus saving power.

[0054] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A gate driving circuit, wherein, include: The signal generation unit provides multiple input selection signals to corresponding multiple selection signal lines; as well as Multiple independent gate driving units are provided. Each gate driving unit is connected to N corresponding selection signal lines to receive N input selection signals corresponding to that gate driving unit. Each input terminal of each gate driving unit is disconnected from the output terminals of all other gate driving units. N is 4. During each row scanning phase, N input selection signals corresponding to that row scanning phase are at preset level states, so that the gate driving unit receiving the N input selection signals provides a gate driving signal with an effective level state to the corresponding pixel unit row. The gate driving unit includes: An input module, connected to the corresponding N selection signal lines, is used to adjust the voltage of the first node according to the corresponding N input selection signals and to provide control signals according to a portion of the N input selection signals; and A pull-down module, connected to the input module and the output of the gate drive unit, is used to pull the gate drive signal down to a low-level voltage according to a valid control signal. The input module includes a first switching element, a second switching element, and a third switching element. The first path terminal, the control terminal, the first path terminal, and the control terminal of the second switching element are respectively connected to N selection signal lines corresponding to the gate driving unit to receive the corresponding N input selection signals. The control terminal of the third switching element is connected to the second path terminal of the first switching element, and the second path terminal of the third switching element is connected to the second path terminal of the second switching element. The first path terminal of the third switching element is the first node, and the voltage at the second path terminal of the first switching element serves as the control signal. The pull-down module includes: a fourth switching element, wherein the control terminal of the fourth switching element receives the control signal, the second path terminal is connected to a low-level voltage, and the first path terminal is a second node; a fifth switching element, wherein the control terminal of the fifth switching element is connected to the first path terminal of the fourth switching element, the first path terminal is connected to the first node, and the second path terminal is connected to the low-level voltage; a sixth switching element, wherein the control terminal of the sixth switching element is connected to the first path terminal of the fourth switching element, the first path terminal is connected to the output terminal of the gate drive circuit, and the second path terminal is connected to the low-level voltage; and a seventh switching element, wherein the control terminal and the second path terminal of the seventh switching element receive a high-level voltage, and the first path terminal is connected to the first path terminal of the fourth switching element. The gate driving circuit is used to drive the display device to operate in the intra-frame touch driving mode, and the touch detection time of the display device is set at any position between adjacent display stages.

2. The gate driving circuit according to claim 1, wherein, The multiple input selection signals are configured by the signal generating unit such that, for different row scanning stages, the N selection signal lines corresponding to the N input selection signals configured to a preset level state are not completely the same, and the N selection signal lines connected to different gate driving units are not completely the same, so that the multiple gate driving units can provide the gate driving signal with an effective level state to the corresponding pixel unit row in the corresponding row scanning stage.

3. The gate driving circuit according to claim 2, wherein, At least one of the selected signal lines is simultaneously connected to multiple of the gate drive units.

4. The gate driving circuit according to claim 2, wherein, Each of the gate driving units includes N-input AND gate logic, and the gate driving unit provides the gate driving signal with a valid level state to the corresponding pixel unit row if and only if all N input selection signals received by the gate driving unit are at a preset level state.

5. The gate driving circuit according to claim 1, wherein, The gate driving unit further includes: An output module, connected to the input module at the first node, is used to output a gate drive signal at an effective level to the output terminal of the gate drive unit according to the voltage of the first node.

6. The gate driving circuit according to claim 5, wherein, The size of the fourth switching element is larger than the size of the seventh switching element, the size of the third switching element is larger than the size of the fifth switching element, and the size of the sixth switching element is at least larger than the size of the fourth switching element and the size of the fifth switching element.

7. The gate driving circuit according to claim 5, wherein, The output module includes: The eighth switching element, wherein the first path terminal of the eighth switching element receives a high-level voltage, the second path terminal is connected to the output terminal of the gate driving unit, and the control terminal is connected to the first node; and The capacitor has its first end connected to the control terminal of the eighth switching element and its second end connected to the second path terminal of the eighth switching element.

8. A display device, comprising: The display panel includes pixel units arranged in an array; The source drive circuit is connected to the display panel and to the corresponding pixel unit via a data line to output a data signal containing display image information; as well as The gate driving circuit according to any one of claims 1 to 7 is connected to each pixel unit row via multiple scan lines, so as to output the corresponding gate driving signal to the corresponding pixel unit row via each scan line.

Images