Thread group scheduling method, general-purpose graphics processor and storage medium

Abstract

The application discloses a thread group scheduling method, a general-purpose graphics processor and a storage medium, and comprises the following steps: acquiring first data locality information, performing a sorting operation on a first initial thread group sequence to obtain a first transition thread group sequence, and performing a sorting operation on a second initial thread group sequence to obtain a second transition thread group sequence; the sorting operation comprises the following steps: traversing each thread group, determining whether there is a priority thread group according to the first data locality information, increasing the priority of the priority thread group, and sorting a plurality of thread groups according to the priority; the priority thread group is a thread group that requests a cache line number of a same prefetch block greater than a preset request quantity threshold value, or a plurality of thread groups that simultaneously request the same prefetch block, and the plurality of thread groups request a cache line number greater than the preset request quantity threshold value; the first transition thread group sequence and the second transition thread group sequence are merged to obtain a target thread group sequence; and a scheduling operation is performed on a target thread group in the target thread group sequence.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of general-purpose graphic processors, and in particular to a thread group scheduling method, a general-purpose graphic processor and a storage medium. BACKGROUND

[0002] With the increasing demand for processor performance in the big data era, general-purpose graphic processors with high computing power are widely used in various general-purpose computing fields.

[0003] From the hardware of the general-purpose graphic processor, the general-purpose graphic processor is composed of multiple stream multiprocessors, each stream multiprocessor is composed of multiple stream processors, and the stream processor can be understood as a computing unit in the general-purpose graphic processor. The internal pipeline of each stream multiprocessor is divided into five stages of instruction fetching, decoding, emitting, executing and writing back, a thread group is taken as an execution unit, and each thread group is composed of 32 threads. The instruction fetching stage fetches one or two instructions from the instruction cache to a ready thread group. The decoding stage decodes the fetched instructions and stores them in the instruction cache corresponding to the thread group. The emitting stage selects a ready thread group according to the thread group scheduling strategy, and emits the instructions in the instruction cache of the thread group into the executing stage. The executing stage includes the execution pipeline of the computing instruction and the memory instruction, the computing instruction will perform the computing operation in the stream processor, and the memory instruction will enter the load storage unit to perform the memory operation of the data cache. The writing back stage writes the results of the executing instruction back to the specified position. The thread scheduling in the general-purpose graphic processor represents the thread group scheduling strategy of the emitting stage, which determines the instruction execution sequence inside the general-purpose graphic processor.

[0004] However, the existing thread scheduling method has the problem of frequent cache jitter caused by memory competition of multiple threads of the general-purpose graphic processor, which reduces the performance of the general-purpose graphic processor. SUMMARY

[0005] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides a thread group scheduling method, a general-purpose graphic processor and a storage medium, which can solve the problem of frequent cache jitter of the existing thread scheduling method.

[0006] According to the thread group scheduling method of the first aspect of the present application, the first data locality information is obtained, the first initial thread group sequence is sorted to obtain the first transition thread group sequence, and the second initial thread group sequence is sorted to obtain the second transition thread group sequence, the first initial thread group sequence includes a plurality of computing thread groups, the computing thread group is a thread group for executing a computing instruction, and the second initial thread group sequence includes a plurality of memory thread groups, the memory thread group is a thread group for executing a memory instruction.

[0007] The sorting operation includes: traversing each thread group, when it is determined according to the first data locality information that there is a priority thread group, increasing the priority of the priority thread group, sorting a plurality of thread groups according to the priority of the plurality of thread groups, and the prefetch block includes a plurality of cache lines, the first data locality information is used to represent the number of cache lines of the prefetch block requested by the thread group in the missing information state holding register storage unit, and the priority thread group is the thread group whose number of cache lines of the same prefetch block requested is greater than a preset request quantity threshold, or is a plurality of thread groups simultaneously requesting the same prefetch block, and the number of cache lines of the prefetch block requested by the plurality of thread groups is greater than the preset request quantity threshold.

[0008] Merging the first transition thread group sequence and the second transition thread group sequence to obtain a target thread group sequence.

[0009] Scheduling operation is performed on a target thread group in the target thread group sequence, and the target thread group is the thread group to be scheduled in the target thread group sequence.

[0010] The thread group scheduling method according to the first aspect of the present application has at least the following beneficial effects:

[0011] According to the first data locality information, the thread groups with data locality in the first initial thread group sequence and the second initial thread group sequence are confirmed as priority thread groups, the priority of the priority thread group is increased, the first initial thread group sequence and the second initial thread group sequence are sorted according to the priority respectively, the first transition thread group sequence and the second transition thread group sequence are obtained, the first transition thread group sequence and the second transition thread group sequence are merged to obtain a target thread group sequence, and scheduling operation is performed on the thread group to be scheduled in the target thread group sequence. Compared with the traditional thread scheduling method, the thread group scheduling method of the first aspect of the present application can preferentially schedule the thread group with data locality, reduce the cache jitter, and improve the performance of the general-purpose graphics processor.

[0012] According to some embodiments of the present application, further comprising:

[0013] Obtaining second data locality information, the second data locality information is used to represent the sum of the number of cache lines of the prefetch block requested by the thread group in the missing information state holding register storage unit and the first level data cache;

[0014] According to the second data locality information and a plurality of prefetch blocks, a target prefetch block is confirmed, and the target prefetch block is the prefetch block whose sum of the number of cache lines in the missing information state holding register storage unit and the first level data cache is greater than a preset prefetch block locality threshold.

[0015] generating a prefetch request for requesting to send a pending cache line of a target prefetch block to the level one data cache, the pending cache line not being sent to the miss information state holding register storage unit and the cache line of the level one data cache;

[0016] sending the prefetch request to a memory system.

[0017] According to some embodiments of the present application, the generating a prefetch request comprises:

[0018] obtaining a data amount of the miss information state holding register storage unit, and generating the prefetch request if the data amount is less than a preset first data amount threshold.

[0019] According to some embodiments of the present application, the sending the prefetch request to a memory system comprises:

[0020] storing the prefetch request in a load store unit;

[0021] obtaining a number of memory access requests in the load store unit;

[0022] sending the prefetch request to a memory system when the number of memory access requests is zero.

[0023] According to some embodiments of the present application, the sorting a plurality of thread groups according to priorities of the plurality of thread groups comprises:

[0024] sorting a plurality of thread groups according to priorities of the plurality of thread groups in a fine-grained manner.

[0025] According to some embodiments of the present application, after the scheduling operation on a target thread group in the target thread group sequence, the method further comprises: reducing the priority of the target thread group.

[0026] According to some embodiments of the present application, the merging the first transition thread group sequence and the second transition thread group sequence comprises:

[0027] obtaining a data amount of the miss information state holding register storage unit;

[0028] if the data amount is greater than a preset second data amount threshold, adding the second transition thread group sequence at the end of the first transition thread group sequence, otherwise adding the first transition thread group sequence at the end of the second transition thread group sequence to obtain a target thread group sequence.

[0029] According to some embodiments of the present application, the scheduling operation on a target thread group in the target thread group sequence comprises:

[0030] sequentially numbering a plurality of thread groups in the sequence of target thread groups;

[0031] sequentially scheduling a plurality of thread groups in the sequence of target thread groups according to the numbering order.

[0032] According to the second aspect of the present application, the general-purpose graphic processor for executing the thread group scheduling method has at least the following beneficial effects:

[0033] According to the first data locality information, the thread groups with data locality in the first initial thread group sequence and the second initial thread group sequence are confirmed as priority thread groups, the priority of the priority thread groups is improved, the first initial thread group sequence and the second initial thread group sequence are sorted according to the priority, respectively, to obtain a first transition thread group sequence and a second transition thread group sequence, the first transition thread group sequence and the second transition thread group sequence are merged to obtain a target thread group sequence, and the thread groups to be scheduled in the target thread group sequence are scheduled. Compared with the traditional general-purpose graphic processor, the general-purpose graphic processor of the second aspect of the present application can preferentially schedule the thread groups with data locality, reduce the cache jitter, and improve the performance of the general-purpose graphic processor.

[0034] According to the third aspect of the present application, the computer readable storage medium has a processor executable program stored therein, and the processor executable program is executed by the processor to implement the thread group scheduling method as described above.

[0035] According to the third aspect of the present application, the computer readable storage medium has at least the following beneficial effects:

[0036] According to the first data locality information, the thread groups with data locality in the first initial thread group sequence and the second initial thread group sequence are confirmed as priority thread groups, the priority of the priority thread groups is improved, the first initial thread group sequence and the second initial thread group sequence are sorted according to the priority, respectively, to obtain a first transition thread group sequence and a second transition thread group sequence, the first transition thread group sequence and the second transition thread group sequence are merged to obtain a target thread group sequence, and the thread groups to be scheduled in the target thread group sequence are scheduled. Compared with the traditional general-purpose graphic processor, the general-purpose graphic processor of the second aspect of the present application can preferentially schedule the thread groups with data locality, reduce the cache jitter, and improve the performance of the general-purpose graphic processor.

[0037] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0039] Figure 1 This is a flowchart of a thread group scheduling method in one embodiment of the present application;

[0040] Figure 2 This is a flowchart of generating and sending a prefetch request in an embodiment of the present application;

[0041] Figure 3 This is a flow chart of sending a prefetch request to a memory system in one embodiment of the present application;

[0042] Figure 4 This is a flowchart of merging the first transition thread group sequence and the second transition thread group sequence in one embodiment of the present application;

[0043] Figure 5 This is a flowchart of scheduling operations on a target thread group in one embodiment of the present application. DETAILED DESCRIPTION

[0044] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0045] In the description of this application, it should be understood that descriptions involving orientation, such as the orientation or positional relationship indicated by up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0046] In the description of this application, "a plurality" refers to more than two. The use of "first" or "second" is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order of the technical features indicated.

[0047] In the description of this application, unless otherwise clearly defined, terms such as setting, installation, and electrical connection should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution.

[0048] Refer to the following Figures 1 to 5The application discloses a thread group scheduling method, a general-purpose graphic processor and a storage medium.

[0049] The thread group scheduling method provided by the application, Figure 1 as shown in the figure, comprises the following steps of:

[0050] Step S100: obtaining first data locality information, performing a sorting operation on a first initial thread group sequence to obtain a first transition thread group sequence, and performing a sorting operation on a second initial thread group sequence to obtain a second transition thread group sequence, wherein the first initial thread group sequence comprises a plurality of calculation thread groups, the calculation thread group is a thread group used for executing a calculation instruction, and the second initial thread group sequence comprises a plurality of memory access thread groups, the memory access thread group is a thread group used for executing a memory access instruction;

[0051] The sorting operation comprises the following steps: traversing each thread group, when it is determined according to the first data locality information that there is a priority thread group, improving the priority of the priority thread group, and sorting the plurality of thread groups according to the priority of the plurality of thread groups, the prefetch block comprises a plurality of cache lines, the first data locality information is used to represent the number of cache lines of a prefetch block requested by a thread group in a missing information state holding register storage unit, the priority thread group is a thread group whose number of requested cache lines of the same prefetch block is greater than a preset request quantity threshold, or a plurality of thread groups that simultaneously request the same prefetch block, and the number of cache lines requested by the plurality of thread groups is greater than the preset request quantity threshold;

[0052] In this step, according to the first data locality information, the thread groups with data locality in the first initial thread group sequence and the second initial thread group sequence are determined, and the priority of the thread groups with data locality is improved, so that the plurality of thread groups in the first initial thread group sequence and the second initial thread group sequence are sorted according to the priority to obtain the first transition thread group sequence and the second transition thread group sequence, and the thread groups with data locality are preferentially scheduled.

[0053] It can be understood that the preset request quantity threshold is not limited, for example, the preset request quantity threshold is set to 2, when the number of cache lines of the same prefetch block requested by a thread group is greater than 2, it is confirmed that the thread group has data locality within the thread group, that is, it is confirmed to be a priority thread group; when more than 2 cache lines in the same prefetch block are simultaneously requested by a plurality of thread groups, it is confirmed that the plurality of thread groups have data locality between thread groups, that is, it is confirmed to be a priority thread group.

[0054] It should be noted that the number of cache lines included in one prefetch block is not limited, for example, the prefetch block can include 5 cache lines, or can include 6 cache lines, and the plurality of cache lines can be continuous or discontinuous.

[0055] Step S200: merging the first transition thread group sequence and the second transition thread group sequence to obtain a target thread group sequence;

[0056] Step S300: performing a scheduling operation on a target thread group in a target thread group sequence, where the target thread group is a thread group to be scheduled in the target thread group sequence.

[0057] In this step, the instructions of the thread groups in the target thread group sequence are scheduled according to the priority order. In other words, the thread groups with higher priorities in the target thread group sequence are scheduled first.

[0058] It should be noted that after the scheduling operation on the target thread group is completed, the above steps are executed in sequence when the next scheduling operation is performed.

[0059] In this embodiment, based on the first data locality information, the first initial thread group sequence and the thread group with data locality in the second initial thread group sequence are identified as priority thread groups, the priority of the priority thread group is increased, and the first initial thread group sequence and the second initial thread group sequence are sorted according to the priority to obtain a first transition thread group sequence and a second transition thread group sequence, respectively. The first transition thread group sequence and the second transition thread group sequence are merged to obtain a target thread group sequence, and a scheduling operation is performed on the thread group to be scheduled in the target thread group sequence. Compared with traditional thread scheduling methods, the thread group scheduling method of the embodiment of the present application can prioritize the scheduling of thread groups with data locality, reduce cache jitter, and improve the performance of general-purpose graphics processors.

[0060] In one embodiment of the present application, Figure 2 As shown, the thread group scheduling method further includes but is not limited to step S400, step S500, step S600 and step S700.

[0061] Step S400: obtaining second data locality information, where the second data locality information is used to represent the sum of the number of cache lines in the missing information state holding register storage unit and the first-level data cache of the prefetch block requested by the thread group;

[0062] In this step, by obtaining the second data locality information, the number of cache lines of the prefetch block in the primary data cache and the miss information status holding register storage unit can be known, so as to confirm the prefetch block with data locality.

[0063] Step S500: Determine a target prefetch block based on the second data locality information and the plurality of prefetch blocks. The target prefetch block is a prefetch block for which the sum of the number of cache lines in the missing information status holding register storage unit and the first-level data cache is greater than a preset prefetch block locality threshold.

[0064] In this step, according to the second data locality information, the target prefetch block is confirmed from the plurality of prefetch blocks, and if the sum of the number of cache lines in the missing information state holding register storage unit and the level one data cache of the prefetch block is greater than the preset prefetch block locality threshold, it indicates that the prefetch block has data locality, and is the target prefetch block.

[0065] It should be noted that the value of the preset prefetch block locality threshold is not limited, for example, the preset prefetch block locality threshold can be 1, 3, 4, etc.

[0066] Step S600: A prefetch request is generated, and the prefetch request is used to request to send the to-be-taken cache line of the target prefetch block to the level one data cache, and the to-be-taken cache line is not sent to the missing information state holding register storage unit and the level one data cache;

[0067] Step S700: The prefetch request is sent to the memory system.

[0068] In this embodiment, by the second data locality information, the prefetch block with data locality is confirmed, and the prefetch request is generated, so that all cache lines of the prefetch block with data locality outside the missing information state holding register storage unit and the level one data cache are prefetched into the level one data cache, reducing on-chip storage resource competition and reducing cache jitter.

[0069] It should be noted that the to-be-taken cache line is stored in the cache line in the level two data cache, DRAM or other cache structure.

[0070] An embodiment of the present application further illustrates the “generating a prefetch request” in step S600, and step S600 includes but is not limited to step S610.

[0071] Step S610: The data amount of the missing information state holding register storage unit is obtained, and if the data amount is less than the preset first data amount threshold, a prefetch request is generated.

[0072] In this embodiment, on the existing general-purpose graphics processor architecture, when the on-chip storage resource is saturated, the level one data cache will reject new memory access requests, resulting in serialization processing of subsequent memory access requests and reducing the memory parallelism of the graphics processor. Therefore, by confirming the data amount of the missing information state holding register storage unit, if the data amount is greater than the preset first data amount threshold, it indicates that the on-chip storage resource is saturated, and the generated prefetch request is stopped, avoiding the competition of the thread group for the storage resource.

[0073] It can be understood that the value of the preset first data amount threshold is not limited.

[0074] An embodiment of the present application further illustrates the “sending the prefetch request to the memory system” in step S700, for example,Figure 3 As shown, step S700 includes but is not limited to step S6710, step S720 and step S730.

[0075] Step S710: store the prefetch request in the load-store unit;

[0076] Step S720: obtain the number of memory access requests in the load-store unit;

[0077] Step S730: when the number of memory access requests is zero, send the prefetch request to the memory system.

[0078] In this embodiment, by storing the prefetch request in the load-store unit, when there is no memory access request to be sent in the load-store unit, the prefetch request is sent to the memory system to request to fetch the to-be-fetched cache line of the target prefetch block into the level-1 data cache.

[0079] In an embodiment of the present application, the step S100 of "sequencing the plurality of thread groups according to the priority of the plurality of thread groups" is further explained, and step S100 includes but is not limited to step S110.

[0080] Step S110: finely sequencing the plurality of thread groups according to the priority of the plurality of thread groups.

[0081] In this embodiment, the plurality of thread groups are finely sequenced according to the priority of the thread groups, and the thread groups with higher priority are arranged preferentially.

[0082] In an embodiment of the present application, after the step S300 of "performing scheduling operation on the target thread group in the target thread group sequence", it further includes but is not limited to step S310.

[0083] Step S310: reducing the priority of the target thread group.

[0084] In this embodiment, after the target thread group is scheduled, the priority of the target thread group is reduced to avoid continuous execution of the target thread group.

[0085] It should be noted that by setting the same initial priority score for the plurality of thread groups, the priority of the thread groups is determined by the priority score of the thread groups, and after confirming that the thread group is the target thread group, the first score value is added to the initial priority score of the target thread group, thereby increasing the priority of the target thread group, and after the target thread group is scheduled, the second score value is reduced to reduce the priority of the target thread group.

[0086] It can be understood that after the target thread group is scheduled, the second score value is reduced, and when the priority score of the target thread group is reduced to the initial priority score, it is no longer reduced.

[0087] It should be noted that the initial priority score, the first score value and the second score value are not limited, for example, the initial priority score can be 100, the first score value can be 30, and the second score value can be 1.

[0088] In an embodiment of the present application, the step S200 of "merging the first transition thread group sequence and the second transition thread group sequence" is further illustrated as shown in the following table. Figure 4

[0089] Step S210: Acquire the data amount of the missing information state holding register storage unit.

[0090] Step S220: If the data amount is greater than the preset second data amount threshold, add the second transition thread group sequence to the tail of the first transition thread group sequence, otherwise add the first transition thread group sequence to the tail of the second transition thread group sequence to obtain the target thread group sequence.

[0091] It should be noted that the existing thread scheduling method basically adopts a round-robin scheduling strategy, and each thread group has equal scheduling opportunities. However, under the round-robin scheduling strategy, it is easy to execute the calculation instructions of each calculation thread group in turn, and then execute the memory access instructions of each memory access thread group in turn. At this time, the instructions of basically all thread groups are long-delay memory access instructions, and there are no more schedulable thread groups to hide the delay, resulting in that the memory access delay in the general-purpose graphics processor is not effectively hidden, and the performance is lost.

[0092] In the embodiment, by acquiring the data amount of the missing information state holding register storage unit, if the data amount is less than the preset second data amount threshold, the first transition thread group sequence is added to the tail of the second transition thread group sequence, the memory access thread group is preferentially scheduled, so that the memory access delay of the memory access thread group is effectively hidden by the calculation instructions of the calculation thread group; if the data amount is greater than the second preset data amount threshold, it indicates that the on-chip storage resource utilization rate is close to saturation, the second transition thread group sequence is added to the tail of the first transition thread group sequence, so that the calculation thread group is preferentially scheduled and executed, the problem of on-chip storage resource competition is alleviated, the cache jitter condition is reduced, and the performance of the graphics processor is improved. It can be understood that the value of the second preset data amount threshold is not limited.

[0093] It should be noted that the first preset data amount threshold can have the same value as the second preset data amount threshold, that is, when it is detected that the data amount of the missing information state holding register storage unit is greater than the first preset data amount value, the prefetch request is stopped, and the priority of the calculation thread group is improved, effectively reducing the problem of on-chip storage resource competition.

[0094] ​Some embodiments of the present application further illustrate the step S300 of "performing scheduling operation on the target thread group sequence", as shown in the following. Figure 5 The step S300 includes but is not limited to the step S310 and the step S320.

[0095] The step S310: sequentially numbering the plurality of thread groups in the target thread group sequence.

[0096] The step S320: performing scheduling operation on the plurality of thread groups in the target thread group sequence according to the numbering order.

[0097] In the present embodiment, the plurality of thread groups in the target thread group sequence are sequentially numbered from small to large, so as to perform scheduling on the target thread group with the smallest number according to the thread group number information.

[0098] In addition, an embodiment of the present application further discloses a general-purpose graphic processor for executing the above-mentioned thread group scheduling method.

[0099] In the present embodiment, according to the first data locality information, the thread groups with data locality in the first initial thread group sequence and the second initial thread group sequence are confirmed as the priority thread groups, the priority of the priority thread groups is improved, the first initial thread group sequence and the second initial thread group sequence are sorted according to the priority respectively, the first transition thread group sequence and the second transition thread group sequence are obtained respectively, the first transition thread group sequence and the second transition thread group sequence are merged, the target thread group sequence is obtained, and the thread groups to be scheduled in the target thread group sequence are scheduled. The general-purpose graphic processor of the present embodiment can preferentially schedule the thread groups with data locality, reduce the cache jitter, and improve the performance of the general-purpose graphic processor.

[0100] In addition, an embodiment of the present application further discloses a computer readable storage medium, wherein a processor executable program is stored, and the processor executable program is executed by a processor to implement the above-mentioned thread group scheduling method.

[0101] In the present embodiment, according to the first data locality information, the thread groups with data locality in the first initial thread group sequence and the second initial thread group sequence are confirmed as the priority thread groups, the priority of the priority thread groups is improved, the first initial thread group sequence and the second initial thread group sequence are sorted according to the priority respectively, the first transition thread group sequence and the second transition thread group sequence are obtained respectively, the first transition thread group sequence and the second transition thread group sequence are merged, the target thread group sequence is obtained, and the thread groups to be scheduled in the target thread group sequence are scheduled. The computer readable storage medium of the present embodiment can preferentially schedule the thread groups with data locality, reduce the cache jitter, and improve the performance of the general-purpose graphic processor.

[0102] Those of ordinary skill in the art will appreciate that all or certain steps, systems in the methods disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Certain physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on computer readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, information structures, program modules or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it is common knowledge to those of ordinary skill in the art that communication media typically embodies computer readable instructions, information structures, program modules or other information in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

[0103] The above detailed description of the application has been made in connection with the accompanying drawings, but the application is not limited to the above-described embodiments, and can be changed within the scope of knowledge of those of ordinary skill in the art without departing from the spirit of the application.

Claims

1. A thread group scheduling method, characterized in that: include: Acquiring first data locality information, performing a sorting operation on a first initial thread group sequence to obtain a first transition thread group sequence, and performing the sorting operation on a second initial thread group sequence to obtain a second transition thread group sequence, wherein the first initial thread group sequence includes a plurality of computing thread groups, each of which is a thread group for executing computing instructions, and the second initial thread group sequence includes a plurality of memory access thread groups, each of which is a thread group for executing memory access instructions; The sorting operation includes: traversing each of the thread groups, and when it is determined according to the first data locality information that a priority thread group exists, increasing the priority of the priority thread group, and sorting the multiple thread groups according to the priorities of the multiple thread groups, the prefetch block includes multiple cache lines, the first data locality information is used to represent the number of cache lines of the prefetch block requested by the thread group in the missing information status holding register storage unit, the priority thread group is the thread group for which the number of cache lines requesting the same prefetch block is greater than a preset request number threshold, or is multiple thread groups requesting the same prefetch block at the same time, and the number of cache lines requested by the multiple thread groups is greater than the preset request number threshold; Merging the first transition thread group sequence and the second transition thread group sequence to obtain a target thread group sequence; A scheduling operation is performed on a target thread group in the target thread group sequence, where the target thread group is the thread group to be scheduled in the target thread group sequence.

2. The thread group scheduling method according to claim 1, characterized in that: Also includes: Obtaining second data locality information, where the second data locality information is used to represent the sum of the number of cache lines of the prefetch block requested by the thread group in the miss information status holding register storage unit and the first-level data cache; Determining a target prefetch block based on the second data locality information and the plurality of prefetch blocks, the target prefetch block being the prefetch block for which the sum of the number of cache lines in the miss information status holding register storage unit and the first-level data cache is greater than a preset prefetch block locality threshold; generating a prefetch request, the prefetch request being used to request sending a to-be-fetched cache line of a target prefetch block to the primary data cache, the to-be-fetched cache line being the cache line that has not been sent to the miss information status holding register storage unit and the primary data cache; The prefetch request is sent to a memory system.

3. The thread group scheduling method according to claim 2, characterized in that: The generating of the prefetch request comprises: The data amount of the missing information status holding register storage unit is obtained, and if the data amount is less than a preset first data amount threshold, the pre-fetch request is generated.

4. The thread group scheduling method according to claim 2, characterized in that: The sending the prefetch request to the memory system includes: storing the prefetch request in a load store unit; Obtaining the number of memory access requests in the load storage unit; When the number of memory access requests is zero, the prefetch request is sent to the memory system.

5. The thread group scheduling method according to claim 1, characterized in that: The sorting of the plurality of thread groups according to their priorities includes: The plurality of thread groups are finely sorted according to their priorities.

6. The thread group scheduling method according to claim 1, characterized in that: After the scheduling operation is performed on the target thread group in the target thread group sequence, the method further includes: reducing the priority of the target thread group.

7. The thread group scheduling method according to claim 1, characterized in that: The merging of the first transition thread group sequence and the second transition thread group sequence includes: Acquire the data amount of the missing information status holding register storage unit; If the data volume is greater than a preset second data volume threshold, the second transition thread group sequence is added to the end of the first transition thread group sequence; otherwise, the first transition thread group sequence is added to the end of the second transition thread group sequence to obtain a target thread group sequence.

8. The thread group scheduling method according to claim 1, characterized in that: The scheduling operation on the target thread group in the target thread group sequence includes: Sequentially numbering the plurality of thread groups in the target thread group sequence; A scheduling operation is performed on the plurality of thread groups in the target thread group sequence according to the numbering order.

9. A general-purpose graphics processor, characterized in that: Used to execute the thread group scheduling method described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that A program executable by a processor is stored therein, and when the program executable by the processor is executed by the processor, it is used to implement the thread group scheduling method according to any one of claims 1 to 8.

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