Pixel circuit, driving method thereof, display substrate and display device

Abstract

A pixel circuit and a driving method thereof, a display substrate and a display device, wherein the pixel circuit is located in the display substrate, the display substrate comprises a first driving mode and a second driving mode, the pixel circuit comprises a first node control sub-circuit, a second node control sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit; the first node control sub-circuit is configured to provide a signal of an initial signal terminal to a first node and a fourth node under the control of a first reset signal terminal and a second scan signal terminal, and provide a signal of a second node to the first node under the control of a third scan signal terminal; the second node control sub-circuit is configured to provide a signal of a reference signal terminal to the second node and a signal of a data signal terminal to a third node under the control of a second reset signal terminal and a first scan signal terminal; a voltage value of a signal of the reference signal terminal in the first driving mode is different from a voltage value of a signal in the second driving mode.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a pixel circuit and its driving method, a display substrate, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure provides a pixel circuit located in a display substrate and configured to drive a light-emitting element to emit light. The display substrate includes a first driving mode and a second driving mode, wherein the refresh rate of the first driving mode is less than the refresh rate of the second driving mode. The pixel circuit includes a first node control sub-circuit, a second node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit.

[0005] The first node control sub-circuit is electrically connected to the first power supply terminal, the first reset signal terminal, the initial signal terminal, the second scan signal terminal, the third scan signal terminal, the first node, the second node, and the fourth node, respectively. It is configured to provide the initial signal terminal to the first node and the fourth node under the control of the first reset signal terminal and the second scan signal terminal, and to provide the second node to the first node under the control of the third scan signal terminal.

[0006] The second node control sub-circuit is electrically connected to the second reset signal terminal, the reference signal terminal, the first scan signal terminal, the data signal terminal, the second node, and the third node, respectively. It is configured to provide the reference signal terminal to the second node and the data signal terminal to the third node under the control of the second reset signal terminal and the first scan signal terminal.

[0007] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide driving current to the third node under the control of the first node and the second node;

[0008] The light-emitting control sub-circuit is electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node under the control of the light-emitting signal terminal.

[0009] The light-emitting element is electrically connected to the fourth node and the second power supply terminal, respectively.

[0010] The voltage value of the signal at the reference signal terminal in the first driving mode is different from the voltage value of the signal in the second driving mode.

[0011] In some possible implementations, the first reset signal terminal and the second reset signal terminal are the same signal terminal.

[0012] In some possible implementations, the voltage value of the signal at the reference signal terminal in the first driving mode is less than the voltage value of the signal in the second driving mode;

[0013] The voltage value of the signal at the reference signal terminal is greater than or equal to the voltage value of the signal at the initial signal terminal.

[0014] In some possible implementations, when the signals of the first reset signal terminal and the second reset signal terminal are valid level signals, the signal of the second scan signal terminal is a valid level signal, and the signals of the first scan signal terminal, the third scan signal terminal and the light emission signal terminal are invalid level signals.

[0015] When the signal at the first scan signal terminal is a valid level signal, the signal at the third scan signal terminal is a valid level signal, and the signals at the first reset signal terminal, the second reset signal terminal, the second scan signal terminal, and the light emission signal terminal are invalid level signals.

[0016] When the signal at the light-emitting signal terminal is an effective level signal, the signals at the first reset signal terminal, the second reset signal terminal, the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal are invalid level signals.

[0017] In some possible implementations, the first node control sub-circuit includes: a reset sub-circuit, a compensation sub-circuit, and a storage sub-circuit;

[0018] The reset sub-circuit is electrically connected to the first reset signal terminal, the initial signal terminal, the second scan signal terminal, the first node, and the fourth node, respectively, and is configured to provide the initial signal terminal to the first node and the fourth node under the control of the first reset signal terminal and the second scan signal terminal;

[0019] The compensation sub-circuit is electrically connected to the first node, the second node and the third scanning signal terminal respectively, and is configured to provide the signal of the second node to the first node under the control of the third scanning signal terminal;

[0020] The storage sub-circuit is electrically connected to the first power supply terminal and the first node, respectively, and is configured to store the voltage difference between the signal of the first power supply terminal and the signal of the first node.

[0021] In some possible implementations, the second node control subcircuit includes: a control subcircuit and a write subcircuit;

[0022] The control sub-circuit is electrically connected to the second reset signal terminal, the reference signal terminal, and the second node, respectively, and is configured to provide the reference signal terminal to the second node under the control of the second reset signal terminal;

[0023] The writing sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal, and the third node, respectively, and is configured to provide the data signal terminal to the third node under the control of the first scan signal terminal.

[0024] In some possible implementations, the reset sub-circuit includes a first transistor and a second transistor, the compensation sub-circuit includes a seventh transistor, and the storage sub-circuit includes a capacitor, the capacitor including a first plate and a second plate.

[0025] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node.

[0026] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fourth node.

[0027] The control electrode of the seventh transistor is electrically connected to the third scan signal terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the second node.

[0028] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0029] In some possible implementations, the write sub-circuit includes a fourth transistor, and the control sub-circuit includes an eighth transistor;

[0030] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node.

[0031] The control electrode of the eighth transistor is electrically connected to the third scan signal terminal, the first electrode of the eighth transistor is electrically connected to the reference signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node.

[0032] In some possible implementations, the first node control sub-circuit includes: a first transistor, a second transistor, a seventh transistor, and a capacitor, the capacitor including: a first plate and a second plate; the second node control sub-circuit includes: a fourth transistor and an eighth transistor; the driving sub-circuit includes: a third transistor; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor.

[0033] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node.

[0034] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fourth node.

[0035] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0036] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node.

[0037] The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0038] The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0039] The control electrode of the seventh transistor is electrically connected to the third scan signal terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the second node.

[0040] The control electrode of the eighth transistor is electrically connected to the third scan signal terminal, the first electrode of the eighth transistor is electrically connected to the reference signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node.

[0041] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0042] In some possible implementations, the transistor types of the first, third through sixth, and eighth transistors are opposite to those of the second and seventh transistors;

[0043] The second and seventh transistors are oxide transistors.

[0044] Secondly, this disclosure also provides a display substrate, comprising: a substrate and a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate, wherein the light-emitting structure layer comprises: a light-emitting element, and the circuit structure layer comprises: the aforementioned pixel circuits arranged in an array.

[0045] In some possible implementations, the circuit structure layer further includes: a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of third scan signal lines, a plurality of light emission signal lines, a plurality of initial signal lines, and a plurality of reference signal lines extending along a first direction and arranged along a second direction, as well as a plurality of first power supply lines and a plurality of data signal lines extending along the second direction and arranged along the first direction, wherein the first direction intersects the second direction;

[0046] The pixel circuit has a first reset signal terminal electrically connected to a first reset signal line, a second reset signal terminal electrically connected to a second reset signal line, a first scan signal terminal electrically connected to a first scan signal line, a second scan signal terminal electrically connected to a second scan signal line, a third scan signal terminal electrically connected to a third scan signal line, an emission signal terminal electrically connected to an emission signal line, an initial signal terminal electrically connected to an initial signal line, a reference signal terminal electrically connected to a reference signal line, a first power supply terminal electrically connected to a first power supply line, and a data signal terminal electrically connected to a data signal line.

[0047] In some possible implementations, the pixel structure of adjacent pixel circuits in the same row is symmetrical with respect to a dummy straight line extending along the second direction;

[0048] The adjacent pixel circuits located in the same row as the pixel circuits include: the first adjacent pixel circuit and the second adjacent pixel circuit.

[0049] In some possible implementations, the pixel circuit includes: a first transistor to an eighth transistor, wherein the gate electrode of the second transistor and the gate electrode of the seventh transistor both include: a first gate electrode and a second gate electrode;

[0050] The second scan signal line includes: a first sub-scan signal line and a second sub-scan signal line that are disposed on different layers and interconnected with each other; the first gate electrode of the second transistor is disposed on the same layer as the first sub-scan signal line; and the second gate electrode of the second transistor is disposed on the same layer as the second sub-scan signal line.

[0051] The third scan signal line includes a third sub-scan signal line and a fourth sub-scan signal line that are disposed on different layers and interconnected. The first gate electrode of the seventh transistor is disposed on the same layer as the third sub-scan signal line, and the second gate electrode of the seventh transistor is disposed on the same layer as the fourth sub-scan signal line.

[0052] In some possible implementations, the pixel circuit further includes a capacitor, which includes a first electrode and a second electrode. The circuit structure layer includes a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fourth conductive layer, a first planarization layer, and a fifth conductive layer, which are sequentially stacked on the substrate.

[0053] The first semiconductor layer includes: an active layer of a first transistor located in at least one pixel circuit, active layers of a third transistor to a sixth transistor, and an active layer of an eighth transistor.

[0054] The first conductive layer includes: a first reset signal line, a second reset signal line, a first scan signal line, a light emission signal line, and a first plate of a capacitor located in at least one pixel circuit, a gate electrode of a first transistor, a gate electrode of a third transistor, a gate electrode of a fourth transistor, a gate electrode of a fifth transistor, a gate electrode of a sixth transistor, and a gate electrode of an eighth transistor.

[0055] The second conductive layer includes: a first sub-scan signal line, a third sub-scan signal line, and a second plate of a capacitor located in at least one pixel circuit, a first gate electrode of a second transistor, and a first gate electrode of a seventh transistor;

[0056] The second semiconductor layer includes: an active layer of a second transistor and an active layer of a seventh transistor located in at least one pixel circuit;

[0057] The third conductive layer includes: a reference signal line, a second sub-scan signal line, a fourth sub-scan signal line, and a second gate electrode of a second transistor and a second gate electrode of a seventh transistor located in at least one pixel circuit;

[0058] The fourth conductive layer includes: an initial signal line and the first and second poles of a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor located in at least one pixel circuit;

[0059] The fifth conductive layer includes: a first power line, a data signal line, and a connection electrode located in at least one pixel circuit, with the light-emitting element connected to the connection circuit.

[0060] In some possible implementations, the second reset signal line and the first scan signal line connected to the pixel circuit are located on the same side of the first plate of the capacitor of the pixel circuit, and the second reset signal line is located on the side of the first scan signal line away from the first plate of the capacitor of the pixel circuit.

[0061] The light-emitting signal line and the first reset signal line connected to the pixel circuit are located on the side of the first electrode of the pixel circuit away from the first scan signal line, and the first reset signal line is located on the side of the light-emitting signal line away from the first electrode of the capacitor of the pixel circuit.

[0062] The first scan signal line includes: a scan main body and a scan connection part, wherein one end of the scan connection part is connected to the scan main body;

[0063] The scanning main body extends along the first direction, and the scanning connection part is "L" shaped.

[0064] In some possible implementations, the first reset signal line includes: a plurality of first reset connection portions and a plurality of second reset connection portions spaced apart, wherein the second reset connection portions are disposed between two adjacent first reset connection portions and connected to the two adjacent first reset connection portions; the second reset signal line includes: a plurality of third reset connection portions and a plurality of fourth reset connection portions spaced apart, wherein the fourth reset connection portions are disposed between two adjacent third reset connection portions and connected to the adjacent third reset connection portions;

[0065] The first reset connection and the third reset connection extend along the first direction. The second reset connection has an opening facing the opening of the light-emitting signal line. The fourth reset connection has an opening facing away from the opening of the first scan signal line. A virtual straight line extending along the second direction passes through the second reset connection of the first reset signal line and the fourth reset connection of the second reset signal line.

[0066] The gate electrode of the first transistor and the first reset connection portion of the first reset signal line are integrally formed, and the gate electrode of the eighth transistor and the fourth reset connection portion of the second reset signal line are integrally formed.

[0067] In some possible implementations, the second plates of capacitors in adjacent pixel circuits located in the same row are connected;

[0068] The first sub-scan signal line of the second scan signal line and the third sub-scan signal line of the third scan signal line connected to the pixel circuit are respectively located on opposite sides of the second plate of the capacitor in the pixel circuit;

[0069] The first sub-scan signal line and the first gate electrode of the second transistor are integrally formed, and the third sub-scan signal line and the first gate electrode of the seventh transistor are integrally formed.

[0070] The orthographic projection of the first sub-scan signal line on the substrate is located between the orthographic projection of the light-emitting signal line on the substrate and the orthographic projection of the first reset signal line on the substrate;

[0071] The orthographic projection of the third sub-scan signal line on the substrate overlaps with the orthographic projection of the scan connection portion of the first scan signal line on the substrate, and the orthographic projection on the substrate is located between the orthographic projection of the scan body portion of the first scan signal line on the substrate and the orthographic projection of the second plate of the capacitor of the connected pixel circuit on the substrate.

[0072] In some possible implementations, the second sub-scan signal line and the second gate electrode of the second transistor are integrally formed, and the fourth sub-scan signal line and the second gate electrode of the seventh transistor are integrally formed.

[0073] The orthographic projection of the second sub-scan signal line onto the substrate at least partially overlaps with the orthographic projection of the first sub-scan signal line onto the substrate.

[0074] The orthographic projection of the fourth sub-scan signal line onto the substrate at least partially overlaps with the orthographic projection of the third sub-scan signal line onto the substrate;

[0075] The orthographic projection of the reference signal line onto the substrate overlaps with the orthographic projection of the second reset signal line onto the substrate.

[0076] In some possible implementations, the fifth insulating layer includes: a plurality of via patterns, the plurality of via patterns including: a first via to a sixth via formed on the first to fifth insulating layers, a seventh via formed on the second to fifth insulating layers, an eighth via formed on the third to fifth insulating layers, a ninth and a tenth via formed on the fourth and fifth insulating layers, and an eleventh via formed on the fifth insulating layer, wherein the eighth via exposes the second plate of the capacitor, and the eleventh via exposes the reference signal line;

[0077] The virtual straight line extending along the second direction passes through the eighth and eleventh vias;

[0078] The eighth via of the pixel circuit is the same as the eighth via of the first adjacent pixel circuit, and the eleventh via of the pixel circuit is the same as the eleventh via of the first adjacent pixel circuit.

[0079] In some possible implementations, the first electrode of the fifth transistor of the pixel circuit is the same electrode as the first electrode of the fifth transistor of the first adjacent pixel circuit, and the first electrode of the eighth transistor of the pixel circuit is the same electrode as the first electrode of the eighth transistor of the first adjacent pixel circuit.

[0080] The orthographic projection of the initial signal line on the substrate overlaps with the orthographic projection of the second reset connection portion of the first reset signal line on the substrate.

[0081] The second electrode of the first transistor, the second electrode of the second transistor, and the second electrode of the sixth transistor are integrally formed, and their orthogonal projections on the substrate overlap with the orthogonal projections of the second scan signal line and the light emission signal line on the substrate.

[0082] The orthographic projection of the first electrode of the fifth transistor onto the substrate overlaps with the orthographic projection of the second electrode of the capacitor and the light-emitting signal line connected to the pixel circuit onto the substrate, and the first electrode of the fifth transistor includes an opening facing the second scan signal line connected to the pixel circuit.

[0083] The first electrode of the second transistor and the first electrode of the seventh transistor are integrally formed, and their orthogonal projection on the substrate overlaps with the orthogonal projection of the light-emitting signal line connected to the second electrode plate of the capacitor and the pixel circuit on the substrate.

[0084] The second electrode of the seventh transistor and the second electrode of the eighth transistor are integrally formed, and their orthogonal projections on the substrate overlap with the orthogonal projections of the first scan signal line connected to the pixel circuit and the third scan signal line connected to the pixel circuit on the substrate.

[0085] The orthographic projection of the first electrode of the eighth transistor onto the substrate overlaps with the orthographic projection of the reference signal line connected to the pixel circuit onto the substrate.

[0086] In some possible implementations, the first power line connected to the pixel circuit is the same power line as the first power line connected to the first adjacent pixel circuit.

[0087] The data signal line and the first power line connected to the pixel circuit are located on both sides of the connecting electrode, and the length of the first power line along the first direction is greater than the length of the data signal line along the first direction.

[0088] In some possible implementations, the first power line connected to the pixel circuit may include: a first power supply section, a second power supply section and a third power supply section arranged sequentially along the second direction, wherein the second power supply section is connected to the first power supply section and the third power supply section respectively;

[0089] The length of the third power supply unit along the first direction is greater than the length of the first power supply unit along the first direction, and the length of the first power supply unit along the first direction is greater than the length of the second power supply unit along the first direction.

[0090] The connection electrode of the pixel circuit is located on the side of the second power supply section of the pixel circuit, near the data signal line connected to the pixel circuit.

[0091] In some possible implementations, the orthographic projection of the first power line on the substrate overlaps with the orthographic projections of the integrally formed structures of the first pole of the fifth transistor, the first pole of the first transistor, the first pole of the second transistor, and the first pole of the seventh transistor, as well as the integrally formed structures of the second pole of the seventh transistor and the second pole of the eighth transistor on the substrate.

[0092] Thirdly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0093] Fourthly, this disclosure also provides a method for driving a pixel circuit, configured to drive the aforementioned pixel circuit, the method comprising:

[0094] The first node control sub-circuit, under the control of the first reset signal terminal and the second scan signal terminal, provides the initial signal terminal signal to the first node and the fourth node; the second node control sub-circuit, under the control of the second reset signal terminal and the first scan signal terminal, provides the reference signal terminal signal to the second node.

[0095] Under the control of the third scan signal terminal, the first node control sub-circuit provides the second node signal to the first node. Under the control of the second reset signal terminal and the first scan signal terminal, the second node control sub-circuit provides the data signal terminal signal to the third node.

[0096] The driving sub-circuit, under the control of the first and second nodes, provides driving current to the third node. The light-emitting control sub-circuit, under the control of the light-emitting signal terminal, provides the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node.

[0097] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0098] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0099] Figure 1 This is a schematic diagram of the pixel circuit in the display substrate provided in an embodiment of the present disclosure;

[0100] Figure 2 A schematic diagram of the structure of a first node control sub-circuit provided for an exemplary embodiment;

[0101] Figure 3 A schematic diagram of the structure of a second node control sub-circuit provided for an exemplary embodiment;

[0102] Figure 4An equivalent circuit diagram of a first node control sub-circuit provided for an exemplary embodiment;

[0103] Figure 5 An equivalent circuit diagram of a second node control sub-circuit provided for an exemplary embodiment;

[0104] Figure 6 An equivalent circuit diagram of a pixel circuit provided for an exemplary embodiment;

[0105] Figure 7 for Figure 6 The provided timing diagram for the pixel circuit;

[0106] Figure 8 This is a schematic diagram after the semiconductor layer pattern has been formed;

[0107] Figure 9A This is a schematic diagram of the pattern of the first conductive layer;

[0108] Figure 9B This is a schematic diagram after the first conductive layer pattern has been formed;

[0109] Figure 10A This is a schematic diagram of the pattern of the second conductive layer;

[0110] Figure 10B This is a schematic diagram after the second conductive layer pattern has been formed;

[0111] Figure 11A This is a schematic diagram of the pattern of the second semiconductor layer;

[0112] Figure 11B This is a schematic diagram after the second semiconductor layer pattern has been formed;

[0113] Figure 12A This is a schematic diagram of the pattern of the third conductive layer;

[0114] Figure 12B This is a schematic diagram after the third conductive layer pattern has been formed;

[0115] Figure 13A This is a schematic diagram of the fifth insulating layer pattern;

[0116] Figure 13B This is a schematic diagram showing the pattern after the fifth insulating layer has been formed.

[0117] Figure 14A This is a schematic diagram of the pattern of the fourth conductive layer;

[0118] Figure 14B This is a schematic diagram after the fourth conductive layer pattern has been formed;

[0119] Figure 15A This is a schematic diagram of the pattern of the first flattening layer;

[0120] Figure 15B This is a schematic diagram after the first flattening layer pattern has been formed;

[0121] Figure 16A This is a schematic diagram of the pattern of the fifth conductive layer;

[0122] Figure 16B This is a schematic diagram after the fifth conductive layer pattern has been formed;

[0123] Figure 17A This is a schematic diagram of the pattern of the second flattening layer;

[0124] Figure 17B This is a schematic diagram showing the formation of the second flattening layer pattern;

[0125] Figure 18A This is a schematic diagram of the anode layer pattern;

[0126] Figure 18B This is a schematic diagram after the anode layer pattern has been formed. Detailed Implementation

[0127] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0128] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0129] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0130] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0131] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0132] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0133] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0134] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0135] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0136] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0137] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0138] The display device includes pixel circuitry that drives light-emitting elements to emit light. The display device has two driving modes: a first driving mode and a second driving mode. The refresh rate (also known as the display frequency) of the first driving mode is lower than that of the second driving mode. This first driving mode can be referred to as a low-frequency driving mode, and the second driving mode as a high-frequency driving mode. The pixel circuitry cannot simultaneously meet the driving requirements of both the first and second driving modes, and it cannot dynamically control the gate voltage of the driving transistors when switching between different driving modes, thus reducing the reliability of the display device.

[0139] Figure 1 This is a schematic diagram of the pixel circuit in a display substrate provided in an embodiment of this disclosure. Figure 1 As shown, the pixel circuit provided in this embodiment is located in a display substrate and is configured to drive the light-emitting element to emit light. The display substrate includes a first driving mode and a second driving mode. The refresh rate of the first driving mode is less than the refresh rate of the second driving mode. The pixel circuit includes a first node control sub-circuit, a second node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit.

[0140] In this disclosure, the first node control sub-circuit is electrically connected to the first power supply terminal VDD, the first reset signal terminal Reset1, the initial signal terminal Vinit, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the first node N1, the second node N2, and the fourth node N4, respectively. It is configured to provide the initial signal terminal Vinit to the first node N1 and the fourth node N4 under the control of the first reset signal terminal Reset1 and the second scan signal terminal Gate2, and to provide the second node N2 signal to the first node N1 under the control of the third scan signal terminal Gate3. The second node N2 control sub-circuit is connected to the second reset signal terminal Reset2, the reference signal terminal Vref, the first scan signal terminal Gate1, the data signal terminal Data, and the second node N4, respectively. Point N2 and the third node N3 are electrically connected and configured to provide the reference signal terminal Vref to the second node N2 and the data signal terminal Data to the third node N3 under the control of the second reset signal terminal Reset2 and the first scan signal terminal Gate1. The driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3 respectively and is configured to provide the driving current to the third node N3 under the control of the first node N1 and the second node N2. The light emission control sub-circuit is electrically connected to the light emission signal terminal EM, the first power supply terminal VDD, the second node N2, the third node N3 and the fourth node N4 respectively and is configured to provide the first power supply terminal VDD to the second node N2 and the third node N3 signal to the fourth node N4 under the control of the light emission signal terminal EM.

[0141] In this disclosure, the voltage value of the reference signal terminal Vref in the first driving mode is different from the voltage value of the signal in the second driving mode.

[0142] In one exemplary embodiment, the refresh rate of the first driving mode can be 1Hz-60Hz, and the refresh rate of the second driving mode can be 60Hz-480Hz. For example, the refresh rate of the first driving mode can be 1Hz, and the refresh rate of the second driving mode can be 120Hz. The content displayed on the display substrate includes multiple display frames. In the first driving mode, the display frames include a refresh frame and at least one hold frame. In the second driving mode, the display frames only include a refresh frame.

[0143] In one exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the second power supply terminal VSS continuously provides a low-level signal.

[0144] In one exemplary embodiment, the light-emitting element is electrically connected to the fourth node N4 and the second power supply terminal VSS, respectively.

[0145] In one exemplary embodiment, the light-emitting element may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. Exemplarily, the anode of the organic light-emitting diode is electrically connected to a fourth node N4, and the cathode of the organic light-emitting diode is electrically connected to a second power supply terminal VSS.

[0146] In one exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0147] This disclosure provides a pixel circuit configured to drive a light-emitting element to emit light. The pixel circuit includes: a first node control subcircuit, a second node control subcircuit, a light-emitting control subcircuit, and a driving subcircuit. The first node control subcircuit is electrically connected to a first power supply terminal, a first reset signal terminal, an initial signal terminal, a second scan signal terminal, a third scan signal terminal, a first node, a second node, and a fourth node, respectively. It is configured to provide the initial signal terminal to the first node and the fourth node under the control of the first reset signal terminal and the second scan signal terminal, and to provide the second node signal to the first node under the control of the third scan signal terminal. The second node control subcircuit is electrically connected to a second reset signal terminal, a reference signal terminal, a first scan signal terminal, a data signal terminal, a second node, and a third node, respectively. The system is configured to provide a reference signal to the second node and a data signal to the third node under the control of the second reset signal terminal and the first scan signal terminal. A driving sub-circuit, electrically connected to the first, second, and third nodes respectively, is configured to provide a driving current to the third node under the control of the first and second nodes. A light-emitting control sub-circuit, electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node respectively, is configured to provide a signal from the first power supply terminal to the second node and a signal from the third node to the fourth node under the control of the light-emitting signal terminal. A light-emitting element is electrically connected to the fourth node and the second power supply terminal respectively. The voltage value of the reference signal terminal in the first driving mode is different from the voltage value of the signal in the second driving mode. This disclosure, through the configuration of the first and second node control sub-circuits, can stabilize the voltages of the first, second, and fourth nodes, and provide different signals to the second node in different driving modes. This allows for dynamic adjustment of the second node's signal, enabling the pixel circuit to simultaneously meet the driving requirements of both the first and second driving modes. Furthermore, it allows for dynamic control of the gate voltage of the driving transistor during switching between different driving modes, improving the reliability of the display device.

[0148] In one exemplary embodiment, the first reset signal terminal Reset1 and the second reset signal terminal Reset2 can be the same signal terminal. Exemplarily, the first reset signal terminal Reset1 and the second reset signal terminal Reset2 can be connected to the same signal line, or connected to two different signal lines with the same signal; this disclosure does not impose any limitations.

[0149] In one exemplary embodiment, when the signals of the first reset signal terminal Reset1 and the second reset signal terminal Reset2 are valid level signals, the signal of the second scan signal terminal Gate2 is valid level signal, and the signals of the first scan signal terminal Gate1, the third scan signal terminal Gate3 and the light emission signal terminal EM are invalid level signals.

[0150] In an exemplary embodiment, when the signal of the first scan signal terminal Gate1 is an effective level signal, the signal of the third scan signal terminal Gate3 is also an effective level signal, and the signals of the first reset signal terminal Reset1, the second reset signal terminal Reset2, the second scan signal terminal Gate2, and the light emission signal terminal EM are ineffective level signals.

[0151] In one exemplary embodiment, when the signal of the light-emitting signal terminal EM is an effective level signal, the first reset signal terminal Reset1, the second reset signal terminal Reset2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are invalid level signals.

[0152] In one exemplary embodiment, the voltage value of the signal when the reference signal terminal Vref is at an active level is greater than the voltage value of the signal when the initial signal terminal Vinit is at an active level. In this disclosure, the voltage value of the signal when the reference signal terminal Vref is at an active level is greater than the voltage value of the signal when the initial signal terminal Vinit is at an active level, allowing charging of the second node N2 to be performed when the signal at the third scan signal terminal is at an active level, thereby improving the charging efficiency of the first node N1.

[0153] In one exemplary embodiment, the voltage value of the reference signal terminal Vref in the first driving mode may be less than the voltage value of the reference signal terminal Vref in the second driving mode.

[0154] In one exemplary embodiment, in the first driving mode, the signal of the reference signal terminal Vref may be the same as or greater than the signal of the initial signal terminal Vinit, and this disclosure does not limit it in any way.

[0155] In one exemplary embodiment, the voltage value of the signal when the initial signal terminal Vinit in the first driving mode is an active level signal can be equal to the voltage value of the signal when the initial signal terminal Vinit in the second driving mode is an active level signal.

[0156] In one exemplary embodiment, Figure 2 A schematic diagram of the structure of the first node control sub-circuit provided for an exemplary embodiment is shown below. Figure 2 As shown, in one exemplary embodiment, the first node control sub-circuit may include: a reset sub-circuit, a compensation sub-circuit, and a storage sub-circuit.

[0157] like Figure 2As shown, the reset sub-circuit is electrically connected to the first reset signal terminal Reset1, the initial signal terminal Vinit, the second scan signal terminal Gate2, the first node N1, and the fourth node N4, respectively. It is configured to provide the initial signal terminal Vinit signal to the first node N1 and the fourth node N4 under the control of the first reset signal terminal Reset1 and the second scan signal terminal Gate2. The compensation sub-circuit is electrically connected to the first node N1, the second node N2, and the third scan signal terminal Gate3, respectively. It is configured to provide the second node N2 signal to the first node N1 under the control of the third scan signal terminal Gate3. The storage sub-circuit is electrically connected to the first power supply terminal VDD and the first node N1, respectively. It is configured to store the voltage difference between the signal of the first power supply terminal VDD and the signal of the first node N1.

[0158] In one exemplary embodiment, Figure 3 A schematic diagram of the structure of the second node control sub-circuit provided as an exemplary embodiment is shown below. Figure 3 As shown, in one exemplary embodiment, the second node control subcircuit may include a control subcircuit and a write subcircuit.

[0159] like Figure 3 As shown, the control sub-circuit is electrically connected to the second reset signal terminal Reset2, the reference signal terminal Vref, and the second node N2, respectively. It is configured to provide the reference signal terminal Vref to the second node N2 under the control of the second reset signal terminal Reset2. The write sub-circuit is electrically connected to the first scan signal terminal Gate1, the data signal terminal Data, and the third node N3, respectively. It is configured to provide the data signal terminal Data to the third node N3 under the control of the first scan signal terminal Gate1.

[0160] Figure 4 An equivalent circuit diagram of a first node control sub-circuit provided for an exemplary embodiment, such as... Figure 4 As shown, in an exemplary embodiment, the reset sub-circuit may include: a first transistor T1 and a second transistor T2; the compensation sub-circuit may include: a seventh transistor T7; and the storage sub-circuit may include: a capacitor C, wherein the capacitor C includes: a first plate C1 and a second plate C2.

[0161] like Figure 4As shown, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal Vinit, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal Gate3, the first electrode of the seventh transistor T7 is electrically connected to the first node N1, and the second electrode of the seventh transistor T7 is electrically connected to the second node N2; the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the first power supply terminal VDD.

[0162] Figure 4 An exemplary structure of the first node control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first node control sub-circuit is not limited to this.

[0163] Figure 5 An equivalent circuit diagram of the second node control sub-circuit provided for an exemplary embodiment is shown below. Figure 5 As shown, in one exemplary embodiment, the writing sub-circuit may include a fourth transistor T4, and the control sub-circuit may include an eighth transistor T8.

[0164] like Figure 5 As shown, the control terminal of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is electrically connected to the third node N3; the control terminal of the eighth transistor T8 is electrically connected to the third scan signal terminal Gate3, the first terminal of the eighth transistor T8 is electrically connected to the reference signal terminal Vref, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2.

[0165] In one exemplary embodiment, the write sub-circuit may include: a plurality of fourth transistors connected in series, wherein the control electrode of all fourth transistors is electrically connected to the first scan signal terminal Gate1, the first electrode of the first fourth transistor T4 is electrically connected to the data signal terminal Data, the second electrode of the i-th fourth transistor T4 is electrically connected to the first electrode of the (i+1)-th fourth transistor T4, and the second electrode of the last fourth transistor T4 is electrically connected to the third node N3. The plurality of fourth transistors connected in series can reduce the leakage current of the pixel circuit, avoid the abnormality of the pixel circuit caused by the failure of one of the fourth transistors to work properly, and improve the reliability of the pixel circuit. Figure 5 The explanation is based on the example of a writing sub-circuit including two fourth transistors.

[0166] Figure 5An exemplary structure of the second node control sub-circuit is shown. It will be readily understood by those skilled in the art that the implementation of the second node control sub-circuit is not limited to this.

[0167] Figure 6 An equivalent circuit diagram of a pixel circuit provided for an exemplary embodiment, such as... Figure 6 As shown, in an exemplary embodiment, the first node control sub-circuit may include: a first transistor T1, a second transistor T2, a seventh transistor T7, and a capacitor C, wherein the capacitor C includes: a first plate C1 and a second plate C2; ​​the second node control sub-circuit may include: a fourth transistor T4 and an eighth transistor T8; the driving sub-circuit may include: a third transistor T3; and the light-emitting control sub-circuit may include: a fifth transistor T5 and a sixth transistor T6.

[0168] like Figure 6 As shown, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal Vinit, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is connected to the light emission signal terminal... The first terminal of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. The control terminal of the sixth transistor T6 is electrically connected to the light emission signal terminal EM, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4. The control terminal of the seventh transistor T7 is electrically connected to the third scan signal terminal Gate3, the first terminal of the seventh transistor T7 is electrically connected to the first node N1, and the second terminal of the seventh transistor T7 is electrically connected to the second node N2. The control terminal of the eighth transistor T8 is electrically connected to the third scan signal terminal Gate3, the first terminal of the eighth transistor T8 is electrically connected to the reference signal terminal Vref, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2. The first plate C1 of capacitor C is electrically connected to the first node N1, and the second plate C2 of capacitor C is electrically connected to the first power supply terminal VDD.

[0169] In one exemplary embodiment, the third transistor T3 can be referred to as the driving transistor, and the third transistor T3 determines the driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS based on the potential difference between its control terminal and the first terminal.

[0170] In one exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When the signal at the light-emitting signal terminal EM is an active level signal, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting element to emit light by forming a drive current path between the first power supply terminal VDD and the second power supply terminal VSS.

[0171] Figure 6 An exemplary structure of the driving subcircuit and the light-emitting control subcircuit is shown. It will be readily understood by those skilled in the art that the implementation of the driving subcircuit and the light-emitting control subcircuit is not limited to this. Figure 6 This explanation uses two fourth transistors as an example.

[0172] In one exemplary embodiment, some of the transistors in the first transistor T1 to the eighth transistor T8 can be oxide transistors, and some transistors can be low-temperature polysilicon transistors. Oxide transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0173] In one exemplary embodiment, the transistor types of the first transistor T1, the third transistors T3 through T6, and the eighth transistor T8 are opposite to those of the second transistor T2 and the seventh transistor T7. For example, the first transistor T1, the third transistors T3 through T6, and the eighth transistor T8 are P-type transistors, and the second transistor T2 and the seventh transistor T7 are N-type transistors.

[0174] In one exemplary embodiment, the first transistor T1, the third transistors T3 to T6 and the eighth transistor T8 can be low-temperature polysilicon transistors, and the second transistor T2 and the seventh transistor T7 can be oxide transistors.

[0175] In one exemplary embodiment, the second transistor T2 and the seventh transistor T7 connected to the first node N1 are oxide transistors, which can effectively reduce the leakage current of the first node N1, maintain the voltage stability of the first node N1, improve the voltage holding capability of the first node in the first driving mode, and improve the compatibility of the display substrate.

[0176] In one exemplary embodiment, the Data signal at the Data terminal is written to the third node N3 when the signal at the first scan signal terminal Gate1 is at an active level. The first node N1 and the second node N2 are short-circuited when the signal at the third scan signal terminal Gate3 is at an active level. Therefore, the compensation path for the threshold voltage of the driving transistor is from the third node N3 through the second node N2 to the first node N1. The second node N2 writes the reference signal Vref signal when the reset signal at the Reset terminal is at an active level. The reference signal Vref signal can be dynamically adjusted according to different driving modes. When the pixel circuit operates in the second driving mode, when the reset signal at the Reset terminal is at an active level, the reference signal terminal can write a signal with a higher voltage value than the reference signal terminal signal in the first driving mode, that is, pre-charging the second node N2. This can improve the charging efficiency of the first node N1 and improve the compensation effect of the threshold voltage of the transistor in the second driving mode, so that the pixel circuit provided by this disclosure can simultaneously meet the requirements of the first driving mode and the second driving mode.

[0177] In one exemplary embodiment, the signals at different reference signal terminals Vref can increase the bias magnitude of the gate-source voltage difference of the driving transistor, thereby improving the hysteresis degradation of the light-emitting device caused by unidirectional bias.

[0178] In one exemplary embodiment, the eighth transistor T8 is connected to the reference signal terminal Vref and the second node N2, and is also connected to the first node N1 via a seventh transistor, which is an oxide transistor. The first node N1 and the second node N2 are the gate electrode and source electrode of the driving transistor, respectively. Therefore, the connection method of the eighth transistor and the seventh transistor allows for high adjustability of the gate-source voltage difference of the driving transistor, enabling dynamic control of the gate voltage of the driving transistor when switching between different driving modes.

[0179] In one exemplary embodiment, the signal of the initial signal terminal Vinit is used to reset the first node N1 and the fourth node N4. The first transistor T1 controls the signal of the initial signal terminal Vinit to be written to the fourth node N4, and the second transistor T2, which is an oxide transistor, controls the signal of the fourth node N4 to be written to the first node N1. This disclosure simplifies the pixel circuit by resetting the first node N1 and the fourth node N4 through the same initial signal terminal Vinit.

[0180] In an exemplary embodiment, when the first reset signal terminal Reset1 and the second reset signal terminal Reset2 are the same signal terminal, the first transistor T1 and the eighth transistor T8 can be provided with signals by separate driving circuits. In the first driving mode, the driving circuit that provides signals to the light emission signal terminal and the circuit that provides signals to the first reset signal terminal and the second reset signal terminal can be refreshed at high frequency. This can realize the signal reset of the fourth node N4 and the signal function of providing a reference signal terminal to the second node, thus ensuring the stability of the signals of the second node N2 and the fourth node N4.

[0181] The following is through Figure 6 The operation of the example pixel circuit illustrates an exemplary embodiment of this disclosure.

[0182] Figure 7 for Figure 6 The provided timing diagram of the pixel circuit is shown. Figure 6 This explanation uses the example of transistors T1, T3 through T6, and T8 being P-type transistors, and transistors T2 and T7 being N-type transistors. Figure 6 The pixel circuit includes transistors T1 to T8, a capacitor C, and 10 signal terminals (data signal terminal Data, first scan signal terminal Gate1, second scan signal terminal Gate2, third scan signal terminal Gate3, first reset signal terminal Reset1, second reset signal terminal Reset2, light emission signal terminal EM, initial signal terminal Vinit, reference signal terminal Vref, and first power supply terminal VDD). Figure 7 This explanation uses the example of the first reset signal terminal Reset1 and the second reset signal terminal Reset2 being the same signal terminal. Figure 6 The operation of the pixel circuit can include:

[0183] In the first stage P1, called the initialization stage, the signals of the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the third scan signal terminal Gate3 are low-level signals, while the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the light emission signal terminal EM are high-level signals. When the first reset signal terminal Reset1 and the second reset signal terminal Reset2 are low-level signals, and the second scan signal terminal Gate2 is high-level signals, the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned on. The initial signal terminal Vinit is provided to the fourth node N4 through the first transistor T1, and also to the first node N1 through the first transistor T1 and the second transistor T2, initializing (resetting) the first node N1, clearing its internal pre-stored voltage, and completing the initialization. The reference signal terminal Vref is provided to the second node N2 through the eighth transistor T8, resetting the second node N2. The signal at the third scan signal terminal Gate3 is a low-level signal, while the signals at the first scan signal terminal Gate1 and the light-emitting signal terminal EM are high-level signals. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are cut off. During this stage, the light-emitting element L does not emit light.

[0184] The second stage, P2, is called the data writing stage or threshold compensation stage. The signals at the first scan signal terminal (Gate1) and the second scan signal terminal (Gate2) are low-level signals, while the signals at the third scan signal terminal (Gate3), the first reset signal terminal (Reset1), the second reset signal terminal (Reset2), and the light emission signal terminal (EM) are high-level signals. The data signal terminal (Data) outputs a data voltage. During this stage, since the first node (N1) is a low-level signal, the third transistor (T3) is turned on. When the signal at the first scan signal terminal (Gate1) is low, the fourth transistor (T4) is turned on. When the signal at the third scan signal terminal (Gate3) is high, the seventh transistor (T7) is turned on. The data voltage output from the data signal terminal (Data) is supplied to the first node (N1) via the turned-on fourth transistor (T4), the third node (N3), the turned-on third transistor (T3), the second node (N2), and the turned-on seventh transistor (T7). The difference between the data voltage output from the data signal terminal (Data) and the threshold voltage of the third transistor (T3) is charged into capacitor C until the voltage at the first node (N1) is Vd - |Vth|, where Vd is the data voltage output from the data signal terminal (Data) and Vth is the threshold voltage of the third transistor (T3). The signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the light-emitting signal terminal EM are all high-level signals, while the signal at the second scan signal terminal Gate2 is low-level. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are all cut off. During this stage, the light-emitting element L does not emit light.

[0185] In the third stage, P3, known as the light-emitting stage, the signals at the light-emitting signal terminal EM, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are low-level signals, while the signals at the first scan signal terminal Gate1, the first reset signal terminal Reset1, and the second reset signal terminal Reset2 are high-level signals. When the signals at the second scan signal terminal Gate2 and the third scan signal terminal Gate3 are low-level signals, and the signals at the first scan signal terminal Gate1, the first reset signal terminal Reset1, and the second reset signal terminal Reset2 are high-level signals, the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are cut off. With the light-emitting signal terminal EM low-level, the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting element L through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element L to emit light.

[0186] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is:

[0187] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0188] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0189] Simulation tests show that the voltage value of the signal at the reference signal terminal of the pixel circuit provided in this embodiment is 6V, and the driving current is approximately the same under different gray levels (e.g., L0, L127, and L255). Therefore, the pixel circuit provided in this embodiment can meet the writing requirements of different gray levels and complete the threshold compensation of the threshold voltage of the driving transistor.

[0190] Simulation tests show that the driving circuits of the pixel circuits provided in this embodiment are roughly the same under the same gray level (e.g., L127) and different reference signal voltage values ​​(-1V, 2V, 4V, 6V). Therefore, the pixel circuits provided in this embodiment can operate at the same gray level voltage without being affected by the reference signal terminal Vref.

[0191] The voltage value of the reference signal terminal is 6V. The driving current is approximately the same under different gray levels (L0 and L255). Therefore, the embodiments of this disclosure can meet the writing requirements of different gray level voltages and complete the threshold compensation of the threshold voltage of the driving transistor.

[0192] This disclosure also provides a display substrate, including: a substrate and a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate, the light-emitting structure layer including: light-emitting elements, and the circuit structure layer including: pixel circuits arranged in an array.

[0193] The pixel circuit is the same as the pixel circuit provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0194] In one exemplary embodiment, the display substrate may be a low-temperature polycrystalline oxide (LTPO) display substrate.

[0195] In one exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and conductive foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In one exemplary embodiment, the light-emitting structure layer includes: an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer sequentially stacked on the substrate; the anode layer includes an anode; the organic structure layer includes an organic light-emitting layer; and the cathode layer includes a cathode.

[0196] In one exemplary embodiment, the light-emitting element may include: a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element, wherein the first light-emitting element emits red light, the second light-emitting element emits blue light, and the third and fourth light-emitting elements emit green light; the area of ​​the anode of the second light-emitting element is larger than the area of ​​the anode of the first light-emitting element, and the anodes of the third and fourth light-emitting elements are symmetrical about a virtual straight line extending along a first direction.

[0197] In one exemplary embodiment, the circuit structure layer may further include: a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of third scan signal lines, a plurality of light emission signal lines, a plurality of initial signal lines, and a plurality of reference signal lines extending along a first direction and arranged along a second direction, and a plurality of first power supply lines and a plurality of data signal lines extending along the second direction and arranged along the first direction, wherein the first direction intersects the second direction.

[0198] The pixel circuit has a first reset signal terminal electrically connected to a first reset signal line, a second reset signal terminal electrically connected to a second reset signal line, a first scan signal terminal electrically connected to a first scan signal line, a second scan signal terminal electrically connected to a second scan signal line, a third scan signal terminal electrically connected to a third scan signal line, an emission signal terminal electrically connected to an emission signal line, an initial signal terminal electrically connected to an initial signal line, a reference signal terminal electrically connected to a reference signal line, a first power supply terminal electrically connected to a first power supply line, and a data signal terminal electrically connected to a data signal line.

[0199] In one exemplary embodiment, the pixel structure of adjacent pixel circuits located in the same row is symmetrical with respect to a dummy straight line extending along a second direction. The adjacent pixel circuits located in the same row as the pixel circuits include: a first adjacent pixel circuit and a second adjacent pixel circuit.

[0200] In one exemplary embodiment, the pixel circuit may include: a first transistor to an eighth transistor.

[0201] In one exemplary embodiment, the gate electrode of the second transistor is a dual-gate structure, meaning the gate electrode of the second transistor includes a first gate electrode and a second gate electrode disposed on different layers. The dual-gate structure of the second transistor's gate electrode can improve its conduction capability.

[0202] In one exemplary embodiment, the gate electrode of the seventh transistor is a dual-gate structure, meaning the gate electrode of the seventh transistor includes a first gate electrode and a second gate electrode disposed on different layers. The dual-gate structure of the seventh transistor's gate electrode can improve the conduction capability of the second transistor.

[0203] In one exemplary embodiment, the second scan signal line includes a first sub-scan signal line and a second sub-scan signal line that are disposed on different layers and interconnected. The first gate electrode of the second transistor is disposed on the same layer as the first sub-scan signal line, and the second gate electrode of the second transistor is disposed on the same layer as the second sub-scan signal line.

[0204] In one exemplary embodiment, the first sub-scan signal line and the second sub-scan signal line can be arranged parallel to each other in the display area of ​​the display substrate and interconnected in the non-display area.

[0205] In one exemplary embodiment, the third scan signal line includes a third sub-scan signal line and a fourth sub-scan signal line that are disposed on different layers and interconnected. The first gate electrode of the seventh transistor is disposed on the same layer as the third sub-scan signal line, and the second gate electrode of the seventh transistor is disposed on the same layer as the fourth sub-scan signal line.

[0206] In one exemplary embodiment, the third sub-scan signal line and the fourth sub-scan signal line can be arranged in parallel in the display area of ​​the display substrate and interconnected in the non-display area.

[0207] In one exemplary embodiment, the pixel circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate. The circuit structure layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fourth conductive layer, a first planarization layer, and a fifth conductive layer, which are sequentially stacked on the substrate.

[0208] In one exemplary embodiment, the first semiconductor layer may include: an active layer of a first transistor located in at least one pixel circuit, active layers of a third transistor to a sixth transistor, and an active layer of an eighth transistor.

[0209] In one exemplary embodiment, the first conductive layer may include: a first reset signal line, a second reset signal line, a first scan signal line, a light emission signal line, and a first electrode of a capacitor located in at least one pixel circuit, a gate electrode of a first transistor, a gate electrode of a third transistor, a gate electrode of a fourth transistor, a gate electrode of a fifth transistor, a gate electrode of a sixth transistor, and a gate electrode of an eighth transistor.

[0210] In one exemplary embodiment, the second conductive layer may include: a first sub-scan signal line, a third sub-scan signal line, and a second plate of a capacitor located in at least one pixel circuit, a first gate electrode of a second transistor, and a first gate electrode of a seventh transistor;

[0211] In one exemplary embodiment, the second semiconductor layer may include: an active layer of a second transistor and an active layer of a seventh transistor located in at least one pixel circuit;

[0212] In one exemplary embodiment, the third conductive layer may include: a reference signal line, a second sub-scan signal line and a fourth sub-scan signal line, as well as a second gate electrode of a second transistor and a second gate electrode of a seventh transistor located in at least one pixel circuit;

[0213] In one exemplary embodiment, the fourth conductive layer may include: an initial signal line and a first and second pole of a first transistor, a first and second pole of a second transistor, a first pole of a fourth transistor, a first pole of a fifth transistor, a second pole of a sixth transistor, a first and second pole of a seventh transistor, and a first and second pole of an eighth transistor located in at least one pixel circuit.

[0214] In one exemplary embodiment, the fifth conductive layer may include: a first power line, a data signal line, and a connection electrode located in at least one pixel circuit, wherein the light-emitting element is connected to the connection circuit.

[0215] In one exemplary embodiment, the second reset signal line and the first scan signal line connected to the pixel circuit are located on the same side of the first plate of the capacitor of the pixel circuit, and the second reset signal line is located on the side of the first scan signal line away from the first plate of the capacitor of the pixel circuit; the light emission signal line and the first reset signal line connected to the pixel circuit are located on the side of the first plate of the pixel circuit away from the first scan signal line, and the first reset signal line is located on the side of the light emission signal line away from the first plate of the capacitor of the pixel circuit.

[0216] In one exemplary embodiment, the display substrate includes a display area and a non-display area, and a pixel circuit is located in the display area. The display substrate may further include a scan driving circuit, a light-emitting driving circuit, and a reset driving circuit located in the non-display area. The scan driving circuit is electrically connected to a first scan signal line, a second scan signal line, and a third scan signal line, respectively. The light-emitting driving circuit is electrically connected to a light-emitting signal line, respectively. The reset driving circuit is electrically connected to a first reset signal line and a second reset signal line, respectively.

[0217] In one exemplary embodiment, the first scan signal line includes a scan main body and a scan connection part, wherein one end of the scan connection part is connected to the scan main body; the scan main body extends along a first direction, and the scan connection part is L-shaped.

[0218] In one exemplary embodiment, the first reset signal line includes: a plurality of first reset connection portions and a plurality of second reset connection portions spaced apart, wherein the second reset connection portions are disposed between and connected to adjacent first reset connection portions; the second reset signal line includes: a plurality of third reset connection portions and a plurality of fourth reset connection portions spaced apart, wherein the fourth reset connection portions are disposed between and connected to adjacent third reset connection portions; the first reset connection portions and the third reset connection portions extend along a first direction, the second reset connection portions have openings facing the light-emitting signal line, and the fourth reset connection portions have openings facing away from the openings of the first scan signal line; a virtual straight line extending along a second direction passes through the second reset connection portions of the first reset signal line and the fourth reset connection portions of the second reset signal line.

[0219] In one exemplary embodiment, the gate electrode of the first transistor and the first reset connection portion of the first reset signal line are integrally formed, and the gate electrode of the eighth transistor and the fourth reset connection portion of the second reset signal line are integrally formed.

[0220] In one exemplary embodiment, the second plates of capacitors in adjacent pixel circuits located in the same row are connected.

[0221] In one exemplary embodiment, the first sub-scanning signal line of the second scan signal line connected to the pixel circuit and the third sub-scanning signal line of the third scan signal line are respectively located on opposite sides of the second electrode plate of the capacitor of the pixel circuit; the first sub-scanning signal line and the first gate electrode of the second transistor are integrally formed, and the third sub-scanning signal line and the first gate electrode of the seventh transistor are integrally formed; the orthographic projection of the first sub-scanning signal line on the substrate is located between the orthographic projection of the light-emitting signal line on the substrate and the orthographic projection of the first reset signal line on the substrate; the orthographic projection of the third sub-scanning signal line on the substrate overlaps with the orthographic projection of the scan connection portion of the first scan signal line on the substrate, and the orthographic projection on the substrate is located between the orthographic projection of the scan body portion of the first scan signal line on the substrate and the orthographic projection of the second electrode plate of the capacitor of the connected pixel circuit on the substrate.

[0222] In one exemplary embodiment, the second sub-scan signal line and the second gate electrode of the second transistor are integrally formed, and the fourth sub-scan signal line and the second gate electrode of the seventh transistor are integrally formed; the orthographic projection of the second sub-scan signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-scan signal line on the substrate; the orthographic projection of the fourth sub-scan signal line on the substrate at least partially overlaps with the orthographic projection of the third sub-scan signal line on the substrate; and the orthographic projection of the reference signal line on the substrate partially overlaps with the orthographic projection of the second reset signal line on the substrate.

[0223] In one exemplary embodiment, the fifth insulating layer includes a plurality of via patterns, including: a first to a sixth via formed on the first to fifth insulating layers, a seventh via formed on the second to fifth insulating layers, an eighth via formed on the third to fifth insulating layers, a ninth and a tenth via formed on the fourth and fifth insulating layers, and an eleventh via formed on the fifth insulating layer, wherein the eighth via exposes the second electrode of the capacitor, and the eleventh via exposes a reference signal line.

[0224] In one exemplary embodiment, a virtual straight line extending along a second direction passes through an eighth via and an eleventh via.

[0225] In one exemplary embodiment, the eighth via of the pixel circuit is the same as the eighth via of the first adjacent pixel circuit, and the eleventh via of the pixel circuit is the same as the eleventh via of the first adjacent pixel circuit.

[0226] In one exemplary embodiment, the first terminal of the fifth transistor of the pixel circuit is the same as the first terminal of the fifth transistor of the first adjacent pixel circuit, and the first terminal of the eighth transistor of the pixel circuit is the same as the first terminal of the eighth transistor of the first adjacent pixel circuit.

[0227] In one exemplary embodiment, the orthographic projection of the initial signal line on the substrate overlaps with the orthographic projection of the second reset connection portion of the first reset signal line on the substrate.

[0228] In one exemplary embodiment, the second electrode of the first transistor, the second electrode of the second transistor, and the second electrode of the sixth transistor are integrally formed, and their orthogonal projections on the substrate overlap with the orthogonal projections of the second scan signal line and the light emission signal line on the substrate.

[0229] The orthographic projection of the first electrode of the fifth transistor onto the substrate overlaps with the orthographic projection of the second electrode of the capacitor and the light-emitting signal line connected to the pixel circuit onto the substrate, and the first electrode of the fifth transistor includes an opening facing the second scan signal line connected to the pixel circuit.

[0230] The first electrode of the second transistor and the first electrode of the seventh transistor are integrally formed, and their orthogonal projection on the substrate overlaps with the orthogonal projection of the light-emitting signal line connected to the second electrode plate of the capacitor and the pixel circuit on the substrate.

[0231] The second electrode of the seventh transistor and the second electrode of the eighth transistor are integrally formed, and their orthogonal projections on the substrate overlap with the orthogonal projections of the first scan signal line connected to the pixel circuit and the third scan signal line connected to the pixel circuit on the substrate.

[0232] The orthographic projection of the first electrode of the eighth transistor onto the substrate overlaps with the orthographic projection of the reference signal line connected to the pixel circuit onto the substrate.

[0233] In one exemplary embodiment, the first power line connected to the pixel circuit and the first power line connected to the first adjacent pixel circuit are the same power line.

[0234] In one exemplary embodiment, the data signal line and the first power line connected to the pixel circuit are located on both sides of the connecting electrode, and the length of the first power line along the first direction is greater than the length of the data signal line along the first direction.

[0235] In one exemplary embodiment, the first power line connected to the pixel circuit may include: a first power section, a second power section, and a third power section arranged sequentially along a second direction, wherein the second power section is connected to the first power section and the third power section respectively; the length of the third power section along the first direction is greater than the length of the first power section along the first direction, and the length of the first power section along the first direction is greater than the length of the second power section along the first direction; the connection electrode of the pixel circuit is located on the side of the second power section of the pixel circuit near the data signal line connected to the pixel circuit.

[0236] In one exemplary embodiment, the orthographic projection of the first power line on the substrate overlaps with the orthographic projection of the integrally formed structures of the first pole of the fifth transistor, the first pole of the first transistor, the first pole of the second transistor, and the first pole of the seventh transistor, as well as the integrally formed structures of the second pole of the seventh transistor and the second pole of the eighth transistor on the substrate.

[0237] The structure of a display substrate is illustrated below using an example of the fabrication process of the display substrate. The "patterning process" described in this disclosure includes depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying and spin coating; and etching can be performed using any one or more of dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process.

[0238] Figures 8 to 16B A schematic diagram of the fabrication process of a display substrate provided for an exemplary embodiment. Figures 8 to 16B This explanation uses a one-row, two-column pixel circuit as an example. For example... Figures 8 to 16B As shown, the fabrication process of a display substrate provided in an exemplary embodiment may include:

[0239] (1) Forming a first semiconductor layer pattern on a substrate includes: depositing a first semiconductor thin film on the substrate, and patterning the first semiconductor thin film using a patterning process to form a first semiconductor layer pattern, such as... Figure 8 As shown, Figure 8 This is a schematic diagram after the semiconductor layer pattern has been formed.

[0240] In one exemplary embodiment, such as Figure 8 As shown, the first semiconductor layer may include: an active layer T11 of a first transistor, an active layer T31 of a third transistor, an active layer T41 of a fourth transistor, an active layer T51 of a fifth transistor, an active layer T61 of a sixth transistor, and an active layer T81 of an eighth transistor located in at least one pixel circuit.

[0241] In one exemplary embodiment, the active layer T31 of the third transistor to the active layer T61 of the sixth transistor can be an integrally formed structure.

[0242] In one exemplary embodiment, the active layer T31 of the third transistor can be in the shape of a "π".

[0243] In one exemplary embodiment, the active layer of the third transistor includes a first side, a second side, a third side, and a fourth side, wherein the first side and the second side are disposed opposite to each other, and the third side and the fourth side are disposed opposite to each other. The active layer T41 of the fourth transistor and the active layer T61 of the sixth transistor are located on the first side of the active layer T31 of the third transistor and extend along a second direction. The active layer T51 of the fifth transistor is located on the second side of the active layer T31 of the third transistor and extends along the second direction. The active layer T11 of the first transistor is located on the third side of the active layer T31 of the third transistor and extends along the second direction. The active layer T81 of the eighth transistor is located on the fourth side of the active layer T31 of the third transistor and extends along the second direction.

[0244] (2) Forming a first conductive layer pattern includes: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive layer pattern located on the first insulating layer, such as... Figure 9A and Figure 9B As shown, where, Figure 9A This is a schematic diagram of the pattern of the first conductive layer. Figure 9B This is a schematic diagram after the first conductive layer pattern has been formed.

[0245] In one exemplary embodiment, such as Figure 9A and Figure 9B As shown, the first conductive layer may include: a first reset signal line RL1, a second reset signal line RL2, a first scan signal line GL1, a light emission signal line EL, and a first electrode C1 of a capacitor located in at least one pixel circuit, a gate electrode T12 of a first transistor, a gate electrode T32 of a third transistor, a gate electrode T42 of a fourth transistor, a gate electrode T52 of a fifth transistor, a gate electrode T62 of a sixth transistor, and a gate electrode T82 of an eighth transistor.

[0246] In one exemplary embodiment, such as Figure 9A and Figure 9B As shown, the second reset signal line RL2 and the first scan signal line GL1 connected to the pixel circuit are located on the same side of the first plate C1 of the capacitor in the pixel circuit, and the second reset signal line RL2 is located on the side of the first scan signal line GL1 away from the first plate C1 of the capacitor in the pixel circuit. The light emission signal line EL and the first reset signal line RL1 connected to the pixel circuit are located on the side of the first plate C1 of the pixel circuit away from the first scan signal line GL1, and the first reset signal line RL1 is located on the side of the light emission signal line EL away from the first plate C1 of the capacitor in the pixel circuit.

[0247] In one exemplary embodiment, the first reset signal line RL1 and the second reset signal line RL2 have the same shape and provide the same signal.

[0248] In one exemplary embodiment, the first reset signal line RL1 may include a plurality of first reset connection portions RL1A and a plurality of second reset connection portions RL1B spaced apart, wherein the second reset connection portions RL1B are disposed between two adjacent first reset connection portions RL1A and connected to the two adjacent first reset connection portions RL1A.

[0249] In one exemplary embodiment, such as Figure 9A As shown, the first reset connection portion RL1A extends along the first direction.

[0250] In one exemplary embodiment, such as Figure 9A As shown, the second reset connection part RL1B is provided with an opening, and the opening direction is towards the light-emitting signal line EL.

[0251] In one exemplary embodiment, such as Figure 9A As shown, the second reset connection RL1B may include: a first sub-connection RL1B_1, a second sub-connection RL1B_2, and a third sub-connection RL1B_3. The first sub-connection RL1B_1 and the third sub-connection RL1B_3 extend along a second direction, and the second sub-connection RL1B_2 extends along a first direction. The first sub-connection RL1B_1 is connected to one of the adjacent first reset connection RL1A and the second sub-connection RL1B_2 of the second reset connection RL1B, respectively. The third sub-connection RL1B_3 is connected to the second sub-connection RL1B_2 and the other adjacent first reset connection RL1A of the second reset connection RL1B, respectively.

[0252] In one exemplary embodiment, the second reset signal line RL2 may include a plurality of third reset connection portions RL2A and a plurality of fourth reset connection portions RL2B spaced apart, wherein the fourth reset connection portion RL2B is disposed between two adjacent third reset connection portions RL2A and is connected to the two adjacent third reset connection portions RL2A.

[0253] In one exemplary embodiment, the third reset connection portion RL2A extends along a first direction.

[0254] In one exemplary embodiment, such as Figure 9A As shown, the fourth reset connection part RL2B has an opening that is away from the first scan signal line GL1.

[0255] In one exemplary embodiment, such as Figure 9AAs shown, the fourth reset connection RL2B may include: a first sub-connection RL2B_1, a second sub-connection RL2B_2, and a third sub-connection RL2B_3. The first sub-connection RL2B_1 and the third sub-connection RL2B_3 extend along a second direction, and the second sub-connection RL2B_2 extends along a first direction. The first sub-connection RL2B_1 is connected to one of the adjacent third reset connection RL2A and the second sub-connection RL2B_2 of the fourth reset connection RL2B, respectively. The third sub-connection RL2B_3 is connected to the second sub-connection RL2B_2 and the other adjacent third reset connection RL2A of the fourth reset connection RL2B, respectively.

[0256] In one exemplary embodiment, the virtual straight line extending along the second direction passes through the second reset connection portion RL1B of the first reset signal line RL1 and the fourth reset connection portion RL2B of the second reset signal line RL2.

[0257] In one exemplary embodiment, the first scan signal line GL1 includes a scan body portion GL1A and a scan connection portion GL1B, wherein one end of the scan connection portion GL1B is connected to the scan body portion GL1A. The scan body portion GL1A extends along a first direction, and the scan connection portion GL1B is L-shaped.

[0258] In one exemplary embodiment, such as Figure 9A and Figure 9B As shown, for any pixel circuit, the gate electrode T12 of the first transistor and the first reset connection RL1A of the first reset signal line RL1 connected to the pixel circuit are integrally formed; the gate electrode T32 of the third transistor and the first plate C1 of the capacitor are integrally formed; the gate electrode T42 of the fourth transistor and the first scan signal line GL1 connected to the pixel circuit are integrally formed; the gate electrode T52 of the fifth transistor and the gate electrode T62 of the sixth transistor and the light emission signal line EL connected to the pixel circuit are integrally formed; and the gate electrode T82 of the eighth transistor and the fourth reset connection RL2B of the second reset signal line RL2 connected to the pixel circuit are integrally formed.

[0259] In one exemplary embodiment, the gate electrode T12 of the first transistor is disposed across the active layer of the first transistor, the gate electrode T32 of the third transistor is disposed across the active layer of the third transistor, the gate electrode T42 of the fourth transistor is disposed across the active layer of the fourth transistor, the gate electrode T52 of the fifth transistor is disposed across the active layer of the fifth transistor, the gate electrode T62 of the sixth transistor is disposed across the active layer of the first transistor, and the gate electrode T82 of the eighth transistor is disposed across the active layer of the eighth transistor. That is, the extending direction of the gate electrode of at least one transistor is perpendicular to the extending direction of the active layer.

[0260] In one exemplary embodiment, the process further includes a conductor-enhancing process. The conductor-enhancing process involves, after forming the first conductive layer pattern, using the semiconductor layer in the control electrode shielding region of multiple transistors (i.e., the region where the semiconductor layer overlaps with the control electrode) as the channel region of the transistor, and processing the semiconductor layer in the region not shielded by the first conductive layer into a conductor-enhancing layer to form the first electrode connection portion and the second electrode connection portion of the transistor. For example... Figure 9B As shown, the first electrode connection portion of the active layer of the third transistor can be reused as the first electrode T63 of the sixth transistor, the second electrode T44 of the fourth transistor, and the second electrode T34 of the third transistor, and the second electrode connection portion of the active layer of the third transistor can be reused as the second electrode T54 of the fifth transistor and the first electrode T33 of the third transistor.

[0261] (3) Forming a second conductive layer pattern includes: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; and patterning the second insulating film and the second conductive film using a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer. Figure 10A and Figure 10B As shown, Figure 10A This is a schematic diagram of the pattern of the second conductive layer. Figure 10B This is a schematic diagram after the second conductive layer pattern has been formed.

[0262] In one exemplary embodiment, such as Figure 10A and Figure 10B As shown, the second conductive layer may include: a first sub-scan signal line GL2A, a third sub-scan signal line GL3A, and a second plate C2 of a capacitor located in at least one pixel circuit, a first gate electrode T22A of a second transistor, and a first gate electrode T72A of a seventh transistor.

[0263] In one exemplary embodiment, the first gate electrode T22A of the second transistor and the first sub-scan signal line GL2A are integrally formed, and the first gate electrode T72A of the seventh transistor and the third sub-scan signal line GL3A are integrally formed.

[0264] In one exemplary embodiment, such as Figure 10A and Figure 10BAs shown, the first sub-scan signal line GL2A of the second scan signal line GL2 and the third sub-scan signal line GL3A of the third scan signal line GL3 connected to the pixel circuit are located on opposite sides of the second plate C2 of the capacitor of the pixel circuit. That is, the first sub-scan signal line GL2A of the second scan signal line GL2 connected to the pixel circuit is located on one side of the second plate of the capacitor of the pixel circuit, and the third sub-scan signal line GL3A of the third scan signal line GL3 connected to the pixel circuit is located on the other side of the second plate C2 of the capacitor of the pixel circuit.

[0265] In one exemplary embodiment, the orthographic projection of the second plate C2 of the capacitor in the pixel circuit onto the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor onto the substrate, and the second plate C2 of the capacitor is provided with a through hole V0 exposing the first plate of the capacitor.

[0266] In one exemplary embodiment, the orthographic projection of the third sub-scan signal line GL3A on the substrate overlaps with the orthographic projection of the scan connection portion of the first scan signal line GL1 on the substrate, and the orthographic projection on the substrate is located between the orthographic projection of the scan body portion of the first scan signal line GL1 on the substrate and the orthographic projection of the second plate C2 of the capacitor of the connected pixel circuit on the substrate.

[0267] In one exemplary embodiment, the orthographic projection of the first sub-scan signal line GL2A on the substrate is located between the orthographic projection of the light-emitting signal line EL on the substrate and the orthographic projection of the first reset signal line RL1 on the substrate, and there is no overlap with the orthographic projections of the active layer of the sixth transistor and the active layer of the first transistor on the substrate.

[0268] In one exemplary embodiment, the second plates C2 of capacitors in adjacent pixel circuits located in the same row are connected. Electrical connection of the second plates C2 of capacitors in adjacent pixel circuits located in the same row can improve the uniformity of the display substrate display.

[0269] (4) Forming a second semiconductor layer pattern includes: on a substrate on which the aforementioned pattern is formed, including: sequentially depositing a third insulating film and a second semiconductor film on the substrate, and patterning the third insulating film and the second semiconductor film using a patterning process to form a third insulating layer pattern and a second semiconductor layer pattern located on the third insulating layer, such as... Figure 11A and Figure 11B As shown, Figure 11A This is a schematic diagram of the pattern of the second semiconductor layer. Figure 11B This is a schematic diagram after the second semiconductor layer pattern has been formed.

[0270] In one exemplary embodiment, such as Figure 11A and Figure 11BAs shown, the second semiconductor layer may include: an active layer T21 of a second transistor located in at least one pixel circuit and an active layer T71 of a seventh transistor.

[0271] In one exemplary embodiment, such as Figure 11A and Figure 11B As shown, the active layer T21 of the second transistor and the active layer T71 of the seventh transistor extend along the second direction, and the virtual straight line extending along the second direction passes through the active layer T21 of the second transistor and the active layer T71 of the seventh transistor.

[0272] In one exemplary embodiment, the active layer T21 of the second transistor is disposed across the first gate electrode of the second transistor, and the active layer T71 of the seventh transistor is disposed across the first gate electrode of the seventh transistor.

[0273] (5) Forming a third conductive layer includes: sequentially depositing a fourth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; and patterning the fourth insulating film and the third conductive film using a patterning process to form a fourth insulating layer pattern and a third conductive layer pattern located on the fourth insulating layer. Figure 12A and Figure 12B As shown, Figure 12A This is a schematic diagram of the pattern of the third conductive layer. Figure 12B This is a schematic diagram after the third conductive layer pattern has been formed.

[0274] In one exemplary embodiment, such as Figure 12A and Figure 12B As shown, the third conductive layer may include: a reference signal line REFL, a second sub-scan signal line GL2B, a fourth sub-scan signal line GL3B, and a second gate electrode T22B of a second transistor and a gate electrode T72B of a seventh transistor located in at least one pixel circuit.

[0275] In one exemplary embodiment, such as Figure 12A and Figure 12B As shown, the second gate electrode T22B of the second transistor and the second sub-scan signal line GL2B are integrally formed. The gate electrode T72B of the seventh transistor and the fourth sub-scan signal line GL3B are integrally formed.

[0276] In one exemplary embodiment, such as Figure 12A and Figure 12B As shown, the orthogonal projection of the reference signal line REFL onto the substrate overlaps with the orthogonal projections of the second reset signal line RL2 and the active layer of the eighth transistor onto the substrate.

[0277] In one exemplary embodiment, such as Figure 12A and Figure 12BAs shown, the orthographic projection of the second sub-scan signal line GL2B on the substrate at least partially overlaps with the orthographic projection of the first sub-scan signal line on the substrate.

[0278] In one exemplary embodiment, such as Figure 12A and Figure 12B As shown, the orthographic projection of the fourth sub-scan signal line GL3B on the substrate at least partially overlaps with the orthographic projection of the third sub-scan signal line on the substrate.

[0279] In one exemplary embodiment, the second gate electrode T22B of the second transistor is disposed across the active layer of the second transistor, and the second gate electrode T72B of the seventh transistor is disposed across the active layer of the seventh transistor.

[0280] (6) Forming a fifth insulating layer pattern includes: depositing a fifth insulating film on a substrate having the aforementioned pattern, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer pattern covering the aforementioned pattern. The fifth insulating layer has multiple via patterns, such as... Figures 13A to 13B As shown, Figure 13A This is a schematic diagram of the fifth insulating layer pattern. Figure 13B This is a schematic diagram showing the formation of the fifth insulating layer pattern.

[0281] In one exemplary embodiment, such as Figure 13A As shown, the multiple via patterns include: a first via V1 to a sixth via V6 formed on the first to fifth insulating layers, a seventh via V7 formed on the second to fifth insulating layers, an eighth via V8 formed on the third to fifth insulating layers, a ninth via V9 and a tenth via V10 formed on the fourth and fifth insulating layers, and an eleventh via V11 formed on the fifth insulating layer. Specifically, the first via V1 exposes the active layer of the eighth transistor, the second via V2 exposes the active layer of the fourth transistor, the third via V3 exposes the active layer of the sixth transistor, the fourth via V4 exposes the active layer of the fifth transistor, the fifth via V5 exposes the first electrode of the third transistor, the sixth via V6 exposes the active layer of the first transistor, the seventh via V7 exposes the first electrode of the capacitor, the eighth via V8 exposes the second electrode of the capacitor, the ninth via V9 exposes the active layer of the seventh transistor, the tenth via 10 exposes the active layer of the second transistor, and the eleventh via V11 exposes the reference signal line REFL.

[0282] In one exemplary embodiment, such as Figure 13A and Figure 13BAs shown, the adjacent pixel circuits located in the same row as the pixel circuit include a first adjacent pixel circuit and a second adjacent pixel circuit. The eighth via of the pixel circuit and the eighth via of the first adjacent pixel circuit are the same via, and the eleventh via of the pixel circuit and the eleventh via of the first adjacent pixel circuit are the same via. Having the eighth via of the pixel circuit and the eighth via of the first adjacent pixel circuit share the same via, and having the eleventh via of the pixel circuit share the same via, simplifies the manufacturing process of the display substrate.

[0283] In one exemplary embodiment, such as Figure 13A and Figure 13B As shown, the virtual straight line extending along the second direction passes through the eighth via V8 and the eleventh via V11.

[0284] (7) Forming a fourth conductive layer pattern includes: depositing a fourth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern, such as... Figure 14A and Figure 14B As shown, Figure 14A This is a schematic diagram of the pattern of the fourth conductive layer. Figure 14B This is a schematic diagram after the fourth conductive layer pattern has been formed.

[0285] In one exemplary embodiment, such as Figure 14A and Figure 14B As shown, the fourth conductive layer may include: an initial signal line INITL and a first electrode T13 and a second electrode T14 of a first transistor, a first electrode T23 and a second electrode T24 of a second transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a second electrode T64 of a sixth transistor, a first electrode T73 and a second electrode T74 of a seventh transistor, and a first electrode T83 and a second electrode T84 of an eighth transistor.

[0286] In one exemplary embodiment, such as Figure 14A and Figure 14B As shown, the first electrode T53 of the fifth transistor in the pixel circuit is the same as the first electrode T53 of the fifth transistor in the first adjacent pixel circuit. The first electrode of the eighth transistor in the pixel circuit is the same as the first electrode of the eighth transistor in the first adjacent pixel circuit.

[0287] In one exemplary embodiment, such as Figure 14A and Figure 14BAs shown, the first electrode T13 of the first transistor and the initial signal line INITL are integrally formed. The second electrodes T14 of the first transistor, T24 of the second transistor, and T64 of the sixth transistor are integrally formed and are in an "L" shape. The first electrodes T23 of the second transistor and T73 of the seventh transistor are integrally formed and extend along the second direction. The second electrodes T74 of the seventh transistor and T84 of the eighth transistor are integrally formed and are in a "T" shape.

[0288] In one exemplary embodiment, such as Figure 14A and Figure 14B As shown, the orthographic projection of the initial signal line INITL on the substrate overlaps with the orthographic projection of the active layer of the first transistor and the second reset connection portion of the first reset signal line RL1 on the substrate.

[0289] In one exemplary embodiment, such as Figure 14A and Figure 14B As shown, the first terminal T83 of the eighth transistor is electrically connected to the active layer of the eighth transistor through the first via, and is electrically connected to the reference signal line REFL through the eleventh via. The first terminal T43 of the fourth transistor is electrically connected to the active layer of the fourth transistor through the second via. The second terminal T64 of the sixth transistor is electrically connected to the active layer of the sixth transistor through the third via. The first terminal T53 of the fifth transistor is electrically connected to the active layer of the fifth transistor through the fourth via, and is electrically connected to the second plate C2 of the capacitor through the eighth via. The first terminal T13 of the first transistor and the second terminal T53 of the second transistor are also connected to the active layer of the capacitor through the eleventh via. Terminal T14 is electrically connected to the active layer of the first transistor through the sixth via. The first terminal T73 and the second terminal T74 of the seventh transistor are electrically connected to the active layer of the seventh transistor through the ninth via. The first terminal T23 and the second terminal T24 of the second transistor are electrically connected to the active layer of the second transistor through the tenth via. The second terminal T84 of the eighth transistor and the second terminal T74 of the seventh transistor are also electrically connected to the first terminal of the third transistor through the fifth via. The first terminal T73 of the seventh transistor and the first terminal T23 of the second transistor are also electrically connected to the first plate through the seventh via.

[0290] In one exemplary embodiment, such as Figure 14A and Figure 14B As shown, the orthographic projection of the integrally formed structure of the second electrode T14 of the first transistor, the second electrode T24 of the second transistor, and the second electrode T64 of the sixth transistor on the substrate overlaps with the orthographic projections of the active layer of the first transistor, the active layer of the second transistor, the active layer of the sixth transistor, the second scan signal line GL2, and the light emission signal line EL on the substrate.

[0291] In one exemplary embodiment, such as Figure 14A and Figure 14BAs shown, the orthographic projection of the first electrode T53 of the fifth transistor on the substrate overlaps with the orthographic projection of the light-emitting signal line EL connected to the active layer of the fifth transistor, the second electrode of the capacitor, and the pixel circuit on the substrate.

[0292] In one exemplary embodiment, such as Figure 14A and Figure 14B As shown, the first terminal T53 of the fifth transistor includes an opening facing the second scan signal line GL2 to which the pixel circuit is connected.

[0293] In one exemplary embodiment, such as Figure 14A and Figure 14B As shown, the orthographic projection of the integral structure of the first electrode T23 of the second transistor and the first electrode T73 of the seventh transistor on the substrate overlaps with the orthographic projection of the active layer of the second transistor, the active layer of the seventh transistor, the second electrode plate C2 of the capacitor, and the light-emitting signal line EL connected to the pixel circuit on the substrate.

[0294] In one exemplary embodiment, such as Figure 14A and Figure 14B As shown, the orthographic projection of the integral structure of the second electrode T74 of the seventh transistor and the second electrode T84 of the eighth transistor on the substrate overlaps with the orthographic projection of the active layer of the seventh transistor, the active layer of the eighth transistor, the first scan signal line GL1 connected to the pixel circuit, and the third scan signal line GL3 connected to the pixel circuit on the substrate.

[0295] In one exemplary embodiment, the orthographic projection of the first electrode T83 of the eighth transistor onto the substrate overlaps with the orthographic projection of the reference signal line REFL, to which the active layer and pixel circuit of the eighth transistor are connected, onto the substrate.

[0296] (8) Forming a first planarization layer pattern includes: depositing a sixth insulating film on a substrate having the aforementioned pattern; patterning the sixth insulating film using a patterning process to form a sixth insulating layer; coating the sixth insulating layer with a first planarization film; and patterning the first planarization film using a patterning process to form a first planarization layer pattern covering the aforementioned pattern. The first planarization layer has multiple via patterns, such as... Figure 15A and Figure 15B As shown, Figure 15A This is a schematic diagram of the pattern of the first flattening layer. Figure 15B This is a schematic diagram after the first flattening layer pattern has been formed.

[0297] In one exemplary embodiment, such as Figure 15A and Figure 15BAs shown, the multiple via patterns include twelfth via V12 to fourteenth via V14 formed on the sixth insulating layer and the first planarization layer. Among them, twelfth via V12 exposes the first terminal of the fourth transistor, thirteenth via V13 exposes the second terminal of the sixth transistor, and fourteenth via V14 exposes the first terminal of the fifth transistor.

[0298] (9) Forming a fifth conductive layer pattern includes: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer pattern, such as... Figure 16A and Figure 16B As shown, Figure 16A This is a schematic diagram of the pattern of the fifth conductive layer. Figure 16B This is a schematic diagram after the fifth conductive layer pattern has been formed.

[0299] In one exemplary embodiment, such as Figure 16A and Figure 16B As shown, the fifth conductive layer may include: a first power line VDDL, a data signal line DL, and a connecting electrode VL.

[0300] In one exemplary embodiment, the data signal line DL and the first power supply line VDDL connected to the pixel circuit are located on both sides of the connecting electrode VL.

[0301] In one exemplary embodiment, the first power line connected to the pixel circuit is the same power line as the first power line connected to the first adjacent pixel.

[0302] In one exemplary embodiment, the first power line VDDL connected to the pixel circuit may include a first power supply section VDDL1, a second power supply section VDDL2, and a third power supply section VDDL3 arranged sequentially along a second direction, wherein the second power supply section VDDL2 is connected to the first power supply section VDDL1 and the third power supply section VDDL3 respectively.

[0303] In one exemplary embodiment, the length of the third power supply unit VDDL3 along the first direction is greater than the length of the first power supply unit VDDL1 along the first direction, and the length of the first power supply unit VDDL1 along the first direction is greater than the length of the second power supply unit VDDL2 along the first direction.

[0304] In one exemplary embodiment, the connection electrode VL of the pixel circuit is located on the side of the second power supply section VDDL2 of the pixel circuit near the data signal line DL to which the pixel circuit is connected.

[0305] In one exemplary embodiment, a recess is provided on the side of the first power line VDDL connected to the pixel circuit near the link electrode VL, and the link electrode VL is located in the recess.

[0306] In one exemplary embodiment, the length of the first power line VDDL along the first direction is greater than the length of the data signal line DL along the first direction.

[0307] In one exemplary embodiment, the data signal line DL connected to the pixel circuit is electrically connected to the first electrode of the fourth transistor through the twelfth via, the connection electrode VL is electrically connected to the second electrode of the sixth transistor through the thirteenth via, and the first power line VDDL connected to the pixel circuit is electrically connected to the first electrode of the fifth transistor through the fourteenth via.

[0308] In one exemplary embodiment, the orthographic projection of the first power line VDDL on the substrate overlaps with the orthographic projection of ...

[0309] (10) Forming a second planarization layer pattern includes: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film to form a second planarization layer pattern, such as... Figure 17A and Figure 17B As shown, Figure 17A This is a schematic diagram of the pattern of the second flattening layer. Figure 17B This is a schematic diagram after the second flattening layer pattern has been formed.

[0310] In one exemplary embodiment, such as Figure 17A and Figure 17B As shown, a fifteenth via V15 is formed in the second planarization layer. The fifteenth via V15 exposes the connection electrode.

[0311] (11) Forming an anode layer pattern includes: depositing an anode thin film on a substrate on which the aforementioned pattern is formed, and patterning the anode thin film using a patterning process to form an anode layer pattern, such as... Figure 18A and Figure 18B As shown, Figure 18A This is a schematic diagram of the anode layer pattern. Figure 18B This is a schematic diagram after the anode layer pattern has been formed.

[0312] In one exemplary embodiment, such as Figure 18A and Figure 18B As shown, the anode layer may include: the anode LA of the light-emitting element.

[0313] (12) Forming an organic structure layer and a cathode layer includes: depositing a pixel definition film on a substrate on which the aforementioned pattern is formed, patterning the pixel definition film by a patterning process to form a pixel definition layer pattern that exposes the anode layer pattern, coating an organic light-emitting material on a substrate on which the pixel definition layer pattern is formed, patterning the organic light-emitting material by a patterning process to form an organic structure layer pattern, depositing a cathode film on a substrate on which the organic material layer pattern is formed, and patterning the cathode film by a patterning process to form a cathode layer.

[0314] In one exemplary embodiment, the organic structure layer may include an organic light-emitting layer of a light-emitting element.

[0315] In one exemplary embodiment, the cathode layer may include the cathodes of a plurality of light-emitting elements.

[0316] In one exemplary embodiment, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0317] In one exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0318] In one exemplary embodiment, the first conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0319] In one exemplary embodiment, the second conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the second conductive layer may include molybdenum.

[0320] In one exemplary embodiment, the third conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the third conductive layer may include molybdenum.

[0321] In one exemplary embodiment, the fourth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the third conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0322] In one exemplary embodiment, the fifth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0323] In one exemplary embodiment, the fifth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0324] In one exemplary embodiment, the anode layer may be made of a transparent conductive material, such as any one or more of indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO).

[0325] In one exemplary embodiment, the cathode layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0326] In one exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0327] In one exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials.

[0328] The display substrate described in this embodiment can be used in display products of any resolution.

[0329] This disclosure also provides a method for driving a pixel circuit. The method for driving a pixel circuit may include the following steps:

[0330] Step 100: Under the control of the first reset signal terminal and the second scan signal terminal, the first node control sub-circuit provides the initial signal terminal signal to the first node and the fourth node. Under the control of the second reset signal terminal and the first scan signal terminal, the second node control sub-circuit provides the reference signal terminal signal to the second node.

[0331] Step 200: Under the control of the third scan signal terminal, the first node control sub-circuit provides the second node signal to the first node. Under the control of the second reset signal terminal and the first scan signal terminal, the second node control sub-circuit provides the data signal terminal signal to the third node.

[0332] Step 300: Under the control of the first and second nodes, the driving sub-circuit provides driving current to the third node. Under the control of the light emission signal terminal, the light emission control sub-circuit provides the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node.

[0333] This disclosure also provides a display device, including a display substrate.

[0334] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0335] In one exemplary embodiment, the display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0336] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0337] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0338] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel circuit located in a display substrate and configured to drive a light-emitting element to emit light, the display substrate comprising: A first driving mode and a second driving mode, wherein the refresh rate of the first driving mode is less than the refresh rate of the second driving mode, and the pixel circuit includes: a first node control sub-circuit, a second node control sub-circuit, an emissive control sub-circuit, and a driving sub-circuit. The first node control sub-circuit is electrically connected to the first power supply terminal, the first reset signal terminal, the initial signal terminal, the second scan signal terminal, the third scan signal terminal, the first node, the second node, and the fourth node, respectively. It is configured to provide the initial signal terminal to the first node and the fourth node under the control of the first reset signal terminal and the second scan signal terminal, and to provide the second node to the first node under the control of the third scan signal terminal. The second node control sub-circuit is electrically connected to the second reset signal terminal, the reference signal terminal, the first scan signal terminal, the data signal terminal, the second node, and the third node, respectively. It is configured to provide the reference signal terminal to the second node and the data signal terminal to the third node under the control of the second reset signal terminal and the first scan signal terminal. The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide driving current to the third node under the control of the first node and the second node; The light-emitting control sub-circuit is electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node under the control of the light-emitting signal terminal. The light-emitting element is electrically connected to the fourth node and the second power supply terminal, respectively. The voltage value of the signal at the reference signal terminal in the first driving mode is different from the voltage value of the signal in the second driving mode.

2. The pixel circuit according to claim 1, wherein, The first reset signal terminal and the second reset signal terminal are the same signal terminal.

3. The pixel circuit according to claim 1 or 2, wherein, The voltage value of the signal at the reference signal terminal in the first driving mode is less than the voltage value of the signal in the second driving mode. The voltage value of the signal at the reference signal terminal is greater than or equal to the voltage value of the signal at the initial signal terminal.

4. The pixel circuit according to claim 1 or 2, wherein, When the signals of the first reset signal terminal and the second reset signal terminal are valid level signals, the signal of the second scan signal terminal is valid level signals, and the signals of the first scan signal terminal, the third scan signal terminal and the light emission signal terminal are invalid level signals; When the signal at the first scan signal terminal is a valid level signal, the signal at the third scan signal terminal is a valid level signal, and the signals at the first reset signal terminal, the second reset signal terminal, the second scan signal terminal, and the light emission signal terminal are invalid level signals. When the signal at the light-emitting signal terminal is an effective level signal, the signals at the first reset signal terminal, the second reset signal terminal, the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal are invalid level signals.

5. The pixel circuit according to claim 1, wherein, The first node control sub-circuit includes: a reset sub-circuit, a compensation sub-circuit, and a storage sub-circuit; The reset sub-circuit is electrically connected to the first reset signal terminal, the initial signal terminal, the second scan signal terminal, the first node, and the fourth node, respectively, and is configured to provide the initial signal terminal to the first node and the fourth node under the control of the first reset signal terminal and the second scan signal terminal; The compensation sub-circuit is electrically connected to the first node, the second node and the third scanning signal terminal respectively, and is configured to provide the signal of the second node to the first node under the control of the third scanning signal terminal; The storage sub-circuit is electrically connected to the first power supply terminal and the first node, respectively, and is configured to store the voltage difference between the signal of the first power supply terminal and the signal of the first node.

6. The pixel circuit according to claim 1, wherein, The second node control sub-circuit includes: a control sub-circuit and a write sub-circuit; The control sub-circuit is electrically connected to the second reset signal terminal, the reference signal terminal, and the second node, respectively, and is configured to provide the reference signal terminal to the second node under the control of the second reset signal terminal; The writing sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal, and the third node, respectively, and is configured to provide the data signal terminal to the third node under the control of the first scan signal terminal.

7. The pixel circuit according to claim 5, wherein, The reset sub-circuit includes a first transistor and a second transistor; the compensation sub-circuit includes a seventh transistor; and the storage sub-circuit includes a capacitor, which includes a first plate and a second plate. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the third scan signal terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the second node. The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

8. The pixel circuit according to claim 6, wherein, The writing sub-circuit includes a fourth transistor, and the control sub-circuit includes an eighth transistor; The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node. The control electrode of the eighth transistor is electrically connected to the third scan signal terminal, the first electrode of the eighth transistor is electrically connected to the reference signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node.

9. The pixel circuit according to claim 1, wherein, The first node control sub-circuit includes: a first transistor, a second transistor, a seventh transistor, and a capacitor, wherein the capacitor includes: a first electrode plate and a second electrode plate; the second node control sub-circuit includes: a fourth transistor and an eighth transistor; the driving sub-circuit includes: a third transistor; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node. The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fourth node. The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node. The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node. The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node. The control electrode of the seventh transistor is electrically connected to the third scan signal terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the second node. The control electrode of the eighth transistor is electrically connected to the third scan signal terminal, the first electrode of the eighth transistor is electrically connected to the reference signal terminal, and the second electrode of the eighth transistor is electrically connected to the second node. The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

10. The pixel circuit according to claim 9, wherein, The transistor types of the first, third to sixth transistors and the eighth transistor are opposite to those of the second and seventh transistors; The second and seventh transistors are oxide transistors.

11. A display substrate, comprising: A substrate and a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate, wherein the light-emitting structure layer includes a light-emitting element, and the circuit structure layer includes an array of pixel circuits as described in any one of claims 1 to 10.

12. The display substrate according to claim 11, wherein, The circuit structure layer further includes: multiple first reset signal lines, multiple second reset signal lines, multiple first scan signal lines, multiple second scan signal lines, multiple third scan signal lines, multiple light emission signal lines, multiple initial signal lines, and multiple reference signal lines extending along a first direction and arranged along a second direction, as well as multiple first power lines and multiple data signal lines extending along the second direction and arranged along the first direction, wherein the first direction intersects the second direction; The pixel circuit has a first reset signal terminal electrically connected to a first reset signal line, a second reset signal terminal electrically connected to a second reset signal line, a first scan signal terminal electrically connected to a first scan signal line, a second scan signal terminal electrically connected to a second scan signal line, a third scan signal terminal electrically connected to a third scan signal line, an emission signal terminal electrically connected to an emission signal line, an initial signal terminal electrically connected to an initial signal line, a reference signal terminal electrically connected to a reference signal line, a first power supply terminal electrically connected to a first power supply line, and a data signal terminal electrically connected to a data signal line.

13. The display substrate according to claim 12, wherein, The pixel structure of adjacent pixel circuits located in the same row is symmetrical with respect to the dummy straight line extending along the second direction; The adjacent pixel circuits located in the same row as the pixel circuits include: the first adjacent pixel circuit and the second adjacent pixel circuit.

14. The display substrate according to claim 13, wherein, The pixel circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the gate electrode of the second transistor and the gate electrode of the seventh transistor each include: a first gate electrode and a second gate electrode. The second scan signal line includes: a first sub-scan signal line and a second sub-scan signal line that are disposed on different layers and interconnected with each other; the first gate electrode of the second transistor is disposed on the same layer as the first sub-scan signal line; and the second gate electrode of the second transistor is disposed on the same layer as the second sub-scan signal line. The third scan signal line includes a third sub-scan signal line and a fourth sub-scan signal line that are disposed on different layers and interconnected. The first gate electrode of the seventh transistor is disposed on the same layer as the third sub-scan signal line, and the second gate electrode of the seventh transistor is disposed on the same layer as the fourth sub-scan signal line.

15. The display substrate according to claim 14, wherein, The pixel circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate. The circuit structure layer includes a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fourth conductive layer, a first planarization layer, and a fifth conductive layer, which are sequentially stacked on the substrate. The first semiconductor layer includes: an active layer of a first transistor located in at least one pixel circuit, active layers of a third transistor to a sixth transistor, and an active layer of an eighth transistor. The first conductive layer includes: a first reset signal line, a second reset signal line, a first scan signal line, a light emission signal line, and a first plate of a capacitor located in at least one pixel circuit, a gate electrode of a first transistor, a gate electrode of a third transistor, a gate electrode of a fourth transistor, a gate electrode of a fifth transistor, a gate electrode of a sixth transistor, and a gate electrode of an eighth transistor. The second conductive layer includes: a first sub-scan signal line, a third sub-scan signal line, and a second plate of a capacitor located in at least one pixel circuit, a first gate electrode of a second transistor, and a second gate electrode of a seventh transistor; The second semiconductor layer includes: an active layer of a second transistor and an active layer of a seventh transistor located in at least one pixel circuit; The third conductive layer includes: a reference signal line, a second sub-scan signal line, a fourth sub-scan signal line, and a second gate electrode of a second transistor and a second gate electrode of a seventh transistor located in at least one pixel circuit; The fourth conductive layer includes: an initial signal line and the first and second poles of a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor located in at least one pixel circuit; The fifth conductive layer includes: a first power line, a data signal line, and a connection electrode located in at least one pixel circuit, with the light-emitting element connected to the connection circuit.

16. The display substrate according to claim 15, wherein, The second reset signal line and the first scan signal line connected to the pixel circuit are located on the same side of the first plate of the capacitor of the pixel circuit, and the second reset signal line is located on the side of the first scan signal line away from the first plate of the capacitor of the pixel circuit. The light-emitting signal line and the first reset signal line connected to the pixel circuit are located on the side of the first electrode of the pixel circuit away from the first scan signal line, and the first reset signal line is located on the side of the light-emitting signal line away from the first electrode of the capacitor of the pixel circuit. The first scan signal line includes: a scan main body and a scan connection part, wherein one end of the scan connection part is connected to the scan main body; The scanning main body extends along the first direction, and the scanning connection part is "L" shaped.

17. The display substrate according to claim 16, wherein, The first reset signal line includes: a plurality of first reset connection parts and a plurality of second reset connection parts arranged at intervals, wherein the second reset connection parts are arranged between two adjacent first reset connection parts and are connected to the two adjacent first reset connection parts; the second reset signal line includes: a plurality of third reset connection parts and a plurality of fourth reset connection parts arranged at intervals, wherein the fourth reset connection parts are arranged between two adjacent third reset connection parts and are connected to the adjacent third reset connection parts. The first reset connection and the third reset connection extend along the first direction. The second reset connection has an opening facing the opening of the light-emitting signal line. The fourth reset connection has an opening facing away from the opening of the first scan signal line. A virtual straight line extending along the second direction passes through the second reset connection of the first reset signal line and the fourth reset connection of the second reset signal line. The gate electrode of the first transistor and the first reset connection portion of the first reset signal line are integrally formed, and the gate electrode of the eighth transistor and the fourth reset connection portion of the second reset signal line are integrally formed.

18. The display substrate according to claim 16 or 17, wherein, The second plates of capacitors in adjacent pixel circuits located in the same row are connected; The first sub-scan signal line of the second scan signal line and the third sub-scan signal line of the third scan signal line connected to the pixel circuit are respectively located on opposite sides of the second plate of the capacitor in the pixel circuit; The first sub-scan signal line and the first gate electrode of the second transistor are integrally formed, and the third sub-scan signal line and the first gate electrode of the seventh transistor are integrally formed. The orthographic projection of the first sub-scan signal line on the substrate is located between the orthographic projection of the light-emitting signal line on the substrate and the orthographic projection of the first reset signal line on the substrate; The orthographic projection of the third sub-scan signal line on the substrate overlaps with the orthographic projection of the scan connection portion of the first scan signal line on the substrate, and the orthographic projection on the substrate is located between the orthographic projection of the scan body portion of the first scan signal line on the substrate and the orthographic projection of the second plate of the capacitor of the connected pixel circuit on the substrate.

19. The display substrate according to claim 18, wherein, The second sub-scan signal line and the second gate electrode of the second transistor are integrally formed, and the fourth sub-scan signal line and the second gate electrode of the seventh transistor are integrally formed. The orthographic projection of the second sub-scan signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-scan signal line on the substrate; The orthographic projection of the fourth sub-scan signal line onto the substrate at least partially overlaps with the orthographic projection of the third sub-scan signal line onto the substrate; The orthographic projection of the reference signal line onto the substrate overlaps with the orthographic projection of the second reset signal line onto the substrate.

20. The display substrate according to claim 14 or 15, wherein, The fifth insulating layer includes: a plurality of via patterns, the plurality of via patterns including: a first via to a sixth via formed on the first to fifth insulating layers, a seventh via formed on the second to fifth insulating layers, an eighth via formed on the third to fifth insulating layers, a ninth and a tenth via formed on the fourth and fifth insulating layers, and an eleventh via formed on the fifth insulating layer, wherein the eighth via exposes the second plate of the capacitor, and the eleventh via exposes the reference signal line; The virtual straight line extending along the second direction passes through the eighth and eleventh vias; The eighth via of the pixel circuit is the same as the eighth via of the first adjacent pixel circuit, and the eleventh via of the pixel circuit is the same as the eleventh via of the first adjacent pixel circuit.

21. The display substrate according to claim 19, wherein, The first electrode of the fifth transistor in the pixel circuit is the same as the first electrode of the fifth transistor in the first adjacent pixel circuit, and the first electrode of the eighth transistor in the pixel circuit is the same as the first electrode of the eighth transistor in the first adjacent pixel circuit. The orthographic projection of the initial signal line on the substrate overlaps with the orthographic projection of the second reset connection portion of the first reset signal line on the substrate. The second electrode of the first transistor, the second electrode of the second transistor, and the second electrode of the sixth transistor are integrally formed, and their orthogonal projections on the substrate overlap with the orthogonal projections of the second scan signal line and the light emission signal line on the substrate. The orthographic projection of the first electrode of the fifth transistor onto the substrate overlaps with the orthographic projection of the second electrode of the capacitor and the light-emitting signal line connected to the pixel circuit onto the substrate, and the first electrode of the fifth transistor includes an opening facing the second scan signal line connected to the pixel circuit. The first electrode of the second transistor and the first electrode of the seventh transistor are integrally formed, and their orthogonal projection on the substrate overlaps with the orthogonal projection of the light-emitting signal line connected to the second electrode plate of the capacitor and the pixel circuit on the substrate. The second electrode of the seventh transistor and the second electrode of the eighth transistor are integrally formed, and their orthogonal projections on the substrate overlap with the orthogonal projections of the first scan signal line connected to the pixel circuit and the third scan signal line connected to the pixel circuit on the substrate. The orthographic projection of the first electrode of the eighth transistor onto the substrate overlaps with the orthographic projection of the reference signal line connected to the pixel circuit onto the substrate.

22. The display substrate according to claim 14 or 15, wherein, The first power line connected to the pixel circuit is the same power line as the first power line connected to the first adjacent pixel circuit. The data signal line and the first power line connected to the pixel circuit are located on both sides of the connecting electrode, and the length of the first power line along the first direction is greater than the length of the data signal line along the first direction.

23. The display substrate according to claim 22, wherein, The first power line connected to the pixel circuit may include: a first power supply section, a second power supply section and a third power supply section arranged sequentially along the second direction, wherein the second power supply section is connected to the first power supply section and the third power supply section respectively. The length of the third power supply unit along the first direction is greater than the length of the first power supply unit along the first direction, and the length of the first power supply unit along the first direction is greater than the length of the second power supply unit along the first direction. The connection electrode of the pixel circuit is located on the side of the second power supply section of the pixel circuit, near the data signal line connected to the pixel circuit.

24. The display substrate according to claim 23, wherein, The orthographic projection of the first power line on the substrate overlaps with the orthographic projections of the first pole of the fifth transistor, the first pole of the first transistor, the first pole of the second transistor, the first pole of the seventh transistor, the first pole of the seventh transistor, and the second pole of the eighth transistor on the substrate.

25. A display device, comprising: The display substrate as described in any one of claims 11 to 24.

26. A method for driving a pixel circuit, configured to drive the pixel circuit as described in any one of claims 1 to 10, the method comprising: The first node control sub-circuit, under the control of the first reset signal terminal and the second scan signal terminal, provides the initial signal terminal signal to the first node and the fourth node; the second node control sub-circuit, under the control of the second reset signal terminal and the first scan signal terminal, provides the reference signal terminal signal to the second node. Under the control of the third scan signal terminal, the first node control sub-circuit provides the second node signal to the first node. Under the control of the second reset signal terminal and the first scan signal terminal, the second node control sub-circuit provides the data signal terminal signal to the third node. The driving sub-circuit, under the control of the first and second nodes, provides driving current to the third node. The light-emitting control sub-circuit, under the control of the light-emitting signal terminal, provides the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node.

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