General purpose parallel matrix multiplier based on reconfigurable computation

By using a general-purpose parallel matrix multiplier based on reconstructed computation, matrix data is split into single-bit matrices for operation, solving the problems of difficulty in signed number computation and resource waste in existing technologies, and realizing efficient matrix multiplication operations.

CN117519641BActive Publication Date: 2026-06-09XIDIAN UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
XIDIAN UNIV
Filing Date
2023-11-24
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

Existing matrix multipliers are inefficient for calculating signed numbers and have large overhead, especially in the shift and accumulation modules where resources are consumed excessively.

Method used

A general-purpose parallel matrix multiplier based on reconstruction computation is adopted. The matrix data is split into single-bit matrices through the matrix reconstruction module, multiplication is performed by the multiplication module, accumulation is performed by the compression module, data shifting is performed by the shift module, and the final result is obtained through the accumulation module. The compression module uses a compressor to compress the data to reduce area overhead.

Benefits of technology

It improves data compression efficiency, reduces the area overhead of compression, shifting, and accumulation modules, enables calculations on both signed and unsigned numbers, and optimizes resource utilization.

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Abstract

The application discloses a general parallel matrix multiplier based on reconstruction calculation. The multiplier comprises a matrix reconstruction module, a multiplication module, a compression module, a shift module and an accumulation module. After matrix data is reconstructed into multiple groups of single-bit data according to bit positions by the matrix reconstruction module, the single-bit data is multiplied in the multiplication module; the multiplication result is compressed by the compression module. The compressor in the compression module can compress six data simultaneously. Finally, the compressed result is shifted by the shift module and accumulated by the accumulation module to obtain the multiplication result of the matrix data. According to the matrix multiplier provided by the application, the compression efficiency can be improved by compressing data by the compression module composed of the compressor; meanwhile, the compressor can also perform partial shift calculation and undertake part of the responsibility of the subsequent shift module, thereby reducing the area cost of the matrix multiplier; by decomposing the matrix data according to bit positions, the calculation of signed numbers and unsigned numbers can be realized.
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