An in-memory computing circuit for implementing energy-efficient multiplication operations

Abstract

This invention provides an in-memory computing circuit for implementing high-efficiency multiplication operations, comprising an in-memory Booth encoder array and an in-memory computing array. The in-memory computing array includes an in-memory partial product generator. The in-memory partial product generator stores the multiplicand, utilizes two complementary latch nodes in the data latch unit to represent the multiplicand and its opposite, and uses two complementary latch nodes in adjacent data latch units to represent twice the multiplicand and twice the opposite. Inversion and shifting are achieved without additional transistor overhead, generating all possible non-zero partial products of the radix-4 Booth algorithm. The multiplier signal controls the in-memory Booth encoder array to generate an encoded signal, which in turn controls a data selector to select one of the four non-zero partial products. This invention is applicable to multiplication operations of arbitrary bit widths, improves the utilization rate of the data latch unit circuit and the symmetry of the in-memory computing unit circuit, and allows for flexible adjustment of computational parallelism.

Description

Technical Field

[0001] This invention relates to an in-memory computing circuit for implementing high-efficiency multiplication operations. Background Technology

[0002] Artificial Intelligence (AI) has been widely applied across various fields, driving the arrival of the "computing power era." AI-related algorithms, such as Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs), require massive amounts of data processing. However, most modern computing systems are built on the traditional von Neumann architecture, physically consisting of independent computing units and data latching units. During the execution of various computational tasks, these systems need to repeatedly transfer large amounts of data between memory and computing units, leading to significant latency and energy consumption, thus limiting data processing efficiency. Due to the long-term unbalanced development of processors and storage devices, the speed gap between memory and processors has widened, a gap known as the "memory wall," resulting in the well-known von Neumann bottleneck. Only by overcoming the von Neumann bottleneck can artificial intelligence be applied to devices with strict limitations on energy consumption and area (such as IoT devices, mobile devices, and wearable devices), achieving "ubiquitous artificial intelligence." To overcome the computational limitations of the traditional von Neumann architecture, Computing In Memory (CIM) emerged. It eliminates the need to transfer data from memory to the processor, integrating computation directly within the memory array. This reduces intermediate data transfers and lightens the processor's workload. In CIM architectures, bus bandwidth is no longer a limiting factor for throughput, significantly improving throughput and energy efficiency. Another significant advantage of CIM is its ability to perform multi-line reads, reducing the number of memory accesses and increasing data throughput. As CIM becomes a popular research area, more and more scholars are engaging in its study; multiplication, addition, subtraction, and logical operations have all been implemented using CIM. The carriers for enabling in-memory computing include various volatile and non-volatile memories such as Static Random-Access Memory (SRAM), Dynamic Random-Access Memory (DRAM), Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), and Flash Memory.Static Random-Access Memory (SRAM) has attracted widespread attention from academia and industry due to its high stability, fast read speed, and high number of erase / write cycles for its data latch cells, as well as its compatibility with advanced logic processes.

[0003] Existing technical solutions: Current SRAM-based in-memory computing implementation technologies can be divided into two types: analog computing in memory (ACIM) and digital computing in memory (DCIM). ACIM typically requires converting the input digital signal into an analog signal, performing single-bit analog multiplication with the logic value stored in the data latch unit to form a multiply-accumulate unit. Simultaneously activating multiple word lines, the discharge current generated by the multiply-accumulate units on the same column can be summed. After being converted back to a digital signal by an analog-to-digital converter, it can be used by subsequent circuits for further computation. Digital computing in memory generally reuses the data latch unit as a logic operation unit, transferring single-bit multiplication (i.e., bitwise AND) to in-memory implementation. Shift accumulators and adders are implemented outside the memory array to complete the multiply-accumulate operation. ACIM's advantage is its high energy efficiency; however, the characteristics of analog computing make it susceptible to factors such as process variations, voltage fluctuations, and circuit noise, resulting in computational accuracy typically below 8 bits. The external digital-to-analog and analog-to-digital converters in the ACIM architecture also introduce additional overhead. DCIM avoids the overhead of data converters and does not suffer from loss of computational accuracy, but its energy efficiency and area efficiency are usually worse than those of analog in-memory computing chips. Summary of the Invention

[0004] Purpose of the invention: The technical problem to be solved by the present invention is to provide an in-memory computing circuit for realizing high-efficiency multiplication operations, which addresses the shortcomings of the prior art. The circuit includes an in-memory Booth encoder array, a row decoder and word line driver circuit, a column decoder and read / write driver circuit, and an in-memory computing array.

[0005] Unlike traditional multiplier circuit designs, all the components described above in this invention are implemented inside or adjacent to the memory, thus eliminating or reducing the overhead of data transfer between the multiplication unit and the memory.

[0006] The in-memory computing circuit has three operating modes: read, write, and compute.

[0007] In read / write mode, the row decoder selects a specific row or cell in the memory chip for reading or writing. If the row decoder selects a row, the word line driver circuit generates the necessary control signals to activate the row, reading data from or writing data to it. The column decoder selects a specific column within the memory row already selected by the row decoder. When the memory system receives an address signal, the column decoder further decodes the address signal to determine the memory column to be accessed. The column decoder ensures that only data on the selected memory column is read or written. The read / write driver circuit controls the data read and write operations. For read operations, the read / write driver circuit amplifies and outputs the data from the selected memory cell to the data bus. For write operations, the read / write driver circuit writes data from the data bus to the selected memory cell. The read / write driver circuit also includes data write and read timing control. The row and column decoders work together to select specific data cells in the memory, while the word line driver circuit and the read / write driver circuit are responsible for activating and processing the selected data cells for read or write operations. These components play a crucial role in the memory system, ensuring that data can be stored and retrieved efficiently.

[0008] In computation mode, the in-memory Booth encoder array receives the multiplier signal and outputs the Booth encoded signal; under the control of the Booth encoded signal, the in-memory computation array performs inversion and shift operations on the multiplicand stored in the memory, and outputs all partial product signals generated by multiplying the multiplier and the multiplicand.

[0009] The in-memory computing array includes n in-memory partial product generator arrays, each in-memory partial product generator array includes m in-memory partial product generators, and each in-memory partial product generator includes k in-memory computing units; where n is the number of rows in the in-memory computing array, k is the bit width of the multiplicand, and k*m is the number of columns in the in-memory computing array.

[0010] Each in-memory computing unit includes a data latch unit, one or more read / write ports, and a data selector array, which includes z data selectors.

[0011] The i-th data latch unit has two complementary data latch nodes Q[i] and QN[i], where i represents the position of the data latch unit, 0 << i << k-1, and the k data latch units store the k-bit multiplicand from right to left in order from the least significant bit to the most significant bit.

[0012] The read / write port performs read / write operations on the in-memory computing array under the control of the peripheral circuit.

[0013] Each data selector includes four control signal inputs: TWO, TWON, NEG, NEGN; four data inputs: W, 2W, 2WN, and WN; and one data output: OUT.

[0014] TWO, ​​TWON, NEG, and NEGN are generated by the in-memory Booth encoder array, while W, 2W, 2WN, and WN are generated by the data latch unit of the in-memory computing unit.

[0015] By utilizing the complementary latch signals inherent in the memory itself and designing a method of cascading k in-memory computing units from right to left, a left-shift circuit within the memory is implemented with zero transistor overhead, thereby generating all possible non-zero partial product candidate signals in the Radix-4 Booth algorithm.

[0016] In each in-memory partial product generator, a multiplicand is stored. Two complementary latch nodes in the data latch unit represent the multiplicand and its opposite. Two complementary latch nodes in adjacent data latch units represent twice the multiplicand and twice the opposite. Inversion and shifting are achieved without adding extra transistor overhead, generating all possible non-zero partial products of the radix-4 Booth algorithm. The specific implementation is as follows: the 2W input terminals of all data selectors in the data selector array of the 0th in-memory unit are grounded, the 2WN input terminals of all data selectors in the data selector array of the 0th in-memory unit are grounded, the W input terminals of all data selectors in the data selector array of the 0th in-memory unit are connected to the Q[0] node of the 0th in-memory unit, and the 0th in-memory unit... The WN input terminals of all data selectors in the data selector array of the x-th in-memory computing unit are connected to the QN[0] node of the x-th in-memory computing unit; the 2W input terminals of all data selectors in the data selector array of the x-th in-memory computing unit are connected to the Q[x-1] node of the x-1 in-memory computing unit; the 2WN input terminals of all data selectors in the data selector array of the x-th in-memory computing unit are connected to the QN[x-1] node of the x-1 in-memory computing unit; the W input terminals of all data selectors in the data selector array of the x-th in-memory computing unit are connected to the Q[x] node of the x-th in-memory computing unit; and the W input terminals of all data selectors in the data selector array of the x-th in-memory computing unit are connected to the QN[x] node of the x-th in-memory computing unit, where 1 << x << k-1.

[0017] Each in-memory computing unit has a set of independent control input terminals for each of its z data selectors, namely {NEG[0],NEGN[0],TWO[0],TWON[0]}, {NEG[1],NEGN[1],TWO[1],TWON[1]},...,{NEG[z-1],NEGN[z-1],TWO[z-1],TWON[z-1]. Among them, NEG[0],NEGN[0],TWO[0],TWON[0] are the control signals of the 0th data selector, and so on.

[0018] Each in-memory computing unit has an independent data selector. The output of the z-th data selector of the x-th in-memory computing unit is denoted as {OUT0[x], OUT1[x], ..., OUT...} z-1 OUT0[x] is the output signal of the 0th data selector of the xth in-memory computing unit.

[0019] The partial product bits with the same index of k in-memory computing units constitute a complete partial product, i.e., {OUT0[0],OUT0[1],...,OUT0[k-1]} constitutes the 0th partial product, {OUT1[0],OUT1[1],...,OUT1[k-1]} constitutes the 1st partial product, and so on, {OUT... z-1 [0],OUT z-1 [1],...,OUT z-1 [k-1]} constitutes the (z-1)th partial product;

[0020] The in-memory partial product generator is capable of generating z partial products simultaneously in a single clock cycle.

[0021] Beneficial effects: (1) Difference from existing analog in-memory computing circuits: This invention is fully digital, without the need for an analog-to-digital converter to convert input data into digital signals, nor a digital-to-analog converter to convert the calculation results into digital signals, thus saving the area and power consumption of the data converter; The scheme proposed in this invention has strong anti-interference ability and is not easily affected by process deviations, voltage fluctuations, temperature changes, and there is no loss of calculation accuracy.

[0022] (2) Differences from existing digital in-memory computing circuits: For the multiplication of two multi-bit numbers: I*W, where I has n bits and W has m bits, existing all-digital implementations use AND or NOR gates to perform single-bit multiplication in a single clock cycle, requiring n clock cycles to obtain n partial products. These partial products are then shifted and summed to obtain the final multiplication result. In contrast, this invention implements the Radix-4 Booth algorithm in-memory, and the computational parallelism can be determined based on specific technology and application requirements. The in-memory partial product generator proposed in this invention can obtain all partial products in at most n / 2 clock cycles. Compared to existing serial computing schemes, the throughput of this invention can be increased by at least 2 times. Since the total number of partial products is reduced by half after Booth encoding, energy consumption is also effectively reduced. Therefore, this invention can effectively improve computational speed while simultaneously improving computational energy efficiency.

[0023] (3) The difference between the in-memory partial product generator proposed in this invention and the existing Booth multiplication circuit: This invention effectively utilizes the complementary signals inherent in the data latch unit itself and the regular array structure of the memory to implement the shift circuit and multi-bit selector circuit with lower overhead, and obtains partial products with lower area and power consumption. Attached Figure Description

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0025] Figure 1 This is a diagram of the in-memory computing circuit architecture of the present invention.

[0026] Figure 2 This is the circuit diagram of the internal Booth encoder.

[0027] Figure 3 This is a symbolic representation of the internal Booth encoder circuit diagram.

[0028] Figure 4 This is a schematic diagram of a line-in-memory Booth encoder array.

[0029] Figure 5 This is a schematic diagram of an 8-line in-memory Booth encoder array.

[0030] Figure 6 This is a schematic diagram of a selector circuit.

[0031] Figure 7 This is a schematic diagram of the symbolic representation of a selector.

[0032] Figure 8 This is a schematic diagram of the in-memory computing unit circuit.

[0033] Figure 9 This is a schematic diagram of the internal partial product generator circuit.

[0034] Figure 10 This is a symbolic representation of an in-memory partial product generator.

[0035] Figure 11 This is a schematic diagram of a partition generator array within a single row of memory.

[0036] Figure 12 This is a schematic diagram of an eight-line internal partial product generator array. Detailed Implementation

[0037] This invention provides an in-memory computing circuit for implementing high-efficiency multiplication operations, including a circuit structure for implementing Radix-4 Booth multiplication in memory. The principle of the Booth algorithm is as follows: Given a multiplier I and a multiplicand W to be multiplied, the two's complement representation of I is:

[0038]

[0039] Where n represents the bit width of I and W, and j represents the j-th bit. Expanding I further, we get:

[0040] I = -I n-1 *2 n-1 +I n-2 *2 n-2 +I n-3 *2 n-3 +...+I3*2 3 +I2*2 2 +I1*2 n1 +I0*2 0 +I -1

[0041] =(-2I n-1 +I n-2 +I n-3 )*2 n-2 +(-2I n-3 +I n-4 +I n-5 )*2 n-4 +(-2I5+I4+I3)*2 4 +(-2I3+I2+I1)*2 2 +(-2I1+I0+I -1 )*2 0

[0042] W*I is represented as:

[0043]

[0044] As shown in the formula above, after the transformation of Radix-4 Booth multiplication, the number of partial products can be halved, thereby improving the operation speed of the multiplier and reducing area and power consumption. Based on the above formula, the multiplier I can be re-encoded, as shown in Table 1, which is called Radix-4 Booth encoding.

[0045] Table 1

[0046]

[0047] According to Table 1, this invention designs an in-memory Booth encoder to control an in-memory partial product generator to produce partial products. The input of the in-memory Booth encoder is three consecutive I bits of the multiplier. 2j+1 I 2j I 2j-1 The output consists of four signals: TWO, TWON, NEG, NEGN, and ZERO, and their truth tables are shown in Table 2. TWON is the inverted form of TWO, and NEGN is the inverted form of NEG. TWO, ​​TWON, NEG, and NEGNN jointly control the selector array in the in-memory partial product generator array, selecting the correct signal to represent the partial product. As shown in Table 2, if the TWO signal is low and the NEG signal is also low, the multiplicand stored in the in-memory partial product generator array is selected, indicating that the partial product is the multiplicand; if the TWO signal is high and the NEG signal is low, the signal of left-shifting the multiplicand stored in the in-memory partial product generator array by one bit is selected, indicating that the partial product is the multiplicand multiplied by 2; if the TWO signal is high and the NEG signal is also high, the signal of inverting the multiplicand and shifting it left by one bit is selected, indicating that the partial product is the multiplicand multiplied by 2; if the TWO signal is low and the NEG signal is high, the signal of inverting the multiplicand stored in the in-memory partial product generator array is selected, indicating that the partial product is the multiplicand multiplied by -1.

[0048] The ZERO signal has a higher priority than the TWO, TWON, NEG, and NEGN signals. If ZERO is high, the partial product is set to zero. Only when ZERO is low do the other signals take effect.

[0049] Table 2

[0050]

[0051] In Table 2 above, x represents any signal. If the ZERO signal is high, the partial product will be set to zero outside the memory calculation circuit.

[0052] The logical expression corresponding to Table 2 is:

[0053]

[0054]

[0055] NEG = I 2j+1

[0056]

[0057]

[0058] in This means inverting TWO. Indicates that NEG is inverted;

[0059] like Figure 1 As shown, this invention proposes a novel in-memory multiplication circuit, including an in-memory Booth encoder array, a row decoder and word line driver circuit, a column decoder and read / write driver circuit, and an in-memory computing array.

[0060] The in-memory computing array comprises n in-memory partial product generator arrays, each array containing m in-memory partial product generators, and each generator containing k in-memory computing units. Here, n is the number of rows in the in-memory computing array, k is the bit width of the multiplicand, and k*m is the number of columns in the array. The value of k is determined based on the required computational precision. The in-memory computing circuit proposed in this invention supports multiplication operations with arbitrary bit widths.

[0061] Each in-memory computing unit includes a data latch unit, one or more read / write ports, and a data selector array, which includes z data selectors.

[0062] Each data latch unit has two complementary data latch nodes Q[x] and QN[x], where 0 << x << k-1, and i represents the data latch unit of the in-memory computation unit storing the x-th bit of the multiplicand. The k data latch units store the k-bit multiplicand in order from least significant bit to most significant bit, from right to left.

[0063] Each data selector includes four control signal inputs: TWO, TWON, NEG, and NEGN; four data inputs: W, 2W, 2WN, and WN; and one data output: OUT. TWO, TWON, NEG, and NEGN are generated by the in-memory Booth encoder, while W, 2W, 2WN, and WN are generated by the data latch unit of the in-memory computing unit.

[0064] This invention utilizes the complementary latch signals inherent in the memory itself and designs a method of cascading k in-memory computing units from right to left to implement a left-shift circuit within the memory with zero transistor overhead, thereby generating all possible non-zero partial product candidate signals in the Radix-4 Booth algorithm as shown in Tables 1 and 2. In each in-memory partial product generator, a multiplicand is stored. Two complementary latch nodes in the data latch unit represent the multiplicand and its opposite. Two complementary latch nodes in adjacent data latch units represent twice the multiplicand and twice the opposite of the multiplicand. Inversion and shifting are achieved without adding extra transistor overhead, generating all possible non-zero partial products of the radix-4 Booth algorithm. The specific implementation is as follows: In each in-memory partial product generator, the 2W input terminals of all data selectors in the data selector array of the 0th in-memory unit are grounded, the 2WN input terminals of all data selectors in the data selector array of the 0th in-memory unit are grounded, and the W input terminals of all data selectors in the data selector array of the 0th in-memory unit are connected to the Q[0] node of the 0th in-memory unit. The WN input terminals of all data selectors in the data selector array of the in-memory computing unit are connected to the QN[0] node of the 0th in-memory computing unit; the 2W input terminals of all data selectors in the data selector array of the xth in-memory computing unit are connected to the Q[x-1] node of the (x-1)th in-memory computing unit; the 2WN input terminals of all data selectors in the data selector array of the xth in-memory computing unit are connected to the QN[x-1] node of the (x-1)th in-memory computing unit; the W input terminals of all data selectors in the data selector array of the xth in-memory computing unit are connected to the Q[x] node of the xth in-memory computing unit; and the W input terminals of all data selectors in the data selector array of the xth in-memory computing unit are connected to the QN[x] node of the xth in-memory computing unit, where 1 << x << k-1.

[0065] Each of the z data selectors in each in-memory computing unit has a set of independent control input terminals, namely {NEG[0],NEGN[0],TWO[0],TWON[0]}, {NEG[1],NEGN[1],TWO[1],TWON[1]},...,{NEG[z-1]; where NEG[0],NEGN[0],TWO[0],TWON[0] are the control signals of the 0th data selector, and so on.

[0066] Each in-memory computing unit has an independent data selector. The output of the z-th data selector of the x-th in-memory computing unit is denoted as {OUT0[x], OUT1[x], ..., OUT...} z-1OUT0[x] is the output signal of the 0th data selector of the xth in-memory computing unit, which is also the xth bit of the 0th partial product. OUT1[x] is the output signal of the 1st data selector of the xth in-memory computing unit, which is also the xth bit of the 1st partial product, and so on. Where 0 << x << k-1.

[0067] The partial product bits with the same index of k in-memory computing units constitute a complete partial product, that is, {OUT0[0],OUT0[1],...,OUT0[k-1]} constitute the 0th partial product, {OUT1[0],,OUT1[1],...,OUT1[k-1]} constitute the 1st partial product, and so on, {OUT... z-1 [0],OUT z-1 [1],...,OUT z-1 [k-1]} constitutes the (z-1)th partial product. That is, the in-memory partial product generator designed in this invention can generate z partial products simultaneously in a single clock cycle. The size of z should be selected according to the specific process and design specifications. The larger z is, the fewer clock cycles are required to complete one multiplication, but the area of ​​the in-memory computing unit is also larger, and the wiring difficulty will also increase.

[0068] In one embodiment of the present invention, an in-memory computing circuit based on Static Random Access Memory (SRAM) is described, and the configuration of this embodiment is as follows:

[0069] 1. The precision of multiplication operation is 8 bits (that is, the bit width of both multiplier I and multiplicand W is 8 bits). A partial product generation circuit is composed of 8 in-memory computing units.

[0070] 2. Four partial products are generated simultaneously in one cycle, meaning that there are four selectors in one in-memory computing unit circuit;

[0071] 3. Each row's in-memory partial product generator array consists of 8 in-memory partial product generators, which store 8 multiplicands;

[0072] 4. One type has 8 rows, which means it has a total storage capacity of 8*8*8=512b.

[0073] An implementation of the in-memory Radix-4 Booth encoder, for example Figure 2 As shown, unlike traditional multiplier designs, the in-memory Radix-4 Booth encoder is placed adjacent to the in-memory computing array and is part of the memory; the symbolic representation of the Radix-4 Booth encoder is as follows: Figure 3 As shown.

[0074] like Figure 4 As shown, four of the above encoders are replicated to form a Booth encoder array. These four encoders encode under the control of the same multiplier, generating four sets of control signals, namely {NEG[0],NEGN[0],TWO[0],TWON[0]},...,{NEG[3],NEGN[3],TWO[3],TWON[3]}. These four sets of control signals control each in-memory partial product generator in a row to simultaneously generate four partial products, that is, each row of the in-memory partial product generator array can simultaneously generate 32 partial products.

[0075] like Figure 5 As shown, eight Booth encoder arrays are replicated, each controlled by an independent multiplier, which controls the eight in-memory partial product generator arrays of this embodiment, generating 256 partial products simultaneously.

[0076] One implementation of the selector circuit is, for example... Figure 6 As shown, a selector outputs a partial product bit.

[0077] The symbolic representation of the selector in this embodiment is as follows: Figure 7 As shown.

[0078] An implementation of a memory computing unit, for example Figure 8 As shown: This in-memory computing unit includes a data latch unit composed of a cross-coupled inverter, the data latch unit has two complementary memory nodes Q and QN; a pair of read / write ports composed of NMOS transistors NMO and NM1; a selector array composed of 4 selectors; BL and BLB are complementary bit lines in the column direction, and WL is the word line in the horizontal direction.

[0079] like Figure 9 As shown, eight in-memory computing units are cascaded from right to left to form an in-memory partial product generator. Under the control of the four sets of control signals {NEG[0],NEGN[0],TWO[0],TWON[0]},...,{NEG[3],NEGN[3],TWO[3],TWON[3]} generated by the Booth encoder array, the in-memory partial product generator outputs four partial product signals consisting of OUT0<7:0>, OUT1<7:0>,......,OUT3<7:0>, which means that all partial product signals of one multiplication are generated in a single cycle.

[0080] Symbolic representation of the internal partial product generator, such as Figure 10 As shown.

[0081] like Figure 11As shown, eight in-memory partial product generators are replicated horizontally to form a row of in-memory partial product generator arrays. OUT0<7:0>, OUT1<7:0>, ..., OUT3<7:0> constitute the partial product output signal of the first in-memory partial product generator, OUT0<15:8>, OUT1<15:8>, ..., OUT3<15:8> constitute the partial product output signal of the second in-memory partial product generator, and so on, until OUT0<63:56>, OUT1<63:56>, ..., OUT3<63:56> constitute the partial product output signal of the eighth in-memory partial product generator.

[0082] like Figure 12 As shown, eight in-memory partial product generator arrays are copied vertically to form an eight-row in-memory partial product generator array.

[0083] This invention provides an in-memory computing circuit for implementing high-efficiency multiplication operations. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. An in-memory computing circuit for implementing high-energy-efficiency multiplication operations, characterized in that, This includes an in-memory Booth encoder array, a row decoder and word line driver circuit, a column decoder and read / write driver circuit, and an in-memory computing array; The in-memory computing circuit has three operating modes: read, write, and compute. In read / write mode, the row decoder selects a specific row or cell in the memory chip for reading or writing. If the row decoder selects a row, the word line driver circuit generates a control signal to activate the row, allowing data to be read from or written to that row. The column decoder selects a specific column within a memory row already selected by the row decoder. When the memory system receives an address signal, the column decoder further decodes the address signal to determine the memory column to be accessed. The column decoder ensures that only data in the selected memory column is read or written. The read / write driver circuit controls the data read and write operations. For read operations, the read / write driver circuit amplifies and outputs the data from the selected memory cell to the data bus. For write operations, the read / write driver circuit writes data from the data bus to the selected memory cell; In computation mode, the in-memory Booth encoder array receives the multiplier signal and outputs the Booth encoded signal; Under the control of the Booth encoding signal, the in-memory computing array performs inversion and shift operations on the multiplicand stored in the memory, and outputs all partial product signals generated by multiplying the multiplier and the multiplicand. By utilizing the complementary latch signals inherent in the memory itself and designing a method of cascading k in-memory computing units from right to left, a left-shift circuit with zero transistor overhead is implemented in memory, thereby generating all non-zero partial product candidate signals in the Radix-4 Booth algorithm.

2. The in-memory computing circuit for implementing high-efficiency multiplication operations according to claim 1, characterized in that, The in-memory computing array includes n in-memory partial product generator arrays, each in-memory partial product generator array includes m in-memory partial product generators, and each in-memory partial product generator includes k in-memory computing units; where n is the number of rows in the in-memory computing array, k is the bit width of the multiplicand, and k*m is the number of columns in the in-memory computing array.

3. The in-memory computing circuit for implementing high-efficiency multiplication operations according to claim 2, characterized in that, Each in-memory computing unit includes a data latch unit, one or more read / write ports, and a data selector array, which includes z data selectors.

4. The in-memory computing circuit for implementing high-efficiency multiplication operations according to claim 3, characterized in that, The i-th data latch unit has two complementary data latch nodes. and Where i represents the position of the data latch unit, The k data latch units store the k-bit multiplicand in order from the least significant bit to the most significant bit, from right to left.

5. The in-memory computing circuit for implementing high-efficiency multiplication operations according to claim 4, characterized in that, The read / write port performs read / write operations on the in-memory computing array under the control of the peripheral circuit.

6. The in-memory computing circuit for implementing high-efficiency multiplication operations according to claim 5, characterized in that, Each data selector includes four control signal inputs: TWO, TWON, NEG, NEGN; four data inputs: W, 2W, 2WN, and WN; and one data output: OUT. , , , The numbers W, 2W, 2WN, and WN are generated by the in-memory Booth encoder array and the data latch unit of the in-memory computing unit.

7. The in-memory computing circuit for implementing high-efficiency multiplication operations according to claim 6, characterized in that, Each in-memory partial product generator stores a multiplicand. Two complementary latch nodes in the data latch unit represent the multiplicand and its opposite. Two complementary latch nodes in adjacent data latch units represent twice the multiplicand and twice the opposite. This achieves inversion and shifting without adding extra transistor overhead, generating all non-zero partial products of the Radix-4 Booth algorithm. Specifically, the 2W inputs of all data selectors in the data selector array of the 0th in-memory unit are grounded, the 2WN inputs of all data selectors in the data selector array of the 0th in-memory unit are grounded, and the W inputs of all data selectors in the data selector array of the 0th in-memory unit are connected to the 0th in-memory unit's... The nodes are connected, and the WN input terminals of all data selectors in the data selector array of the 0th in-memory computing unit are connected to the 0th in-memory computing unit. The nodes are connected; the 2W input terminals of all data selectors in the data selector array of the x-th in-memory computing unit are connected to the (x-1)-th in-memory computing unit. The nodes are connected, and the 2WN input terminals of all data selectors in the data selector array of the x-th in-memory computing unit are connected to the (x-1)-th in-memory computing unit. The nodes are connected, and the W input terminals of all data selectors in the data selector array of the x-th in-memory computing unit are connected to the x-th in-memory computing unit. The nodes are connected, and the W input terminals of all data selectors in the data selector array of the x-th in-memory computing unit are connected to the x-th in-memory computing unit. The nodes are connected, among which, .

8. The in-memory computing circuit for implementing high-efficiency multiplication operations according to claim 7, characterized in that, Each of the z data selectors in each in-memory computing unit has a set of independent control input terminals, namely , ； in It is the control signal for the 0th data selector; Each in-memory computing unit has an independent data selector. The output of the z-th data selector in the x-th in-memory computing unit is denoted as... , It is the output signal of the 0th data selector of the xth in-memory computing unit.

9. The in-memory computing circuit for implementing high-efficiency multiplication operations according to claim 8, characterized in that, The partial product bits with the same index of k in-memory computing units constitute a complete partial product. Forming the 0th partial product, This forms the first partial product, and so on. This constitutes the (z-1)th partial product; The in-memory partial product generator is capable of generating z partial products simultaneously in a single clock cycle.

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