Semiconductor devices and their fabrication methods, electronic devices

Abstract

This application provides a semiconductor device and its fabrication method, as well as an electronic device, relating to the field of semiconductor technology, capable of reducing the subthreshold swing of transistors. The semiconductor device includes a transistor. The transistor includes a channel, a source, and a drain; the source and drain are disposed at opposite ends of the channel; a first intercalation layer is disposed between the source and the channel, and the first intercalation layer is in contact with both the source and the channel. The channel is made of a lightly doped semiconductor or an intrinsic semiconductor. The drain is made of a heavily doped semiconductor. The source is made of a P-type heavily doped semiconductor; wherein, the first intercalation layer is made of a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the channel semiconductor; or, the source is made of an N-type heavily doped semiconductor; the first intercalation layer is made of a low work function material, and the Fermi level of the low work function material is no more than 1 / 3 of the band gap of the channel semiconductor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are semiconductor devices with positive controllability. They have advantages such as small size, simple process, and easy control of device characteristics, and are currently the main active devices for manufacturing large-scale integrated circuits.

[0003] Figure 1 A current-mode MOSFET (N+PN+) is provided in the prior art. However, due to the limitations imposed by the Boltzmann distribution of charge carriers, leakage current is generated by thermal excitation, causing the transistor's current-gate control efficiency to be unable to exceed a subthreshold swing of 60 meV / dec at room temperature. This limits improvements in switching efficiency, reduction of on-state current, and energy consumption. Therefore, reducing the subthreshold swing by modifying device materials and structure has become a hot research topic in the industry in recent years. Summary of the Invention

[0004] This application provides a semiconductor device and its fabrication method, as well as an electronic device, which can reduce the subthreshold swing of transistors.

[0005] This application provides a semiconductor device including a transistor. The transistor includes a channel, a source, and a drain; the source and drain are disposed at opposite ends of the channel; a first intercalation layer is disposed between the source and the channel, and the first intercalation layer is in contact with both the source and the channel. The channel is made of a lightly doped semiconductor or an intrinsic semiconductor. The drain is made of a heavily doped semiconductor. The source is made of a P-type heavily doped semiconductor. In some possible implementations, the first intercalation layer is made of a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the channel semiconductor; in other possible implementations, the source is made of an N-type heavily doped semiconductor; the first intercalation layer is made of a low work function material, and the Fermi level of the low work function material is no more than 1 / 3 of the band gap of the channel semiconductor.

[0006] In the semiconductor device provided in this application embodiment, a first intercalation layer is provided between the source and channel of the transistor. The first intercalation layer can form a Schottky contact with the channel. Taking the P-type heavily doped semiconductor used in the source of the transistor as an example, the first intercalation layer uses a high work function material. The Fermi level of this high work function material is no more than 1 / 3 of the band gap of the valence band of the channel semiconductor. In this case, due to the band structure limitation of the P-type heavily doped semiconductor used in the source, only electrons with energy between the top of the semiconductor valence band and the Fermi surface near the first intercalation layer can enter the first intercalation layer. In this way, the electron energy can be limited to a small range, which is equivalent to forming a "cold" source (i.e., forming "cold" electrons). When the gate voltage of the transistor is not high enough, there are not enough high-energy electrons to cross the Schottky barrier formed by the first intercalation layer 10 and the channel C, and the leakage current is smaller than that of a conventional MOS transistor. When the gate bias increases, the channel barrier decreases, allowing "cold" electrons to quickly cross the barrier and pass through the channel, and the current increases rapidly, thus exhibiting an ultra-low subthreshold swing.

[0007] Of course, when the source of the transistor uses a heavily doped N-type semiconductor, the first intercalation layer uses a low work function material. The Fermi level of this low work function material is no more than 1 / 3 of the band gap of the channel semiconductor conduction band. In this case, due to the band structure limitation of the N-type heavily doped semiconductor used in the source, only holes with energy between the bottom of the semiconductor conduction band and the vicinity of the Fermi surface of the first intercalation layer can enter the first intercalation layer. In this way, the hole energy can be confined to a small range, which is equivalent to forming a "cold" source (i.e., forming a "cold" hole). When the gate voltage (negative voltage) of the transistor is not high enough, there are not enough high-energy holes to cross the Schottky barrier formed by the first intercalation layer and the channel, and the leakage current is small. When the gate negative bias increases, the channel barrier decreases, allowing the "cold" holes to quickly cross the barrier and pass through the channel, and the current increases rapidly, exhibiting an ultra-low subthreshold swing.

[0008] In some possible implementations, the source and channel have the same doping polarity. For example, the source may be a heavily p-doped semiconductor, and the channel a lightly p-doped semiconductor. Another example is the source being a heavily n-doped semiconductor, and the channel a lightly n-doped semiconductor.

[0009] In some possible implementations, the drain and source have opposite doping polarities; the drain is in contact with the channel; thus forming a transistor with a source-drain asymmetric structure. For example, the source is a heavily p-doped semiconductor, the drain is a heavily p-doped semiconductor, the channel is a lightly p-doped semiconductor, and the first intercalation layer is a high work function material. Another example is that the source is a heavily p-doped semiconductor, the drain is a heavily p-doped semiconductor, the channel is a lightly p-doped semiconductor, and the first intercalation layer is a low work function material.

[0010] In some possible implementations, the drain and source have the same doping polarity; a second intercalation layer is disposed between the drain and the channel, and the second intercalation layer is in contact with both the drain and the channel; thus forming a transistor with a source-drain symmetrical structure. For example, the source and drain can both be made of heavily p-type doped semiconductors, the channel can be made of lightly p-type doped semiconductors, and both the first and second intercalation layers can be made of high work function materials. As another example, the source and drain can both be made of heavily n-type doped semiconductors, the channel can be made of lightly n-type doped semiconductors, and both the first and second intercalation layers can be made of low work function materials.

[0011] In some possible implementations, the high work function material may include one or more metallic materials selected from Au, Ni, Pt, Pd, Ru, and Ir.

[0012] In some possible implementations, the high work function material may include one or more metal silicide materials selected from NiSi2, Pt2Si, Pd2Si, and IrSi.

[0013] When silicon or germanium-silicon semiconductors are used in the channel, compared to using a metal material with a high work function in the first intercalation layer, using a metal silicide with a high work function can reduce defects and impurities at the interface between the first intercalation layer and the channel, resulting in a better matching effect between the first intercalation layer and the channel at the interface.

[0014] In some possible implementations, the low work function material may include one or more metallic materials selected from Al, Ta, and Ti.

[0015] In some possible implementations, at least one material selected from TaN and TaSiNi is used.

[0016] In some possible implementations, the thickness of the first intercalation layer is 1 to 10 nm; thus ensuring that the charge carriers remain in a "cold" state after passing through the relatively thin first intercalation layer, ensuring the effect of the cold source.

[0017] In some possible implementations, the second intercalation layer is made of the same material as the first intercalation layer.

[0018] In some possible implementations, the second intercalation layer has the same thickness as the first intercalation layer.

[0019] This application also provides a method for fabricating a semiconductor device, comprising: providing a substrate and sequentially depositing an oxide layer and a gate layer on the substrate surface; exposing a drain by etching the oxide layer and the gate layer, and forming a heavily doped drain at the drain end; exposing a source by etching the substrate to form a transistor channel in the region between the source and drain ends on the substrate surface; forming a first intercalation layer on the side of the channel located at the source end; wherein the first intercalation layer is made of a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the channel semiconductor valence band; or, the first intercalation layer is made of a low work function material, and the Fermi level of the low work function material is no more than 1 / 3 of the band gap of the channel semiconductor conduction band; forming a heavily doped semiconductor layer at the source end as the source of the transistor; wherein the doping polarities of the source and drain are opposite; the intercalation layer is made of a high work function material, and the source is made of a P-type heavily doped semiconductor; or, the intercalation layer is made of a low work function material, and the source is made of an N-type heavily doped semiconductor.

[0020] This application also provides a method for fabricating a semiconductor device, comprising: providing a substrate and sequentially depositing an oxide layer and a gate layer on the substrate surface; exposing a source and a drain by etching the substrate to form a transistor channel in the region between the source and drain on the substrate surface; forming intercalation layers on the sides of the channel at the source and drain; wherein the intercalation layers are made of a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the channel semiconductor valence band; or, the intercalation layers are made of a low work function material, and the Fermi level of the low work function material is no more than 1 / 3 of the band gap of the channel semiconductor conduction band; and forming heavily doped semiconductor layers at the source and drain as the source and drain of the transistor, respectively; wherein the intercalation layers are made of a high work function material, and both the source and drain are made of P-type heavily doped semiconductors; or, the intercalation layers are made of a low work function material, and both the source and drain are made of N-type heavily doped semiconductors.

[0021] This application also provides an electronic device, including a printed circuit board and a semiconductor device as provided in any of the aforementioned possible implementations; the semiconductor device is electrically connected to the printed circuit board. Attached Figure Description

[0022] Figure 1 A schematic diagram of the structure of a MOS transistor provided in the prior art;

[0023] Figure 2 A schematic diagram of a transistor structure provided in an embodiment of this application;

[0024] Figure 3 A schematic diagram of the on and off states of a transistor is provided for embodiments of this application;

[0025] Figure 4A transistor provided in the embodiments of this application and a current-voltage transfer characteristic curve of a transistor provided in the related art;

[0026] Figure 5 A flowchart illustrating a method for fabricating a transistor, as provided in an embodiment of this application;

[0027] Figure 6 A schematic diagram illustrating the manufacturing process of a transistor, provided as an embodiment of this application;

[0028] Figure 7 A schematic diagram of a transistor structure provided in an embodiment of this application;

[0029] Figure 8 A schematic diagram of a transistor structure provided in an embodiment of this application;

[0030] Figure 9 A flowchart illustrating a method for fabricating a transistor, as provided in an embodiment of this application;

[0031] Figure 10 A schematic diagram illustrating the manufacturing process of a transistor, provided as an embodiment of this application;

[0032] Figure 11 A schematic diagram of a transistor structure provided in an embodiment of this application;

[0033] Figure 12 A schematic diagram of a transistor structure provided in an embodiment of this application;

[0034] Figure 13 A flowchart illustrating a method for fabricating a transistor, as provided in an embodiment of this application;

[0035] Figure 14 A schematic diagram of a transistor structure provided in an embodiment of this application;

[0036] Figure 15 This is a flowchart illustrating a method for fabricating a transistor, as provided in an embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Words such as "connected," "linked," etc., are used to express communication or interaction between different components and may include direct connection or indirect connection through other components. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Terms such as "upper," "lower," "left," and "right," etc., are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0039] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0040] This application provides an electronic device, which includes a printed circuit board (PCB) and semiconductor devices connected to the PCB. The semiconductor devices contain transistors. This application does not limit the configuration of the semiconductor devices. Indicatively, the semiconductor devices can be applied to fields such as logic, storage, analog, and sensing; the semiconductor devices can be memory, processors, sensors, etc. This application does not limit the configuration of the electronic device. Indicatively, the electronic device can be a mobile phone, tablet computer, laptop, in-vehicle computer, smartwatch, smart bracelet, etc.

[0041] In the electronic device provided in this application embodiment, the transistor inside the semiconductor device is a cold source Schottky filed effect transistor. This transistor adopts a novel "cold source" maintenance mechanism, channel barrier and current conduction mechanism. By jointly controlling the charge carriers through the cold source electrode and the Schottky channel barrier, it can achieve an ultra-steep subthreshold swing over a wide current range, thereby improving the current switching efficiency and on-state current of the transistor and enhancing the performance of the semiconductor device.

[0042] It is understood that transistors can generally be divided into P-type transistors (i.e., PMOS) and N-type transistors (i.e., NMOS). The following describes the specific configuration of the P-type cold source Schottky transistor (hereinafter referred to as P-type transistor) and N-type cold source Schottky transistor (hereinafter referred to as N-type transistor) used in the semiconductor devices provided in the embodiments of this application, in conjunction with specific embodiments.

[0043] Example 1

[0044] like Figure 2 As shown, this embodiment provides an N-type transistor 01, which includes a channel C and a source S and a drain D located at both ends of the channel C. A first intercalation layer 10 is disposed between the source S and the channel C, and the first intercalation layer 10 is in contact with both the source S and the channel C. The channel C is in contact with the drain D. The source S is a heavily p-doped semiconductor (denoted as P+). The drain D is a heavily n-doped semiconductor (denoted as N+). The channel C is a lightly p-doped semiconductor (denoted as P-) or an intrinsic semiconductor (denoted as i). The following description of this embodiment uses a lightly p-doped semiconductor as an example.

[0045] Of course, transistor 01 also contains other components, such as the gate G and the gate insulating layer located between the gate G and the channel C. For details, please refer to the relevant instructions, which will not be elaborated here.

[0046] It should be noted that, for the heavily doped and lightly doped components involved in this application, the doping concentration can typically be greater than 1E19 / cm³. 3 Defined as heavily doped, with a doping concentration less than 1E19 / cm³. 3 It is defined as lightly doped. Of course, in practice, those skilled in the art can define the doping concentration of heavily doped and lightly doped according to the intrinsic semiconductor material used (such as silicon, germanium silicon, etc.) and the specific doping element (such as trivalent (group 1) element, pentavalent (group 1) element, etc.). This application does not limit the specific doping concentration of lightly doped and heavily doped; it can be set according to actual needs.

[0047] This embodiment does not impose specific restrictions on the semiconductor materials used in the source (S), channel (C), and drain (D), nor on the doping elements and doping concentrations used in the source (S), channel (C), and drain (D).

[0048] In some possible implementations, the source (S) and channel (C) can be made of P-type silicon, with boron (B) as the P-type dopant; the drain (D) can be made of N-type silicon, with phosphorus (P) as the N-type dopant. The doping concentration of the source (S) can be 1E19 / cm³. 3 ~1E21 / cm 3 The doping concentration of C in the channel can be 1E17 / cm. 3 ~1E19 / cm 3 The doping concentration of the drain electrode D can be 1E19 / cm³. 3 ~1E21 / cm 3 .

[0049] In this N-type transistor 01, the doping polarity of the source S matches the work function of the material forming the first intercalation layer 10, which is the core factor constituting the cold source. The doping polarity of the source S and the material of the first intercalation layer 10 directly determine the energy confinement range of the "cold" electrons. In practice, a high work function material for the first intercalation layer 10 can be selected based on the P-type doped source S. The Fermi level of this high work function material is no more than 1 / 3 of the bandgap of the channel semiconductor.

[0050] In this case, the first intercalation layer 10 can form a Schottky contact with the channel C. Due to the band structure limitation of the p-type heavily doped semiconductor used in the source S, only electrons with energy between the top of the semiconductor valence band and the Fermi level of the first intercalation layer 10 can enter the first intercalation layer 10. In this way, the electron energy can be confined to a small range, which is equivalent to forming a "cold" source (i.e., forming "cold" electrons). (Reference) Figure 3 As shown in Figure (a), the off-state energy band structure of the transistor demonstrates that when the gate voltage is insufficient, not enough high-energy electrons can overcome the Schottky barrier formed by the first intercalation layer 10 and the channel C, resulting in a smaller leakage current compared to a conventional MOSFET. (Reference) Figure 3 As shown in the schematic diagram of the on-state energy band of the transistor in (b), when the gate bias increases, the channel barrier decreases, allowing "cold" electrons to quickly cross the barrier and pass through the channel, and the current increases rapidly, thus exhibiting an ultra-low subthreshold swing.

[0051] As illustrated, the high work function material forming the first intercalation layer 10 can be a metallic material, a metal silicide, or a mixture of a metallic material and a metal silicide. The metallic material can be one or more of Au, Ni, Pt, Pd, Ru, and Ir, and the metal silicide can be one or more of NiSi2, Pt2Si, Pd2Si, and IrSi.

[0052] It is understandable that when the channel C uses silicon or germanium-silicon semiconductor, compared to the first intercalation layer 10 using a metal material with a high work function, using a metal silicide with a high work function can reduce defects and impurities at the interface between the first intercalation layer 10 and the channel C, resulting in a better matching effect between the first intercalation layer 10 and the channel C at the interface.

[0053] Furthermore, to prevent electrons from becoming "hot" when passing through the first intercalation layer 10, the thickness of the first intercalation layer 10 can be set to 1nm to 10nm. This ensures that the electrons remain "cool" after passing through the relatively thin first intercalation layer 10, thus maintaining the cooling effect. Illustrated, in some possible implementations, the thickness of the first intercalation layer 10 can be set to 2nm to 5nm.

[0054] In summary, the transistor 01 provided in this embodiment provides a novel "cold source" maintenance mechanism, channel barrier and current conduction mechanism by setting the first intercalation layer 10 to directly contact the channel C to form a Schottky contact, thereby improving the current switching efficiency and on-state current of the transistor and reducing the driving voltage and energy consumption.

[0055] In addition, compared with setting other doped regions (such as N+ doped regions) between the first intercalation layer 10 and the channel C, this application sets the first intercalation layer 10 and the channel C to form a Schottky contact, which enables electrons to directly enter the channel C after passing through the first intercalation layer 10. This reduces the thermal problems caused by various scattering mechanisms before electrons enter the channel C, better maintains the "cold" state of electrons, ensures the cold source effect, and provides a better ultra-steep subthreshold swing scheme.

[0056] Figure 4In this diagram, s1 is a schematic diagram of the current-voltage transfer characteristic curve of a transistor provided in Embodiment 1, s2 is the current-voltage transfer characteristic curve of a conventional transistor (such as an N+PN+ structure) in the prior art, and s3 is the current-voltage transfer characteristic curve of a tunneling transistor (such as a P+iN+ structure). From s1 and s3, it can be seen that compared to a tunneling transistor, the cold-source Schottky transistor provided in Embodiment 1 has a higher current density, thus overcoming the disadvantage of tunneling transistors being unable to be widely used due to their small drive current. Comparing s1 and s2, it can be seen that compared to conventional transistors, the cold-source Schottky transistor provided in Embodiment 1 can better maintain electrons in a "cold" state, thereby achieving an ultra-steep subthreshold swing over a larger current range.

[0057] For illustrative purposes only, please refer to the following: Figure 2 As shown, Embodiment 1 of this application also provides a method for fabricating an N-type transistor O1 with a channel C using a lightly doped P-type semiconductor as described above. Figure 5 As shown, the manufacturing method may include:

[0058] Step 11, Reference Figure 6 As shown in (a) and (b), a substrate 1 is provided, and a channel layer 2 is formed by lightly doping the surface of the substrate 1 with P-type doping.

[0059] As illustrated, substrate 1 can be made of semiconductor materials, such as bulk silicon, silicon on insulating substrate (SOI), silicon germanium (SiGe), germanium (Ge), gallium nitride (GaN), indium gallium arsenide (InGaAs), etc.

[0060] Schematic, in some possible implementations, step 01 above may include: providing a silicon substrate (1), implanting a p-type dopant (such as boron) onto the silicon substrate (1), with a doping concentration of 1E17 / cm. 3 ~1E19 / cm 3 Thus, a lightly doped P-type channel layer 2 is formed on the surface of the silicon substrate (1).

[0061] It is understood that a channel layer 2 is formed on the surface of substrate 1 by light doping in step 11. In this case, the undoped portion below the channel layer 2 serves as the substrate of the device. The channel layer 2 is used to form the channel of the transistor through subsequent fabrication processes, which can be referred to in the subsequent fabrication processes.

[0062] Step 12, Reference Figure 6 As shown in (c), an oxide layer 3 and a gate layer 4 are sequentially deposited on the surface of the channel layer 2.

[0063] It should be noted that the gate layer 4 mentioned above can be a single film layer or multiple film layers (for example, it may include a polysilicon layer and a metal layer). The gate layer 4 is used to form the gate of the transistor through subsequent fabrication processes, which can be referred to in the subsequent fabrication processes for details.

[0064] Indicatively, in some possible implementations, step 02 above may include: growing an oxide layer (such as a silicon dioxide layer) in situ on the surface of the channel layer 2, and then sequentially depositing a polysilicon layer and a metal layer.

[0065] Step 13, Reference Figure 6 As shown in (d), the drain is exposed by etching the oxide layer 3 and the gate layer 4, and an N-type heavily doped semiconductor is formed at the drain as the drain of the transistor.

[0066] Schematic, in some possible implementations, step 13 may include: exposing the drain end on the surface of the channel layer 2 by etching the oxide layer 3 and the gate layer 4, and performing N-type heavy doping on the drain region of the channel layer 2, with a doping concentration of 1E20 / cm³. 3 ~1E21 / cm 3 This is used to form the drain D of the transistor.

[0067] Indicatively, in some other possible implementations, step 13 may include: exposing the drain in the substrate 1 by etching the oxide layer 3, the gate layer 4, and the channel layer 2, and depositing an N-type heavily doped semiconductor (such as N-type silicon) in the drain region to form the drain D of the transistor.

[0068] Step 14, Reference Figure 6 As shown in (e) and (f), the source end S' is exposed by etching the substrate 1, and a first intercalation layer 10 is formed on the side of the channel layer 2 located at the source end S'.

[0069] The first intercalation layer 10 is made of a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the bandgap of the channel semiconductor. The specific selection of this high work function material can be found in the aforementioned description.

[0070] It can be understood here that after the source terminal S' is exposed through step 03, the portion of the gate layer 4 located between the source and drain terminals forms the gate of the transistor, and the portion of the channel layer 2 located between the source and drain terminals forms the channel of the transistor.

[0071] Indicatively, in some possible implementations, step 03 may include: etching the substrate 1, and simultaneously etching the other films (2, 3, 4) on the substrate 1 to expose the source end S'; and depositing metal (such as Au, Ni, Pt, Pd, Ru, Ir) or epitaxial metal silicide (such as NiSi2, Pt2Si, Pd2Si, IrSi) on the side of the channel layer 2 located at the source end S' to form a first intercalation layer 10.

[0072] Step 15, Reference Figure 6 As shown in (g), a P-type heavily doped semiconductor layer is formed at the source end S' as the source S of the transistor.

[0073] Indicatively, in some possible implementations, step 15 above may include: depositing P-type silicon at the source end S' and annealing it to form the source S of the transistor.

[0074] It should be noted that the first intercalation layer 10 formed in step 14 should at least cover the side of the channel layer 2 located at the source end S'. The first intercalation layer 10 can also extend to the source end S' region as needed, and this application does not limit this.

[0075] For example, in some possible implementations, refer to Figure 6 As shown in (f) and (g), the first intercalation layer 10 formed by step 14 can only cover the side of the channel layer 2 located on the source end S' side, without covering the exposed source end S' region in the substrate 1. In this case, the source S is formed directly on the surface of the substrate 1 by step 15.

[0076] For example, among some possible implementation methods, refer to Figure 7 As shown, the first intercalation layer 10 formed in step 15 covers the side of the channel layer 2 located at the source end S' and extends to cover the exposed source end S' region in the substrate 1. In this case, the source electrode S is formed on the surface of the first intercalation layer 10 located at the source end S' region in step 15.

[0077] Of course, as part of the overall transistor fabrication, other fabrication steps may be included after step 15, such as forming a metal contact layer on the surface of the source S and drain D. This application does not limit this, and in practice, an appropriate process can be selected for fabrication as needed.

[0078] For the fabrication method of the N-type transistor 01 with intrinsic semiconductor channel C in this embodiment, the process of lightly doping the surface of substrate 1 in step 11 can be omitted based on the aforementioned fabrication process (steps 11 to 15). The oxide layer 3 and the gate layer 4 can be deposited sequentially on the surface of substrate 1 directly in step 12. The subsequent fabrication process is basically the same and will not be described in detail here.

[0079] Example 2

[0080] Compared to the N-type transistor 01 provided in Embodiment 1, which has an asymmetric source-drain structure, as Figure 8 As shown, this embodiment two provides an N-type transistor 02 with a source-drain symmetrical structure. The differences between this N-type transistor 02 and the N-type transistor 01 in embodiment one will be explained below.

[0081] like Figure 8 As shown, in this transistor 02, both the drain D and the source S are P-type heavily doped semiconductors (P+), meaning that the doping polarity of the drain D and the source S is the same. A first intercalation layer 10 is disposed between the source S and the channel C, and a second intercalation layer 20 is disposed between the drain D and the channel C; the first intercalation layer 10 is in contact with both the source S and the channel C, and the second intercalation layer 20 is in contact with both the drain D and the channel C.

[0082] In this embodiment, the second intercalation layer 20 is configured similarly to the first intercalation layer 10. Both the first intercalation layer 10 and the second intercalation layer 20 are made of high work function materials, and the Fermi level of the high work function material is no more than 1 / 3 of the bandgap of the channel semiconductor. For specific details regarding the first intercalation layer 10 and the second intercalation layer 20 in this second embodiment, such as materials and thicknesses, please refer to the description of the first intercalation layer 10 in the first embodiment; these details will not be repeated here.

[0083] In some possible ways to simplify the manufacturing process and reduce manufacturing costs, the drain (D) and source (S) can be formed simultaneously in the same manufacturing process, that is, the materials and doping concentrations of the drain (D) and source (S) are the same.

[0084] In some possible ways, in order to simplify the manufacturing process and reduce the manufacturing cost, the second intercalation layer 20 and the first intercalation layer 10 can be formed simultaneously using the same manufacturing process, that is, the materials, thicknesses and other properties of the second intercalation layer 20 and the first intercalation layer 10 are the same.

[0085] It is understood that in this second embodiment, by setting the source S and drain D of the N-type transistor 02 to be symmetrical, and intercalation layers (10, 20) are provided between the source S, drain D and channel C, both the source S and drain D can serve as cold sources. The source S and drain D are equivalent structures, so that the source S and drain D can be formed simultaneously in one process when manufacturing the transistor 02, and the first intercalation layer 10 and the second intercalation layer 20 can be formed simultaneously in one process, which simplifies the manufacturing process. In addition, for integrated circuits using this transistor 02, the transistor setting based on the source-drain symmetrical structure can simplify the circuit structure.

[0086] For illustrative purposes only, please refer to the following: Figure 8As shown, this second embodiment also provides a method for fabricating a lightly doped P-type transistor O2 with the channel C as described above. Figure 9 As shown, the manufacturing method may include:

[0087] Step 21, Reference Figure 10 As shown in (a) and (b), a substrate 1 is provided, and a channel layer 2 is formed by lightly doping the surface of the substrate 1 with P-type doping.

[0088] Step 22, Reference Figure 10 As shown in (c), an oxide layer 3 and a gate layer 4 are sequentially deposited on the surface of the channel layer 2.

[0089] Steps 21 and 22 above are basically the same as steps 11 and 12 in the aforementioned embodiment one. For details, please refer to the relevant descriptions of steps 11 and 12 above, which will not be repeated here.

[0090] Step 23, Reference Figure 10 As shown in (d) and (e), the source end S' and the drain end D' are exposed by etching the substrate 1, and a first intercalation layer 10 and a second intercalation layer 20 are formed on the side of the channel layer 2 located at the source end S' and the drain end D', respectively.

[0091] In this design, both the first intercalation layer 10 and the second intercalation layer 20 employ high work function materials, wherein the Fermi level of the high work function material is no more than one-third of the bandgap of the channel semiconductor. The specific selection of this high work function material can be found in the preceding explanation and will not be repeated here.

[0092] The first intercalation layer 10 and the second intercalation layer 20 can be formed separately through two manufacturing processes, or they can be formed simultaneously using the same manufacturing process. Of course, in order to simplify the process and reduce manufacturing costs, the first intercalation layer 10 and the second intercalation layer 20 can be formed simultaneously using the same sequential process.

[0093] Step 24, Reference Figure 10 As shown in (f), P-type heavily doped semiconductor layers are formed at the source end S' and the drain end D' to serve as the source S and drain D of the transistor, respectively.

[0094] Indicatively, in some possible implementations, step 15 above may include: depositing P-type silicon at the source end S' and the drain end D' and annealing it to form the source S and drain D of the transistor.

[0095] It should be noted that the first intercalation layer 10 formed in step 23 at least covers the side of the channel layer 2 located at the source end S', such as Figure 10 As shown in (e), the first intercalation layer 10 may only cover the side of the channel layer 2 located at the source end S'; depending on actual needs, refer to Figure 11As shown, the first interpolation layer 10 can also extend to the source end S' region, and this application does not limit this. Similarly, the second interpolation layer 20 is configured as follows.

[0096] In this embodiment, the method for fabricating an N-type transistor 02 with an intrinsic semiconductor channel C can be omitted from the aforementioned fabrication process (steps 21 to 24). The process of lightly doping the surface of the substrate 1 in step 21 can be omitted. The oxide layer 3 and the gate layer 4 can be deposited sequentially on the surface of the substrate 1 in step 22. The subsequent fabrication process remains basically the same and will not be described in detail here.

[0097] Example 3

[0098] like Figure 12 As shown, this embodiment provides a P-type transistor 03, which includes a channel C and a source S and a drain D located at both ends of the channel C. A first intercalation layer 10 is disposed between the source S and the channel C, and the first intercalation layer 10 is in contact with both the source S and the channel C. The source S is made of an N-type heavily doped semiconductor (denoted as N+). The drain D is made of a P-type heavily doped semiconductor (denoted as P+). The channel C is made of an N-type lightly doped semiconductor (denoted as N-) or an intrinsic semiconductor (denoted as i).

[0099] In this P-type transistor 03, the first intercalation layer 10 uses a low work function material, and the Fermi level of this low work function material is no more than 1 / 3 of the band gap of the channel semiconductor conduction band. In this case, the first intercalation layer 10 can form a Schottky contact with the channel C. Due to the band structure limitation of the N-type heavily doped semiconductor used in the source S, only holes with energy between the bottom of the semiconductor conduction band and the vicinity of the Fermi surface of the first intercalation layer 10 can enter the first intercalation layer 10. This confines the hole energy to a small range, effectively forming a "cold" source (i.e., a "cold" hole). When the gate voltage (negative voltage) of the transistor is not high enough, there are not enough high-energy holes to cross the Schottky barrier formed by the first intercalation layer 10 and the channel C, resulting in a small leakage current. When the gate negative bias increases, the channel barrier decreases, allowing "cold" holes to quickly cross the barrier and pass through the channel, causing the current to increase rapidly and exhibiting an ultra-low subthreshold swing.

[0100] It is understandable that the doping concentration of the source S and the work function of the material forming the first intercalation layer 10 are the core factors constituting the cold source. The source S and the matching first intercalation layer 10 directly determine the energy limit range of the "cold" hole. In practice, the doping concentration of the source S and the material used for the first intercalation layer 10 can be specifically set according to needs.

[0101] Schematic, the low work function material forming the first intercalation layer 10 can be one or more of Al, Ta, Ti, TaN, and TaSiNi.

[0102] To prevent holes from becoming "hot" as they pass through the first intercalation layer 10, the thickness of the first intercalation layer 10 can be set to 1nm to 10nm. This ensures that the holes remain "cold" after passing through the relatively thin first intercalation layer 10, thus maintaining the cooling effect. Illustrated, in some possible implementations, the thickness of the first intercalation layer 10 can be set to 2nm to 5nm.

[0103] For illustrative purposes only, please refer to the following: Figure 12 As shown, Embodiment 3 of this application also provides a method for fabricating a transistor 03 with N-type doped channel C as described above. Figure 13 As shown, the manufacturing method may include:

[0104] Step 31: Provide a substrate and lightly dope the surface of the substrate with N-type to form a channel layer.

[0105] Step 32: Sequentially deposit an oxide layer and a gate layer on the surface of the channel layer.

[0106] Step 33: Expose the drain by etching the oxide layer and the gate layer, and form a heavily doped P-type layer at the drain as the drain of the transistor.

[0107] Step 34: Expose the source end by etching the substrate and form the first intercalation layer on the side of the channel layer located at the source end.

[0108] The first intercalation layer uses a low work function material, and the Fermi level of this material is no more than 1 / 3 of the bandgap of the channel semiconductor. The specific selection of this low work function material can be found in the preceding explanation and will not be repeated here.

[0109] Step 35: Form an N-type heavily doped semiconductor layer at the source end as the source of the transistor.

[0110] For the fabrication method of the N-type transistor 03 with intrinsic semiconductor channel C in this embodiment, the process of lightly doping the surface of substrate 1 in step 31 can be omitted based on the aforementioned fabrication process (steps 31 to 35). The oxide layer 3 and the gate layer 4 can be deposited sequentially on the surface of substrate 1 directly in step 32. The subsequent fabrication process is basically the same and will not be described in detail here.

[0111] The P-type transistor 03 provided in this embodiment 3 is similar to the N-type transistor 01 in embodiment 1. Both are source-drain asymmetric structures. The difference lies in the different polarities of the source, drain, and channel, and the different materials used in the first intercalation layer. For the fabrication method of this P-type transistor 03, please refer to the relevant technology and the relevant description in embodiment 1. It will not be repeated here.

[0112] Example 4

[0113] Compared to the P-type transistor 03 provided in Embodiment 3, which has a source-drain asymmetric structure, as Figure 14 As shown, this embodiment four provides a P-type transistor 04 with a source-drain symmetrical structure. The differences between this P-type transistor 04 and the N-type transistor 03 of embodiment three will be explained below.

[0114] like Figure 14 As shown, in this transistor 04, both the drain D and the source S are N-type heavily doped semiconductors (N+), meaning that the drain D and the source S have the same doping polarity. A first intercalation layer 10 is disposed between the source S and the channel C, and a second intercalation layer 20 is disposed between the drain D and the channel C; the first intercalation layer 10 is in contact with both the source S and the channel C, and the second intercalation layer 20 is in contact with both the drain D and the channel C.

[0115] In this embodiment, the second intercalation layer 20 is configured similarly to the first intercalation layer 10 (see the previous embodiment). Both the first intercalation layer 10 and the second intercalation layer 20 are made of low work function materials, and the Fermi level of the low work function material is no more than 1 / 3 of the bandgap of the channel semiconductor. For specific details regarding the configuration of the first intercalation layer 10 and the second intercalation layer 20 in this fourth embodiment, such as materials and thicknesses, please refer to the description of the first intercalation layer 10 in the third embodiment; these details will not be repeated here.

[0116] Indicatively, this fourth embodiment also provides a method for fabricating a P-type transistor O4 with a lightly doped N-type channel C as described above, such as... Figure 15 As shown, the manufacturing method may include:

[0117] Step 41: Provide a substrate and lightly dope the surface of the substrate with N-type to form a channel layer.

[0118] Step 42: Sequentially deposit an oxide layer and a gate layer on the surface of the channel layer.

[0119] Step 43: Expose the source and drain ends by etching the substrate, and form the first intercalation layer and the second intercalation layer on the sides of the channel layer located at the source and drain ends, respectively.

[0120] The first and second intercalation layers mentioned above use the same low work function material, and the Fermi level of this low work function material is no more than 1 / 3 of the bandgap of the channel semiconductor conduction band. The specific selection of this low work function material can be found in the previous explanation and will not be repeated here.

[0121] Step 44: Form N-type heavily doped semiconductor layers at the source and drain ends to serve as the source and drain of the transistor, respectively.

[0122] In this embodiment, the method for fabricating a P-type transistor 04 with an intrinsic semiconductor channel C can be omitted from the aforementioned fabrication process (steps 41 to 44). The process of lightly doping the surface of the substrate 1 in step 41 can be omitted. The oxide layer 3 and the gate layer 4 can be deposited sequentially on the surface of the substrate 1 in step 42. The subsequent fabrication process remains basically the same and will not be described in detail here.

[0123] The P-type transistor 04 provided in this embodiment 4 is similar to the N-type transistor 02 in embodiment 2. Both are source-drain symmetrical structures. The difference lies in the different polarities of the source, drain, and channel, and the different materials used in the first intercalation layer. For relevant descriptions and manufacturing methods of the P-type transistor 04, please refer to the relevant technologies and the relevant descriptions in embodiment 1. They will not be repeated here.

[0124] It should be noted that the foregoing embodiments of this application are all illustrated using planar MOSFETs (metal oxide semiconductor field effect transistors) as an example, but this application is not limited to this. The cold source Schottky transistor configuration provided in the embodiments of this application is also applicable to transistors with various gate control structures such as vertical MOSFETs, fin field effect transistors (FinFETs), gate all around field effect transistors (GAAFETs), ferroelectric field effect transistors (FeFETs), and floating gate field effect transistors.

[0125] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized by, Including transistors; The transistor includes a channel, a source, and a drain; the source and drain are disposed at both ends of the channel; A first intercalation layer is disposed between the source electrode and the channel, and the first intercalation layer is in contact with both the source electrode and the channel; The channel is made of lightly doped semiconductor or intrinsic semiconductor, and the drain is made of heavily doped semiconductor. The source electrode is a P-type heavily doped semiconductor; the first intercalation layer is a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the valence band of the channel semiconductor. Alternatively, the source may be an N-type heavily doped semiconductor; the first intercalation layer may be a low work function material, and the Fermi level of the low work function material may be no more than 1 / 3 of the bandgap of the channel semiconductor.

2. The semiconductor device according to claim 1, characterized in that, The source electrode and the channel electrode have the same doping polarity.

3. The semiconductor device according to claim 1 or 2, characterized in that, The drain electrode has the opposite doping polarity to the source electrode; The drain electrode is in contact with the channel.

4. The semiconductor device according to claim 1, characterized in that, The drain and the source have the same doping polarity; A second intercalation layer is provided between the drain and the channel, and the second intercalation layer is in contact with both the drain and the channel.

5. The semiconductor device according to claim 1, characterized in that, The high work function material includes one or more metallic materials selected from Au, Ni, Pt, Pd, Ru, and Ir.

6. The semiconductor device according to claim 1, characterized in that, The high work function material includes one or more metal silicide materials selected from NiSi2, Pt2Si, Pd2Si, and IrSi.

7. The semiconductor device according to claim 1, characterized in that, The low work function material includes one or more of Al, Ta, Ti, TaN, and TaSiNi.

8. The semiconductor device according to claim 1, characterized in that, The thickness of the first intercalation layer is 1~10nm.

9. The semiconductor device according to claim 4, characterized in that, The second intercalation layer is made of the same material as the first intercalation layer.

10. The semiconductor device according to claim 4 or 9, characterized in that, The second intercalation layer has the same thickness as the first intercalation layer.

11. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, and an oxide layer and a gate layer are sequentially deposited on the surface of the substrate; The drain is exposed by etching the oxide layer and the gate layer, and a heavily doped drain is formed at the drain. The source terminal is exposed by etching the substrate to form a transistor channel in the region on the substrate surface between the source terminal and the drain terminal; A first intercalation layer is formed on the side of the channel located at the source end; wherein the first intercalation layer is made of a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the valence band of the channel semiconductor; or, the first intercalation layer is made of a low work function material, and the Fermi level of the low work function material is no more than 1 / 3 of the band gap of the conduction band of the channel semiconductor. A heavily doped semiconductor layer is formed at the source end as the source of the transistor; wherein the doping polarity of the source is opposite to that of the drain; the intercalation layer uses the high work function material and the source uses a P-type heavily doped semiconductor; or, the intercalation layer uses the low work function material and the source uses an N-type heavily doped semiconductor.

12. A method for fabricating a semiconductor device, characterized in that, A substrate is provided, and an oxide layer and a gate layer are sequentially deposited on the surface of the substrate; The source and drain terminals are exposed by etching the substrate to form a transistor channel in the region between the source and drain terminals on the substrate surface; Intercalation layers are formed on the sides of the channel at the source and drain ends, respectively; wherein the intercalation layers are made of high work function materials, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the channel semiconductor valence band; or, the intercalation layers are made of low work function materials, and the Fermi level of the low work function material is no more than 1 / 3 of the band gap of the channel semiconductor conduction band. Heavily doped semiconductor layers are formed at the source and drain ends to serve as the source and drain of the transistor, respectively; wherein the intercalation layer uses the high work function material, and both the source and drain are P-type heavily doped semiconductors; or, the intercalation layer uses the low work function material, and both the source and drain are N-type heavily doped semiconductors.

13. An electronic device comprising a printed circuit board and a semiconductor device as described in any one of claims 1-10; The semiconductor device is electrically connected to the printed circuit board.

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