Semiconductor epitaxial structure, preparation method therefor and use thereof

Abstract

The application provides a semiconductor epitaxial structure, a preparation method and application thereof. The p-type semiconductor layer of the semiconductor epitaxial structure comprises a p-type barrier layer, the p-type barrier layer comprises at least one p-type structure, the p-type structure comprises a barrier front sublayer, a p-type nitride microstructure and a barrier rear sublayer arranged in sequence, the p-type nitride microstructure comprises a plurality of nano protrusions distributed on the surface of the barrier front sublayer away from the active layer, the barrier rear sublayer covers the plurality of nano protrusions and the surface of the barrier front sublayer not covered by the nano protrusions; the material of the barrier front sublayer is a first nitride doped with an acceptor impurity, the material of the nano protrusions is a second nitride, and the valence band of the second nitride is higher than that of the first nitride. The p-type nitride microstructure is arranged in the p-type barrier layer to reduce the activation energy of the acceptor doping, and a stronger polarization effect is formed at the interface, so that the hole concentration is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a semiconductor epitaxial structure, its preparation method, and its application. Background Technology

[0002] In recent years, significant progress has been made in the research of nitride-based devices, but many challenges remain. Low-resistivity p-type doping is one of the obstacles hindering the widespread application of nitride materials. Mg is the primary p-type dopant, but the Mg-H passivation effect is a major factor restricting the development of nitride-based devices. This is because Mg has a low activation efficiency, typically less than 1%, and the increased Al content in nitrides leads to higher ionization energy, further complicating the achievement of high carrier concentration and high mobility. Furthermore, since electrons migrate faster than holes and the concentration of free electrons is higher, the distribution of electrons and holes in the active layer tends to be uneven. Holes tend to concentrate in the active layer closer to the p-type layer, gradually decaying towards the n-type layer, which is detrimental to electron-hole recombination.

[0003] Therefore, improving the doping efficiency and conductivity of p-type nitride materials is of great significance for the application of nitride materials, and there is an urgent need to propose a semiconductor epitaxial structure with a p-type nitride layer with high hole concentration. Summary of the Invention

[0004] To solve all or part of the above-mentioned technical problems, the present invention provides the following technical solutions:

[0005] One objective of this invention is to provide a semiconductor epitaxial structure comprising an n-type semiconductor layer, an active layer, and a p-type semiconductor layer sequentially disposed along a first direction. The p-type semiconductor layer includes a p-type barrier layer, and the p-type barrier layer includes at least one p-type structure sequentially disposed along a first direction away from the active layer. The p-type structure includes a pre-barrier sublayer, a p-type nitride microstructure, and a post-barrier sublayer sequentially disposed along the first direction away from the active layer. The p-type nitride microstructure includes a plurality of nanoprotrusions distributed on the surface of the pre-barrier sublayer away from the active layer. The post-barrier sublayer covers the plurality of nanoprotrusions and the surface of the pre-barrier sublayer not covered by the nanoprotrusions. The material of the pre-barrier sublayer is a first nitride doped with acceptor impurities, and the material of the nanoprotrusions is a second nitride, wherein the valence band of the second nitride is higher than that of the first nitride.

[0006] This invention introduces p-type nitride microstructures into a p-type barrier layer. The higher valence band of the second nitride constituting the p-type nitride microstructure balances the energy levels of the first nitride and the acceptor impurity, reducing the activation energy of acceptor doping and thus increasing the hole concentration in the p-type barrier layer. Furthermore, a strong polarization effect can be formed at the interfaces between the p-type nitride microstructure and the pre-barrier and post-barrier sublayers, resulting in a high-hole-concentration two-dimensional hole gas at the interfaces, further increasing the hole concentration.

[0007] In some embodiments, a plurality of the nanoprotrusions are spaced apart along a second direction, which is perpendicular to the first direction.

[0008] In some embodiments, the nanoprotrusions are hemispherical in shape, and the radius of the nanoprotrusions is 500-1500 nm.

[0009] In some embodiments, the distance between two adjacent nanoprotrusions is 100-1000 nm.

[0010] In some embodiments, the material of the sublayer behind the barrier is the same as the material of the sublayer in front of the barrier.

[0011] In some embodiments, the first nitride is Mg-doped AlGaN, and the second nitride is Mg-doped GaN.

[0012] In some embodiments, the Al concentration in the post-barrier sublayer is lower than the Al concentration in the pre-barrier sublayer. The post-barrier sublayer has a higher Al concentration than the pre-barrier sublayer, which increases the polarization effect between them, forming a high-hole-concentration two-dimensional hole gas at their interface, synergistically enhancing the hole concentration with the p-type nitride microstructure.

[0013] In some preferred embodiments, the Al concentration in the sublayer behind the barrier is more than 10% lower than the Al concentration in the sublayer in front of the barrier.

[0014] In some embodiments, the thickness of the n-type semiconductor layer is 1-5 μm.

[0015] In some embodiments, the active layer includes 2-15 quantum well structures, each quantum well structure including a quantum well layer with a thickness of 1-5 nm and a quantum barrier layer with a thickness of 6-25 nm.

[0016] In some embodiments, the thicknesses of the pre-barrier sublayer and the post-barrier sublayer in the p-type barrier layer are 5-10 nm, respectively.

[0017] In some embodiments, the p-type semiconductor layer further includes a p-type nitride top layer, and the p-type barrier layer and the p-type nitride top layer are sequentially disposed along a first direction.

[0018] In some embodiments, the thickness of the p-type nitride top layer is 50-150 nm.

[0019] The nitrides contained in the aforementioned n-type semiconductor layer, p-type nitride top layer, quantum well layer, and quantum barrier layer can be any existing one or more combinations, and the present invention does not impose any particular limitation on them, such as GaN, AlN, AlGaN, InN, InGaN, AlInN, AlInGaN, etc.

[0020] The second objective of this invention is to provide a method for preparing a semiconductor epitaxial structure, comprising:

[0021] An n-type semiconductor layer and an active layer are sequentially grown on a substrate;

[0022] A p-type semiconductor layer is grown on the active layer;

[0023] The p-type semiconductor layer includes a p-type barrier layer. The p-type barrier layer includes at least one p-type structure sequentially disposed along a first direction away from the active layer. The p-type structure includes a pre-barrier sublayer, a p-type nitride microstructure, and a post-barrier sublayer sequentially disposed along the first direction away from the active layer. The p-type nitride microstructure includes a plurality of nano-protrusions distributed on the surface of the pre-barrier sublayer away from the active layer. The post-barrier sublayer covers the plurality of nano-protrusions and the surface of the pre-barrier sublayer not covered by the nano-protrusions. The material of the pre-barrier sublayer is a first nitride doped with acceptor impurities, and the material of the nano-protrusions is a second nitride, wherein the valence band of the second nitride is higher than that of the first nitride.

[0024] In some embodiments, growing a p-type semiconductor layer on the active layer includes:

[0025] S1: Grow the front sublayer of the barrier layer on the active layer;

[0026] S2: Growing In nanostructures on the sublayer in front of the barrier;

[0027] S3: Under inert atmosphere conditions, nitrogen source is introduced to perform N thermal annealing treatment on the In nanostructure to transform the In nanostructure into an InN nanostructure.

[0028] S4: Anneal the InN nanostructure and introduce a growth source to grow the nanoprotrusions and the back layer of the barrier on the front sublayer.

[0029] The preparation method provided by the present invention can form multiple nano-protrusions between the pre-barrier sublayer and the post-barrier sublayer, and the multiple nano-protrusions constitute the p-type nitride microstructure to increase the hole concentration.

[0030] In some embodiments, the annealing treatment of the InN nanostructure specifically includes:

[0031] S41: Under inert atmosphere conditions, the InN nanostructure is subjected to thermal annealing treatment with the introduction of a selected metal source, so that In in the InN nanostructure precipitates to form vacancy-N bond aggregation centers, and selected metal atoms in the selected metal source diffuse toward the vacancy-N bond aggregation centers to generate the nano protrusions.

[0032] S42: Under inert atmosphere conditions, the structure obtained in step S41 is subjected to Mg thermal annealing treatment.

[0033] Mg thermal annealing can form Mg pre-deposition, reduce the Mg memory effect of the sublayer behind the barrier, and improve the Mg incorporation efficiency of the sublayer behind the barrier.

[0034] In some embodiments, S41 specifically includes: introducing a Ga source to perform the thermal annealing treatment for 30-90 seconds under conditions of a temperature of 1000-1150℃, a pressure of 100-300 torr, and an inert atmosphere, thereby forming nano-protrusions made of GaN material.

[0035] In some embodiments, S42 specifically includes: introducing a Mg source to perform the Mg thermal annealing treatment for 100-300s under conditions of a temperature of 950-1050℃, a pressure of 100-300 torr, and an inert atmosphere.

[0036] In some embodiments, step S2 specifically includes:

[0037] S21: Under the conditions of first temperature and first pressure, the sublayer in front of the barrier is subjected to thermal annealing for a first preset time in a reducing atmosphere;

[0038] S22: Perform In thermal annealing on the sublayer in front of the barrier;

[0039] S23: Repeat S21-S22 a preset number of times.

[0040] Step S21 removes surface dislocations of the sublayer before the potential barrier through thermal annealing, which helps to improve the aggregation uniformity of In atoms.

[0041] In some embodiments, step S21 specifically includes: performing thermal annealing on the front sublayer of the barrier for 10-30 seconds under conditions of a temperature of 650-750°C, a pressure of 200-400 torr, and an H2 atmosphere.

[0042] In some embodiments, step S22 specifically includes:

[0043] S221: Under the conditions of second temperature, second pressure and inert atmosphere, the first In heat annealing treatment is carried out at a first flow rate for a second preset time.

[0044] S222: Under the conditions of third temperature, third pressure and inert atmosphere, the In source is introduced at a second flow rate to perform a second In heat annealing treatment for a third preset time;

[0045] Wherein, the second temperature is higher than the third temperature, and the first flow rate is higher than the second flow rate.

[0046] Step S221 involves first performing In thermal annealing at a relatively high temperature, which improves the in-plane migration of In atoms in the sublayer before the barrier and, combined with a higher In source flux, promotes a uniform distribution of In atoms. Then, In thermal annealing is performed at a relatively low temperature, which promotes the aggregation of In atoms into nuclei and, combined with a lower In source flux, improves the migration ability of In atoms on the surface of the nucleation center, thus stabilizing the distribution of In aggregation centers. As a result, In nanostructures can be formed on the surface of the sublayer before the barrier, providing a basis for the formation of p-type nitride microstructures.

[0047] In some embodiments, the preset number of times is 5 to 20 times.

[0048] In some embodiments, step S221 specifically includes: performing the first In thermal annealing treatment for 10-30 seconds by introducing an In source with a flow rate of 1000-2000 sccm under conditions of a temperature of 650-750°C, a pressure of 300-600 torr, and an N2 atmosphere; then stopping the introduction of the In source and performing thermal annealing treatment for 5-15 seconds under conditions of a temperature of 650-750°C, a pressure of 300-600 torr, and an N2 atmosphere.

[0049] In some embodiments, step S222 specifically includes: introducing an In source with a flow rate of 5000-1200 sccm to perform the second In thermal annealing treatment for 20-100 seconds under conditions of a temperature of 600-700°C, a pressure of 100-300 torr, and an N2 atmosphere; then stopping the introduction of the In source and performing a thermal annealing treatment for 10-40 seconds under conditions of a temperature of 600-700°C, a pressure of 100-300 torr, and an N2 atmosphere.

[0050] Steps S221 and S222 involve performing thermal annealing for a certain period of time after the In thermal annealing process is completed, under the condition that the In source is stopped. This can further promote the aggregation and nucleation of In atoms covering the sublayer surface deposited in front of the barrier.

[0051] In some embodiments, the growth of the sublayer in front of the barrier includes: growing a thickness of 5-10 nm and a Mg doping concentration of 2×10⁻⁶ under conditions of a temperature of 780-850°C and a pressure of 100-300 torr. 19 -2×10 20 cm -3 The potential barrier of the sublayer.

[0052] In some embodiments, the growth of the sublayer behind the barrier includes: growing a thickness of 5-10 nm and a Mg doping concentration of 2×10⁻⁶ under conditions of a temperature of 780-850°C and a pressure of 100-300 torr. 19 -2×10 20 cm -3 The potential barrier behind the sublayer.

[0053] In some embodiments, step S3 specifically includes: introducing NH3 at a flow rate of 20-100 slm to perform the N-heat annealing treatment for 120-480 s under conditions of a temperature of 650-750℃ and a pressure of 100-300 torr.

[0054] In some embodiments, steps S1-S4 are performed once or repeated multiple times; preferably, steps S1-S4 are performed 1-5 times.

[0055] In some embodiments, the growth of the n-type semiconductor layer includes: growing a thickness of 1-5 μm and a Si doping concentration of 1×10⁻⁶ under conditions of a temperature of 1050-1250°C and a pressure of 100-400 torr. 18 -1×10 19 cm -3 n-type semiconductor layer.

[0056] In some embodiments, the active layer includes 2-15 quantum well structures sequentially disposed along a first direction away from the n-type semiconductor layer, each quantum well structure including a stacked quantum well layer and a quantum barrier layer, and the growth of the quantum well structure includes:

[0057] Quantum well layers with a thickness of 1-5 nm are grown under conditions of temperature 650-850℃ and pressure 150-350 torr.

[0058] A quantum barrier layer with a thickness of 6-25 nm is grown on the quantum well layer under conditions of temperature 700-950℃ and pressure 150-350 torr.

[0059] In some embodiments, the preparation method further includes growing the p-type nitride top layer on the p-type barrier layer.

[0060] In some embodiments, the growth of the p-type nitride top layer includes: growing a thickness of 50-150 nm and a Mg doping concentration of 1×10⁻⁶ under conditions of a temperature of 950-1050°C and a pressure of 200-600 torr. 19 -1×10 20 cm -3 The top layer of the p-type nitride.

[0061] A third objective of this invention is to provide a semiconductor epitaxial structure, wherein the semiconductor epitaxial structure is prepared by any of the methods described herein.

[0062] The fourth objective of this invention is to provide a semiconductor device, the semiconductor device comprising the aforementioned semiconductor epitaxial structure.

[0063] Compared with the prior art, the present invention has at least the following beneficial effects:

[0064] This invention introduces p-type nitride microstructures into a p-type barrier layer. By utilizing the higher valence band of the second nitride in the p-type nitride microstructure to balance the energy levels of the first nitride and the acceptor impurity, the activation energy of acceptor doping is reduced, thereby increasing the hole concentration in the p-type barrier layer. Furthermore, a strong polarization effect can be formed at the interfaces between the p-type nitride microstructure and the pre-barrier and post-barrier sublayers, thereby forming a two-dimensional hole gas with a high hole concentration at the interface, further increasing the hole concentration.

[0065] The p-type barrier layer provided by this invention has an Al component concentration difference between the post-barrier sublayer and the pre-barrier sublayer, thereby increasing the polarization effect between the pre-barrier sublayer and the post-barrier sublayer, forming a two-dimensional hole gas with high hole concentration at the interface between the two, which synergistically increases the hole concentration with the p-type nitride microstructure.

[0066] The semiconductor epitaxial structure provided by this invention, based on the high hole concentration in the p-type semiconductor layer, can balance the injection of electrons in the n-type semiconductor layer and holes in the p-type semiconductor layer, thereby improving the brightness of the epitaxial structure, reducing the operating voltage, and mitigating the droop effect that occurs in the epitaxial structure with increasing injection current. This semiconductor epitaxial structure is suitable for high-current operating conditions, meeting the current application requirements for high-power epitaxial wafers. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1This is a schematic diagram of a semiconductor epitaxial structure according to one embodiment of the present invention;

[0069] Figure 2 This is a schematic diagram of the semiconductor epitaxial structure in another embodiment of the present invention;

[0070] Figure 3 This is a schematic diagram of the semiconductor epitaxial structure in another embodiment of the present invention;

[0071] 100 - Substrate, 200 - n-type semiconductor layer, 300 - Active layer, 401 - p-type structure, 4011 - Pre-barrier sublayer, 4012 - Post-barrier sublayer, 4013 - Nano-protrusion, 402 - p-type nitride top layer. Detailed Implementation

[0072] The technical solutions of the present invention will be described in detail below with reference to specific embodiments, so that those skilled in the art can better understand and implement the technical solutions of the present invention. The specific functional details disclosed herein should not be construed as limiting, but are merely intended to form the basis of the claims and to teach those skilled in the art to employ the representative basis of the invention in different ways in any suitable detailed embodiment.

[0073] To address the problems of low activation efficiency and low hole concentration of p-type dopants (e.g., Mg) in existing p-type semiconductor structures, this invention provides a semiconductor epitaxial structure based on a high-hole-concentration p-type barrier layer by setting p-type nitride microstructures in the p-type nitride layer to increase the hole concentration.

[0074] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the semiconductor epitaxial structure provided by the present invention. The semiconductor epitaxial structure includes a substrate 100, an n-type semiconductor layer 200, an active layer 300, and a p-type semiconductor layer sequentially disposed along a first direction.

[0075] The p-type semiconductor layer includes a p-type barrier layer, which includes a p-type structure 401. The p-type structure 401 includes a pre-barrier sublayer 4011, a p-type nitride microstructure, and a post-barrier sublayer 4012, which are sequentially arranged along a first direction away from the active layer 300. The p-type nitride microstructure includes a plurality of nano-protrusions 4013 distributed on the surface of the pre-barrier sublayer 4011 away from the active layer 300. The post-barrier sublayer 4012 covers the plurality of nano-protrusions 4013 and the surface of the pre-barrier sublayer 4011 not covered by the nano-protrusions 4013. The material of the pre-barrier sublayer 4011 is a first nitride doped with acceptor impurities, and the material of the nano-protrusions 4012 is a second nitride. The valence band of the second nitride is higher than that of the first nitride.

[0076] Furthermore, the material of the barrier sublayer 4011 can be Mg-doped AlGaN, i.e., the first nitride is AlGaN; the material of the nano-protrusions 4012 can be Mg-doped GaN, i.e., the second nitride is GaN.

[0077] Furthermore, the material of the back sublayer 4012 can be the same as that of the front sublayer 4011, for example, Mg-doped AlGaN.

[0078] Furthermore, the Al concentration in the sublayer 4012 behind the barrier is lower than the Al concentration in the sublayer 4011 in front of the barrier. For example, the Al concentration in the sublayer 4012 behind the barrier is more than 10% lower than the Al concentration in the sublayer 4011 in front of the barrier.

[0079] Please refer to Figure 2 In another embodiment, the p-type barrier layer includes a plurality of p-type structures 401 arranged sequentially along a first direction away from the active layer 300.

[0080] Please refer to Figure 3 In another embodiment, the p-type semiconductor layer further includes a p-type nitride top layer 402, and the p-type barrier layer and the p-type nitride top layer 402 are sequentially disposed along a first direction.

[0081] The present invention also provides a method for preparing a semiconductor epitaxial structure, the method comprising:

[0082] (1) An n-type semiconductor layer and an active layer are grown sequentially on the substrate.

[0083] The substrate serves as the support for the growth of the semiconductor epitaxial structure, and the n-type semiconductor layer is the injection layer for charge carriers (electrons) in the active layer.

[0084] The method for growing an n-type semiconductor layer on a substrate can be as follows: Under conditions of 1050-1250℃ and 100-400 torr, a thickness of 1-5 μm and a Si doping concentration of 1×10⁻⁶ can be grown. 18 -1×10 19 cm -3 n-type semiconductor layer.

[0085] The active layer serves as the active region of the semiconductor epitaxial structure, where charge carriers recombine and emit light. The active layer may include 2-15 quantum well structures sequentially arranged along a first direction away from the n-type semiconductor layer. Each quantum well structure includes a stacked quantum well layer and a quantum barrier layer. The growth of the quantum well structures may include:

[0086] A1: A quantum well layer with a thickness of 1-5 nm is grown under conditions of temperature of 650-850℃ and pressure of 150-350 torr.

[0087] A2: A quantum barrier layer with a thickness of 6-25 nm is grown on the quantum well layer under the conditions of temperature of 700-950℃ and pressure of 150-350 torr.

[0088] (2) Growing a p-type semiconductor layer on the active layer, including the following steps S1-S4:

[0089] S1. Grow a barrier sublayer on the active layer.

[0090] The growth of the sublayer in front of the barrier includes: growing a thickness of 5-10 nm and a Mg doping concentration of 2 × 10⁻⁶ under conditions of temperature 780-850℃, pressure 100-300 torr. 19 -2×10 20 cm -3 The potential barrier of the sublayer.

[0091] S2. In nanostructures are grown on the sublayer in front of the barrier.

[0092] In one embodiment, step S2 specifically includes:

[0093] S21. Under the conditions of first temperature and first pressure, the sublayer in front of the barrier is subjected to thermal annealing for a first preset time in a reducing atmosphere.

[0094] The sublayer in front of the barrier is subjected to thermal annealing for 10-30 seconds under the conditions of 650-750℃, 200-400 torr, and H2 atmosphere.

[0095] Thermal annealing in a reducing atmosphere can act as a dislocation etching process, removing the dislocation distribution on the sublayer surface before the barrier and improving the uniformity of In atom aggregation after annealing.

[0096] S22. Perform In thermal annealing on the sublayer in front of the barrier.

[0097] In an In-source heat treatment is performed at a temperature of 600-750℃.

[0098] In thermal annealing forms an In atom-covered deposition on the surface of the sublayer in front of the barrier.

[0099] S23. Repeat S21-S22 5-20 times to form In nanostructures.

[0100] To further improve the uniformity of In atom nucleation and the distribution stability of In nanostructures, in another embodiment, step S22 specifically includes:

[0101] S221. Under the conditions of second temperature, second pressure and inert atmosphere, the first In heat annealing treatment is carried out at a first flow rate for a second preset time.

[0102] Under conditions of 650-750℃, 300-600 torr and N2 atmosphere, an In source with a flow rate of 1000-2000 sccm is introduced to perform the first In thermal annealing treatment for 10-30s; then the In source is stopped, and a thermal annealing treatment is performed for 5-15s under conditions of 650-750℃, 300-600 torr and N2 atmosphere.

[0103] In the first In thermal annealing process, the relatively high temperature can improve the in-plane migration of In atoms in the sublayer in front of the barrier, and the relatively high In flux can improve the uniformity of In atom distribution in the plane. Combined with the thermal annealing process under the condition of stopping the supply of In source, the uniformity of In atom nucleation is achieved.

[0104] S222. Under the conditions of third temperature, third pressure and inert atmosphere, the In source is introduced at a second flow rate to perform a second In heat annealing treatment for a third preset time.

[0105] Under conditions of 600-700℃, 100-300 torr and N2 atmosphere, an In source with a flow rate of 500-1200 sccm is introduced to perform the second In thermal annealing treatment for 20-100s; then the In source is stopped, and thermal annealing treatment is performed for 10-40s under conditions of 600-700℃, 100-300 torr and N2 atmosphere.

[0106] In the second In thermal annealing process, the relatively low temperature can improve the aggregation and nucleation of In atoms at the In atom nucleation center, and the relatively low In flow rate can improve the migration ability of the In nucleation center surface, thereby improving the distribution stability of the In aggregation center.

[0107] S3. Under inert atmosphere conditions, nitrogen source is introduced to perform N thermal annealing treatment on In nanostructures.

[0108] Under conditions of 650-750℃ and 100-300 torr, N-heat annealing is performed by introducing NH3 at a flow rate of 20-100 slm for 120-480s.

[0109] N-thermal annealing transforms In nanostructures into InN nanostructures.

[0110] S4. Anneal the InN nanostructure and introduce a growth source to grow nano-protrusions on the pre-barrier sublayer and the post-barrier sublayer.

[0111] In one embodiment, the annealing process in step S4 specifically includes:

[0112] S41. Under inert atmosphere conditions, the InN nanostructure is subjected to thermal annealing treatment with the introduction of a selected metal source.

[0113] The thermal annealing process causes In to precipitate in the InN nanostructure, forming vacancy-N bond aggregation centers, and selected metal atoms from the selected metal source diffuse toward the vacancy-N bond aggregation centers to generate nanoprotrusions.

[0114] The selected metal source can be a Ga source. Under the conditions of a temperature of 1000-1150℃, a pressure of 100-300 torr and an inert atmosphere, the Ga source is introduced to carry out the thermal annealing treatment for 30-90s to form GaN nanoprotrusions.

[0115] By utilizing the higher GaN valence band to balance the p-type barrier layer and the Mg acceptor level, the activation energy of Mg acceptor doping is reduced, thereby increasing the hole concentration in the p-type barrier layer. Furthermore, a strong polarization effect can be formed at the interface between the GaN nanoprotrusions and the p-type barrier layer, creating a high-hole-concentration two-dimensional hole gas at the interface, further increasing the hole concentration.

[0116] S42: Under inert atmosphere conditions, the structure obtained in step S41 is subjected to Mg thermal annealing treatment.

[0117] Under conditions of 950-1050℃, 100-300 torr and inert atmosphere, Mg source is introduced for Mg thermal annealing for 100-300s.

[0118] Mg thermal annealing can form Mg pre-deposition, reduce the Mg memory effect of the sublayer behind the barrier, and improve the Mg incorporation efficiency of the sublayer behind the barrier.

[0119] The growth of the sublayer behind the barrier can include: growing a thickness of 5-10 nm and a Mg doping concentration of 2 × 10⁻⁶ under conditions of 780-850℃ and 100-300 torr. 19 -2×10 20 cm -3 The potential barrier behind the sublayer.

[0120] In another embodiment, steps S1-S4 are repeated to form a p-type barrier layer composed of multiple p-type structures, for example, repeating the steps 2, 3, 4, or 5 times.

[0121] In another embodiment, the above preparation method further includes growing a p-type nitride top layer on a p-type barrier layer.

[0122] Furthermore, the growth of the p-type nitride top layer can include: growing a thickness of 50-150 nm and a Mg doping concentration of 1×10⁻⁶ under conditions of 950-1050 °C and 200-600 torr.19 -1×10 20 cm -3 The top layer of the p-type nitride.

[0123] The present invention also provides a semiconductor device comprising the above-described semiconductor epitaxial structure.

[0124] The technical solution of the present invention will now be described in full and in detail with reference to specific embodiments.

[0125] Example 1

[0126] This embodiment provides a semiconductor epitaxial structure, which includes an n-type GaN layer, an active layer, and a p-type semiconductor layer sequentially disposed on a substrate. The p-type semiconductor layer includes a p-type barrier layer and a p-type GaN top layer sequentially disposed along the direction away from the active layer.

[0127] The substrate is a sapphire substrate; the thickness of the n-type GaN layer is 3 μm; the active layer has 5 quantum well structures, each of which has an InGaN quantum well layer with a thickness of 2 nm and a GaN quantum barrier layer with a thickness of 10 nm.

[0128] The p-type barrier layer includes a p-type structure comprising a pre-barrier sublayer, a p-type nitride microstructure, and a post-barrier sublayer. The p-type nitride microstructure includes multiple nanoprotrusions distributed on the surface of the pre-barrier sublayer away from the active layer. The pre-barrier and post-barrier sublayers are formed of Mg-doped AlGaN, and the nanoprotrusions are formed of Mg-doped GaN. The radius of the nanoprotrusions is 800 nm, and the distance between two adjacent nanoprotrusions is approximately 650 nm.

[0129] Furthermore, the pre-barrier sublayer and post-barrier sublayer of the p-type barrier layer are both 8 nm thick; the thickness of the top layer of the p-type GaN is 100 nm.

[0130] The method for preparing the semiconductor epitaxial structure in this embodiment includes the following steps:

[0131] (1) Provide a sapphire substrate as a support for subsequent film growth, and place the sapphire substrate in the growth chamber of a metal-organic chemical vapor deposition (MOCVD) system.

[0132] (2) Under the conditions of temperature of 1150℃ and pressure of 300 torr, the growth thickness is 3μm and the Si doping concentration is 5×10⁻⁶. 18 cm -3 An n-type semiconductor layer made of GaN (denoted as n-type GaN layer).

[0133] (3) Growing an active layer on an n-type GaN layer includes the following steps:

[0134] S31: A quantum well layer (denoted as InGaN quantum well layer) with a thickness of 2nm is grown on an n-type GaN layer under the conditions of temperature of 750℃ and pressure of 300 torr.

[0135] S32: Adjust the temperature to 800℃ to grow a 10nm thick quantum barrier layer (denoted as GaN quantum barrier layer) on the InGaN quantum well layer.

[0136] S33: Repeat S31-S32 5 times to form an active layer with 5 quantum well structures.

[0137] (4) Under the conditions of 800℃ and 200 torr, a layer with a thickness of 8nm and a Mg doping concentration of 5×10⁻⁶ is grown on the active layer. 19 cm -3 The material is the front sublayer of AlGaN (denoted as AlGaN front sublayer).

[0138] (5) Growing In nanostructures on the AlGaN barrier sublayer, including the following steps:

[0139] S51: Under the conditions of 700℃ and 300 torr, the structure obtained in step (4) is subjected to thermal annealing for 20s in H2 atmosphere to remove dislocations on the surface of the sublayer before the AlGaN barrier and improve the uniformity of In atom aggregation after annealing.

[0140] S52: Perform In thermal annealing on the sublayer before the AlGaN barrier, including:

[0141] S521: Under conditions of 700℃ and 400 torr, TMI is introduced into an N2 atmosphere at a flow rate of 1500 sccm for a first In heat annealing treatment for 20s. Then, the TMI is stopped and the heat annealing treatment is carried out in an N2 atmosphere for 10s.

[0142] S522: Reduce the temperature to 620℃ and adjust the pressure to 200 torr. In an N2 atmosphere, introduce TMIn at a flow rate of 800 sccm for a second In heat annealing treatment for 40 seconds. Then, stop introducing TMIn and heat anneal in an N2 atmosphere for 20 seconds.

[0143] S53: Repeat S51-S52 a total of 8 times to form In nanostructures.

[0144] (6) Under the conditions of 700℃ and 200 torr, NH3 with a flow rate of 60slm was introduced to perform N heat annealing treatment for 300s, so that the In nanostructure was transformed into the InN nanostructure.

[0145] (7) Under the conditions of temperature of 1100℃, pressure of 200 torr and inert atmosphere, TMG with a flow rate of 240 sccm was introduced to carry out Ga heat annealing treatment for 60s.

[0146] Ga thermal annealing breaks the In-N bonds in the InN nanostructure, causing In to precipitate from the InN aggregation center and form a vacancy-N bond aggregation center. Ga atoms then diffuse toward the vacancy-N bond aggregation center to form nano-protrusions in the GaN material.

[0147] (8) Under the conditions of 1000℃ and 200 torr, Cp2Mg was introduced into the N2 atmosphere for Mg thermal annealing for 200s.

[0148] Mg thermal annealing forms Mg pre-deposition, which can reduce the Mg memory effect of the sublayer behind the AlGaN barrier and improve the Mg incorporation efficiency.

[0149] (9) Under the conditions of 800℃ and 200 torr, a growth thickness of 8nm and a Mg doping concentration of 5×10⁻⁶ were achieved. 19 cm -3 The material is an AlGaN barrier back sublayer (denoted as AlGaN barrier back sublayer), forming a p-type structure.

[0150] Since the Ga thermal annealing treatment in step (7) also causes Ga atoms to diffuse into the front layer of the AIGaN barrier, the AIGaN front sublayer and the AIGaN back sublayer have an Al component concentration difference, which increases the polarization effect between the interface of the AIGaN front sublayer and the AIGaN back sublayer, and forms a two-dimensional hole gas with a high hole concentration at the interface, further increasing the hole concentration.

[0151] (10) Under the conditions of 1000℃ temperature and 400 torr pressure, a growth thickness of 100nm and a Mg doping concentration of 5×10⁻⁶ were achieved. 19 cm -3 The p-type GaN top layer is used to obtain a semiconductor epitaxial structure.

[0152] Example 2

[0153] Example 2 provides a semiconductor epitaxial structure, such as Figure 2 As shown, the semiconductor epitaxial structure of Example 2 differs from that of Example 1 only in that the p-type barrier layer has five p-type structures. The rest is the same as that of Example 1 and will not be described again here.

[0154] The difference between the preparation method of Example 2 and Example 1 is that steps (4)-(9) in Example 2 are repeated 5 times, which will not be repeated here.

[0155] Example 3

[0156] Example 3 provides a semiconductor epitaxial structure and its fabrication method, specifically including the following steps:

[0157] (1) Provide a sapphire substrate and place the sapphire substrate in the growth chamber of the MOCVD system.

[0158] (2) Under the conditions of a temperature of 1050℃ and a pressure of 100 torr, a growth thickness of 1μm and a Si doping concentration of 1×10⁻⁶ were achieved. 18 cm -3 An n-type semiconductor layer made of GaN (denoted as n-type GaN layer).

[0159] (3) Growing an active layer on an n-type GaN layer includes the following steps:

[0160] S31: A quantum well layer (denoted as InGaN quantum well layer) with a thickness of 1 nm is grown on an n-type GaN layer under the conditions of 650℃ and 150 torr.

[0161] S32: Adjust the temperature to 700℃ to grow a 6nm thick quantum barrier layer (denoted as InGaN quantum well layer) on the InGaN quantum well layer.

[0162] S33: Repeat S31-S32 15 times to form an active layer with 15 quantum well structures.

[0163] (4) Under the conditions of a temperature of 780℃ and a pressure of 100 torr, a 5nm thick Mg doping concentration of 2×10⁻⁶ is grown on the active layer. 19 cm -3 The material is the front sublayer of AlGaN (denoted as AlGaN front sublayer).

[0164] (5) Growing In nanostructures on the AlGaN barrier sublayer, including the following steps:

[0165] S51: Under the conditions of 650℃ and 200 torr, the structure obtained in step (4) is subjected to thermal annealing for 10s in H2 atmosphere to remove the dislocation distribution on the sublayer surface before the AlGaN barrier and improve the uniformity of In atom aggregation after annealing.

[0166] S52: Perform In thermal annealing on the sublayer before the AlGaN barrier, including:

[0167] S521: Under the conditions of 650℃ and 300 torr, TMIn with a flow rate of 1000 sccm is introduced into the N2 atmosphere for the first In heat annealing treatment for 10s, then the TMIn is stopped and the heat annealing treatment is carried out in the N2 atmosphere for 5s.

[0168] S522: Reduce the temperature to 600℃ and adjust the pressure to 100 torr. In an N2 atmosphere, introduce TMIn at a flow rate of 500 sccm for a second In heat annealing treatment for 20 seconds. Then, stop introducing TMIn and heat anneal in an N2 atmosphere for 10 seconds.

[0169] S53: Repeat S51-S52 a total of 5 times to form In nanostructures.

[0170] (6) Under the conditions of 650℃ and 100 torr, NH3 with a flow rate of 20slm was introduced to perform N heat annealing treatment for 120s so that the In nanostructure was transformed into the InN nanostructure.

[0171] (7) Under the conditions of temperature of 1000℃, pressure of 100 torr and inert atmosphere, TMG with a flow rate of 125 sccm was introduced to perform Ga heat annealing for 30s.

[0172] Ga thermal annealing breaks the In-N bonds in the InN nanostructure, causing In to precipitate from the InN aggregation center and form a vacancy-N bond aggregation center. Ga atoms then diffuse toward the vacancy-N bond aggregation center to form a GaN nanoprotrusion with a radius of about 500 nm.

[0173] (8) Under the conditions of 950℃ and 100 torr, Cp2Mg was introduced into the N2 atmosphere for Mg thermal annealing for 100s.

[0174] Mg thermal annealing forms Mg pre-deposition, which can reduce the Mg memory effect of the sublayer behind the AlGaN barrier and improve the Mg incorporation efficiency.

[0175] (9) Under the conditions of a temperature of 780℃ and a pressure of 100 torr, a growth thickness of 5 nm and a Mg doping concentration of 2×10⁻⁶ were achieved. 19 cm -3 The material is an AlGaN barrier back sublayer (denoted as AlGaN barrier back sublayer), forming a p-type structure.

[0176] (10) Under the conditions of a temperature of 950℃ and a pressure of 200 torr, a growth thickness of 50 nm and a Mg doping concentration of 1×10⁻⁶ were achieved.19 cm -3 The p-type GaN top layer is used to obtain a semiconductor epitaxial structure.

[0177] Example 4

[0178] Example 4 provides a semiconductor epitaxial structure and its fabrication method, specifically including the following steps:

[0179] (1) Provide a sapphire substrate as a support for subsequent film growth, and place the sapphire substrate in the growth chamber of the MOCVD system.

[0180] (2) Under the conditions of a temperature of 1250℃ and a pressure of 400 torr, a growth thickness of 5μm and a Si doping concentration of 1×10⁻⁶ were achieved. 19 cm -3 An n-type semiconductor layer made of GaN (denoted as n-type GaN layer).

[0181] (3) Growing an active layer on an n-type GaN layer includes the following steps:

[0182] S31: A quantum well layer (denoted as InGaN quantum well layer) with a thickness of 5nm is grown on an n-type GaN layer under the conditions of temperature of 850℃ and pressure of 350torr.

[0183] S32: Adjust the temperature to 950℃ to grow a 25nm thick quantum barrier layer (denoted as GaN quantum barrier layer) on the InGaN quantum well layer.

[0184] S33: Repeat S31-S32 twice to form an active layer with two quantum well structures.

[0185] (4) Under the conditions of temperature of 850℃ and pressure of 300 torr, a 10 nm thick Mg doping concentration of 2×10⁻⁶ is grown on the active layer. 20 cm -3 The material is the front sublayer of AlGaN (denoted as AlGaN front sublayer).

[0186] (5) Growing In nanostructures on the AlGaN barrier sublayer, including the following steps:

[0187] S51: Under the conditions of 750℃ and 400 torr, the structure obtained in step (4) is subjected to thermal annealing for 30s in H2 atmosphere to remove dislocations on the surface of the sublayer before the AlGa barrier and improve the uniformity of In atom aggregation after annealing.

[0188] S52: Perform In thermal annealing on the sublayer before the AlGaN barrier, including:

[0189] S521: Under conditions of 750℃ and 600 torr, TMI is introduced into an N2 atmosphere at a flow rate of 2000 sccm for the first In heat annealing treatment for 30s. Then, the TMI is stopped and the heat annealing treatment is carried out in an N2 atmosphere for 15s.

[0190] S522: Reduce the temperature to 700℃ and adjust the pressure to 300 torr. In an N2 atmosphere, introduce TMIn at a flow rate of 1200 sccm for a second In heat annealing treatment for 100s. Then stop introducing TMIn and heat anneal in an N2 atmosphere for 40s.

[0191] S53: Repeat S51-S52 20 times to form In nanostructures.

[0192] (6) Under the conditions of 750℃ and 300 torr, NH3 with a flow rate of 100 slm was introduced for N heat annealing for 480s to transform the In nanostructure into the InN nanostructure.

[0193] (7) Under the conditions of temperature of 1150℃, pressure of 300 torr and inert atmosphere, TMG with a flow rate of 380 sccm was introduced to carry out Ga heat annealing treatment for 90s.

[0194] Ga thermal annealing breaks the In-N bonds in the InN nanostructure, causing In to precipitate from the InN aggregation center and form a vacancy-N bond aggregation center. Ga atoms then diffuse toward the vacancy-N bond aggregation center to form a GaN nanoprotrusion with a radius of about 1500 nm.

[0195] (8) Under the conditions of 1050℃ and 300 torr, Cp2Mg was introduced into the N2 atmosphere for Mg heat annealing for 300s.

[0196] Mg thermal annealing forms Mg pre-deposition, which can reduce the Mg memory effect of the sublayer behind the barrier and improve the Mg incorporation efficiency.

[0197] (9) Under the conditions of temperature of 850℃ and pressure of 300 torr, a growth thickness of 10 nm and a Mg doping concentration of 2×10⁻⁶ were achieved. 20 cm -3 The material is the barrier back sublayer (denoted as AIGaN barrier back sublayer).

[0198] (10) Repeat steps (4) to (9) three times to form a p-type barrier layer with three p-type structures.

[0199] (11) Under the conditions of a temperature of 1050℃ and a pressure of 600 torr, a growth thickness of 150 nm and a Mg doping concentration of 1×10⁻⁶ were achieved. 20 cm -3 The p-type GaN top layer is used to obtain a semiconductor epitaxial structure.

[0200] Example 5

[0201] The only difference between Example 5 and Example 1 is that in the method for preparing the semiconductor epitaxial structure in Example 5, step S52 involves introducing TMI at a constant flow rate. Specifically, step S52 in Example 5 is as follows:

[0202] Under conditions of 700℃ and 400 torr, TMIn was introduced into an N2 atmosphere at a flow rate of 1500 sccm for In heat annealing for 60s. Then, the introduction of TMIn was stopped, and heat annealing was performed in an N2 atmosphere for 30s.

[0203] The remaining steps are the same as in Example 1, and will not be repeated here.

[0204] In Example 5, annealing was performed under conditions of continuous high flow of TMIn. This process, to some extent, prevented In atoms from migrating sufficiently, resulting in an unstable distribution of In atoms and uneven In atom aggregation centers. Compared to Example 1, the nanoprotrusions formed in Example 5 were less uniformly distributed.

[0205] Example 6

[0206] The only difference between Example 6 and Example 1 is that in the method for preparing the semiconductor epitaxial structure in Example 6, step S52 involves introducing TMI at a constant flow rate. Specifically, step S52 in Example 6 is as follows:

[0207] Under conditions of 620℃ and 200 torr, TMIn was introduced into a N2 atmosphere at a flow rate of 800 sccm for In heat annealing for 60s. Then, the introduction of TMIn was stopped, and heat annealing was carried out in a N2 atmosphere for 30s.

[0208] The remaining steps are the same as in Example 1, and will not be repeated here.

[0209] Example 6 involves annealing at a relatively low temperature and with a low flow rate of TMIn, which to some extent results in uneven in-plane distribution of In atoms and uneven In atom aggregation centers. Compared to Example 1, the nanoprotrusions formed in Example 6 are less uniformly distributed.

[0210] Comparative Example 1

[0211] Comparative Example 1 provides a semiconductor epitaxial structure without a p-type nitride microstructure. The only difference from Example 1 is that the method for growing the AlGaN barrier layer uses a conventional process. The method for growing the AlGaN barrier layer is as follows:

[0212] Under conditions of 800℃ and 200 torr, a growth thickness of 16 nm and a Mg doping concentration of 5 × 10⁻⁶ were achieved. 19 cm -3 AIGaN barrier layer.

[0213] The remaining steps are the same as in Example 1, and will not be repeated here.

[0214] Comparative Example 2

[0215] The only difference between Comparative Example 2 and Example 1 is that step (6) is not performed in the preparation of the semiconductor epitaxial structure. The rest is the same as in Example 1, and will not be repeated here.

[0216] Without N-thermal annealing, the In nanostructure is transformed into an InN nanostructure. This results in the formation of an In nanostructure between the pre-barrier sublayer and the post-barrier sublayer, which increases the absorption of light emitted from the active layer, thereby reducing the light extraction efficiency.

[0217] Comparative Example 3

[0218] The only difference between Comparative Example 3 and Example 1 is that step (8) is not performed during the preparation of the semiconductor epitaxial structure; the rest is the same as in Example 1.

[0219] Without Mg thermal annealing, the Mg memory effect is high during the growth of the sublayer behind the barrier, which reduces the Mg incorporation efficiency in the sublayer behind the barrier, thereby reducing the hole injection capability of the active layer.

[0220] The semiconductor epitaxial structures from the above embodiments and comparative examples were fabricated into chips using the same process and tested. The voltage VF / V and luminance Lop / mW were tested under an injection current of 2mA, and the luminous efficiency ratio droop / % was tested under 100mA and 20mA conditions. The test structures are shown in Table 1.

[0221] Table 1. Relevant performance of chips obtained from the epitaxial structures in the embodiments and comparative examples of this invention.

[0222] VF / V Lop / mW / 2mA droop / % Example 1 2.84 13.7 35.1 Example 2 2.82 14.5 32.4 Example 3 2.86 13.3 35.8 Example 4 2.83 14.7 33.1 Example 5 2.89 12.3 37.3 Example 6 2.91 11.8 39.2 Comparative Example 1 2.96 10.1 42.2 Comparative Example 2 2.94 8.4 46.5 Comparative Example 3 2.89 11.2 40.6

[0223] The semiconductor epitaxial structure provided by this invention, based on the high hole concentration in the p-type semiconductor layer, can balance the injection of electrons in the n-type semiconductor layer and holes in the p-type semiconductor layer, thereby improving the brightness of the epitaxial structure, reducing the operating voltage, and mitigating the droop effect that occurs in the epitaxial structure with increasing injection current. This semiconductor epitaxial structure is suitable for high-current operating conditions, meeting the current application requirements for high-power epitaxial wafers.

[0224] All aspects, embodiments, features, and examples of this invention are to be regarded as illustrative in all respects and are not intended to limit the invention, the scope of which is defined only by the claims. Other embodiments, modifications, and uses will become apparent to those skilled in the art without departing from the spirit and scope of the invention as claimed.

[0225] In addition, the inventors of this case also conducted experiments with other raw materials, process operations, and process conditions described in this specification, referring to the aforementioned embodiments, and obtained relatively ideal results in all cases.

[0226] Although the invention has been described with reference to illustrative embodiments, those skilled in the art will understand that various other changes, omissions, and / or additions can be made without departing from the spirit and scope of the invention, and that elements of the embodiments can be substituted with substantially equivalents. Furthermore, many modifications can be made without departing from the scope of the invention to adapt particular situations or materials to the teachings of the invention. Therefore, this invention is not intended to be limited to the specific embodiments disclosed for carrying out the invention, but rather is intended to encompass all embodiments falling within the scope of the appended claims. Moreover, unless specifically stated otherwise, any use of the terms first, second, etc., does not indicate any order or importance, but is used to distinguish one element from another.

Claims

1. A semiconductor epitaxial structure, comprising a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer sequentially disposed along a first direction, characterized in that: The p-type semiconductor layer includes a p-type barrier layer. The p-type barrier layer includes at least one p-type structure sequentially disposed along a first direction away from the active layer. The p-type structure includes a pre-barrier sublayer, a p-type nitride microstructure, and a post-barrier sublayer sequentially disposed along the first direction away from the active layer. The p-type nitride microstructure includes a plurality of nano-protrusions distributed on the surface of the pre-barrier sublayer away from the active layer. The post-barrier sublayer covers the plurality of nano-protrusions and the surface of the pre-barrier sublayer not covered by the nano-protrusions. The material of the pre-barrier sublayer is a first nitride doped with acceptor impurities, and the material of the nano-protrusions is a second nitride, wherein the valence band of the second nitride is higher than that of the first nitride.

2. The semiconductor epitaxial structure according to claim 1, characterized in that: The plurality of nanoprotrusions are spaced apart along a second direction, which is perpendicular to the first direction.

3. The semiconductor epitaxial structure according to claim 1, characterized in that: The radius of the nanoprotrusion is 500-1500 nm.

4. The semiconductor epitaxial structure according to claim 1, characterized in that: The distance between two adjacent nanoprotrusions is 100-1000 nm.

5. The semiconductor epitaxial structure according to claim 1, characterized in that: The material of the sublayer behind the barrier is the same as the material of the sublayer in front of the barrier.

6. The semiconductor epitaxial structure according to claim 1, characterized in that: The first nitride is Mg-doped AlGaN, and the second nitride is Mg-doped GaN.

7. The semiconductor epitaxial structure according to claim 1, characterized in that: The Al concentration in the sublayer behind the barrier is lower than the Al concentration in the sublayer in front of the barrier.

8. The semiconductor epitaxial structure according to claim 7, characterized in that: The Al concentration in the sublayer behind the barrier is more than 10% lower than the Al concentration in the sublayer in front of the barrier.

9. The semiconductor epitaxial structure according to claim 1, characterized in that: The thickness of the n-type semiconductor layer is 1-5 μm; the active layer includes 2-15 quantum well structures, each quantum well structure including a quantum well layer with a thickness of 1-5 nm and a quantum barrier layer with a thickness of 6-25 nm; the thicknesses of the pre-barrier sublayer and the post-barrier sublayer are 5-10 nm, respectively.

10. The semiconductor epitaxial structure according to claim 1, characterized in that: The p-type semiconductor layer further includes a p-type nitride top layer, and the p-type barrier layer and the p-type nitride top layer are sequentially disposed along a first direction.

11. A method for preparing a semiconductor epitaxial structure, characterized in that, include: An n-type semiconductor layer and an active layer are sequentially grown on a substrate; A p-type semiconductor layer is grown on the active layer; The p-type semiconductor layer includes a p-type barrier layer. The p-type barrier layer includes at least one p-type structure sequentially disposed along a first direction away from the active layer. The p-type structure includes a pre-barrier sublayer, a p-type nitride microstructure, and a post-barrier sublayer sequentially disposed along the first direction away from the active layer. The p-type nitride microstructure includes a plurality of nano-protrusions distributed on the surface of the pre-barrier sublayer away from the active layer. The post-barrier sublayer covers the plurality of nano-protrusions and the surface of the pre-barrier sublayer not covered by the nano-protrusions. The material of the pre-barrier sublayer is a first nitride doped with acceptor impurities, and the material of the nano-protrusions is a second nitride, wherein the valence band of the second nitride is higher than that of the first nitride.

12. The preparation method according to claim 11, characterized in that, The process of growing a p-type semiconductor layer on the active layer includes: S1: Grow the front sublayer of the barrier layer on the active layer; S2: Growing In nanostructures on the sublayer in front of the barrier; S3: Under inert atmosphere conditions, nitrogen source is introduced to perform N thermal annealing treatment on the In nanostructure to transform the In nanostructure into an InN nanostructure. S4: Anneal the InN nanostructure and introduce a growth source to grow the nanoprotrusions and the back layer of the barrier on the front sublayer.

13. The preparation method according to claim 12, characterized in that, The annealing treatment of the InN nanostructure specifically includes: S41: Under inert atmosphere conditions, the InN nanostructure is subjected to thermal annealing treatment with the introduction of a selected metal source, so that In in the InN nanostructure precipitates to form vacancy-N bond aggregation centers, and selected metal atoms in the selected metal source diffuse toward the vacancy-N bond aggregation centers to generate the nano protrusions. S42: Under inert atmosphere conditions, the structure obtained in step S41 is subjected to Mg thermal annealing treatment.

14. The preparation method according to claim 13, characterized in that: Step S41 specifically includes: introducing a Ga source to perform the thermal annealing treatment for 30-90 seconds under conditions of a temperature of 1000-1150℃, a pressure of 100-300 torr and an inert atmosphere.

15. The preparation method according to claim 13, characterized in that: Step S42 specifically includes: introducing a Mg source to perform the Mg thermal annealing treatment for 100-300s under the conditions of a temperature of 950-1050℃, a pressure of 100-300 torr and an inert atmosphere.

16. The preparation method according to claim 12, characterized in that, Step S2 specifically includes: S21: Under the conditions of first temperature and first pressure, the sublayer in front of the barrier is subjected to thermal annealing for a first preset time in a reducing atmosphere; S22: Perform In thermal annealing on the sublayer in front of the barrier; S23: Repeat S21-S22 a preset number of times.

17. The preparation method according to claim 16, characterized in that: Step S21 specifically includes: performing thermal annealing on the front sublayer of the barrier for 10-30 seconds under the conditions of a temperature of 650-750℃, a pressure of 200-400 torr, and an H2 atmosphere.

18. The preparation method according to claim 16, characterized in that: Step S22 specifically includes: S221: Under the conditions of second temperature, second pressure and inert atmosphere, the first In heat annealing treatment is carried out at a first flow rate for a second preset time. S222: Under the conditions of third temperature, third pressure and inert atmosphere, the In source is introduced at a second flow rate to perform a second In heat annealing treatment for a third preset time; Wherein, the second temperature is higher than the third temperature, and the first flow rate is higher than the second flow rate.

19. The preparation method according to claim 16, characterized in that: The preset number of times is 5 to 20.

20. The preparation method according to claim 18, characterized in that, Step S221 specifically includes: performing the first In thermal annealing treatment for 10-30 seconds by introducing an In source with a flow rate of 1000-2000 sccm under the conditions of a temperature of 650-750℃, a pressure of 300-600 torr and an N2 atmosphere; then stopping the introduction of the In source and performing thermal annealing treatment for 5-15 seconds under the conditions of a temperature of 650-750℃, a pressure of 300-600 torr and an N2 atmosphere.

21. The preparation method according to claim 18, characterized in that, Step S222 specifically includes: under conditions of temperature 600-700℃, pressure 100-300 torr and N2 atmosphere, introducing an In source with a flow rate of 500-1200 sccm to perform the second In thermal annealing treatment for 20-100s; then stopping the In source and performing thermal annealing treatment for 10-40s under conditions of temperature 600-700℃, pressure 100-300 torr and N2 atmosphere.

22. The preparation method according to claim 12, characterized in that: The growth of the sublayer in front of the barrier includes: growing a thickness of 5-10 nm and a Mg doping concentration of 2 × 10⁻⁶ under conditions of temperature 780-850℃ and pressure 100-300 torr. 19 -2×10 20 cm -3 The potential barrier of the sublayer.

23. The preparation method according to claim 12, characterized in that: The growth of the sublayer behind the barrier includes: growing a thickness of 5-10 nm and a Mg doping concentration of 2 × 10⁻⁶ under conditions of temperature 780-850℃, pressure 100-300 torr. 19 -2×10 20 cm -3 The potential barrier behind the sublayer.

24. The preparation method according to claim 12, characterized in that: Step S3 specifically includes: under conditions of temperature of 650-750℃ and pressure of 100-300 torr, NH3 with a flow rate of 20-100 slm is introduced to carry out the N-heat annealing treatment for 120-480s.

25. The preparation method according to claim 11, characterized in that: The growth of the n-type semiconductor layer includes: growing a thickness of 1-5 μm and a Si doping concentration of 1×10⁻⁶ under conditions of temperature of 1050-1250℃ and pressure of 100-400 torr. 18 -1×10 19 cm -3 n-type semiconductor layer.

26. The preparation method according to claim 11, characterized in that: The active layer includes 2-15 quantum well structures sequentially arranged along a first direction away from the n-type semiconductor layer. Each quantum well structure includes a stacked quantum well layer and a quantum barrier layer. The growth of the quantum well structure includes: Quantum well layers with a thickness of 1-5 nm are grown under conditions of temperature 650-850℃ and pressure 150-350 torr. A quantum barrier layer with a thickness of 6-25 nm is grown on the quantum well layer under conditions of temperature 700-950℃ and pressure 150-350 torr.

27. The preparation method according to claim 11, characterized in that: The preparation method further includes growing a p-type nitride top layer on the p-type barrier layer.

28. The preparation method according to claim 27, characterized in that: The growth of the p-type nitride top layer includes: growing a thickness of 50-150 nm and a Mg doping concentration of 1×10⁻⁶ under conditions of 950-1050℃ and 200-600 torr. 19 -1×10 20 cm -3 The top layer of the p-type nitride.

29. The preparation method according to claim 12, characterized in that: Steps S1-S4 can be performed once or repeated multiple times.

30. The preparation method according to claim 29, characterized in that: Perform steps S1-S4 1-5 times.

31. A semiconductor epitaxial structure, characterized in that, The semiconductor epitaxial structure is prepared by the preparation method according to any one of claims 11-30.

32. A semiconductor device, characterized in that, Includes the semiconductor epitaxial structure as described in any one of claims 1-10 and 31.

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