Shift register and driving method thereof, display substrate, and display device

Abstract

A shift register and a driving method thereof, a display substrate, and a display device. The shift register includes: a storage subcircuit, a node control subcircuit, and an output control subcircuit; the storage subcircuit is electrically connected to a first node and a first power supply terminal, respectively, and is configured to store the voltage difference between the signal of the first node and the signal of the first power supply terminal; the node control subcircuit is electrically connected to a signal input terminal, a first clock signal terminal, a second clock signal terminal, a first node, and a second node, respectively, and is configured to provide the signal of the signal input terminal to the first node under the control of the first clock signal terminal, and to provide the signal of the first node to the second node under the control of the second clock signal terminal; the output control subcircuit is electrically connected to the second node, the first power supply terminal, the second power supply terminal, and the signal output terminal, respectively, and is configured to provide the signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the second node.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a shift register and a driving method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a shift register, comprising: a storage subcircuit, a node control subcircuit, and an output control subcircuit;

[0005] The storage sub-circuit is electrically connected to the first node and the first power supply terminal, respectively, and is configured to store a voltage difference between a signal at the first node and a signal at the first power supply terminal;

[0006] The node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node, and the second node, respectively, and is configured to provide the signal of the signal input terminal to the first node under the control of the first clock signal terminal, and provide the signal of the first node to the second node under the control of the second clock signal terminal;

[0007] The output control subcircuit is electrically connected to the second node, the first power supply terminal, the second power supply terminal and the signal output terminal respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the second node.

[0008] In some possible implementations, the output control subcircuit includes: a first output control subcircuit and a second output control subcircuit;

[0009] The first output control subcircuit is electrically connected to the second node, the third node, the first power supply terminal, and the second power supply terminal, respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the third node under the control of the second node;

[0010] The second output control subcircuit is electrically connected to the third node, the first power supply terminal, the second power supply terminal and the signal output terminal respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the third node.

[0011] In some possible implementations, the method further includes: a noise reduction sub-circuit;

[0012] The noise reduction sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the second node and the third node, respectively, and is configured to provide the signal of the first power supply terminal or the second power supply terminal to the second node under the control of the first clock signal terminal, the second clock signal terminal and the third node.

[0013] In some possible implementations, the storage subcircuit includes: a capacitor, the capacitor including: a first plate and a second plate;

[0014] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0015] In some possible implementations, the node control subcircuit includes: a first transistor and a second transistor;

[0016] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0017] The control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node.

[0018] In some possible implementations, the first output control subcircuit includes: a third transistor and a fourth transistor, and the second output control subcircuit includes: a fifth transistor and a sixth transistor;

[0019] A control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first power supply terminal, and a second electrode of the third transistor is electrically connected to the third node;

[0020] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0021] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal;

[0022] The control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal;

[0023] The third transistor and the fourth transistor are of opposite transistor types, and the fifth transistor and the sixth transistor are of opposite transistor types.

[0024] In some possible implementations, the noise reduction sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0025] A control electrode of the seventh transistor is electrically connected to the first clock signal terminal, a first electrode of the seventh transistor is electrically connected to the first power supply terminal, and a second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;

[0026] The control electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second node;

[0027] a control electrode of the ninth transistor electrically connected to the third node, a first electrode of the ninth transistor electrically connected to the second node, and a second electrode of the ninth transistor electrically connected to the second electrode of the tenth transistor;

[0028] The control electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the first electrode of the tenth transistor is electrically connected to the second power supply terminal;

[0029] The seventh transistor and the eighth transistor are of the same transistor type, the ninth transistor and the tenth transistor are of the same transistor type, and the seventh transistor and the ninth transistor are of opposite transistor types.

[0030] In some possible implementations, the storage subcircuit includes: a capacitor, the capacitor includes: a first plate and a second plate; the node control subcircuit includes: a first transistor and a second transistor; the output control subcircuit includes: a third transistor, a fourth transistor, a fifth transistor and a sixth transistor

[0031] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal;

[0032] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0033] The control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0034] A control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first power supply terminal, and a second electrode of the third transistor is electrically connected to the third node;

[0035] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0036] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal;

[0037] The control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal;

[0038] The first transistor, the second transistor, the third transistor, and the fifth transistor are P-type transistors, and the fourth transistor and the sixth transistor are N-type transistors and oxide transistors.

[0039] In some possible implementations, the device further includes: a noise reduction subcircuit, wherein the storage subcircuit includes a capacitor, which includes a first plate and a second plate; the node control subcircuit includes a first transistor and a second transistor; the output control subcircuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; and the noise reduction subcircuit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor.

[0040] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal;

[0041] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0042] The control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0043] A control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first power supply terminal, and a second electrode of the third transistor is electrically connected to the third node;

[0044] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0045] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal;

[0046] The control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal;

[0047] A control electrode of the seventh transistor is electrically connected to the first clock signal terminal, a first electrode of the seventh transistor is electrically connected to the first power supply terminal, and a second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;

[0048] The control electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second node;

[0049] a control electrode of the ninth transistor electrically connected to the third node, a first electrode of the ninth transistor electrically connected to the second node, and a second electrode of the ninth transistor electrically connected to the second electrode of the tenth transistor;

[0050] The control electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the first electrode of the tenth transistor is electrically connected to the second power supply terminal;

[0051] The first transistor, the second transistor, the third transistor, the fifth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the fourth transistor, the sixth transistor, the ninth transistor, and the tenth transistor are N-type transistors and are oxide transistors.

[0052] In some possible implementations, the clock signal at the first clock signal terminal and the clock signal at the second clock signal terminal are inverted signals of each other;

[0053] The signal at the signal input end is a first pulse signal, the duration of the first pulse signal is equal to the period of the clock signal at the first clock signal end,

[0054] The signal at the signal output end is a second pulse signal, the duration of the second pulse signal is equal to the duration of the first pulse signal, and the start time of the second pulse signal is the end time of the first pulse signal.

[0055] In some possible implementations, the clock signal at the first clock signal terminal and the clock signal at the second clock signal terminal are inverted signals of each other;

[0056] The signal at the signal input end is a third pulse signal, the duration of the third pulse signal is equal to N times the period of the clock signal at the first clock signal end, where N is a positive integer greater than or equal to 2;

[0057] The signal at the signal output end is a fourth pulse signal, the duration of the fourth pulse signal is equal to the duration of the third pulse signal, and the difference between the start time of the fourth pulse signal and the start time of the third pulse signal is equal to the period of the clock signal at the first clock signal end.

[0058] In a second aspect, the present disclosure further provides a display substrate comprising: a display area and a non-display area, the display substrate comprising: a base and a circuit structure layer disposed on the base, the circuit structure layer comprising: a gate drive circuit located in the non-display area and an array-arranged pixel circuit located in the display area, the gate drive circuit comprising: a plurality of cascaded shift registers described above, the pixel circuit comprising: a light emitting signal line, a scanning signal line, and a reset signal line;

[0059] The signal output terminal of the i-th stage shift register is electrically connected to the signal input terminal of the i+1-th stage shift register, 1≤i≤M-1, where M is the total number of stages of the shift register;

[0060] The gate driving circuit is electrically connected to at least one of a light emitting signal line, a scanning signal line, and a reset signal line.

[0061] In some possible implementations, the further comprising: a first clock signal line, a second clock signal line, a first power line, and a second power line extending along a first direction, the first power line, the second power line, the first clock signal line, and the second clock signal line being arranged along a second direction, and the first direction intersecting the second direction;

[0062] The first power supply terminals of all shift registers are electrically connected to the first power supply line, the second power supply terminals of all shift registers are electrically connected to the second power supply line, the first clock signal terminal of the i-th stage shift register is electrically connected to the first clock signal line, the second clock signal terminal of the i-th stage shift register is electrically connected to the second clock signal line, the first clock signal terminal of the i+1-th stage shift register is electrically connected to the second clock signal line, and the second clock signal terminal of the i+1-th stage shift register is electrically connected to the first clock signal line.

[0063] In some possible implementations, the shift register includes: first to tenth transistors and a capacitor, the capacitor including: a first plate and a second plate; the circuit structure layer includes: a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer sequentially stacked on a substrate;

[0064] The first semiconductor layer includes: an active layer of a first transistor, an active layer of a second transistor, an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a seventh transistor, and an active layer of an eighth transistor;

[0065] The first conductive layer includes: a control electrode of a first transistor, a control electrode of a second transistor, a control electrode of a third transistor, a control electrode of a fifth transistor, a control electrode of a seventh transistor, a control electrode of an eighth transistor, a first plate of a capacitor, and a signal output line;

[0066] The second conductive layer includes: a second plate of a capacitor;

[0067] The second semiconductor layer includes: an active layer of a fourth transistor, an active layer of a sixth transistor, an active layer of a ninth transistor, and an active layer of a tenth transistor;

[0068] The third conductive layer includes: a control electrode of the fourth transistor, a control electrode of the sixth transistor, a control electrode of the ninth transistor, and a control electrode of the tenth transistor;

[0069] The fourth conductive layer includes: a first clock signal line, a second clock signal line, a first power line, a second power line, a first electrode and a second electrode of the first transistor to a first electrode and a second electrode of the sixth transistor, a first electrode of the seventh transistor, a second electrode of the eighth transistor, a first electrode of the ninth transistor, a first electrode of the tenth transistor, a first connection signal line, a second connection signal line, and a third connection signal line;

[0070] The signal output line is connected to the second electrode of the fifth transistor and the second electrode of the sixth transistor respectively;

[0071] The first connection signal line is connected to the active layer of the third transistor and the control electrode of the ninth transistor respectively;

[0072] The second connection signal line is connected to the active layer of the third transistor and the control electrode of the eighth transistor respectively;

[0073] The third connection signal line is connected to the control electrode of the tenth transistor and the control electrode of the second transistor respectively.

[0074] In some possible implementations, the fifth transistor and the sixth transistor are located on the same side of the first power line, and the fifth transistor and the sixth transistor are arranged along the first direction;

[0075] The third transistor is located on a side of the fifth transistor away from the first power line, the fourth transistor is located on a side of the sixth transistor away from the first power line, and the third and fourth transistors are arranged along the first direction. The third and fifth transistors are arranged along the second direction, and the fourth and sixth transistors are arranged along the second direction;

[0076] The eighth transistor is located on a side of the third transistor away from the fifth transistor, the ninth transistor is located on a side of the fourth transistor away from the sixth transistor, the eighth transistor and the ninth transistor are arranged along the first direction, the third transistor and the eighth transistor are arranged along the second direction, and the fourth transistor and the ninth transistor are arranged along the second direction;

[0077] The seventh transistor is located on a side of the eighth transistor away from the third transistor, the tenth transistor is located on a side of the ninth transistor away from the fourth transistor, the seventh transistor and the tenth transistor are arranged along the first direction, the seventh transistor and the eighth transistor are arranged along the second direction, and the ninth transistor and the tenth transistor are arranged along the second direction;

[0078] The second transistor is located between the seventh transistor and the tenth transistor, the first transistor is located on a side of the seventh transistor away from the eighth transistor, and the capacitor is located on a side of the tenth transistor away from the ninth transistor;

[0079] The second power line is located on a side of the capacitor away from the tenth transistor, the first clock signal line is located on a side of the second power line away from the capacitor, and the second clock signal line is located on a side of the first clock signal line away from the second power line.

[0080] In some possible implementations, the active layer of the first transistor and the active layer of the second transistor are an integrally formed structure, and the active layer of the seventh transistor and the active layer of the eighth transistor are an integrally formed structure;

[0081] The active layer of the third transistor includes a first active connection portion, a second active connection portion, and a third active connection portion; the first active connection portion and the third active connection portion extend along a first direction, and the second active connection portion extends along a second direction and is connected to the first active connection portion and the third active connection portion, respectively;

[0082] The first active connection portion is located on a side of the second active connection portion close to the integrally formed structure of the active layer of the seventh transistor and the active layer of the eighth transistor, and the third active connection portion is located on a side of the second active connection portion away from the integrally formed structure of the active layer of the seventh transistor and the active layer of the eighth transistor;

[0083] A straight line extending along the second direction passes through the first active connection portion and the active layer of the second transistor;

[0084] A straight line extending along the second direction passes through the third active connection and the active layer of the first transistor.

[0085] In some possible implementations, the first plate of the capacitor includes: a first capacitor main portion and a first capacitor connecting portion connected to each other;

[0086] The control electrode of the first transistor and the control electrode of the seventh transistor are integrally formed and are located on a side of the first capacitor connecting portion away from the first capacitor main body;

[0087] A virtual straight line extending along the second direction passes through the control electrode of the eighth transistor and the integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor.

[0088] A virtual straight line extending along the second direction passes through the control electrode of the third transistor and the control electrode of the eighth transistor;

[0089] A virtual straight line extending along the second direction passes through the control electrode of the fifth transistor and the control electrode of the third transistor.

[0090] A virtual straight line extending along the second direction passes through the signal output line and the control electrode of the second transistor.

[0091] In some possible implementations, the second plate of the capacitor includes: a second capacitor main body and a second capacitor connecting portion connected to each other, the second capacitor connecting portion being located on one side of the second capacitor main body;

[0092] The area of ​​the first capacitor body portion of the first electrode plate of the capacitor is greater than the area of ​​the second capacitor body portion of the second electrode plate of the capacitor;

[0093] The orthographic projections of the second capacitor main body and the second capacitor connecting portion on the substrate at least partially overlap with the orthographic projection of the first capacitor main body of the first plate of the capacitor on the substrate, and do not overlap with the orthographic projection of the first capacitor connecting portion of the first plate of the capacitor on the substrate.

[0094] In some possible implementations, an orthographic projection of the active layer of the sixth transistor on the substrate and an orthographic projection of the active layer of the fifth transistor on the substrate are respectively located on opposite sides of an orthographic projection of the signal output line on the substrate, and a straight line extending along the first direction passes through the active layer of the fifth transistor and the active layer of the sixth transistor;

[0095] a straight line extending along the first direction passing through the active layer of the fourth transistor and the third active connection portion of the active layer of the third transistor;

[0096] A straight line extending along the first direction passes through the active layer of the ninth transistor and the active layer of the eighth transistor, and a straight line extending along the first direction passes through the active layer of the tenth transistor and the active layer of the seventh transistor.

[0097] In some possible implementations, the virtual straight line extending along the second direction passes through the control electrode of the fourth transistor, the control electrode of the sixth transistor, and the control electrode of the ninth transistor;

[0098] The control electrode of the tenth transistor includes a first electrode connection portion, a second electrode connection portion, and a third electrode connection portion. The first electrode connection portion and the third electrode connection portion extend along the second direction, and the second electrode connection portion extends along the first direction and is connected to the first electrode connection portion and the third electrode connection portion, respectively.

[0099] The first electrode connection portion is located on a side of the second electrode connection portion close to the control electrode of the ninth transistor, and the third electrode connection portion is located on a side of the second electrode connection portion away from the control electrode of the ninth transistor;

[0100] A virtual straight line extending along the second direction passes through an orthographic projection of the first electrode connection portion of the control electrode of the tenth transistor on the substrate and an orthographic projection of the first capacitor body portion of the first plate of the capacitor on the substrate;

[0101] The orthographic projection of the third electrode connection portion of the control electrode of the tenth transistor on the substrate is located on a side of the orthographic projection of the first plate of the capacitor on the substrate away from the orthographic projection of the integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor on the substrate.

[0102] In some possible implementations, the fifth insulating layer is provided with a plurality of via patterns, the plurality of via patterns including: a first via to a sixth via provided in the first insulating layer, the second insulating layer, and the fifth insulating layer, a seventh via to a thirteenth via provided in the second insulating layer to the fifth insulating layer, a fourteenth via provided in the third insulating layer to the fifth insulating layer, a fifteenth via to an eighteenth via provided in the fourth insulating layer to the fifth insulating layer, and a nineteenth via to a twenty-second via provided in the fifth insulating layer;

[0103] The third via hole exposes the active layer of the third transistor, and the twenty-second via hole exposes the control electrode of the tenth transistor;

[0104] There are four third vias, a virtual straight line extending along the first direction passes through a first third via and a second third via, and the first third via and the second third via expose the first active connection portion of the active layer of the third transistor, a virtual straight line extending along the first direction passes through a third third via and a fourth third via, and the third third via and the fourth third via expose the third active connection portion of the active layer of the third transistor, and a virtual straight line extending along the second direction passes through the second third via and the third third via;

[0105] There are two twenty-second via holes. The first twenty-second via hole exposes the second electrode connection portion of the control electrode of the tenth transistor, and the second twenty-second via hole exposes the third electrode connection portion of the control electrode of the tenth transistor.

[0106] In some possible implementations, the first electrode of the third transistor, the first electrode of the fifth transistor, the first electrode of the seventh transistor, and the first power line are integrally formed, the first electrode of the fourth transistor, the first electrode of the sixth transistor, the first electrode of the tenth transistor and the second power line are integrally formed, the second electrode of the first transistor and the first electrode of the second transistor are integrally formed, the second electrode of the third transistor and the second electrode of the fourth transistor are integrally formed, the second electrode of the second transistor, the second electrode of the eighth transistor, and the first electrode of the ninth transistor are integrally formed, and the second electrode of the fifth transistor and the second electrode of the sixth transistor are integrally formed;

[0107] The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the signal output line on the substrate;

[0108] The orthographic projection of the second power line on the substrate partially overlaps with the integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor, the control electrode of the tenth transistor, and the orthographic projection of the second capacitor connecting portion of the second electrode plate of the capacitor on the substrate;

[0109] An orthographic projection of the first clock signal line on the substrate partially overlaps with an orthographic projection of the control electrode of the tenth transistor and an integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor on the substrate;

[0110] The second clock signal line overlaps with the orthographic projection of the control electrode of the connected transistor on the substrate;

[0111] An orthographic projection of the integrally formed structure of the second electrode of the first transistor and the first electrode of the second transistor on the substrate partially overlaps with an orthographic projection of the first capacitor connecting portion of the first electrode plate of the capacitor on the substrate;

[0112] The orthographic projections of the integrated structure of the second electrode of the third transistor and the second electrode of the fourth transistor on the substrate partially overlap with the orthographic projections of the control electrode of the sixth transistor and the control electrode of the fifth transistor on the substrate;

[0113] The orthographic projection of the integrally formed structure of the second electrode of the fifth transistor and the second electrode of the sixth transistor on the substrate partially overlaps with the orthographic projection of the signal output line on the substrate;

[0114] The orthographic projection of the integrated structure of the second electrode of the second transistor, the second electrode of the eighth transistor, and the first electrode of the ninth transistor on the substrate partially overlaps with the orthographic projection of the control electrode of the third transistor and the control electrode of the fourth transistor on the substrate;

[0115] An orthographic projection of the first connection signal line on the substrate partially overlaps with an orthographic projection of the control electrode of the ninth transistor on the substrate;

[0116] An orthographic projection of the second connection signal line on the substrate partially overlaps with an orthographic projection of the control electrode of the eighth transistor on the substrate;

[0117] An orthographic projection of the third connection signal line on the substrate partially overlaps with an orthographic projection of the control electrode of the second transistor and the control electrode of the tenth transistor on the substrate.

[0118] In some possible implementations, the first electrode and the second electrode of the third transistor are connected to the active layer of the third transistor through a third third via hole and a fourth third via hole, respectively;

[0119] The first connecting signal line is connected to the active layer of the third transistor through the first third via hole;

[0120] The second connecting signal line is connected to the active layer of the third transistor through the second third via hole;

[0121] The third connection signal line is connected to the control electrode of the tenth transistor through the first twenty-second via hole;

[0122] One of the first clock signal line and the second clock signal line is connected to the control electrode of the tenth transistor through a second twenty-second via hole.

[0123] In a third aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0124] In a fourth aspect, the present disclosure further provides a shift register driving method, configured to drive the above-mentioned shift register, the method comprising:

[0125] The storage subcircuit stores a voltage difference between a signal at the first node and a signal at the first power supply terminal;

[0126] The node control subcircuit provides the signal of the signal input terminal to the first node under the control of the first clock signal terminal, and provides the signal of the first node to the second node under the control of the second clock signal terminal;

[0127] The output control subcircuit provides the signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the second node.

[0128] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0129] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0130] Figure 1 A schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure;

[0131] Figure 2 A schematic structural diagram of an output control subcircuit provided by an exemplary embodiment;

[0132] Figure 3 A schematic structural diagram of a shift register provided by an exemplary embodiment;

[0133] Figure 4 An equivalent circuit diagram of a storage subcircuit provided for an exemplary embodiment;

[0134] Figure 5 An equivalent circuit diagram of a node control subcircuit provided for an exemplary embodiment;

[0135] Figure 6 An equivalent circuit diagram of an output control subcircuit provided for an exemplary embodiment;

[0136] Figure 7 An equivalent circuit diagram of a noise reduction subcircuit provided for an exemplary embodiment;

[0137] Figure 8 An equivalent circuit diagram of a shift register provided for an exemplary embodiment;

[0138] Figure 9 An equivalent circuit diagram of a shift register provided for another exemplary embodiment;

[0139] Figure 10 An operating timing diagram of a shift register provided for an exemplary embodiment;

[0140] Figure 11 An operation timing diagram of a shift register provided for another exemplary embodiment;

[0141] Figure 12 A schematic structural diagram of a display substrate provided by an exemplary embodiment;

[0142] Figure 13 is a schematic diagram after forming a first semiconductor layer pattern;

[0143] Figure 14A is a schematic diagram of a first conductive layer pattern;

[0144] Figure 14B is a schematic diagram after forming a first conductive layer pattern;

[0145] Figure 15A is a schematic diagram of a second conductive layer pattern;

[0146] Figure 15B A schematic diagram after forming a second conductive layer pattern;

[0147] Figure 16A is a schematic diagram of a pattern of a second semiconductor layer;

[0148] Figure 16B is a schematic diagram after forming a second semiconductor layer pattern;

[0149] Figure 17A is a schematic diagram of a pattern of a third conductive layer;

[0150] Figure 17B is a schematic diagram after forming the third conductive layer pattern;

[0151] Figure 18 is a schematic diagram after forming a fifth insulating layer pattern;

[0152] Figure 19A is a schematic diagram of a pattern of a fourth conductive layer;

[0153] Figure 19B Schematic diagram after forming the fourth conductive layer pattern. DETAILED DESCRIPTION

[0154] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0155] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0156] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0157] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0158] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0159] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0160] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0161] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0162] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0163] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0164] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0165] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0166] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0167] The display substrate includes: pixel circuits, light-emitting elements, and gate drive circuits. The gate drive circuits are configured to provide gate signals to the pixel circuits so that the pixel circuits can drive the light-emitting elements to emit light. The gate drive circuits occupy a large area and consume a large amount of power.

[0168] Figure 1 This is a schematic diagram of the structure of the shift register provided by the embodiment of the present disclosure. Figure 1 As shown, the shift register provided by the embodiment of the present disclosure may include: a storage sub-circuit, a node control sub-circuit and an output control sub-circuit.

[0169] like Figure 1As shown, the storage sub-circuit is electrically connected to the first node N1 and the first power supply terminal VGH, respectively, and is configured to store the voltage difference between the signal of the first node N1 and the signal of the first power supply terminal VGH; the node control sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB, the first node N1 and the second node N2, respectively, and is configured to provide the signal of the signal input terminal IN to the first node N1 under the control of the first clock signal terminal CK, and to provide the signal of the first node N1 to the second node N2 under the control of the second clock signal terminal CB; the output control sub-circuit is electrically connected to the second node N2, the first power supply terminal VGH, the second power supply terminal VGL and the signal output terminal OUT, respectively, and is configured to provide the signal of the first power supply terminal VGH or the second power supply terminal VGL to the signal output terminal OUT under the control of the second node N2.

[0170] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal.

[0171] In an exemplary embodiment, the signals at the first clock signal terminal CK and the second clock signal terminal CB may be periodic pulse signals.

[0172] The shift register provided by the embodiment of the present disclosure includes: a storage subcircuit, a node control subcircuit and an output control subcircuit; the storage subcircuit is electrically connected to the first node and the first power supply terminal, respectively, and is configured to store the voltage difference between the signal of the first node and the signal of the first power supply terminal; the node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node and the second node, respectively, and is configured to provide the signal of the signal input terminal to the first node under the control of the first clock signal terminal, and to provide the signal of the first node to the second node under the control of the second clock signal terminal; the output control subcircuit is electrically connected to the second node, the first power supply terminal, the second power supply terminal and the signal output terminal, respectively, and is configured to provide the signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the second node. The shift register provided by the present disclosure can reduce the area occupied and power consumption of the shift register through the cooperation of the storage subcircuit, the node control subcircuit and the output control subcircuit.

[0173] Figure 2 FIG. 1 is a schematic diagram of the structure of an output control subcircuit provided by an exemplary embodiment. Figure 2 As shown, in an exemplary embodiment, the output control subcircuit may include: a first output control subcircuit and a second output control subcircuit.

[0174] like Figure 2As shown, the first output control sub-circuit is electrically connected to the second node N2, the third node N3, the first power supply terminal VGH and the second power supply terminal VGL, respectively, and is configured to provide the signal of the first power supply terminal VGH or the second power supply terminal VGL to the third node N3 under the control of the second node N2; the second output control sub-circuit is electrically connected to the third node N3, the first power supply terminal VGH, the second power supply terminal VGL and the signal output terminal OUT, respectively, and is configured to provide the signal of the first power supply terminal VGH or the second power supply terminal VGL to the signal output terminal OUT under the control of the third node N3.

[0175] Figure 3 FIG. 1 is a structural diagram of a shift register provided by an exemplary embodiment. Figure 3 As shown, in an exemplary embodiment, the shift register may further include a noise reduction sub-circuit. The noise reduction sub-circuit is electrically connected to the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, the second node N2, and the third node N3, respectively, and is configured to provide a signal from the first power supply terminal VGH or the second power supply terminal VGL to the second node N2 under the control of the first clock signal terminal CK, the second clock signal terminal CB, and the third node N3.

[0176] The present disclosure can maintain the voltage value of the signal at the second node N2 by setting a noise reduction subcircuit, so that the signal at the second node N2 is in a stable state, preventing the second node N2 from floating and causing the voltage value of the signal to be changed, thereby improving the reliability of the shift register.

[0177] Figure 4 FIG. 1 is an equivalent circuit diagram of a storage subcircuit provided by an exemplary embodiment. Figure 4 As shown, in an exemplary embodiment, the storage subcircuit may include a capacitor C, which includes a first plate C1 and a second plate C2. The first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the first power supply terminal VGH.

[0178] Figure 4 An exemplary structure of the storage sub-circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the storage sub-circuit is not limited thereto.

[0179] Figure 5 FIG. 1 is an equivalent circuit diagram of a node control subcircuit provided by an exemplary embodiment. Figure 5 As shown, in an exemplary embodiment, the node control subcircuit may include: a first transistor T1 and a second transistor T2.

[0180] like Figure 5As shown, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second clock signal terminal CB, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2.

[0181] Figure 5 An exemplary structure of the node control subcircuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the node control subcircuit is not limited thereto.

[0182] Figure 6 FIG. 1 is an equivalent circuit diagram of an output control subcircuit provided by an exemplary embodiment. Figure 6 As shown, in an exemplary embodiment, the first output control subcircuit in the output control subcircuit may include: a third transistor T3 and a fourth transistor T4, and the second output control subcircuit may include: a fifth transistor T5 and a sixth transistor T6.

[0183] like Figure 6 As shown, the control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode of the third transistor T3 is electrically connected to the first power supply terminal VGH, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT; the control electrode of the sixth transistor T6 is electrically connected to the third node N3, the first electrode of the sixth transistor T6 is electrically connected to the second power supply terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT.

[0184] In one exemplary embodiment, the third transistor T3 and the fourth transistor T4 are of opposite transistor types, meaning that the first output control subcircuit is equivalent to a set of inverters. The fifth transistor T5 and the sixth transistor T6 are of opposite transistor types, meaning that the second output control subcircuit is equivalent to a set of inverters. The output control subcircuit in the present disclosure is equivalent to two inverters connected in series.

[0185] Figure 6 An exemplary structure of the output control subcircuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the output control subcircuit is not limited thereto.

[0186] Figure 7FIG. 1 is an equivalent circuit diagram of a noise reduction subcircuit provided by an exemplary embodiment. Figure 7 As shown, in an exemplary embodiment, the noise reduction sub-circuit may include: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10.

[0187] like Figure 7 As shown, the control electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal CK, the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal VGH, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the eighth transistor T8; the control electrode of the eighth transistor T8 is electrically connected to the third node N3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the third node N3, the first electrode of the ninth transistor T9 is electrically connected to the second node N2, and the second electrode of the ninth transistor T9 is electrically connected to the second electrode of the tenth transistor T10; the control electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, and the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VGL.

[0188] In an exemplary embodiment, the seventh transistor T7 and the eighth transistor T8 may be of the same transistor type.

[0189] In an exemplary embodiment, the ninth transistor T9 and the tenth transistor T10 may be of the same transistor type.

[0190] In an exemplary embodiment, the transistor types of the seventh transistor T7 and the ninth transistor T9 may be opposite.

[0191] Figure 7 An exemplary structure of the noise reduction sub-circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the noise reduction sub-circuit is not limited thereto.

[0192] In an exemplary embodiment, transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0193] Figure 8 FIG. 1 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment. Figure 8As shown, in an exemplary embodiment, the storage subcircuit in the shift register may include: a capacitor C, the capacitor C includes: a first plate C1 and a second plate C2; ​​the node control subcircuit may include: a first transistor T1 and a second transistor T2; the output control subcircuit may include: a third transistor T3, a fourth transistor T4, a fifth transistor and a sixth transistor T6.

[0194] like Figure 8 As shown, the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the first power supply terminal VGH; the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second clock signal terminal CB, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second node N2, and the first electrode of the third transistor T3 is electrically connected to the first power supply terminal VGH , the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT; the control electrode of the sixth transistor T6 is electrically connected to the third node N3, the first electrode of the sixth transistor T6 is electrically connected to the second power supply terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT.

[0195] In an exemplary embodiment, the first transistor T1 , the second transistor T2 , the third transistor T3 , and the fifth transistor T5 may be P-type transistors.

[0196] In an exemplary embodiment, the fourth transistor T4 and the sixth transistor T6 may be N-type transistors and oxide transistors. Oxide transistors can reduce leakage current, improve the performance of the shift register, and reduce the power consumption of the shift register.

[0197] Figure 9 FIG. 1 is an equivalent circuit diagram of a shift register provided by another exemplary embodiment. Figure 9As shown, in an exemplary embodiment, the shift register may further include: a noise reduction subcircuit, the storage subcircuit may include: a capacitor C, the capacitor C includes: a first plate C1 and a second plate C2; ​​the node control subcircuit may include: a first transistor T1 and a second transistor T2; the output control subcircuit may include: a third transistor T3, a fourth transistor T4, a fifth transistor and a sixth transistor T6; the noise reduction subcircuit may include: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10.

[0198] like Figure 9 As shown, the first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the first power supply terminal VGH; the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second clock signal terminal CB, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode of the third transistor T3 is electrically connected to the first power supply terminal VGH, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, and the control electrode of the fifth transistor T5 is electrically connected to the third node N3. The first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth transistor T5 is electrically connected to the signal output terminal OUT; the control electrode of the sixth transistor T6 is electrically connected to the third node N3, the first electrode of the sixth transistor T6 is electrically connected to the second power supply terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT; the control electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal CK, the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal VGH, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the eighth transistor T8; the control electrode of the eighth transistor T8 is electrically connected to the third node N3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2; the control electrode of the ninth transistor T9 is electrically connected to the third node N3, the first electrode of the ninth transistor T9 is electrically connected to the second node N2, and the second electrode of the ninth transistor T9 is electrically connected to the second electrode of the tenth transistor T10; the control electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, and the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VGL.

[0199] In an exemplary embodiment, the first transistor T1 , the second transistor T2 , the third transistor T3 , the fifth transistor T5 , the seventh transistor T7 , and the eighth transistor T8 may be P-type transistors.

[0200] In an exemplary embodiment, the fourth transistor T4, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 may be N-type transistors and oxide transistors. Oxide transistors can reduce leakage current, improve the performance of the shift register, and reduce the power consumption of the shift register.

[0201] In an exemplary embodiment, the clock signal at the first clock signal terminal CK and the clock signal at the second clock signal terminal CB are inverted signals.

[0202] In an exemplary embodiment, the signal at the signal input terminal IN can be a first pulse signal, the signal at the signal output terminal OUT can be a second pulse signal, the duration of the first pulse signal is equal to the period of the clock signal at the first clock signal terminal CK, the duration of the second pulse signal is equal to the duration of the first pulse signal, and the start time of the second pulse signal is the end time of the first pulse signal.

[0203] In an exemplary embodiment, the signal at the signal input terminal IN can be a third pulse signal, the duration of the third pulse signal is equal to N times the period of the clock signal at the first clock signal terminal CK, and N is a positive integer greater than or equal to 2; the signal at the signal output terminal OUT can be a fourth pulse signal, the duration of the fourth pulse signal is equal to the duration of the third pulse signal, and the difference between the start time of the fourth pulse signal and the start time of the third pulse signal is equal to the period of the clock signal at the first clock signal terminal CK.

[0204] The shift register provided by the present disclosure includes only one capacitor and a small number of transistors, thereby reducing the area occupied by the shift register and lowering power consumption.

[0205] The shift register provided by the present disclosure can not only output a pulse signal with a shorter duration, but also output a signal with a longer duration, that is, it has a variety of waveform outputs and a wide range of applicability.

[0206] Figure 10 The following is a working timing diagram of a shift register provided by an exemplary embodiment. Figure 11 An operation timing diagram of a shift register provided for another exemplary embodiment. Figure 10 and Figure 11 Can be applied to Figure 8 and Figure 9 The shift register shown, Figure 10 The following is an example of a shift register outputting a short duration pulse signal. Figure 11 The following explanation is given by taking the shift register outputting a pulse signal with a long duration as an example.

[0207] Below through Figure 8 The working process of the shift register of the example is described in detail. Figure 8 For example, in the shift register provided, the first transistor T1, the second transistor T2, the third transistor T3 and the fifth transistor T5 are P-type transistors, and the fourth transistor T4 and the sixth transistor T6 are N-type transistors. Figure 8 The shift register includes a first transistor T1 to a sixth transistor T6, a capacitor (capacitor C) and four signal terminals (a first clock signal terminal CK, a second clock signal terminal CB, a signal input terminal IN and a signal output terminal OUT).

[0208] In an exemplary embodiment, Figure 10 As shown, Figure 8 The working process of the provided shift register may include:

[0209] In the first phase P1, the signal at the first clock signal terminal CK is a low-level signal, and the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, and the signal at the second node N2 remains a high-level signal. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5. In this phase, the signal at the first node N1 is a high-level signal, the signal at the second node N2 is a high-level signal, the signal at the third node N3 is a low-level signal, and the signal at the signal output terminal OUT is a high-level signal.

[0210] In the second phase P2, the signal at the first clock signal terminal CK is a high-level signal, and the signals at the signal input terminal IN and the second clock signal terminal CB are low-level signals. The signal at the first clock signal terminal CK is a high-level signal, the first transistor T1 is turned off, and the low-level signal at the signal input terminal IN cannot be transmitted to the first node N1. The first node N1 maintains the high-level signal of the previous phase. The signal at the second clock signal terminal CB is a low-level signal. The second transistor T2 is turned on, and the high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this phase, the signal at the first node N1 is a high-level signal, the signal at the second node N2 is a high-level signal, the signal at the third node N3 is a low-level signal, and the signal at the signal output terminal OUT is a high-level signal.

[0211] In the third phase P3, the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signal at the second clock signal terminal CB is high-level signal. The signal at the first clock signal terminal CK is low-level signal, the first transistor T1 is turned on, and the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is high-level signal, the second transistor T2 is turned off, and the second node N2 maintains the high-level signal of the previous phase. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5. In this phase, the signal at the first node N1 is low-level signal, the signal at the second node N2 is high-level signal, the signal at the third node N3 is low-level signal, and the signal at the signal output terminal OUT is high-level signal.

[0212] In the fourth phase P4, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level signal. The signal at the first clock signal terminal CK is high-level signal, the first transistor T1 is turned off, and the high-level signal at the signal input terminal IN cannot be transmitted to the first node N1. The first node N1 maintains the low-level signal from the previous phase. The signal at the second clock signal terminal CB is low-level signal, the second transistor T2 is turned on, and the low-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 via the turned-on third transistor T3. The sixth transistor T6 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT via the turned-on sixth transistor T6. In this phase, the signal at the first node N1 is low-level signal, the signal at the second node N2 is low-level signal, the signal at the third node N3 is high-level signal, and the signal at the signal output terminal OUT is low-level signal.

[0213] In the fifth phase P5, the signal at the first clock signal terminal CK is a low-level signal, while the signals at the second clock signal terminal CB and the signal input terminal IN are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, and the second node N2 maintains the low-level signal from the previous phase. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3. The sixth transistor T6 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6. In this phase, the signal at the first node N1 is a high-level signal, the signal at the second node N2 is a low-level signal, the signal at the third node N3 is a high-level signal, and the signal at the signal output terminal OUT is a low-level signal.

[0214] In the sixth phase P6, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level signal. The signal at the first clock signal terminal CK is high-level signal, the first transistor T1 is turned off, and the first node N1 maintains the high-level signal of the previous phase. The signal at the second clock signal terminal CB is low-level signal, the second transistor T2 is turned on, and the high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this phase, the signal at the first node N1 is high-level signal, the signal at the second node N2 is high-level signal, the signal at the third node N3 is low-level signal, and the signal at the signal output terminal OUT is high-level signal.

[0215] In an exemplary embodiment, Figure 11 As shown, Figure 8 The working process of the provided shift register may include:

[0216] In the first phase P1, the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signal at the second clock signal terminal CB is high-level signal. The signal at the first clock signal terminal CK is low-level signal, the first transistor T1 is turned on, and the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is high-level signal, the second transistor T2 is turned off, and the signal at the second node N2 remains low-level signal. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3. The sixth transistor T6 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6. In this phase, the signal at the first node N1 is low-level signal, the signal at the second node N2 is low-level signal, the signal at the third node N3 is high-level signal, and the signal at the signal output terminal OUT is low-level signal.

[0217] In the second phase P2, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level signal. The signal at the first clock signal terminal CK is high-level signal, the first transistor T1 is turned off, and the high-level signal at the signal input terminal IN cannot be transmitted to the first node N1. The first node N1 maintains the low-level signal of the previous phase. The signal at the second clock signal terminal CB is low-level signal, the second transistor T2 is turned on, and the low-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 via the turned-on third transistor T3. The sixth transistor T6 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT via the turned-on sixth transistor T6. In this phase, the signal at the first node N1 is low-level signal, the signal at the second node N2 is low-level signal, the signal at the third node N3 is high-level signal, and the signal at the signal output terminal OUT is low-level signal.

[0218] In the third phase P3, the signal at the first clock signal terminal CK is a low-level signal, while the signals at the second clock signal terminal CB and the signal input terminal IN are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, and the second node N2 maintains the low-level signal of the previous phase. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3. The sixth transistor T6 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6. In this phase, the signal at the first node N1 is a high-level signal, the signal at the second node N2 is a low-level signal, the signal at the third node N3 is a high-level signal, and the signal at the signal output terminal OUT is a low-level signal.

[0219] In the fourth phase P4, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level signal. The signal at the first clock signal terminal CK is high-level signal, the first transistor T1 is turned off, and the first node N1 maintains the high-level signal of the previous phase. The signal at the second clock signal terminal CB is low-level signal, the second transistor T2 is turned on, and the high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this phase, the signal at the first node N1 is high-level signal, the signal at the second node N2 is high-level signal, the signal at the third node N3 is low-level signal, and the signal at the signal output terminal OUT is high-level signal.

[0220] In the fifth phase P5, the signal at the first clock signal terminal CK is a low-level signal, while the signals at the second clock signal terminal CB and the signal input terminal IN are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, and the second node N2 maintains the high-level signal from the previous phase. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5. In this phase, the signal at the first node N1 is a high-level signal, the signal at the second node N2 is a high-level signal, the signal at the third node N3 is a low-level signal, and the signal at the signal output terminal OUT is a high-level signal.

[0221] In the sixth phase P6, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level signal. The signal at the first clock signal terminal CK is high-level signal, the first transistor T1 is turned off, and the first node N1 maintains the high-level signal of the previous phase. The signal at the second clock signal terminal CB is low-level signal, the second transistor T2 is turned on, and the high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this phase, the signal at the first node N1 is high-level signal, the signal at the second node N2 is high-level signal, the signal at the third node N3 is low-level signal, and the signal at the signal output terminal OUT is high-level signal.

[0222] In the seventh stage P7, the signal at the first clock signal terminal CK is a low-level signal, while the signals at the second clock signal terminal CB and the signal input terminal IN are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, and the second node N2 maintains the high-level signal from the previous stage. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high-level signal, the signal at the second node N2 is a high-level signal, the signal at the third node N3 is a low-level signal, and the signal at the signal output terminal OUT is a high-level signal.

[0223] In the eighth stage P8, the signal at the first clock signal terminal CK is a high-level signal, while the signals at the second clock signal terminal CB and the signal input terminal IN are low-level signals. The signal at the first clock signal terminal CK is a high-level signal, the first transistor T1 is turned off, and the low-level signal at the signal input terminal IN cannot be transmitted to the first node N1. The first node N1 maintains the high-level signal of the previous stage. The signal at the second clock signal terminal CB is a low-level signal, the second transistor T2 is turned on, and the high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high-level signal, the signal at the second node N2 is a high-level signal, the signal at the third node N3 is a low-level signal, and the signal at the signal output terminal OUT is a high-level signal.

[0224] In the ninth stage P9, the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signal at the second clock signal terminal CB is high-level signal. The signal at the first clock signal terminal CK is low-level signal, the first transistor T1 is turned on, and the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is high-level signal, the second transistor T2 is turned off, and the second node N2 maintains the high-level signal of the previous stage. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4. The fifth transistor T5 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is low-level signal, the signal at the second node N2 is high-level signal, the signal at the third node N3 is low-level signal, and the signal at the signal output terminal OUT is high-level signal.

[0225] In the tenth stage P10, the signal at the first clock signal terminal CK is a high-level signal, while the signals at the second clock signal terminal CB and the signal input terminal IN are low-level signals. The signal at the first clock signal terminal CK is a high-level signal, the first transistor T1 is turned off, and the first node N1 maintains the low-level signal from the previous stage. The signal at the second clock signal terminal CB is a low-level signal, the second transistor T2 is turned on, and the low-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 via the turned-on third transistor T3. The sixth transistor T6 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT via the turned-on sixth transistor T6. In this stage, the signal at the first node N1 is a low-level signal, the signal at the second node N2 is a low-level signal, the signal at the third node N3 is a high-level signal, and the signal at the signal output terminal OUT is a low-level signal.

[0226] Below through Figure 9 The working process of the shift register of the example is described in detail. Figure 9 For example, in the provided shift register, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are P-type transistors, and the fourth transistor T4, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 are N-type transistors. Figure 9 The shift register includes a first transistor T1 to a tenth transistor T10, a capacitor (capacitor C) and four signal terminals (a first clock signal terminal CK, a second clock signal terminal CB, a signal input terminal IN and a signal output terminal OUT).

[0227] In an exemplary embodiment, Figure 10 As shown, Figure 9 The working process of the provided shift register may include:

[0228] In the first phase P1, the signal at the first clock signal terminal CK is a low-level signal, and the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, the tenth transistor T10 is turned on, and the signal at the second node N2 remains a high-level signal. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4. The fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 is turned off, the low-level signal at the second power supply terminal VGL cannot be written to the second node N2. The signal at the first power supply terminal VGH can be transmitted to the second node N2 through the turned-on seventh transistor T7 and eighth transistor T8. The signal at the second node N2 remains a high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0229] In the second phase P2, the signal at the first clock signal terminal CK is a high-level signal, and the signals at the signal input terminal IN and the second clock signal terminal CB are low-level signals. The signal at the first clock signal terminal CK is a high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, and the low-level signal at the signal input terminal IN cannot be transmitted to the first node N1. The first node N1 maintains the high-level signal of the previous phase. The signal at the second clock signal terminal CB is a low-level signal. The second transistor T2 is turned on, and the tenth transistor T10 is turned off. The high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4. The fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 and the tenth transistor T10 are both turned off, the low-level signal at the second power supply terminal VGL cannot be written to the second node N2. The signal at the second node N2 remains a high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0230] In the third phase P3, the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signal at the second clock signal terminal CB is high-level signal. The signal at the first clock signal terminal CK is low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the low-level signal at the signal input terminal IN is transmitted to the first node N1 via the turned-on first transistor T1. The signal at the second clock signal terminal CB is high-level signal, the second transistor T2 is turned off, the tenth transistor T10 is turned on, and the fourth transistor T4 is turned on. The low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4. The fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 is turned off, the low-level signal at the second power supply terminal VGL cannot be written to the second node N2. The signal at the first power supply terminal VGH can be transmitted to the second node N2 via the turned-on seventh transistor T7 and eighth transistor T8. The signal at the second node N2 remains high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a low level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0231] In the fourth phase P4, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level. The signal at the first clock signal terminal CK is high-level, the first transistor T1 and the seventh transistor T7 are turned off, and the high-level signal at the signal input terminal IN cannot be transmitted to the first node N1. The first node N1 maintains the low-level signal of the previous phase. The signal at the second clock signal terminal CB is low-level, the second transistor T2 is turned on, the tenth transistor T10 is turned off, and the low-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 via the turned-on third transistor T3. The sixth transistor T6 and the ninth transistor T9 are turned on, and the eighth transistor T8 is turned off. Since the seventh transistor T7 and the eighth transistor T8 are both turned off, the high-level signal at the first power supply terminal VGH cannot be written to the second node N2. The signal at the second node N2 remains low-level, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT via the turned-on sixth transistor T6. In this stage, the signal at the first node N1 is a low level signal, the signal at the second node N2 is a low level signal, the signal at the third node N3 is a high level signal, and the signal at the signal output terminal OUT is a low level signal.

[0232] In the fifth phase P5, the signal at the first clock signal terminal CK is a low-level signal, and the signals at the second clock signal terminal CB and the signal input terminal IN are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, the tenth transistor T10 is turned on, and the second node N2 maintains the low-level signal of the previous phase. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3. The sixth transistor T6 and the ninth transistor T9 are turned on, and the eighth transistor T8 is turned off. Since the ninth transistor T9 and the tenth transistor T10 are turned on, the low-level signal at the second power supply terminal VLG is transmitted to the second node N2 through the turned-on ninth transistor T9 and the tenth transistor T10. The signal at the second node N2 remains a low-level signal, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a low level signal, the signal at the third node N3 is a high level signal, and the signal at the signal output terminal OUT is a low level signal.

[0233] In the sixth phase P6, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level signal. The signal at the first clock signal terminal CK is high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, the first node N1 maintains the high-level signal of the previous phase, the signal at the second clock signal terminal CB is low-level signal, the second transistor T2 is turned on, the tenth transistor T10 is turned off, the high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2, the fourth transistor T4 is turned on, the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 and the tenth transistor T10 are both turned off, the low-level signal at the second power supply terminal VLG cannot be transmitted to the second node N2, the signal at the second node N2 remains high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0234] In an exemplary embodiment, Figure 11 As shown, Figure 9 The working process of the provided shift register may include:

[0235] In the first phase P1, the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signal at the second clock signal terminal CB is high-level signal. The signal at the first clock signal terminal CK is low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is high-level signal, the second transistor T2 is turned off, the tenth transistor T10 is turned on, and the signal at the second node N2 remains low-level signal. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3. The sixth transistor T6 and the ninth transistor T9 are turned on, and the eighth transistor T8 is turned off. The low-level signal at the second power supply terminal VGL is transmitted to the second node N2 through the turned-on ninth transistor T9 and the tenth transistor T10. The signal at the second node N2 remains low-level signal, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6. In this stage, the signal at the first node N1 is a low level signal, the signal at the second node N2 is a low level signal, the signal at the third node N3 is a high level signal, and the signal at the signal output terminal OUT is a low level signal.

[0236] In the second phase P2, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level signal. The signal at the first clock signal terminal CK is high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, and the high-level signal at the signal input terminal IN cannot be transmitted to the first node N1. The first node N1 maintains the low-level signal of the previous phase. The signal at the second clock signal terminal CB is low-level signal, the second transistor T2 is turned on, the tenth transistor T10 is turned off, and the low-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 via the turned-on third transistor T3. The sixth transistor T6 and the ninth transistor T9 are turned on, and the eighth transistor T8 is turned off. Since the seventh transistor T7 and the eighth transistor T8 are both turned off, the high-level signal at the first power supply terminal VGH cannot be transmitted to the second node N2. The signal at the second node N2 remains low-level signal, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT via the turned-on sixth transistor T6. In this stage, the signal at the first node N1 is a low level signal, the signal at the second node N2 is a low level signal, the signal at the third node N3 is a high level signal, and the signal at the signal output terminal OUT is a low level signal.

[0237] In the third phase P3, the signal at the first clock signal terminal CK is a low-level signal, while the signals at the second clock signal terminal CB and the signal input terminal IN are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, the tenth transistor T10 is turned on, and the second node N2 maintains the low-level signal of the previous phase. The third transistor T3 is turned on, and the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 through the turned-on third transistor T3. The sixth transistor T6 and the ninth transistor T9 are turned on, and the eighth transistor T8 is turned off. The low-level signal at the second power supply terminal VGL is transmitted to the second node N2 through the turned-on ninth transistor T9 and the tenth transistor T10. The signal at the second node N2 remains a low-level signal, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT through the turned-on sixth transistor T6. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a low level signal, the signal at the third node N3 is a high level signal, and the signal at the signal output terminal OUT is a low level signal.

[0238] In the fourth phase P4, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level signal. The signal at the first clock signal terminal CK is high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, the first node N1 maintains the high-level signal of the previous phase, the signal at the second clock signal terminal CB is low-level signal, the second transistor T2 is turned on, the tenth transistor T10 is turned off, the high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2, the fourth transistor T4 is turned on, the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 and the tenth transistor T10 are both turned off, the low-level signal at the second power supply terminal VGL cannot be transmitted to the second node N2, the signal at the second node N2 remains high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0239] In the fifth phase P5, the signal at the first clock signal terminal CK is a low-level signal, and the signals at the second clock signal terminal CB and the signal input terminal IN are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, the tenth transistor T10 is turned on, and the signal at the second node N2 remains the high-level signal from the previous phase. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4. The fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. The high-level signal at the first power supply terminal VGH is transmitted to the second node N2 through the turned-on seventh transistor T7 and the eighth transistor T8. The signal at the second node N2 remains a high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0240] In the sixth phase P6, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, and the signal at the second clock signal terminal CB is low-level signal. The signal at the first clock signal terminal CK is high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, the first node N1 maintains the high-level signal of the previous phase, the signal at the second clock signal terminal CB is low-level signal, the second transistor T2 is turned on, the tenth transistor T10 is turned off, the high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2, the fourth transistor T4 is turned on, the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 and the tenth transistor T10 are both turned off, the low-level signal at the second power supply terminal VGL cannot be transmitted to the second node N2, the signal at the second node N2 remains high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0241] In the seventh phase P7, the signal at the first clock signal terminal CK is a low-level signal, and the signals at the second clock signal terminal CB and the signal input terminal IN are high-level signals. The signal at the first clock signal terminal CK is a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the high-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is a high-level signal, the second transistor T2 is turned off, the tenth transistor T10 is turned on, and the second node N2 maintains the high-level signal of the previous phase. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4. The fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. The high-level signal at the first power supply terminal VGH is transmitted to the second node N2 through the turned-on seventh transistor T7 and the eighth transistor T8. The signal at the second node N2 remains a high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0242] In the eighth phase P8, the signal at the first clock signal terminal CK is a high-level signal, while the signals at the second clock signal terminal CB and the signal input terminal IN are low-level signals. The signal at the first clock signal terminal CK is a high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, and the low-level signal at the signal input terminal IN cannot be transmitted to the first node N1. The first node N1 maintains the high-level signal of the previous phase. The signal at the second clock signal terminal CB is a low-level signal, the second transistor T2 is turned on, the tenth transistor T10 is turned off, and the high-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 via the turned-on fourth transistor T4. The fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Since the ninth transistor T9 and the tenth transistor T10 are both turned off, the low-level signal at the second power supply terminal VGL cannot be transmitted to the second node N2. The signal at the second node N2 remains a high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT via the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a high level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0243] In the ninth stage P9, the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals, and the signal at the second clock signal terminal CB is high-level signal. The signal at the first clock signal terminal CK is low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the low-level signal at the signal input terminal IN is transmitted to the first node N1 through the turned-on first transistor T1. The signal at the second clock signal terminal CB is high-level signal, the second transistor T2 is turned off, the tenth transistor T10 is turned on, and the second node N2 maintains the high-level signal of the previous stage. The fourth transistor T4 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the third node N3 through the turned-on fourth transistor T4. The fifth transistor T5 and the eighth transistor T8 are turned on, and the ninth transistor T9 is turned off. Because the ninth transistor T9 is turned off, the low-level signal at the second power supply terminal VGL cannot be transmitted to the second node N2. The signal at the second node N2 remains high-level signal, and the high-level signal at the first power supply terminal VGH is transmitted to the signal output terminal OUT through the turned-on fifth transistor T5. In this stage, the signal at the first node N1 is a low level signal, the signal at the second node N2 is a high level signal, the signal at the third node N3 is a low level signal, and the signal at the signal output terminal OUT is a high level signal.

[0244] In the tenth stage P10, the signal at the first clock signal terminal CK is a high-level signal, while the signals at the second clock signal terminal CB and the signal input terminal IN are low-level signals. The signal at the first clock signal terminal CK is a high-level signal, the first transistor T1 and the seventh transistor T7 are turned off, the first node N1 maintains the low-level signal of the previous stage, the signal at the second clock signal terminal CB is a low-level signal, the second transistor T2 is turned on, the tenth transistor T10 is turned off, the low-level signal at the first node N1 is transmitted to the second node N2 via the turned-on second transistor T2, the third transistor T3 is turned on, the high-level signal at the first power supply terminal VGH is transmitted to the third node N3 via the turned-on third transistor T3, the sixth transistor T6 and the ninth transistor T9 are turned on, and the eighth transistor T8 is turned off. Since the seventh transistor T7 and the eighth transistor T8 are both turned off, the high-level signal at the first power supply terminal VGH cannot be transmitted to the second node N2. The signal at the second node N2 remains a low-level signal, and the low-level signal at the second power supply terminal VGL is transmitted to the signal output terminal OUT via the turned-on sixth transistor T6. In this stage, the signal at the first node N1 is a low level signal, the signal at the second node N2 is a low level signal, the signal at the third node N3 is a high level signal, and the signal at the signal output terminal OUT is a low level signal.

[0245] The present disclosure also provides a display substrate, comprising a display area and a non-display area. The display substrate comprises a base and a circuit structure layer disposed on the base. The circuit structure layer comprises a gate drive circuit located in the non-display area and an array-arranged pixel circuit located in the display area. The gate drive circuit comprises a plurality of cascaded shift registers. The pixel circuit comprises a light-emitting signal line, a scanning signal line, and a reset signal line.

[0246] The signal output end of the i-th stage shift register is electrically connected to the signal input end of the i+1-th stage shift register, 1≤i≤M-1, and M is the total number of stages of the shift register.

[0247] In the present disclosure, the gate driving circuit may be electrically connected to at least one signal line among the light emitting signal line, the scanning signal line, and the reset signal line.

[0248] In an exemplary embodiment, the pixel circuit may be a 7T1C or 8T1C circuit structure, which is not limited in the present disclosure.

[0249] The shift register may be the shift register provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be described in detail here.

[0250] The cascade relationship of multiple shift registers in the gate drive circuit may vary for different display products. Regardless of the cascade relationship of the multiple shift registers, each shift register drives several rows of sub-pixels. As long as a large-area device such as this is modified, and the additional space created by this modification, the simple translation or stretching of small devices is within the scope of protection of this disclosure.

[0251] In an exemplary embodiment, the display substrate disclosed herein can be applied to a display device having a gate driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0252] In an exemplary embodiment, the circuit structure layer may further include: a pixel circuit and a reset signal line, a light emitting signal line, and a scan signal line connected to the pixel circuit. The gate drive circuit may provide a signal for at least one of the reset signal line, the light emitting signal line, and the scan signal line.

[0253] In an exemplary embodiment, the display substrate may further include a light emitting structure layer disposed on a side of the circuit structure layer away from the substrate. The light emitting structure layer includes light emitting elements arranged in an array in the display area.

[0254] In an exemplary embodiment, the light emitting element may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), wherein the OLED may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).

[0255] In an exemplary embodiment, the display substrate may further include other film layers, such as spacers and columns, etc., which is not limited in the present disclosure.

[0256] Figure 12 A schematic structural diagram of a display substrate is provided for an exemplary embodiment. Figure 12 As shown, in an exemplary embodiment, the display substrate may further include: a first clock signal line CLK1, a second clock signal line CLK2, a first power line VHL and a second power line VLL extending along a first direction, the first power line VHL, the second power line VLL, the first clock signal line CLK1 and the second clock signal line CLK2 are arranged along a second direction, and the first direction intersects the second direction.

[0257] The first power supply terminals of all shift registers are electrically connected to the first power supply line, the second power supply terminals of all shift registers are electrically connected to the second power supply line, the first clock signal terminal of the i-th stage shift register is electrically connected to the first clock signal line, the second clock signal terminal of the i-th stage shift register is electrically connected to the second clock signal line, the first clock signal terminal of the i+1-th stage shift register is electrically connected to the second clock signal line, and the second clock signal terminal of the i+1-th stage shift register is electrically connected to the first clock signal line.

[0258] like Figure 12 As shown, the shift register includes: a first transistor T1 to a tenth transistor T10 and a capacitor C, and the capacitor C includes: a first plate and a second plate.

[0259] In an exemplary embodiment, the circuit structure layer may include: a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer sequentially stacked on a substrate;

[0260] The first semiconductor layer includes: an active layer of a first transistor, an active layer of a second transistor, an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a seventh transistor, and an active layer of an eighth transistor;

[0261] The first conductive layer includes: a control electrode of the first transistor, a control electrode of the second transistor, a control electrode of the third transistor, a control electrode of the fifth transistor, a control electrode of the seventh transistor, a control electrode of the eighth transistor, a first plate of the capacitor and a signal output line;

[0262] The second conductive layer includes: a second plate of the capacitor;

[0263] The second semiconductor layer includes: an active layer of a fourth transistor, an active layer of a sixth transistor, an active layer of a ninth transistor, and an active layer of a tenth transistor;

[0264] The third conductive layer includes: a control electrode of the fourth transistor, a control electrode of the sixth transistor, a control electrode of the ninth transistor, and a control electrode of the tenth transistor;

[0265] The fourth conductive layer includes: a first clock signal line, a second clock signal line, a first power line, a second power line, a first electrode and a second electrode of the first transistor to a first electrode and a second electrode of the sixth transistor, a first electrode of the seventh transistor, a second electrode of the eighth transistor, a first electrode of the ninth transistor, a first electrode of the tenth transistor, a first connecting signal line, a second connecting signal line, and a third connecting signal line;

[0266] The signal output line is connected to the second electrode of the fifth transistor and the second electrode of the sixth transistor respectively; the first connection signal line is connected to the active layer of the third transistor and the control electrode of the ninth transistor respectively; the second connection signal line is connected to the active layer of the third transistor and the control electrode of the eighth transistor respectively; the third connection signal line is connected to the control electrode of the tenth transistor and the control electrode of the second transistor respectively.

[0267] like Figure 12As shown, in an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 are located on the same side of the first power line VHL, and the fifth transistor T5 and the sixth transistor T6 are arranged along the first direction; the third transistor T3 is located on the side of the fifth transistor T5 away from the first power line VHL, the fourth transistor T4 is located on the side of the sixth transistor T6 away from the first power line VHL, the third transistor T3 and the fourth transistor T4 are arranged along the first direction, the third transistor T3 and the fifth transistor T5 are arranged along the second direction, and the fourth transistor T4 and the sixth transistor T6 are arranged along the second direction; the eighth transistor T8 is located on the side of the third transistor T3 away from the fifth transistor T5, the ninth transistor T9 is located on the side of the fourth transistor T4 away from the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 are arranged along the first direction, the third transistor T3 and the eighth transistor T8 are arranged along the second direction, and the fourth transistor T4 and the ninth transistor T9 are arranged along the first direction. The seventh transistor T7 is arranged along the second direction; the seventh transistor T7 is located on the side of the eighth transistor T8 away from the third transistor T3, the tenth transistor T10 is located on the side of the ninth transistor T9 away from the fourth transistor T4, the seventh transistor T7 and the tenth transistor T10 are arranged along the first direction, the seventh transistor Y7 and the eighth transistor T8 are arranged along the second direction, and the ninth transistor T9 and the tenth transistor T10 are arranged along the second direction; the second transistor T2 is located between the seventh transistor T7 and the tenth transistor T10, the first transistor T1 is located on the side of the seventh transistor T7 away from the eighth transistor T8, and the capacitor C is located on the side of the tenth transistor T10 away from the ninth transistor T9; the second power line VLL is located on the side of the capacitor C away from the tenth transistor T10, the first clock signal line CLK1 is located on the side of the second power line VLL away from the capacitor C, and the second clock signal line CLK2 is located on the side of the first clock signal line CLK1 away from the second power line VLL.

[0268] In an exemplary embodiment, the active layer of the first transistor and the active layer of the second transistor are an integrally formed structure, and the active layer of the seventh transistor and the active layer of the eighth transistor are an integrally formed structure;

[0269] The active layer of the third transistor includes a first active connection portion, a second active connection portion, and a third active connection portion; the first active connection portion and the third active connection portion extend along a first direction, and the second active connection portion extends along a second direction and is connected to the first active connection portion and the third active connection portion, respectively;

[0270] The first active connection portion is located on a side of the second active connection portion close to the integrally formed structure of the active layer of the seventh transistor and the active layer of the eighth transistor, and the third active connection portion is located on a side of the second active connection portion away from the integrally formed structure of the active layer of the seventh transistor and the active layer of the eighth transistor;

[0271] A straight line extending along the second direction passes through the first active connection portion and the active layer of the second transistor;

[0272] A straight line extending along the second direction passes through the third active connection and the active layer of the first transistor.

[0273] In an exemplary embodiment, the first plate of the capacitor includes: a first capacitor body portion and a first capacitor connecting portion connected to each other;

[0274] The control electrode of the first transistor and the control electrode of the seventh transistor are integrally formed and are located on a side of the first capacitor connecting portion away from the first capacitor main body;

[0275] A virtual straight line extending along the second direction passes through the control electrode of the eighth transistor and the integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor.

[0276] A virtual straight line extending along the second direction passes through the control electrode of the third transistor and the control electrode of the eighth transistor;

[0277] A virtual straight line extending along the second direction passes through the control electrode of the fifth transistor and the control electrode of the third transistor.

[0278] A virtual straight line extending along the second direction passes through the signal output line and the control electrode of the second transistor.

[0279] In an exemplary embodiment, the second plate of the capacitor includes: a second capacitor main body and a second capacitor connecting portion connected to each other, the second capacitor connecting portion being located on one side of the second capacitor main body;

[0280] The area of ​​the first capacitor body portion of the first electrode plate of the capacitor is greater than the area of ​​the second capacitor body portion of the second electrode plate of the capacitor;

[0281] The orthographic projections of the second capacitor main body and the second capacitor connecting portion on the substrate at least partially overlap with the orthographic projection of the first capacitor main body of the first plate of the capacitor on the substrate, and do not overlap with the orthographic projection of the first capacitor connecting portion of the first plate of the capacitor on the substrate.

[0282] In an exemplary embodiment, an orthographic projection of the active layer of the sixth transistor on the substrate and an orthographic projection of the active layer of the fifth transistor on the substrate are respectively located on opposite sides of an orthographic projection of the signal output line on the substrate, and a straight line extending along the first direction passes through the active layer of the fifth transistor and the active layer of the sixth transistor;

[0283] a straight line extending along the first direction passing through the active layer of the fourth transistor and the third active connection portion of the active layer of the third transistor;

[0284] A straight line extending along the first direction passes through the active layer of the ninth transistor and the active layer of the eighth transistor, and a straight line extending along the first direction passes through the active layer of the tenth transistor and the active layer of the seventh transistor.

[0285] In an exemplary embodiment, a virtual straight line extending along the second direction passes through the control electrode of the fourth transistor, the control electrode of the sixth transistor, and the control electrode of the ninth transistor;

[0286] The control electrode of the tenth transistor includes a first electrode connection portion, a second electrode connection portion, and a third electrode connection portion. The first electrode connection portion and the third electrode connection portion extend along the second direction, and the second electrode connection portion extends along the first direction and is connected to the first electrode connection portion and the third electrode connection portion, respectively.

[0287] The first electrode connection portion is located on a side of the second electrode connection portion close to the control electrode of the ninth transistor, and the third electrode connection portion is located on a side of the second electrode connection portion away from the control electrode of the ninth transistor;

[0288] A virtual straight line extending along the second direction passes through an orthographic projection of the first electrode connection portion of the control electrode of the tenth transistor on the substrate and an orthographic projection of the first capacitor body portion of the first plate of the capacitor on the substrate;

[0289] The orthographic projection of the third electrode connection portion of the control electrode of the tenth transistor on the substrate is located on a side of the orthographic projection of the first plate of the capacitor on the substrate away from the orthographic projection of the integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor on the substrate.

[0290] In an exemplary embodiment, the fifth insulating layer is provided with a plurality of via patterns, the plurality of via patterns including: a first via to a sixth via provided in the first insulating layer, the second insulating layer, and the fifth insulating layer, a seventh via to a thirteenth via provided in the second insulating layer to the fifth insulating layer, a fourteenth via provided in the third insulating layer to the fifth insulating layer, a fifteenth via to an eighteenth via provided in the fourth insulating layer to the fifth insulating layer, and a nineteenth via to a twenty-second via provided in the fifth insulating layer; the third via exposes the active layer of the third transistor, and the twenty-second via exposes the control electrode of the tenth transistor;

[0291] There are four third vias, a virtual straight line extending along the first direction passes through a first third via and a second third via, and the first third via and the second third via expose the first active connection portion of the active layer of the third transistor, a virtual straight line extending along the first direction passes through a third third via and a fourth third via, and the third third via and the fourth third via expose the third active connection portion of the active layer of the third transistor, and a virtual straight line extending along the second direction passes through the second third via and the third third via;

[0292] There are two twenty-second via holes. The first twenty-second via hole exposes the second electrode connection portion of the control electrode of the tenth transistor, and the second twenty-second via hole exposes the third electrode connection portion of the control electrode of the tenth transistor.

[0293] In an exemplary embodiment, the first electrode of the third transistor, the first electrode of the fifth transistor, the first electrode of the seventh transistor, and the first power line are integrally formed, the first electrode of the fourth transistor, the first electrode of the sixth transistor, the first electrode of the tenth transistor and the second power line are integrally formed, the second electrode of the first transistor and the first electrode of the second transistor are integrally formed, the second electrode of the third transistor and the second electrode of the fourth transistor are integrally formed, the second electrode of the second transistor, the second electrode of the eighth transistor, and the first electrode of the ninth transistor are integrally formed, and the second electrode of the fifth transistor and the second electrode of the sixth transistor are integrally formed;

[0294] The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the signal output line on the substrate; the orthographic projection of the second power line on the substrate partially overlaps with the orthographic projection of the control electrode of the first transistor and the control electrode of the seventh transistor, the control electrode of the tenth transistor and the second capacitor connecting portion of the second plate of the capacitor on the substrate; the orthographic projection of the first clock signal line on the substrate partially overlaps with the orthographic projection of the control electrode of the tenth transistor and the orthographic projection of the integral structure of the control electrode of the first transistor and the control electrode of the seventh transistor on the substrate; the second clock signal line partially overlaps with the orthographic projection of the control electrode of the connected transistor on the substrate; the orthographic projection of the integral structure of the second electrode of the first transistor and the first electrode of the second transistor on the substrate partially overlaps with the orthographic projection of the first capacitor connecting portion of the first plate of the capacitor on the substrate; the second electrode of the third transistor and the integral structure of the second electrode of the fourth transistor The orthographic projection of the integrated structure on the substrate partially overlaps with the orthographic projection of the control electrode of the sixth transistor and the control electrode of the fifth transistor on the substrate; the orthographic projection of the second electrode of the fifth transistor and the second electrode of the sixth transistor on the substrate partially overlaps with the orthographic projection of the signal output line on the substrate; the orthographic projection of the second electrode of the second transistor, the second electrode of the eighth transistor and the first electrode of the ninth transistor on the substrate partially overlaps with the orthographic projection of the control electrode of the third transistor and the control electrode of the fourth transistor on the substrate; the orthographic projection of the first connecting signal line on the substrate partially overlaps with the orthographic projection of the control electrode of the ninth transistor on the substrate; the orthographic projection of the second connecting signal line on the substrate partially overlaps with the orthographic projection of the control electrode of the eighth transistor on the substrate; the orthographic projection of the third connecting signal line on the substrate partially overlaps with the orthographic projection of the control electrode of the second transistor and the control electrode of the tenth transistor on the substrate.

[0295] In an exemplary embodiment, the first electrode and the second electrode of the third transistor are connected to the active layer of the third transistor through a third third via and a fourth third via respectively; the first connecting signal line is connected to the active layer of the third transistor through the first third via; the second connecting signal line is connected to the active layer of the third transistor through the second third via; the third connecting signal line is connected to the control electrode of the tenth transistor through the first twenty-second via; and one of the first clock signal line and the second clock signal line is connected to the control electrode of the tenth transistor through the second twenty-second via.

[0296] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. Figures 13 to 18 The display substrate includes Figure 9 The provided shift register, ie, the shift register includes: a first transistor T1 to a tenth transistor T10 , which is described by way of example.

[0297] (1) forming a first semiconductor layer pattern on a substrate, including: depositing a first semiconductor film on the substrate, and patterning the first semiconductor film through a patterning process to form a first semiconductor layer pattern. Figure 13 As shown, Figure 13 FIG. 4 is a schematic diagram after forming the first semiconductor layer pattern.

[0298] In an exemplary embodiment, Figure 13As shown, the first semiconductor layer pattern may include an active layer T11 of a first transistor, an active layer T21 of a second transistor, an active layer T31 of a third transistor, an active layer T51 of a fifth transistor, an active layer T71 of a seventh transistor, and an active layer T81 of an eighth transistor.

[0299] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0300] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0301] In an exemplary embodiment, the first semiconductor layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0302] In an exemplary embodiment, Figure 13As shown, the active layer T11 of the first transistor and the active layer T21 of the second transistor may be an integrally formed structure, and the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor may be an integrally formed structure.

[0303] In an exemplary embodiment, Figure 13 As shown, the active layer T11 of the first transistor extends along the first direction and can be a strip-shaped structure, and the active layer T21 of the second transistor extends along the second direction and can be a strip-shaped structure. The integrated structure of the active layer T11 of the first transistor and the active layer T21 of the second transistor can be an inverted "L" shape, and the opening of the inverted "L" shape faces the integrated structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor.

[0304] In an exemplary embodiment, Figure 13 As shown, the active layer T71 of the seventh transistor can be an "n" type, and the active layer T81 of the eighth transistor can be an "L" type. The integrated structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor can be an "S" type rotated 90 degrees.

[0305] In an exemplary embodiment, Figure 13 As shown, the active layer T31 of the third transistor may be located on a side of the integrally formed structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor away from the integrally formed structure of the active layer T11 of the first transistor and the active layer T21 of the second transistor.

[0306] In an exemplary embodiment, Figure 13 As shown, the active layer T31 of the third transistor may include a first active connection portion T31A, a second active connection portion T31B, and a third active connection portion T31C. The first active connection portion T31A and the third active connection portion T31C extend along a first direction, and the second active connection portion T31B extends along a second direction and is connected to the first active connection portion T31A and the third active connection portion T31C, respectively.

[0307] In an exemplary embodiment,

[0308] Figure 13 As shown, the first active connection portion T31A and the third active connection portion T31C are respectively located on opposite sides of the second active connection portion T31B. The first active connection portion T31A is located on a side of the second active connection portion T31B that is close to the integral structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor, and the third active connection portion T31C is located on a side of the second active connection portion T31B that is away from the integral structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor.

[0309] In an exemplary embodiment, Figure 13 As shown, the straight line extending along the second direction passes through the first active connection portion T31A and the active layer T21 of the second transistor.

[0310] In an exemplary embodiment, Figure 13 As shown, the straight line extending along the second direction passes through the third active connection portion T31C and the active layer T11 of the first transistor.

[0311] In an exemplary embodiment, Figure 13 As shown, the active layer T51 of the fifth transistor is located on a side of the active layer T31 of the third transistor away from the integrated structure of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor, and extends along the first direction. The active layer T51 of the fifth transistor may be square.

[0312] (2) forming a first conductive layer pattern, comprising: depositing a first insulating film and a first conductive film on a substrate having the aforementioned pattern formed thereon, patterning the first insulating film and the first conductive film by a patterning process to form a first insulating layer pattern and a first conductive layer pattern disposed on the first insulating layer pattern, such as Figure 14A and Figure 14B As shown, Figure 14A is a schematic diagram of the first conductive layer pattern, Figure 14B Schematic diagram after forming the first conductive layer pattern.

[0313] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the first conductive layer pattern may include: a control electrode T12 of the first transistor, a control electrode T22 of the second transistor, a control electrode T32 of the third transistor, a control electrode T52 of the fifth transistor, a control electrode T72 of the seventh transistor, a control electrode T82 of the eighth transistor, a first electrode plate C1 of the capacitor and a signal output line OUTL.

[0314] In an exemplary embodiment, the first conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0315] In an exemplary embodiment, the first insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a first gate insulating layer.

[0316] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the first plate C1 of the capacitor may include: a first capacitor main body C11 and a first capacitor connecting portion C12 connected to each other. The first capacitor connecting portion C12 is located on one side of the first capacitor main body C11.

[0317] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the area of ​​the first capacitor connecting portion C12 is smaller than the area of ​​the first capacitor main portion C11.

[0318] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor are an integrally formed structure. The integrally formed structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor extends along the second direction and can be in a strip shape.

[0319] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the integrally formed structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor may be located on a side of the first capacitor connecting portion C12 away from the first capacitor main portion C11 .

[0320] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the control electrode T22 of the second transistor and the first plate C1 of the capacitor are located on the same side of the integrally formed structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor, and the control electrode T22 of the second transistor is located on the side of the first plate C1 of the capacitor close to the signal output line. The control electrode T22 of the second transistor can be "L"-shaped, rotated 90 degrees.

[0321] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the control electrode T82 of the eighth transistor can be located on one side of the integrally formed structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor, and a virtual straight line extending along the second direction passes through the control electrode T82 of the eighth transistor and the integrally formed structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor.

[0322] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the control electrode T82 of the eighth transistor extends along the second direction and can be in a strip shape.

[0323] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the control electrode T32 of the third transistor can be located on the side of the integrally formed structure where the control electrode T82 of the eighth transistor is away from the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor, and a virtual straight line extending along the second direction passes through the control electrode T32 of the third transistor and the control electrode T82 of the eighth transistor.

[0324] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the control electrode T32 of the third transistor extends along the second direction and may be in a strip shape.

[0325] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the control electrode T52 of the fifth transistor can be located on a side of the control electrode T32 of the third transistor away from the control electrode T82 of the eighth transistor, and a virtual straight line extending along the second direction passes through the control electrode T52 of the fifth transistor and the control electrode T32 of the third transistor.

[0326] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the control electrode T52 of the fifth transistor extends along the second direction and can be in a strip shape.

[0327] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the signal output line OUTL may be located on a side of the control electrode T22 of the second transistor away from the first electrode plate C1 of the capacitor, and a virtual straight line extending along the second direction passes through the signal output line OUTL and the control electrode T22 of the second transistor.

[0328] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the signal output line OUTL extends along the second direction and may be in a strip shape.

[0329] In an exemplary embodiment, Figure 14A and Figure 14B As shown, the control electrode T12 of the first transistor is arranged across the active layer of the first transistor, the control electrode T22 of the second transistor is arranged across the active layer of the second transistor, the control electrode T32 of the third transistor is arranged across the active layer of the third transistor, the control electrode T52 of the fifth transistor is arranged across the active layer of the fifth transistor, the control electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor, and the control electrode T82 of the eighth transistor is arranged across the active layer of the eighth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0330] In an exemplary embodiment, this process also includes a conductorization process. After forming the first conductive layer, the semiconductor layer in the control electrode shielding area of ​​multiple transistors (i.e., the area where the semiconductor layer and the control electrode overlap) is used as the channel area of ​​the transistor, and the semiconductor layer in the area not shielded by the first conductive layer is processed into a conductorization layer to form the electrode connection part of the transistor. Figure 14B As shown, the interconnected electrode connection portions of the active layer T71 of the seventh transistor and the active layer T81 of the eighth transistor in the present disclosure are processed into a conductive layer, forming a conductive structure that can be reused as the second electrode of the seventh transistor and the first electrode of the eighth transistor.

[0331] (3) forming a second conductive layer pattern, comprising: depositing a second insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second insulating film and the second conductive film by a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer pattern, such as Figure 15A and Figure 15B As shown, Figure 15A is a schematic diagram of the second conductive layer pattern, Figure 15B Schematic diagram after forming the second conductive layer pattern.

[0332] In an exemplary embodiment, Figure 15A and Figure 15B As shown, the second conductive layer pattern may include: a second plate C2 of the capacitor.

[0333] In an exemplary embodiment, the second conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0334] In an exemplary embodiment, the second insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a second gate insulating layer.

[0335] In an exemplary embodiment, Figure 15A and Figure 15B As shown, the second plate C2 of the capacitor may include: a second capacitor main body C21 and a second capacitor connecting portion C22 connected to each other. The second capacitor connecting portion C22 is located on one side of the second capacitor main body C21.

[0336] In an exemplary embodiment, Figure 15A and Figure 15B As shown, the second plate C2 of the capacitor may be in an L-shape, wherein the second capacitor body C21 may be in a strip shape and extend along the second direction, and the second capacitor connecting portion C22 may be in a strip shape and extend along the first direction.

[0337] In an exemplary embodiment, Figure 15A and Figure 15B As shown, the area of ​​the first capacitor main body C11 of the first electrode plate of the capacitor is larger than the area of ​​the second capacitor main body C21 of the second electrode plate of the capacitor.

[0338] In an exemplary embodiment, Figure 15A and Figure 15B As shown, the orthographic projections of the second capacitor main portion C21 and the second capacitor connecting portion C22 on the substrate at least partially overlap with the orthographic projection of the first capacitor main portion of the first plate of the capacitor on the substrate, and do not overlap with the orthographic projection of the first capacitor connecting portion of the first plate of the capacitor on the substrate.

[0339] (4) forming a second semiconductor layer pattern, comprising: depositing a third insulating film and a second semiconductor film on the substrate formed with the aforementioned pattern, patterning the third insulating film and the second semiconductor film through a patterning process to form a third insulating layer pattern and a second semiconductor layer pattern disposed on the third insulating layer pattern. Figure 16A and Figure 16B As shown, Figure 16A Schematic diagram of the second semiconductor layer pattern Figure 16B Schematic diagram after forming the second semiconductor layer pattern.

[0340] In an exemplary embodiment, Figure 16A and Figure 16B As shown, the second semiconductor layer pattern may include an active layer T41 of the fourth transistor, an active layer T61 of the sixth transistor, an active layer T91 of the ninth transistor, and an active layer T101 of the tenth transistor.

[0341] In one exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0342] In an exemplary embodiment, the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.

[0343] In an exemplary embodiment, Figure 16A and Figure 16B As shown, the active layer T91 of the ninth transistor and the active layer T101 of the tenth transistor are an integrated structure.

[0344] In an exemplary embodiment, Figure 16A and Figure 16B As shown, the active layer T61 of the sixth transistor extends along the first direction and may be a strip-shaped structure. The orthographic projection of the active layer T61 of the sixth transistor on the substrate and the orthographic projection of the active layer T51 of the fifth transistor on the substrate are respectively located on opposite sides of the orthographic projection of the signal output line OUTL on the substrate, and a straight line extending along the first direction passes through the active layer T51 of the fifth transistor and the active layer T61 of the sixth transistor.

[0345] In an exemplary embodiment, an orthographic projection of the active layer T51 of the fifth transistor on the substrate and an orthographic projection of the active layer T61 of the sixth transistor on the substrate may be symmetrically arranged along a virtual straight line extending in the second direction.

[0346] In an exemplary embodiment, Figure 16A and Figure 16B As shown, the active layer T41 of the fourth transistor extends along the first direction and may be a strip-shaped structure. A straight line extending along the first direction passes through the active layer T41 of the fourth transistor and the third active connection portion of the active layer T31 of the third transistor.

[0347] In an exemplary embodiment, an orthographic projection of the active layer T41 of the fourth transistor on the substrate and an orthographic projection of the third active connection portion of the active layer T31 of the third transistor on the substrate may be symmetrically arranged along a virtual straight line extending along the second direction.

[0348] In an exemplary embodiment, Figure 16A and Figure 16B As shown, the active layer T91 of the ninth transistor may be an inverted "L" type, and the active layer T101 of the tenth transistor may be an "n" type. A straight line extending along the first direction passes through the active layer T91 of the ninth transistor and the active layer T81 of the eighth transistor, and a straight line extending along the first direction passes through the active layer T101 of the tenth transistor and the active layer T71 of the seventh transistor.

[0349] In an exemplary embodiment, an orthographic projection of the active layer T91 of the ninth transistor on the substrate and an orthographic projection of the active layer T81 of the eighth transistor on the substrate may be symmetrically arranged along a virtual straight line extending in the second direction.

[0350] (5) forming a third conductive layer pattern, comprising: depositing a fourth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film and the third conductive film by a patterning process to form a fourth insulating layer pattern and a third conductive layer pattern disposed on the fourth insulating layer pattern, such as Figure 17A and Figure 17B As shown, Figure 17A is a schematic diagram of the third conductive layer pattern, Figure 17B Schematic diagram after forming the third conductive layer pattern.

[0351] In an exemplary embodiment, Figure 17A and Figure 17B As shown, the third conductive layer pattern may include: a control electrode T42 of the fourth transistor, a control electrode T62 of the sixth transistor, a control electrode T92 of the ninth transistor, and a control electrode T102 of the tenth transistor.

[0352] In an exemplary embodiment, the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0353] In an exemplary embodiment, the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.

[0354] In an exemplary embodiment, Figure 17A and Figure 17B As shown, the control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor extend along the second direction and may be strip-shaped. The control electrode T42 of the fourth transistor is located on one side of the control electrode T62 of the sixth transistor, and a virtual straight line extending along the second direction passes through the control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor.

[0355] In an exemplary embodiment, Figure 17A and Figure 17BAs shown, the control electrode T92 of the ninth transistor extends along the second direction and may be in a strip shape. The control electrode T92 of the ninth transistor may be located on a side of the control electrode T42 of the fourth transistor away from the control electrode T62 of the sixth transistor, and a virtual straight line extending along the second direction passes through the control electrode T42 of the fourth transistor and the control electrode T92 of the ninth transistor.

[0356] In an exemplary embodiment, Figure 17A and Figure 17B As shown, the control electrode T102 of the tenth transistor may be located on a side of the control electrode T92 of the ninth transistor away from the control electrode T42 of the fourth transistor.

[0357] In an exemplary embodiment, Figure 17A and Figure 17B As shown, the control electrode T102 of the tenth transistor may include a first electrode connection portion T102A, a second electrode connection portion T102B, and a third electrode connection portion T102C. The first electrode connection portion T102A and the third electrode connection portion T102C extend along the second direction, and the second electrode connection portion T102B extends along the first direction and is connected to the first electrode connection portion T102A and the third electrode connection portion T102C, respectively.

[0358] In an exemplary embodiment, Figure 17A and Figure 17B As shown, the first electrode connection portion T102A and the third electrode connection portion T102C are respectively located on two opposite sides of the second electrode connection portion T102B. The first electrode connection portion T102A can be located on a side of the second electrode connection portion T102B close to the control electrode T92 of the ninth transistor, and the third electrode connection portion T102C can be located on a side of the second electrode connection portion T102B away from the control electrode T92 of the ninth transistor.

[0359] In an exemplary embodiment, Figure 17A and Figure 17B As shown, a virtual straight line extending along the second direction passes through the orthographic projection of the first electrode connection portion T102A of the control electrode T102 of the tenth transistor and the orthographic projection of the first capacitor body portion of the first plate of the capacitor on the substrate. The orthographic projection of the third electrode connection portion T102C of the control electrode T102 of the tenth transistor on the substrate is located on a side of the orthographic projection of the first plate of the capacitor on the substrate that is away from the orthographic projection of the integrated structure of the control electrodes of the first transistor and the seventh transistor on the substrate.

[0360] In an exemplary embodiment, Figure 17A and Figure 17BAs shown, the control electrode T42 of the fourth transistor is arranged across the active layer T41 of the fourth transistor, the control electrode T62 of the sixth transistor is arranged across the active layer T61 of the sixth transistor, the control electrode T92 of the ninth transistor is arranged across the active layer T91 of the ninth transistor, and the control electrode T102 of the tenth transistor is arranged across the active layer T101 of the tenth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0361] In an exemplary embodiment, this process also includes a conductorization process. After forming the third conductive layer, the second semiconductor layer in the control electrode shielding area of ​​multiple transistors (i.e., the area where the semiconductor layer and the control electrode overlap) is used as the channel area of ​​the transistor, and the semiconductor layer in the area not shielded by the third conductive layer is processed into a conductorization layer to form the electrode connection part of the transistor. Figure 17B As shown, the interconnected electrode connection portions of the active layer T91 of the ninth transistor and the active layer T101 of the tenth transistor in the present disclosure are processed into a conductive layer, forming a conductive structure that can be reused as the second electrode of the ninth transistor and the second electrode of the tenth transistor.

[0362] (6) forming a fifth insulating layer pattern, comprising: depositing a third insulating film on the substrate having the aforementioned pattern, patterning the fifth insulating film through a patterning process to form a fifth insulating layer pattern covering the aforementioned structure, wherein the fifth insulating layer is provided with a plurality of via patterns, such as Figure 18 As shown, Figure 18 is a schematic diagram after forming the fifth insulation layer pattern.

[0363] In an exemplary embodiment, Figure 18 As shown, the multiple via patterns may include: first vias V1 to sixth vias V6 opened in the first insulating layer, the second insulating layer and the fifth insulating layer, seventh vias V7 to thirteenth vias V13 opened in the second insulating layer to the fifth insulating layer, fourteenth vias V14 opened in the third insulating layer to the fifth insulating layer, fifteenth vias V15 to eighteenth vias V18 opened in the fourth insulating layer to the fifth insulating layer, and nineteenth vias V19 to twenty-second vias V22 opened in the fifth insulating layer.

[0364] In an exemplary embodiment, the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer may be referred to as a second gate insulating layer.

[0365] like Figure 18As shown, the first via hole V1 exposes the active layer T11 of the first transistor, the second via hole V2 exposes the active layer T21 of the second transistor, the third via hole V3 exposes the active layer T31 of the third transistor, the fourth via hole V4 exposes the active layer T51 of the fifth transistor, the fifth via hole V5 exposes the active layer T71 of the seventh transistor, the sixth via hole V6 exposes the active layer T81 of the eighth transistor, the seventh via hole V7 exposes the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor, the eighth via hole V8 exposes the control electrode T22 of the second transistor, the ninth via hole V9 exposes the control electrode T32 of the third transistor, the tenth via hole V10 exposes the control electrode T52 of the fifth transistor, and the eleventh via hole V11 exposes the control electrode T72 of the eighth transistor. The twelfth via hole V12 exposes the first plate C1 of the capacitor, the thirteenth via hole V13 exposes the signal output line OUTL, and the fourteenth via hole V14 exposes the second plate C2 of the capacitor; the fifteenth via hole V15 exposes the active layer T41 of the fourth transistor, the sixteenth via hole V16 exposes the active layer T61 of the sixth transistor, the seventeenth via hole V17 exposes the active layer T91 of the ninth transistor, the eighteenth via hole V18 exposes the active layer T101 of the tenth transistor, the nineteenth via hole V19 exposes the control electrode T42 of the fourth transistor, the twentieth via hole V20 exposes the control electrode T62 of the sixth transistor, the twenty-first via hole V21 exposes the control electrode T92 of the ninth transistor, and the twenty-second via hole V22 exposes the control electrode T102 of the tenth transistor.

[0366] In an exemplary embodiment, Figure 18 As shown, the number of third vias V3 is four, a virtual straight line extending along the first direction passes through the first third via and the second third via, and the first third via and the second third via expose the first active connection portion of the active layer T31 of the third transistor, a virtual straight line extending along the first direction passes through the third third via and the fourth third via, and the third third via and the fourth third via expose the third active connection portion of the active layer T31 of the third transistor, and a virtual straight line extending along the second direction passes through the second third via and the third third via.

[0367] In an exemplary embodiment, Figure 18 As shown, there are multiple fourth via holes V4, and the multiple fourth via holes V4 are arranged in an array.

[0368] In an exemplary embodiment, Figure 18 As shown, there may be a plurality of thirteenth via holes V13 , and the plurality of thirteenth via holes V13 are arranged along the second direction.

[0369] In an exemplary embodiment, Figure 18As shown, there are multiple sixteenth via holes V16 , and the multiple sixteenth via holes V16 are arranged in an array.

[0370] In an exemplary embodiment, Figure 18 As shown, the number of the twenty-second via holes V22 may be two, the first twenty-second via hole exposes the second electrode connection portion of the control electrode T102 of the tenth transistor, and the second twenty-second via hole exposes the third electrode connection portion of the control electrode T102 of the tenth transistor.

[0371] (7) forming a fourth conductive layer pattern, comprising: depositing a fourth metal film on the substrate on which the aforementioned pattern is formed, and patterning the fourth metal film through a patterning process to form a fourth metal layer pattern, such as Figure 19A and Figure 19B As shown, Figure 19A is a schematic diagram of the fourth conductive layer pattern, Figure 19B Schematic diagram after forming the fourth conductive layer pattern.

[0372] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the fourth conductive layer pattern may include: a first clock signal line CLK1, a second clock signal line CLK2, a first power line VHL, a second power line VLL, a first electrode T13 and a second electrode T14 of the first transistor to a first electrode T63 and a second electrode T64 of the sixth transistor, a first electrode T73 of the seventh transistor, a second electrode T84 of the eighth transistor, a first electrode T93 of the ninth transistor, a first electrode T103 of the tenth transistor, a first connection signal line L1, a second connection signal line L2 and a third connection signal line L3.

[0373] In an exemplary embodiment, the fourth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0374] In an exemplary embodiment, Figure 19A and Figure 19BAs shown, the first electrode T33 of the third transistor, the first electrode T53 of the fifth transistor, the first electrode T73 of the seventh transistor and the first power line VHL are an integrated structure, the first electrode T43 of the fourth transistor, the first electrode T63 of the sixth transistor, the first electrode T103 of the tenth transistor and the second power line VLL are an integrated structure, the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are an integrated structure, the second electrode T34 of the third transistor and the second electrode T44 of the fourth transistor are an integrated structure, the second electrode T24 of the second transistor, the second electrode T84 of the eighth transistor and the first electrode T93 of the ninth transistor are an integrated structure, and the second electrode T54 of the fifth transistor and the second electrode T64 of the sixth transistor are an integrated structure.

[0375] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the first power line VHL is located on a side of the integrally formed structure of the second electrode T54 of the fifth transistor and the second electrode T64 of the sixth transistor away from the second power line VLL, the second power line VLL is located on a side of the integrally formed structure of the second electrode T14 of the first transistor and the first electrode T23 of the second transistor away from the first power line VHL, the first clock signal line CLK1 is located on a side of the second power line VLL away from the first power line VHL, and the second clock signal line CLK2 is located on a side of the first clock signal line CLK1 away from the second power line VLL.

[0376] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the first power line VHL extends along the first direction and may be in a strip shape. The orthographic projection of the first power line VHL on the substrate at least partially overlaps with the orthographic projection of the signal output line OUTL on the substrate.

[0377] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the first electrode T33 of the third transistor, the first electrode T53 of the fifth transistor, and the first electrode T73 of the seventh transistor extend along the second direction, and the first electrode T33 of the third transistor, the first electrode T53 of the fifth transistor, and the first electrode T73 of the seventh transistor are located on a side of the first power line VHL close to the second power line VLL.

[0378] In an exemplary embodiment, Figure 19A and Figure 19BAs shown, the second power line VLL extends along the first direction and can be strip-shaped. The orthographic projection of the second power line VLL on the substrate partially overlaps with the orthographic projections on the substrate of the integrally formed structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor, the control electrode of the tenth transistor, and the second capacitor connection portion of the second plate C2 of the capacitor.

[0379] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the first electrode T43 of the fourth transistor, the first electrode T63 of the sixth transistor, and the first electrode T103 of the tenth transistor extend along the second direction, and the first electrode T43 of the fourth transistor, the first electrode T63 of the sixth transistor, and the first electrode T103 of the tenth transistor are located on a side of the second power line VLL close to the first power line VHL.

[0380] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the first clock signal line CLK1 extends along a first direction and can be in a strip shape. The orthographic projection of the first clock signal line CLK1 on the substrate partially overlaps with the orthographic projection of the control electrode T102 of the tenth transistor and the integrally formed structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor on the substrate.

[0381] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the second clock signal line CLK2 extends along the first direction and can be in a strip shape. The second clock signal line CLK2 partially overlaps with the orthographic projection of the control electrode T102 of the tenth transistor or the integrally formed structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor on the substrate. When the second clock signal terminal in the shift register is electrically connected to the second clock signal line, the orthographic projection of the second clock signal line CLK2 on the substrate partially overlaps with the orthographic projection of the control electrode T102 of the tenth transistor on the substrate. When the first clock signal terminal in the shift register is electrically connected to the second clock signal line, the orthographic projection of the second clock signal line CLK2 on the substrate partially overlaps with the orthographic projection of the integrally formed structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor on the substrate. Figure 19A and Figure 19B The description is made by taking an example where the orthographic projection of the second clock signal line CLK2 on the substrate partially overlaps with the orthographic projection of the control electrode T102 of the tenth transistor on the substrate.

[0382] In an exemplary embodiment, Figure 19A and Figure 19BAs shown, the integrally formed structure of the second electrode T14 of the first transistor and the first electrode T23 of the second transistor can be "L"-shaped, and the orthographic projection of the integrally formed structure of the second electrode T14 of the first transistor and the first electrode T23 of the second transistor on the substrate partially overlaps with the orthographic projection of the first capacitor connecting portion of the first electrode plate of the capacitor on the substrate.

[0383] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the integrally formed structure of the second electrode T34 of the third transistor and the second electrode T44 of the fourth transistor can be an "I" shape rotated 90 degrees, and the orthographic projection of the integrally formed structure of the second electrode T34 of the third transistor and the second electrode T44 of the fourth transistor on the substrate partially overlaps with the orthographic projection of the control electrode T62 of the sixth transistor and the control electrode T52 of the fifth transistor on the substrate.

[0384] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the integrated structure of the second electrode T54 of the fifth transistor and the second electrode T64 of the sixth transistor extends along the first direction and can be in a strip shape. The orthographic projection of the integrated structure of the second electrode T54 of the fifth transistor and the second electrode T64 of the sixth transistor on the substrate partially overlaps with the orthographic projection of the signal output line OUTL on the substrate.

[0385] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the integrally formed structure of the second electrode T24 of the second transistor, the second electrode T84 of the eighth transistor, and the first electrode T93 of the ninth transistor can be a "earth" shape rotated 90 degrees, and the orthographic projection of the second electrode T24 of the second transistor, the second electrode T84 of the eighth transistor, and the first electrode T93 of the ninth transistor on the substrate partially overlaps with the orthographic projection of the control electrode T32 of the third transistor and the control electrode T42 of the fourth transistor on the substrate.

[0386] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the first connection signal line L1 extends along the first direction and can be in a strip shape. The orthographic projection of the first connection signal line L1 on the substrate partially overlaps with the orthographic projection of the control electrode T92 of the ninth transistor on the substrate.

[0387] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the second connection signal line L2 extends along the first direction and can be in a strip shape. The orthographic projection of the second connection signal line L2 on the substrate partially overlaps with the orthographic projection of the control electrode T82 of the eighth transistor on the substrate.

[0388] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the third connection signal line L3 extends along the first direction and can be strip-shaped. The orthographic projection of the third connection signal line L3 on the substrate partially overlaps with the orthographic projections of the control electrode T22 of the second transistor and the control electrode T102 of the tenth transistor on the substrate.

[0389] In an exemplary embodiment, Figure 19A and Figure 19BAs shown, the first electrode T13 and the second electrode T14 of the first transistor are connected to the active layer of the first transistor through the first via hole, the first electrode T23 and the second electrode T24 of the second transistor are connected to the active layer of the second transistor through the second via hole, the first electrode T33 and the second electrode T34 of the third transistor are connected to the active layer of the third transistor through the third third via hole and the fourth third via hole respectively, the first electrode T43 and the second electrode T44 of the fourth transistor are connected to the active layer of the fourth transistor exposed through the fifteenth via hole, the first electrode T53 and the second electrode T54 of the fifth transistor are connected to the active layer of the fourth transistor exposed through the fifteenth via hole, and the first electrode T53 and the second electrode T54 of the fifth transistor are connected to the active layer of the third transistor exposed through the fifteenth via hole. The second electrode T55 is connected to the active layer of the fifth transistor via a fourth via. The first electrode T63 and the second electrode T65 of the sixth transistor are connected to the active layer of the sixth transistor via a sixteenth via. The first electrode T73 of the seventh transistor is connected to the active layer of the seventh transistor via a fifth via. The second electrode T84 of the eighth transistor is connected to the active layer of the eighth transistor via a sixth via. The first electrode T93 of the ninth transistor is connected to the active layer of the ninth transistor via a seventeenth via. The first electrode T103 of the tenth transistor is connected to the active layer of the tenth transistor via an eighteenth via. The integrated structure of the second electrode T14 of the first transistor and the first electrode T23 of the second transistor is connected to the first electrode plate C1 of the capacitor via a twelfth via. The integrated structure of the second electrode T34 of the third transistor and the second electrode T44 of the fourth transistor is connected to the control electrode T62 of the sixth transistor via a twentieth via and to the control electrode T52 of the fifth transistor via a tenth via. The second electrode T24 of the second transistor, the second electrode T84 of the eighth transistor, and the first electrode T93 of the ninth transistor are integrally formed and connected to the control electrode T42 of the fourth transistor through the nineteenth via, and to the control electrode T32 of the third transistor through the ninth via. The second electrode T54 of the fifth transistor and the second electrode T64 of the sixth transistor are integrally formed and connected to the signal output line OUTL through the thirteenth via. The first connecting signal line L1 is connected to the active layer of the third transistor through the first third via and to the control electrode T92 of the ninth transistor through the twenty-first via. The second connecting signal line L2 is connected to the active layer of the third transistor through the second third via and to the control electrode T82 of the eighth transistor through the eleventh via V11. The third connecting signal line L3 is connected to the control electrode T102 of the tenth transistor through the first twenty-second via and to the control electrode T22 of the second transistor through the eighth via. One of the first and second clock signal lines CLK2 is connected to the integrated structure of the control electrode T12 of the first transistor and the control electrode T72 of the seventh transistor via a seventh via. The other of the first and second clock signal lines CLK2 is connected to the control electrode T102 of the tenth transistor via a second twenty-second via. The second power line VLL is connected to the second plate C2 of the capacitor via a fourteenth via.

[0390] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the control electrode T92 of the ninth transistor is connected to the integrated structure of the second electrode of the third transistor and the second electrode of the fourth transistor through the first connecting signal line L1 and the active layer of the third transistor.

[0391] In an exemplary embodiment, Figure 19A and Figure 19B As shown, the control electrode T82 of the eighth transistor is connected to the integrated structure of the second electrode of the third transistor and the second electrode of the fourth transistor through the second connection signal line L2 and the active layer of the third transistor.

[0392] An embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0393] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0394] In an exemplary embodiment, the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device may be any product or component with a display function, such as an LCD panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0395] The present disclosure also provides a shift register driving method, which is configured to drive a shift register. The method includes the following steps:

[0396] Step 100: The storage subcircuit stores a voltage difference between a signal at a first node and a signal at a first power supply terminal;

[0397] Step 200: The node control subcircuit provides a signal from the signal input terminal to the first node under the control of the first clock signal terminal, and provides a signal from the first node to the second node under the control of the second clock signal terminal.

[0398] Step 300: The output control subcircuit provides a signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the second node.

[0399] The shift register is the shift register provided by any of the aforementioned embodiments, and its implementation principle and effect are similar, which will not be described in detail here.

[0400] The drawings of the embodiments of the present invention only relate to the structures involved in the embodiments of the present invention, and other structures may refer to general designs.

[0401] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present invention. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0402] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A shift register comprising: a storage subcircuit, a node control subcircuit, and an output control subcircuit; The storage sub-circuit is electrically connected to the first node and the first power supply terminal, respectively, and is configured to store a voltage difference between a signal at the first node and a signal at the first power supply terminal; The node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node, and the second node, respectively, and is configured to provide the signal of the signal input terminal to the first node under the control of the first clock signal terminal, and provide the signal of the first node to the second node under the control of the second clock signal terminal; The output control subcircuit is electrically connected to the second node, the first power supply terminal, the second power supply terminal and the signal output terminal respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the second node.

2. The shift register according to claim 1, wherein: The output control subcircuit includes: a first output control subcircuit and a second output control subcircuit; The first output control subcircuit is electrically connected to the second node, the third node, the first power supply terminal, and the second power supply terminal, respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the third node under the control of the second node; The second output control subcircuit is electrically connected to the third node, the first power supply terminal, the second power supply terminal and the signal output terminal respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the third node.

3. The shift register according to claim 1 or 2, further comprising: noise reduction sub-circuit; The noise reduction sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the second node and the third node, respectively, and is configured to provide the signal of the first power supply terminal or the second power supply terminal to the second node under the control of the first clock signal terminal, the second clock signal terminal and the third node.

4. The shift register according to claim 1, wherein: The storage sub-circuit includes: a capacitor, the capacitor includes: a first plate and a second plate; The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

5. The shift register according to claim 1, wherein: The node control subcircuit includes: a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node. The shift register according to claim 2 , wherein: The first output control subcircuit includes: a third transistor and a fourth transistor, and the second output control subcircuit includes: a fifth transistor and a sixth transistor; A control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first power supply terminal, and a second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the third node; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal; The control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal; The third transistor and the fourth transistor are of opposite transistor types, and the fifth transistor and the sixth transistor are of opposite transistor types.

7. The shift register according to claim 3, wherein: The noise reduction sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; A control electrode of the seventh transistor is electrically connected to the first clock signal terminal, a first electrode of the seventh transistor is electrically connected to the first power supply terminal, and a second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; The control electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second node; a control electrode of the ninth transistor electrically connected to the third node, a first electrode of the ninth transistor electrically connected to the second node, and a second electrode of the ninth transistor electrically connected to the second electrode of the tenth transistor; The control electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the first electrode of the tenth transistor is electrically connected to the second power supply terminal; The seventh transistor and the eighth transistor are of the same transistor type, the ninth transistor and the tenth transistor are of the same transistor type, and the seventh transistor and the ninth transistor are of opposite transistor types.

8. The shift register according to claim 1, wherein: The storage subcircuit includes: a capacitor, the capacitor includes: a first plate and a second plate; the node control subcircuit includes: a first transistor and a second transistor; the output control subcircuit includes: a third transistor, a fourth transistor, a fifth transistor and a sixth transistor The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node; A control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first power supply terminal, and a second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the third node; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal; The control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal; The first transistor, the second transistor, the third transistor, and the fifth transistor are P-type transistors, and the fourth transistor and the sixth transistor are N-type transistors and oxide transistors.

9. The shift register according to claim 1 , further comprising: The noise reduction subcircuit includes a storage subcircuit comprising a capacitor, the capacitor comprising a first plate and a second plate; the node control subcircuit comprising a first transistor and a second transistor; the output control subcircuit comprising a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; and the noise reduction subcircuit comprising a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the second clock signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node; A control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first power supply terminal, and a second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the third node; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the signal output terminal; The control electrode of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the signal output terminal; A control electrode of the seventh transistor is electrically connected to the first clock signal terminal, a first electrode of the seventh transistor is electrically connected to the first power supply terminal, and a second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; The control electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second node; a control electrode of the ninth transistor electrically connected to the third node, a first electrode of the ninth transistor electrically connected to the second node, and a second electrode of the ninth transistor electrically connected to the second electrode of the tenth transistor; The control electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the first electrode of the tenth transistor is electrically connected to the second power supply terminal; The first transistor, the second transistor, the third transistor, the fifth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the fourth transistor, the sixth transistor, the ninth transistor, and the tenth transistor are N-type transistors and are oxide transistors.

10. The shift register according to claim 1, wherein: The clock signal at the first clock signal end and the clock signal at the second clock signal end are inverted signals to each other; The signal at the signal input end is a first pulse signal, the duration of the first pulse signal is equal to the period of the clock signal at the first clock signal end, The signal at the signal output end is a second pulse signal, the duration of the second pulse signal is equal to the duration of the first pulse signal, and the start time of the second pulse signal is the end time of the first pulse signal.

11. The shift register according to claim 1, wherein: The clock signal at the first clock signal end and the clock signal at the second clock signal end are inverted signals to each other; The signal at the signal input end is a third pulse signal, the duration of the third pulse signal is equal to N times the period of the clock signal at the first clock signal end, where N is a positive integer greater than or equal to 2; The signal at the signal output end is a fourth pulse signal, the duration of the fourth pulse signal is equal to the duration of the third pulse signal, and the difference between the start time of the fourth pulse signal and the start time of the third pulse signal is equal to the period of the clock signal at the first clock signal end.

12. A display substrate, comprising: The display substrate comprises a display area and a non-display area, the display substrate comprising: a base and a circuit structure layer provided on the base, the circuit structure layer comprising: a gate drive circuit located in the non-display area and an array-arranged pixel circuit located in the display area, the gate drive circuit comprising: a plurality of cascaded shift registers according to any one of claims 1 to 11, the pixel circuit comprising: a light emitting signal line, a scanning signal line, and a reset signal line; The signal output terminal of the i-th stage shift register is electrically connected to the signal input terminal of the i+1-th stage shift register, 1≤i≤M-1, where M is the total number of stages of the shift register; The gate driving circuit is electrically connected to at least one of a light emitting signal line, a scanning signal line, and a reset signal line.

13. The display substrate according to claim 12, further comprising: A first clock signal line, a second clock signal line, a first power line, and a second power line extending along a first direction, the first power line, the second power line, the first clock signal line, and the second clock signal line being arranged along a second direction, the first direction intersecting the second direction; The first power supply terminals of all shift registers are electrically connected to the first power supply line, the second power supply terminals of all shift registers are electrically connected to the second power supply line, the first clock signal terminal of the i-th stage shift register is electrically connected to the first clock signal line, the second clock signal terminal of the i-th stage shift register is electrically connected to the second clock signal line, the first clock signal terminal of the i+1-th stage shift register is electrically connected to the second clock signal line, and the second clock signal terminal of the i+1-th stage shift register is electrically connected to the first clock signal line.

14. The display substrate according to claim 13, wherein: The shift register includes: first to tenth transistors and a capacitor, the capacitor includes: a first plate and a second plate; the circuit structure layer includes: a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer and a fourth conductive layer stacked sequentially on a substrate; The first semiconductor layer includes: an active layer of a first transistor, an active layer of a second transistor, an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a seventh transistor, and an active layer of an eighth transistor; The first conductive layer includes: a control electrode of a first transistor, a control electrode of a second transistor, a control electrode of a third transistor, a control electrode of a fifth transistor, a control electrode of a seventh transistor, a control electrode of an eighth transistor, a first plate of a capacitor, and a signal output line; The second conductive layer includes: a second plate of a capacitor; The second semiconductor layer includes: an active layer of a fourth transistor, an active layer of a sixth transistor, an active layer of a ninth transistor, and an active layer of a tenth transistor; The third conductive layer includes: a control electrode of the fourth transistor, a control electrode of the sixth transistor, a control electrode of the ninth transistor, and a control electrode of the tenth transistor; The fourth conductive layer includes: a first clock signal line, a second clock signal line, a first power line, a second power line, a first electrode and a second electrode of the first transistor to a first electrode and a second electrode of the sixth transistor, a first electrode of the seventh transistor, a second electrode of the eighth transistor, a first electrode of the ninth transistor, a first electrode of the tenth transistor, a first connection signal line, a second connection signal line, and a third connection signal line; The signal output line is connected to the second electrode of the fifth transistor and the second electrode of the sixth transistor respectively; The first connection signal line is connected to the active layer of the third transistor and the control electrode of the ninth transistor respectively; The second connection signal line is connected to the active layer of the third transistor and the control electrode of the eighth transistor respectively; The third connection signal line is connected to the control electrode of the tenth transistor and the control electrode of the second transistor respectively.

15. The display substrate according to claim 14, wherein: The fifth transistor and the sixth transistor are located on the same side of the first power line, and the fifth transistor and the sixth transistor are arranged along the first direction; The third transistor is located on a side of the fifth transistor away from the first power line, the fourth transistor is located on a side of the sixth transistor away from the first power line, the third transistor and the fourth transistor are arranged along the first direction, the third transistor and the fifth transistor are arranged along the second direction, and the fourth transistor and the sixth transistor are arranged along the second direction; The eighth transistor is located on a side of the third transistor away from the fifth transistor, the ninth transistor is located on a side of the fourth transistor away from the sixth transistor, the eighth transistor and the ninth transistor are arranged along the first direction, the third transistor and the eighth transistor are arranged along the second direction, and the fourth transistor and the ninth transistor are arranged along the second direction; The seventh transistor is located on a side of the eighth transistor away from the third transistor, the tenth transistor is located on a side of the ninth transistor away from the fourth transistor, the seventh transistor and the tenth transistor are arranged along the first direction, the seventh transistor and the eighth transistor are arranged along the second direction, and the ninth transistor and the tenth transistor are arranged along the second direction; The second transistor is located between the seventh transistor and the tenth transistor, the first transistor is located on a side of the seventh transistor away from the eighth transistor, and the capacitor is located on a side of the tenth transistor away from the ninth transistor; The second power line is located on a side of the capacitor away from the tenth transistor, the first clock signal line is located on a side of the second power line away from the capacitor, and the second clock signal line is located on a side of the first clock signal line away from the second power line.

16. The display substrate according to claim 14 or 15, wherein: The active layer of the first transistor and the active layer of the second transistor are an integrally formed structure, and the active layer of the seventh transistor and the active layer of the eighth transistor are an integrally formed structure; The active layer of the third transistor includes a first active connection portion, a second active connection portion, and a third active connection portion; the first active connection portion and the third active connection portion extend along a first direction, and the second active connection portion extends along a second direction and is connected to the first active connection portion and the third active connection portion, respectively; The first active connection portion is located on a side of the second active connection portion close to the integrally formed structure of the active layer of the seventh transistor and the active layer of the eighth transistor, and the third active connection portion is located on a side of the second active connection portion away from the integrally formed structure of the active layer of the seventh transistor and the active layer of the eighth transistor; A straight line extending along the second direction passes through the first active connection portion and the active layer of the second transistor; A straight line extending along the second direction passes through the third active connection and the active layer of the first transistor.

17. The display substrate according to claim 16, wherein: The first plate of the capacitor includes: a first capacitor main body and a first capacitor connecting portion connected to each other; The control electrode of the first transistor and the control electrode of the seventh transistor are integrally formed and are located on a side of the first capacitor connecting portion away from the first capacitor main portion; A virtual straight line extending along the second direction passes through the control electrode of the eighth transistor and the integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor; A virtual straight line extending along the second direction passes through the control electrode of the third transistor and the control electrode of the eighth transistor; A virtual straight line extending along the second direction passes through the control electrode of the fifth transistor and the control electrode of the third transistor; A virtual straight line extending along the second direction passes through the signal output line and the control electrode of the second transistor.

18. The display substrate according to claim 17, wherein: The second electrode plate of the capacitor includes: a second capacitor main body portion and a second capacitor connecting portion connected to each other, the second capacitor connecting portion being located on one side of the second capacitor main body portion; The area of ​​the first capacitor body portion of the first electrode plate of the capacitor is greater than the area of ​​the second capacitor body portion of the second electrode plate of the capacitor; The orthographic projections of the second capacitor main body and the second capacitor connecting portion on the substrate at least partially overlap with the orthographic projection of the first capacitor main body of the first plate of the capacitor on the substrate, and do not overlap with the orthographic projection of the first capacitor connecting portion of the first plate of the capacitor on the substrate.

19. The display substrate according to claim 18, wherein: An orthographic projection of the active layer of the sixth transistor on the substrate and an orthographic projection of the active layer of the fifth transistor on the substrate are respectively located on opposite sides of an orthographic projection of the signal output line on the substrate, and a straight line extending along the first direction passes through the active layer of the fifth transistor and the active layer of the sixth transistor; a straight line extending along the first direction passing through the active layer of the fourth transistor and the third active connection portion of the active layer of the third transistor; A straight line extending along the first direction passes through the active layer of the ninth transistor and the active layer of the eighth transistor, and a straight line extending along the first direction passes through the active layer of the tenth transistor and the active layer of the seventh transistor.

20. The display substrate according to claim 18 or 19, wherein: A virtual straight line extending along the second direction passes through the control electrode of the fourth transistor, the control electrode of the sixth transistor, and the control electrode of the ninth transistor; The control electrode of the tenth transistor includes: a first electrode connection portion, a second electrode connection portion, and a third electrode connection portion, wherein the first electrode connection portion and the third electrode connection portion extend along the second direction, and the second electrode connection portion extends along the first direction and is connected to the first electrode connection portion and the third electrode connection portion, respectively; The first electrode connection portion is located on a side of the second electrode connection portion close to the control electrode of the ninth transistor, and the third electrode connection portion is located on a side of the second electrode connection portion away from the control electrode of the ninth transistor; A virtual straight line extending along the second direction passes through an orthographic projection of the first electrode connection portion of the control electrode of the tenth transistor on the substrate and an orthographic projection of the first capacitor body portion of the first plate of the capacitor on the substrate; The orthographic projection of the third electrode connection portion of the control electrode of the tenth transistor on the substrate is located on a side of the orthographic projection of the first plate of the capacitor on the substrate away from the orthographic projection of the integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor on the substrate.

21. The display substrate according to claim 20, wherein: The fifth insulating layer is provided with a plurality of via patterns, the plurality of via patterns including: a first via to a sixth via provided in the first insulating layer, the second insulating layer, and the fifth insulating layer, a seventh via to a thirteenth via provided in the second insulating layer to the fifth insulating layer, a fourteenth via provided in the third insulating layer to the fifth insulating layer, a fifteenth via to an eighteenth via provided in the fourth insulating layer to the fifth insulating layer, and a nineteenth via to a twenty-second via provided in the fifth insulating layer; The third via hole exposes the active layer of the third transistor, and the twenty-second via hole exposes the control electrode of the tenth transistor; There are four third vias, a virtual straight line extending along the first direction passes through a first third via and a second third via, and the first third via and the second third via expose the first active connection portion of the active layer of the third transistor, a virtual straight line extending along the first direction passes through a third third via and a fourth third via, and the third third via and the fourth third via expose the third active connection portion of the active layer of the third transistor, and a virtual straight line extending along the second direction passes through the second third via and the third third via; There are two twenty-second via holes. The first twenty-second via hole exposes the second electrode connection portion of the control electrode of the tenth transistor, and the second twenty-second via hole exposes the third electrode connection portion of the control electrode of the tenth transistor.

22. The display substrate according to claim 21, wherein The first electrode of the third transistor, the first electrode of the fifth transistor, the first electrode of the seventh transistor, and the first power line are integrally formed, the first electrode of the fourth transistor, the first electrode of the sixth transistor, the first electrode of the tenth transistor and the second power line are integrally formed, the second electrode of the first transistor and the first electrode of the second transistor are integrally formed, the second electrode of the third transistor and the second electrode of the fourth transistor are integrally formed, the second electrode of the second transistor, the second electrode of the eighth transistor, and the first electrode of the ninth transistor are integrally formed, and the second electrode of the fifth transistor and the second electrode of the sixth transistor are integrally formed; The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the signal output line on the substrate; The orthographic projection of the second power line on the substrate partially overlaps with the integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor, the control electrode of the tenth transistor, and the orthographic projection of the second capacitor connecting portion of the second electrode plate of the capacitor on the substrate; An orthographic projection of the first clock signal line on the substrate partially overlaps with an orthographic projection of the control electrode of the tenth transistor and an integrally formed structure of the control electrode of the first transistor and the control electrode of the seventh transistor on the substrate; The second clock signal line overlaps with the orthographic projection of the control electrode of the connected transistor on the substrate; An orthographic projection of the integrally formed structure of the second electrode of the first transistor and the first electrode of the second transistor on the substrate partially overlaps with an orthographic projection of the first capacitor connecting portion of the first electrode plate of the capacitor on the substrate; The orthographic projections of the integrated structure of the second electrode of the third transistor and the second electrode of the fourth transistor on the substrate partially overlap with the orthographic projections of the control electrode of the sixth transistor and the control electrode of the fifth transistor on the substrate; The orthographic projection of the integrally formed structure of the second electrode of the fifth transistor and the second electrode of the sixth transistor on the substrate partially overlaps with the orthographic projection of the signal output line on the substrate; The orthographic projection of the integrated structure of the second electrode of the second transistor, the second electrode of the eighth transistor, and the first electrode of the ninth transistor on the substrate partially overlaps with the orthographic projection of the control electrode of the third transistor and the control electrode of the fourth transistor on the substrate; An orthographic projection of the first connection signal line on the substrate partially overlaps with an orthographic projection of the control electrode of the ninth transistor on the substrate; An orthographic projection of the second connection signal line on the substrate partially overlaps with an orthographic projection of the control electrode of the eighth transistor on the substrate; An orthographic projection of the third connection signal line on the substrate partially overlaps with an orthographic projection of the control electrode of the second transistor and the control electrode of the tenth transistor on the substrate.

23. The display substrate according to claim 22, wherein: The first electrode and the second electrode of the third transistor are connected to the active layer of the third transistor through a third third via hole and a fourth third via hole respectively; The first connecting signal line is connected to the active layer of the third transistor through the first third via hole; The second connecting signal line is connected to the active layer of the third transistor through the second third via hole; The third connection signal line is connected to the control electrode of the tenth transistor through the first twenty-second via hole; One of the first clock signal line and the second clock signal line is connected to the control electrode of the tenth transistor through a second twenty-second via hole.

24. A display device comprising: The display substrate according to any one of claims 12 to 23.

25. A method for driving a shift register, configured to drive the shift register according to any one of claims 1 to 11, the method comprising: The storage subcircuit stores a voltage difference between a signal at the first node and a signal at the first power supply terminal; The node control subcircuit provides the signal of the signal input terminal to the first node under the control of the first clock signal terminal, and provides the signal of the first node to the second node under the control of the second clock signal terminal; The output control subcircuit provides the signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the second node.

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