Array substrate, display panel and display device

Abstract

The present disclosure provides an array substrate, a display panel and a display device, and relates to the technical field of display, and is used for improving the resolution of the display panel. The array substrate comprises a pixel circuit, a data line, a multiplexing circuit, an input signal line, an output signal line group, a first gate line and a second gate line group. One data line is connected with one column of pixel circuits. A plurality of multiplexing circuits are arranged into a plurality of columns along a first direction, and one column comprises a plurality of multiplexing circuits arranged along a second direction. One input signal line is connected with one multiplexing circuit. One output signal line group comprises a plurality of output signal lines, the plurality of output signal lines are connected with the same multiplexing circuit, and one output signal line is connected with one data line. One second gate line group comprises a plurality of second gate lines, one second gate line is connected with one first gate line, and the plurality of second gate lines of one second gate line group are connected with the plurality of multiplexing circuits of one column. The array substrate is used for preparing the display device.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, the requirements for display devices are becoming increasingly stringent. Among these requirements, high pixel density and narrow bezels are important development directions for display devices. How to improve the pixel density and reduce the bezel width of display devices is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] The purpose of the embodiments of this disclosure is to provide an array substrate, a display panel, and a display device for increasing the pixel density of the display panel and reducing the bezel width of the display panel.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, an array substrate is provided. The array substrate includes a substrate, multiple rows of pixel circuits, multiple data lines, multiple multiplexed circuits, multiple input signal lines, multiple output signal line groups, multiple first gate lines, and multiple second gate line groups. The substrate includes a display area and a fan-out area adjacent to the display area. The multiple rows of pixel circuits are disposed in the display area, arranged along a first direction, and each row of pixel circuits includes multiple pixel circuits arranged along a second direction, the first direction intersecting the second direction. The multiple data lines are at least partially disposed in the display area and arranged at intervals along the first direction, each extending along the second direction, with one data line connected to one row of pixel circuits. The multiple multiplexed circuits are disposed in the fan-out area, arranged in multiple columns along the first direction, each column including multiple multiplexed circuits arranged along the second direction. The multiple input signal lines are disposed in the fan-out area, located on the side of the multiple multiplexed circuits away from the display area, with one input signal line connected to one multiplexed circuit. The plurality of output signal line groups are disposed in the fan-out area and located on the side of the plurality of multiplexing circuits closest to the display area. Each output signal line group includes multiple output signal lines. The multiple output signal lines included in one output signal line group are connected to the same multiplexing circuit, and each output signal line is connected to a data line. The plurality of first gate lines are disposed in the fan-out area and located on the side of the plurality of multiplexing circuits furthest from the display area. A second gate line group includes multiple second gate lines, and each second gate line is connected to a first gate line. The multiple second gate lines included in a second gate line group are connected to a column of the plurality of multiplexing circuits.

[0006] The array substrate provided in the embodiments of this disclosure includes a plurality of multiplexed circuits disposed in a fan-out region, arranged in multiple columns along a first direction. A column of multiplexed circuits includes multiple multiplexed circuits arranged along a second direction. The arrangement direction of the multiple multiplexed circuits in a column can have a certain angle with the second direction. The multiple multiplexed circuits are also arranged in multiple rows along the second direction, with each row including multiple multiplexed circuits arranged along the first direction. Based on this, multiple rows of multiplexed circuits can be provided in the fan-out region, which is beneficial for increasing the number of multiplexed circuits in the fan-out region, thereby increasing the number of input signal lines and output signal lines, and increasing the number of data lines, to reduce the spacing between data lines, improve the pixel circuit density of the array substrate, improve the pixel density of the display panel, and enable the display panel to achieve a high pixel density. Multiple first gate lines are disposed in the fan-out region and located on the side of the multiple multiplexed circuits away from the display area. Each of the multiple second gate line groups includes multiple second gate lines, with one second gate line connected to one first gate line. A second gate line group comprises multiple second gate lines connected to a column of multiple multiplexed circuits, and each multiplexed circuit is connected to multiple second gate lines comprised of a second gate line group. In other words, multiple multiplexed circuits in a column share multiple second gate lines from a single second gate line group and, through the second gate line group, share multiple first gate lines. Based on this, it is not necessary to separately provide first gate lines extending along the first direction for each row of multiplexed circuits. This helps to reduce the spacing between two adjacent multiplexed circuits along the second direction, thereby reducing the width of the fan-out area along the second direction, which facilitates the achievement of a narrow bezel on the array substrate.

[0007] In some embodiments, any two adjacent multiplexed circuits in the same column are staggered in the first direction, and a multiplexed circuit closer to the display area is offset to the same side compared to a multiplexed circuit farther from the display area.

[0008] In some embodiments, two adjacent columns of multiplexing circuits are symmetrically arranged along the first direction.

[0009] In some embodiments, the angle between the line connecting the geometric centers of the contours of the orthographic projections of any two adjacent multiplexed circuits in the same column onto the substrate and the second direction is α; 4°≤α≤30°.

[0010] In some embodiments, any two adjacent multiplexed circuits in the same column are spaced D1 in the first direction and D2 in the second direction; wherein D1, D2 and α satisfy: tanα=D2 / D1.

[0011] In some embodiments, the shape of the outline of the orthographic projection of the multiplexing circuit on the substrate is rectangular.

[0012] In some embodiments, the plurality of second gate lines belonging to a second gate line group include a plurality of first sub-lines and a plurality of second sub-lines. The multiplexing circuit includes a plurality of N-type transistors and a plurality of P-type transistors. The plurality of control electrodes of the plurality of N-type transistors are respectively connected to the plurality of first sub-lines, the plurality of first electrodes of the plurality of N-type transistors are all connected to the input signal lines, and the plurality of second electrodes of the plurality of N-type transistors are respectively connected to a plurality of output signal lines of the output signal line group. The plurality of control electrodes of the plurality of P-type transistors are respectively connected to the plurality of second sub-lines, the plurality of first electrodes of the plurality of P-type transistors are all connected to the input signal lines, and the plurality of second electrodes of the plurality of P-type transistors are respectively connected to a plurality of output signal lines of the output signal line group. One output signal line is connected to the second electrode of one N-type transistor and the second electrode of one P-type transistor.

[0013] In some embodiments, the N-type transistor and the P-type transistor connected to the same output signal line are in the same conduction state.

[0014] In some embodiments, the N-type transistor has the same size as the P-type transistor.

[0015] In some embodiments, the plurality of N-type transistors and the plurality of P-type transistors belonging to the same multiplexing circuit are arranged at intervals along the second direction, and the two ends of the plurality of N-type transistors and the plurality of P-type transistors are respectively flush along the first direction.

[0016] In some embodiments, any two adjacent multiplexed circuits in the same column are spaced apart in the first direction and have a second spaced apart in the second direction.

[0017] In some embodiments, two adjacent multiplexed circuits in the same column are spaced apart along the first direction, and at least a portion of the two multiplexed circuits are arranged opposite each other along the first direction.

[0018] In some embodiments, multiple N-type transistors and multiple P-type transistors belonging to two adjacent multiplexing circuits in the same column and being closest to each other are arranged opposite to each other along the first direction. The multiple N-type transistors belonging to two adjacent multiplexing circuits in the same column have a third spacing in the second direction, and the multiple P-type transistors belonging to two adjacent multiplexing circuits in the same column have a fourth spacing in the second direction.

[0019] In some embodiments, the first sub-line includes a plurality of first extension segments and a plurality of second extension segments. The plurality of first extension segments all extend along the second direction, and at least one first extension segment is configured to form the gate of an N-type transistor. The plurality of second extension segments all extend along the first direction, and each end of a second extension segment is connected to a first extension segment. The second sub-line includes a plurality of third extension segments and a plurality of fourth extension segments. The plurality of third extension segments all extend along the second direction, and at least one third extension segment is configured to form the gate of a P-type transistor. The plurality of fourth extension segments all extend along the first direction, and each end of a fourth extension segment is connected to a third extension segment.

[0020] In some embodiments, an output signal line group includes three output signal lines, and the multiplexing circuit is connected to the three output signal lines. The multiplexing circuit includes a P-type semiconductor layer, an N-type semiconductor layer, a source pattern, and three drain patterns. The P-type semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern spaced apart along the first direction. The N-type semiconductor layer includes a third semiconductor pattern and a fourth semiconductor pattern spaced apart along the first direction. The source pattern includes a first source, a second source, and a first connection portion. The first source and the second source are spaced apart along the first direction and both extend along the second direction. The first connection portion is connected to the adjacent ends of the first source and the second source, and is connected to the input signal line. The first source is connected to the first semiconductor pattern and the third semiconductor pattern, respectively, and the second source is connected to the second semiconductor pattern and the fourth semiconductor pattern, respectively. The three drain patterns are spaced apart along the first direction and all extend along the second direction. Two of the drain patterns are located on either side of the first source along the first direction and are both connected to the first semiconductor pattern and the third semiconductor pattern. Another drain pattern is arranged side by side with the second source along the first direction and is connected to the second semiconductor pattern and the fourth semiconductor pattern; a drain pattern is connected to an output signal line.

[0021] In some embodiments, an output signal line group includes two output signal lines, and the multiplexing circuit is connected to the two output signal lines. The multiplexing circuit includes a P-type semiconductor layer and an N-type semiconductor layer. The P-type semiconductor layer includes a fifth semiconductor pattern. The N-type semiconductor layer includes a sixth semiconductor pattern. The source pattern extends along the second direction and is connected to the fifth semiconductor pattern, the sixth semiconductor pattern, and the input signal line. The two drain patterns are located on opposite sides of the source pattern along the first direction, and both drain patterns are connected to the fifth and sixth semiconductor patterns. Each drain pattern is connected to one output signal line.

[0022] In some embodiments, the plurality of N-type transistors and the plurality of P-type transistors belonging to the same multiplexing circuit are arranged at intervals along the second direction, and the plurality of N-type transistors and the plurality of P-type transistors are staggered in the first direction.

[0023] In some embodiments, along the second direction, portions of the plurality of N-type transistors of the same multiplexing circuit are arranged opposite to portions of the plurality of P-type transistors.

[0024] In some embodiments, portions of two adjacent multiplexed circuits in the same column are arranged opposite each other along the second direction.

[0025] In some embodiments, two adjacent multiplexing circuits belonging to the same column and the nearest N-type transistors and P-type transistors are spaced apart along the first direction, and portions of the N-type transistors belonging to the two adjacent multiplexing circuits belonging to the same column are arranged opposite each other along the second direction, and portions of the P-type transistors belonging to the two adjacent multiplexing circuits belonging to the same column are arranged opposite each other along the second direction.

[0026] In some embodiments, the first sub-line includes a plurality of fifth extension segments and a plurality of sixth extension segments. The plurality of fifth extension segments all extend along the second direction, and one fifth extension segment is configured to form the gate of an N-type transistor. The plurality of sixth extension segments form an angle with the first direction, and each end of one sixth extension segment is connected to two fifth extension segments. The second sub-line includes a plurality of seventh extension segments and a plurality of eighth extension segments. The plurality of seventh extension segments all extend along the second direction, and one seventh extension segment is configured to form the gate of a P-type transistor. The plurality of eighth extension segments form an angle with the first direction, and each end of one eighth extension segment is connected to one seventh extension segment.

[0027] In some embodiments, an output signal line group includes four output signal lines, and the multiplexing circuit is connected to the four output signal lines. The multiplexing circuit further includes a P-type semiconductor layer, an N-type semiconductor layer, a source pattern, and four drain patterns. The P-type semiconductor layer includes a seventh semiconductor pattern and an eighth semiconductor pattern spaced apart along the first direction. The N-type semiconductor layer includes a ninth semiconductor pattern and a tenth semiconductor pattern spaced apart along the first direction.

[0028] The source pattern includes a third source, a fourth source, and a second connection portion. The third and fourth sources are spaced apart along the first direction. The second connection portion is connected to the adjacent ends of the third and fourth sources and is also connected to the input signal line. The third source is connected to the seventh and ninth semiconductor patterns, and the fourth source is connected to the eighth and tenth semiconductor patterns.

[0029] The four drain patterns are spaced apart along the first direction; two drain patterns are located on both sides of the third source along the first direction and are connected to the seventh semiconductor pattern and the ninth semiconductor pattern; the other two drain patterns are located on both sides of the fourth source along the first direction and are connected to the eighth semiconductor pattern and the tenth semiconductor pattern; one drain pattern is connected to an output signal line.

[0030] In some embodiments, the channel length of the N-type transistor and the P-type transistor is L, and the source-drain width of the N-type transistor and the P-type transistor is W. SD One of the multiplexing circuits is connected to M output signal lines; a column of multiplexing circuits includes N multiplexing circuits; the spacing between two adjacent pixel circuits along the first direction is P. Pixel In the region where the multiplexing circuit is located, the width of the output signal line along the first direction is W. data The interval between two adjacent output signal lines is S. data Among them, L and W SD M, N, P Pixel W data and S data Satisfy: 2MNP pixel =2[ML+(M+1)W SD ]+2MN(W data +S data )+R design Among them, R design For design redundancy, R design The value range is ±5μm.

[0031] In some embodiments, the L, W SD M, N, P Pixel W data and S data It also approximately satisfies:

[0032]

[0033] In some embodiments, the width-to-length ratio W / L of the N-type transistor and the P-type transistor is ≥38μm / 7μm. And / or, the source-drain width W of the N-type transistor and the P-type transistor... SD ≤5μm; and / or, the spacing P between two adjacent pixel circuits along the first direction Pixel ≤7.2μm. And / or, the width W of the output signal line along the first direction. data ≤2μm. And / or, the spacing S between two adjacent output signal lines. data ≤3.25μm.

[0034] In some embodiments, the width of the input signal line along the first direction is W1, wherein W1 ≤ 2.5 μm. And / or, the interval between two adjacent input signal lines along the first direction is W2, wherein W2 ≤ 7.2 μm.

[0035] In some embodiments, two adjacent multiplexed circuits in the same column are aligned at both ends along the first direction.

[0036] In some embodiments, a column includes two multiplexing circuits, and a multiplexing circuit includes a plurality of transistors; the plurality of transistors are arranged in multiple rows along the second direction, and each row includes at least one transistor.

[0037] In some embodiments, one of the multiplexing circuits includes three transistors. The three transistors are arranged in a first row and a second row along the direction proximate to the display area, with the first row including two transistors and the second row including one transistor.

[0038] In some embodiments, one of the multiplexing circuits includes two transistors; the two transistors are arranged in two rows along the second direction, with one transistor in each row.

[0039] In some embodiments, one of the multiplexing circuits is connected to M output signal lines, where M ≥ 2. The array substrate includes (Q × M) first gate lines, which are divided into Q groups, each group comprising M first gate lines, where O ≥ 2. A second gate line group is connected to a group of first gate lines, and along the first direction, the plurality of second gate line groups are alternately connected to the Q groups of first gate lines.

[0040] In some embodiments, one of the multiplexing circuits is connected to M output signal lines, where M ≥ 2. The array substrate includes (Q × 2M) first gate lines, which are divided into Q groups. Each group includes 2M first gate lines, and the 2M first gate lines in each group are divided into M subgroups. Each subgroup includes two first gate lines connected in parallel, and a second gate line is connected to the two first gate lines of a subgroup; wherein, O ≥ 2. A second gate line group is connected to a group of first gate lines, and along the first direction, the plurality of second gate line groups are alternately connected to the first gate lines of the Q groups.

[0041] In some embodiments, the array substrate further includes a plurality of third connection portions located between and connected to the two first gate lines of a subgroup. A second gate line is connected to the third connection portion.

[0042] In some embodiments, the number of third connections is greater than the number of second gate lines connected to two first gate lines of a subgroup.

[0043] In some embodiments, the multiplexing circuit includes a plurality of transistors. The width-to-length ratio of the channel of the transistor is W / L, wherein W / L ≥ 180 / 35.

[0044] In some embodiments, the array substrate further includes multiple test signal lines, at least one third gate line, at least one fourth gate line, multiple signal transmission lines, multiple first test transistors, and multiple second test transistors. The multiple test signal lines include at least one first test signal line and at least one second test signal line, with the first test signal line being farther away from the display area than the second test signal line. The third gate line is disposed on the side of the multiple test signal lines farther from the display area. The fourth gate line is disposed on the side of the multiple test signal lines closer to the display area. The multiple signal transmission lines are arranged at intervals along the first direction, with one end of each signal transmission line configured to connect to a data line and the other end configured to connect to a driver chip. The plurality of first test transistors are disposed between the plurality of test signal lines and the third gate line. Along the second direction, the plurality of first test transistors are arranged in two rows. Each row includes a plurality of first transistor groups arranged along the first direction. Each first transistor group includes at least one first test transistor. The plurality of first transistor groups in the two rows are alternately arranged in the first direction. The gate of the first test transistor is connected to the third gate line, the first electrode is connected to a first test signal line, and the second electrode is connected to a signal transmission line. The plurality of second test transistors are disposed between the plurality of test signal lines and the fourth gate line. Along the second direction, the plurality of second test transistors are arranged in two rows. Each row includes a plurality of second transistor groups arranged along the first direction. Each second transistor group includes at least one second test transistor. The plurality of second transistor groups in the two rows are alternately arranged in the first direction. The gate of the second test transistor is connected to the fourth gate line, the first electrode is connected to a second test signal line, and the second electrode is connected to a signal transmission line.

[0045] In some embodiments, the array substrate has four test signal lines. Two test signal lines farther from the display area are first test signal lines, and two test signal lines closer to the display area are second test signal lines. The first terminals of the plurality of first test transistors are respectively connected to two of the first test signal lines, and along the first direction, the first terminals of the plurality of first test transistors are alternately connected to two of the first test signal lines. The first terminals of the plurality of second test transistors are respectively connected to two of the second test signal lines, and along the first direction, the first terminals of the plurality of second test transistors are alternately connected to two of the second test signal lines.

[0046] In some embodiments, a first transistor group includes two first test transistors; and / or, a second transistor group includes two second test transistors.

[0047] In some embodiments, the array substrate further includes multiple test signal lines, multiple test transistors, two fifth gate lines, and multiple signal transmission lines. The multiple test signal lines are disposed in the fan-out region. The multiple test transistors are disposed on the side of the multiple test signal lines near the display area and arranged in two rows along the second direction. Each row includes multiple test transistors spaced apart along the first direction, belonging to two adjacent test transistors in each row, and staggered along the first direction. The two fifth gate lines are spaced apart along the second direction. The orthographic projection of one fifth gate line onto the substrate overlaps with the orthographic projection of a row of test transistors onto the substrate and is configured to form the gate of a row of test transistors. The multiple signal transmission lines are spaced apart along the first direction. One end of each signal transmission line is configured to connect to a data line, and the other end is configured to connect to a driver chip. The first electrode of each test transistor is connected to a test signal line, and the second electrode is connected to a signal transmission line.

[0048] In some embodiments, the plurality of test transistors are arranged in multiple columns along the first direction, each column including two test transistors arranged along the second direction; at least a portion of the two test transistors in a column are arranged opposite each other along the second direction, and adjacent columns of test transistors are spaced apart in the first direction.

[0049] In some embodiments, the multiple test signal lines are divided into multiple groups, with each group comprising two test signal lines. Two test transistors in one column are respectively connected to the two test signal lines in one group, and along the first direction, multiple columns of test transistors are alternately connected to multiple groups of test signal lines.

[0050] In some embodiments, the signal transmission line includes a first region, the first gate line includes a second region, and the orthographic projections of the first region and the second region on the substrate coincide. The first region is provided with a cutout pattern, and / or the second region is provided with a cutout pattern.

[0051] On the other hand, a display panel is provided. The display panel includes an encapsulation cover and an array substrate as described in any of the above embodiments. The encapsulation cover is disposed on a first side of the array substrate, which is the side of the array substrate from which the pixel circuitry is located.

[0052] In another aspect, a display device is provided. The display device includes a driver circuit board and the aforementioned display panel. The driver circuit board is connected to an array substrate of the display panel and is configured to transmit control signals to the array substrate.

[0053] The above-described display panel and display device have the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0055] Figure 1 This is a schematic diagram of the planar structure of a display device according to some embodiments;

[0056] Figure 2 This is a block diagram of a display device according to some embodiments;

[0057] Figure 3 This is a schematic diagram of the stacked structure of a display device according to some embodiments;

[0058] Figure 4 This is a structural diagram of an array substrate according to some embodiments;

[0059] Figure 5 for Figure 4 A magnified view of a portion of region A in the middle;

[0060] Figure 6 for Figure 5 A magnified view of a portion of region B in the middle;

[0061] Figure 7 for Figure 4 Another magnified view of region A in the middle;

[0062] Figure 8 for Figure 7 A magnified view of a portion of region C in the middle;

[0063] Figure 9 This is another structural diagram of an array substrate according to some embodiments;

[0064] Figure 10 for Figure 9 A magnified view of a portion of region D in the middle;

[0065] Figure 11 This is yet another structural diagram of an array substrate according to some embodiments;

[0066] Figure 12 This is yet another structural diagram of an array substrate according to some embodiments;

[0067] Figure 13This is yet another structural diagram of an array substrate according to some embodiments;

[0068] Figure 14 This is yet another structural diagram of an array substrate according to some embodiments;

[0069] Figure 15 This is a structural diagram of a test circuit for an array substrate according to some embodiments;

[0070] Figure 16 This is another structural diagram of a test circuit for an array substrate according to some embodiments;

[0071] Figure 17 This is a structural diagram showing the overlap of a first gate line and a signal transmission line according to some embodiments. Detailed Implementation

[0072] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0073] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0074] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0075] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0076] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0077] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0078] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0079] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0080] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0081] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0082] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0083] See Figure 1 The present disclosure provides a display device, wherein the display device 1000 is a product having an image display function. Exemplarily, the display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0084] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone (phone), watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle display, flight display, etc.

[0085] From the perspective of the light emission type of the display device 1000, the display device 1000 can be a liquid crystal display (LCD), or it can also be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a mini / micro light-emitting display (MLED), etc. From the perspective of the form of the display device 1000, the display device 1000 can be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 can be rectangular or circular, etc. The embodiments of this disclosure do not specifically limit this. The following uses a rectangular and flat liquid crystal display device as an example to illustrate some embodiments of this disclosure, but the implementation of this disclosure is not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0086] In some embodiments, see Figure 2 The display device 1000 includes a display panel 1100 and a driver circuit board 1200. The driver circuit board 1200 may include, for example, a timing controller (TCON), a DC / DC power management chip, and an adjustable resistor voltage divider circuit (generating Vcom), etc. The driver circuit board 1200 may also include other circuit structures, which will not be listed here. The driver circuit board 1200 is electrically connected to the display panel 1100 and is used to transmit control signals to the display panel 1100, thereby driving the display panel 1100 to display images. In addition, the display device 1000 may also include a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display device 1000 to realize various functions such as touch control, photography, video recording, or fingerprint recognition; specific limitations are not specified here.

[0087] like Figure 2As shown, the display panel 1100 may include multiple sub-pixels P. A sub-pixel P can be understood as the smallest light-emitting unit in the display panel 1100, and each sub-pixel P includes a pixel circuit 102. The multiple sub-pixels P can be arranged in multiple rows and columns. Multiple sub-pixels arranged along a first direction X are called a row of sub-pixels P, and multiple sub-pixels arranged along a second direction Y are called a column of sub-pixels P. The first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y are perpendicular. The display panel 1100 may also include a gate driver on array (GOA) 103 and a source driver IC 104. The gate driver circuit 103 can be connected to the pixel circuit 102 of a row of sub-pixels P via a scan signal line GL. The source driver IC 104 can be connected to the pixel circuit 102 of a column of sub-pixels P via an input signal line DL and transmits data signals to the pixel circuit 102 of the column of sub-pixels P.

[0088] If the display device 1000 is a liquid crystal display device, refer to Figure 3 The display device 1000 may further include a backlight 1300 disposed on the backlight side of the display panel 1100. For example, the backlight 1300 may be a direct-lit backlight or an edge-lit backlight, etc. The backlight 1300 is used to provide backlight for the display panel 1100, and the display panel is used to adjust the amount of light passing through the display panel 1100, thereby displaying different gray levels.

[0089] Continue reading Figure 3 The display panel 1100 is a liquid crystal display panel. In this case, the display panel 1100 may include an array substrate 100 and an encapsulation cover plate 200 (also referred to as a color filter substrate) disposed opposite each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the encapsulation cover plate 200. When the encapsulation cover plate 200 is a color filter substrate, it can encapsulate the display panel 1100 and filter the light incident on it, so that each sub-pixel emits light of a single color (e.g., red, green, and blue), thereby enabling the display panel 1100 to achieve color display. Of course, the display panel 1100 may also include other structures. Exemplarily, the display panel 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the encapsulation cover plate 200 near the liquid crystal layer 300, etc., which will not be listed individually in the embodiments of this disclosure.

[0090] It is understood that when the display device 1000 is an OLED display device or a QLED display device, the display panel may include an array substrate, a light-emitting device, and an encapsulation substrate stacked together. In this case, the encapsulation substrate may be, for example, an encapsulation film. The types of display devices and the structures included in the display devices disclosed herein are not limited thereto, and any other suitable display devices may be considered.

[0091] In some embodiments, see Figure 4 The array substrate 100 may include a display area AA and a peripheral area BB surrounding the display area AA. The peripheral area BB includes a fanout area BB1 located on one side of and adjacent to the display area AA. Specifically, the fanout area BB1 is the region within the peripheral area BB located on one side of the display area AA. The fanout area BB1 is adjacent to one edge of the display area AA, meaning that the fanout area BB1 near one edge of the display area AA coincides with the edge of the display area AA near the fanout area BB1. The fanout area BB1 can be used to lead out signal lines (such as data lines, clock signal lines, power signal lines, etc.) from the display area and the peripheral area and bond them to a driver circuit board or source driver chip. For example, as... Figure 4 As shown, the fan-out area BB1 is adjacent to the lower edge of the display area AA.

[0092] Among them, the source driver chip refers to the chip used to transmit data signals to multiple data lines DL. In order to reduce the cost of the source driver chip, a multiplexer (MUX) circuit can be set in the fan-out area BB1 to reduce the number of output signals of the source driver chip, thereby reducing the cost of the source driver chip and the manufacturing cost of the display panel.

[0093] In related technologies, an array substrate is provided, including multiple multiplexed circuits arranged along a first direction X. However, as the pixel density of the display panel 1100 increases, the pitch of the pixel circuits 102 in the first direction X becomes smaller and smaller. With the same display area AA size, the number of data lines DL included in the array substrate 100 increases, and the spacing between adjacent data lines DL becomes smaller and smaller. Due to the limited wiring space of the multiplexed circuits, single-row multiplexed circuits can no longer meet the needs of the increasing number of data lines DL.

[0094] To solve the above-mentioned technical problems, the array substrate 100 provided in the embodiments of this disclosure, such as... Figure 4As shown, the array substrate 100 also includes a substrate 101 and multiple pixel circuits 102, multiple data lines DL, multiple multiplexed circuits 10, multiple input signal lines 20, multiple output signal line groups 30, multiple first gate lines 40, and multiple second gate line groups 50 disposed on the substrate 101. Among these, Figure 4 Only a few pixel circuits 102 are shown as examples.

[0095] Multiple pixel circuits 102 are disposed within the display area AA, and the multiple pixel circuits 102 are arranged in multiple columns. The multiple columns of pixel circuits 102 are arranged along a first direction X, and each column of pixel circuits 102 includes multiple pixel circuits 102 arranged along a second direction Y. The first direction X and the second direction Y intersect, and exemplarily, the first direction X and the second direction Y are perpendicular to each other.

[0096] Pixel circuit 102 includes a plurality of thin film transistors (TFTs) and at least one capacitor Cst. Exemplarily, pixel circuit 102 can be a "3T1C" circuit, a "5T1C" circuit, etc., and the embodiments of this disclosure are not limited thereto, and any other pixel circuit can be considered as long as the same technical concept is applied. Here, "T" refers to TFT, and the number before "T" indicates the number of TFTs; "C" refers to capacitor Cst, and the number before "C" indicates the number of capacitors Cst.

[0097] At least a portion of multiple data lines DL are disposed within the display area AA, and the multiple data lines DL are arranged at intervals along the first direction X. The multiple data lines DL all extend along the second direction Y. One data line DL is connected to a column of pixel circuits 102 to transmit data signals to the column of pixel circuits 102 connected to the data line DL.

[0098] Multiple multiplexer circuits 10 are disposed in the fan-out area BB1, and the multiple multiplexer circuits 10 are arranged in multiple columns along the first direction X, in the attached... Figure 4 In the diagram, two multiplexed circuits 10 in a row are labeled 11. A row of multiplexed circuits 10 includes multiple multiplexed circuits 10 arranged along the second direction Y. For example, Figure 4As shown, the arrangement direction of multiple multiplexed circuits 10 in a column can have a certain angle with the second direction. The multiple multiplexed circuits 10 are also arranged in multiple rows in the second direction Y, with each row including multiple multiplexed circuits 10 arranged along the first direction X. Based on this, multiple rows of multiplexed circuits 10 can be provided in the fan-out area BB1, which is beneficial for increasing the number of multiplexed circuits 10 in the fan-out area BB1, thereby increasing the number of input signal lines 20 and output signal lines 31, and increasing the number of data lines DL, so as to reduce the spacing between data lines DL, improve the pixel circuit density of the array substrate 100, improve the pixel density of the display panel, and enable the display panel to achieve a high pixel density.

[0099] For example, a column may include 2, 3, 4, 8, or any other number of multiplexed circuits 10 arranged along the second direction Y, such as... Figure 4 As shown, a column may include four multiplexing circuits 10. Of course, the embodiments of this disclosure are not limited to this, as long as the same technical concept is used.

[0100] Multiple input signal lines 20 are disposed in the fan-out area BB1 and located on the side of the multiple multiplexing circuits 10 away from the display area AA. Each input signal line 20 is connected to one multiplexing circuit 10. For example, the multiple input signal lines 20 are spaced apart along a first direction X, and all of the multiple input signal lines 20 extend along a second direction Y. The input signal lines 20 are configured to transmit the data signals required by the data line DL.

[0101] Multiple output signal line groups 30 are disposed in the fan-out area BB1, and the multiple output signal line groups 30 are located on the side of the multiple multiplexers 10 closest to the display area AA. Each output signal line group 30 includes multiple output signal lines 31. The multiple output signal lines 31 included in an output signal line group 30 are connected to the same multiplexer 10, and each output signal line 31 is connected to a data line DL. Figure 4 The example provided is only illustrative of an output signal line group 30 comprising two output signal lines 31 and should not be construed as a limitation of this application. For example, an output signal line group 30 may also include three, four, or other numbers of output signal lines 31.

[0102] Multiple first gate lines 40 are disposed in the fan-out area BB1 and located on the side of the multiple multiplexed circuits 10 away from the display area AA. Each of the multiple second gate line groups 50 includes multiple second gate lines 51, and each second gate line 51 is connected to one first gate line 40. The multiple second gate lines 51 included in a second gate line group 50 are connected to a column of multiple multiplexed circuits 10, and each multiplexed circuit 10 is connected to the multiple second gate lines 51 included in a second gate line group 50. That is, the multiple multiplexed circuits 10 in a column share the multiple second gate lines 51 of a second gate line group 50, and share multiple first gate lines 40 through the second gate line group 50. Based on this, it is not necessary to set a first gate line extending along the first direction X for each row of multiplexed circuits 10. This is beneficial to reduce the spacing between two adjacent multiplexed circuits 10 along the second direction Y, which in turn is beneficial to reduce the width of the fan-out area BB1 along the second direction, thus enabling the array substrate 100 to achieve a narrow bezel.

[0103] like Figure 4 As shown, the multiplexing circuit 10 is connected to an input signal line 20, multiple output signal lines 31 of an output signal line group 30, and multiple second gate lines 51 of a second gate line group 50. One output signal line 31 may correspond to at least one second gate line 51. The multiplexing circuit 10 is configured to, under the control of a control signal from at least one of the multiple second gate lines 51 corresponding to one output signal line 31, transmit a data signal from the input signal line 20 to the output signal line 31, and then to the data line DL via the output signal line 31, thereby transmitting a data signal to a column of pixel circuits 102 connected to the data line DL. Exemplarily, one output signal line 31 may correspond to one second gate line 51, or one output signal line 31 may correspond to two second gate lines 51.

[0104] In some embodiments, see Figure 4 Any two adjacent multiplexed circuits 10 belonging to the same column are staggered in the first direction X, that is, the two adjacent multiplexed circuits 10 are offset from each other in the first direction X. In this way, the multiple input signal lines 20 and multiple output signal line groups 30 connected to the multiple multiplexed circuits 10 in the same column can have more than enough wiring space in the first direction X, which is beneficial to the wiring arrangement of the multiple input signal lines 20 and multiple output signal line groups 30.

[0105] For example, two adjacent multiplexing circuits 10 may be partially offset in the first direction X, that is, portions of adjacent multiplexing circuits 10 may be arranged opposite each other in the second direction Y (e.g. Figure 4(As shown). Alternatively, two adjacent multiplexing circuits 10 can be completely offset in the first direction X, that is, the projections of adjacent multiplexing circuits 10 along the second direction Y do not coincide.

[0106] Among any two adjacent multiplexed circuits 10 belonging to the same column, the multiplexed circuit 10 closer to the display area AA is offset to the same side along the first direction X compared to the multiplexed circuit 10 farther from the display area AA. In other words, the arrangement direction of the multiple multiplexed circuits 10 in a column has an angle with the second direction Y, and along the second direction Y, the multiple multiplexed circuits 10 in a column are tilted to the same side of the first direction X in sequence. In this way, the multiple output signal line groups 30 connected to the multiple multiple multiplexed circuits 10 in the same column can be arranged sequentially in the first direction X, and the space occupied by each will not overlap. This can effectively avoid wiring interference between the multiple output signal line groups 30, and it is also conducive to the uniform arrangement of the multiple output signal lines 31 included in the multiple output signal line groups 30 in the first direction X. That is to say, it is conducive to the wiring setup of multiple input signal lines 20 and multiple output signal line groups 30.

[0107] For example, such as Figure 4 As shown, in the first column of multiplexing circuits 10 from left to right along the first direction X, in any two adjacent multiplexing circuits 10, the multiplexing circuit 10 closer to the display area AA is offset to the right along the first direction X compared to the multiplexing circuit 10 farther away from the display area AA.

[0108] In some embodiments, such as Figure 4 As shown, the multiplexed circuits 10 in two adjacent columns are symmetrically arranged along the first direction X. That is, the multiplexed circuits 10 belonging to two adjacent columns have a different offset direction along the first direction X compared to the multiplexed circuits that are farther away from the display area AA. This is beneficial for the wiring arrangement of multiple input signal lines 20.

[0109] For example, along the first direction X from left to right, in any two adjacent multiplexed circuits 10 of the odd-numbered multiplexed circuits 10, the multiplexed circuit 10 closer to the display area AA is offset to the right compared to the multiplexed circuit 10 farther from the display area AA; and in any two adjacent multiplexed circuits 10 of the even-numbered multiplexed circuits 10, the multiplexed circuit 10 closer to the display area AA is offset to the left compared to the multiplexed circuit 10 farther from the display area AA. Alternatively, in any two adjacent multiplexed circuits 10 of the even-numbered multiplexed circuits 10, the multiplexed circuit 10 closer to the display area AA is offset to the right compared to the multiplexed circuit 10 farther from the display area AA; and in any two adjacent multiplexed circuits 10 of the odd-numbered multiplexed circuits 10, the multiplexed circuit 10 closer to the display area AA is offset to the left compared to the multiplexed circuit 10 farther from the display area AA.

[0110] For example, such as Figure 4 As shown, along the first direction X from left to right, in any two adjacent multiplexed circuits 10 of the first and third columns, the multiplexed circuit 10 closer to the display area AA is offset to the right compared to the multiplexed circuit 10 farther from the display area AA; and in any two adjacent multiplexed circuits 10 of the second and fourth columns, the multiplexed circuit 10 closer to the display area AA is offset to the left compared to the multiplexed circuit 10 farther from the display area AA.

[0111] In some embodiments, such as Figure 4 As shown, the line L1 connecting the geometric centers of the outlines of any two adjacent multiplexed circuits 10 in the same column and projected onto the substrate, forms an angle α with the second direction Y, where 4°≤α≤30°. This helps to reduce the spacing between two adjacent multiplexed circuits 10 in the first direction X, allowing for the placement of as many multiplexed circuits 10 as possible within the fan-out region BB1. This increases the number of input signal lines 20 and output signal lines 31, as well as the number of data lines DL, thereby reducing the spacing between data lines DL, increasing the pixel circuit density of the array substrate 100, and ultimately increasing the pixel density of the display panel, enabling the display panel to achieve a high pixel density. For example, α can be 4°, 5°, 10°, 20°, 25°, or 30°, etc., and will not be listed here.

[0112] In some embodiments, see Figure 4 The shape of the outline of the orthographic projection of the multiplexing circuit 10 on the substrate can be rectangular.

[0113] In some embodiments, such as Figure 4As shown, any two adjacent multiplexed circuits 10 belonging to the same column have a spacing of D1 along the first direction X and a spacing of D2 along the second direction Y. The spacing between the two multiplexed circuits 10 in the first direction X can be understood as the distance between the geometric centers of their orthographic projections onto the substrate 101 in the first direction X. Similarly, the spacing between the two multiplexed circuits 10 in the second direction Y can be understood as the distance between the geometric centers of their orthographic projections onto the substrate 101 in the second direction X. Where D1, D2, and α satisfy:

[0114] tanα=D2 / D1

[0115] In some embodiments, see Figure 5 The multiple second gate lines 51 belonging to a second gate line group 50 include multiple first sub-lines 52 and multiple second sub-lines 53. The multiplexing circuit 10 includes multiple N-type transistors 11 and multiple P-type transistors 12. At this time, one output signal line 31 corresponds to two second gate lines 51. Under the control of one second gate line 51, one N-type transistor and one P-type transistor 12 transmit the data signal from the input signal line to one output signal line 31.

[0116] Multiple control electrodes of multiple N-type transistors 11 are respectively connected to multiple first sub-lines 52. Multiple first electrodes of multiple N-type transistors 11 are each connected to an input signal line 20. Multiple second electrodes of multiple N-type transistors 11 are respectively connected to multiple output signal lines 31 of an output signal line group 30. An N-type transistor 11 is configured to, under the control of the first sub-line 52 connected to its control electrode, transmit a data signal from the input signal line 20 to the output signal line 31 connected to the N-type transistor 11, and further transmit it to the data line DL connected to the output signal line.

[0117] Multiple control electrodes of multiple P-type transistors 12 are respectively connected to multiple second sub-lines 53, multiple first electrodes of multiple P-type transistors 12 are each connected to input signal lines 20, and multiple second electrodes of multiple P-type transistors 12 are respectively connected to multiple output signal lines 31 of output signal line group 30. A P-type transistor 12 is configured to, under the control of the second sub-lines 53 connected to its control electrode, transmit data signals from the input signal line 20 to the output signal line 31 connected to the P-type transistor 12, and further transmit them to the data line DL connected to the output signal line.

[0118] The input signal line 20, connected to the multiplexing circuit 10, is simultaneously connected to the first terminals of multiple N-type transistors 11 and multiple P-type transistors 12. Similarly, an output signal line 31 is electrically connected to both an N-type transistor 11 and a P-type transistor 12. In other words, each output signal line 31 is electrically connected to an N-type transistor 11 and a P-type transistor 12. Thus, the N-type transistors 11 and P-type transistors 12 connected to the same output signal line 31 are connected in parallel, forming a Complementary Metal Oxide Semiconductor (CMOS) transmission gate. CMOS transmission gates have low on-resistance (several hundred ohms) and high off-resistance (greater than 10 ohms). 9 (Oh). In this case, the CMOS transmission gate composed of N-type transistor 11 and P-type transistor 12 is beneficial for data signal transmission. For example, when the CMOS transmission gate is turned on, the data signal transmitted by the input signal line 20 can be transmitted to the output signal line 31, and the signal transmission loss is small; when the CMOS transmission gate is turned off, the cutoff resistance between the input signal line 20 and the output signal line 31 is extremely large, which can avoid leakage current.

[0119] In some embodiments, the N-type transistor 11 and the P-type transistor 12 connected to the same output signal line 31 are in the same conduction state. That is, the N-type transistor 11 and the P-type transistor 12 connected to the same output signal line 31 are either simultaneously turned on or simultaneously turned off. It should be noted that the same conduction state of the N-type transistor 11 and the P-type transistor 12 does not mean that their on-resistances are the same, but rather that both are either in the on or off state.

[0120] For example, when it is necessary to transmit a data signal to the output signal line 31, a high-voltage signal is transmitted to the first sub-line 52 connected to the N-type transistor 11 to turn on the N-type transistor 11, and a low-voltage signal is transmitted to the second sub-line 53 connected to the P-type transistor 12 to turn on the P-type transistor 12. At this time, the data signal on the input signal line 20 is transmitted to the output signal line 31. When it is not necessary to transmit a data signal to the output signal line 31, a low-voltage signal is transmitted to the first sub-line 52 connected to the N-type transistor 11 to turn off the N-type transistor 11, and a high-voltage signal is transmitted to the second sub-line 53 connected to the P-type transistor 12 to turn off the P-type transistor 12.

[0121] Of course, in other examples, the conduction states of the N-type transistor 11 and the P-type transistor 12 connected to the same output signal line 31 may also be different. For example, in two adjacent frame periods, the N-type transistor 11 and the P-type transistor 12 connected to the same output signal line 31 may each conduct once. Of course, the control timing of the N-type transistor 11 and the P-type transistor 12 is not limited to this, and the embodiments disclosed herein will not be listed one by one.

[0122] For example, the number of first sub-lines 52 included in a second gate line group 50, the number of N-type transistors 11 included in a multiplexing circuit 10, the number of P-type transistors 12 included in a multiplexing circuit 10, and the number of output signal lines 31 included in an output signal line group 30 are all equal. For example, as Figure 5 As shown, the multiplexing circuit 10 includes three N-type transistors 11 and three P-type transistors 12. At this time, a second gate line group 50 includes three first sub-lines 52 and three second sub-lines 53, and an output signal line group 30 includes three output signal lines 31.

[0123] In some embodiments, see Figure 5 and Figure 6 An output signal line group 30 includes three output signal lines 31, and a multiplexing circuit 10 is connected to the three output signal lines 31. In this case, the multiplexing circuit 10 may include three N-type transistors 11 and three P-type transistors 12. The multiplexing circuit 10 also includes a P-type semiconductor layer 14, an N-type semiconductor layer 13, a source pattern 15, and three drain patterns 16.

[0124] The P-type semiconductor layer 14 includes a first semiconductor pattern 141 and a second semiconductor pattern 142 disposed at intervals along a first direction X. One of the first semiconductor pattern 141 and the second semiconductor pattern 142 is used to form a channel structure for one P-type transistor 12, and the other is used to form a channel structure for two P-type transistors 12. Hereinafter, embodiments of this disclosure will be described exemplarily using an example where the first semiconductor pattern 141 forms a channel structure for two P-type transistors 12, and the second semiconductor pattern 142 is used to form a channel structure for one P-type transistor 12.

[0125] The N-type semiconductor layer 13 includes a third semiconductor pattern 131 and a fourth semiconductor pattern 132 spaced apart along a first direction X. One of the third semiconductor pattern 131 and the fourth semiconductor pattern 132 is used to form a channel structure for one N-type transistor 11, and the other is used to form a channel structure for two N-type transistors 11. Hereinafter, embodiments of this disclosure will be described exemplarily using the example of the third semiconductor pattern 131 forming a channel structure for two N-type transistors 11 and the fourth semiconductor pattern 132 forming a channel structure for one N-type transistor 11.

[0126] The source pattern 15 includes a first source 151, a second source 152, and a first connection portion 153. The first source 151 and the second source 152 are spaced apart along a first direction X and both extend along a second direction Y. The first source 151 is connected to a first semiconductor pattern 141 and a third semiconductor pattern 131 to form the first electrode (e.g., the source) of two P-type transistors 12 and two N-type transistors 11. The second source 152 is connected to a second semiconductor pattern 142 and a fourth semiconductor pattern 132 to form the first electrode of one P-type transistor 12 and one N-type transistor 11.

[0127] The first connection portion 153 is connected to the adjacent ends (ends near the input signal line 20) of the first source 151 and the second source 152, and is also connected to the input signal line 20. The first connection portion 153 is used to connect the first source 151 and the second source 152 to each other, and to connect the first source 151 and the second source 152 to the input signal line 20. That is, the first terminals of the three P-type transistors 12 and the three N-type transistors 11 included in the multiplexing circuit 10 are interconnected, i.e., the three P-type transistors 12 and the three N-type transistors 11 are common sources.

[0128] Three drain patterns 16 are spaced apart along a first direction X and extend along a second direction Y. Two of the drain patterns 16 are located on either side of the first source 151 along the first direction X and are connected to the first semiconductor pattern 141 and the third semiconductor pattern 131. The third drain pattern 16 is arranged side by side with the second source 152 along the first direction X and is connected to the second semiconductor pattern 142 and the fourth semiconductor pattern 132. A P-type transistor 12 and an N-type transistor 11 share a drain pattern 16, and each drain pattern 16 is connected to an output signal line 31. Each drain pattern 16 is used to form the second terminal (e.g., drain) of a P-type transistor 12 and an N-type transistor 11. Compared to arranging three P-type transistors 12 and three N-type transistors 11 spaced apart along the first direction X, the above-described embodiments of this disclosure provide that the three P-type transistors 12 and three N-type transistors 11 are spaced apart along the second direction Y. This is beneficial for reducing the size of the three P-type transistors 12 and three N-type transistors 11 along the first direction X, thereby allowing as many multiplexing circuits 10 as possible to be arranged in the fan-out region BB1, increasing the pixel circuit density of the array substrate 100, increasing the pixel density of the display panel, and enabling the display panel to achieve a high pixel density.

[0129] exist Figure 5 and Figure 6In this context, different filling patterns are used only to represent different structures, and not to define the film layer in which the corresponding structure is located. For example, the P-type semiconductor layer 14 and the N-type semiconductor layer 13 are located in different film layers, the input signal line and the second gate line group 50 are located in one film layer (e.g., the gate conductive layer), and the first gate line 40, the output signal line 31, the source pattern 15 and the drain pattern 16 are located in one film layer (e.g., the source-drain conductive layer).

[0130] In some embodiments, such as Figure 5 and Figure 6 As shown, the dimensions of N-type transistor 11 and P-type transistor 12 are the same. In other words, the width-to-length ratio of N-type transistor 11 is the same as that of P-type transistor 12, so that the on-resistance and off-resistance of N-type transistor 11 and P-type transistor 12 are respectively equal or approximately equal.

[0131] Continue reading Figure 5 Multiple N-type transistors 11 and multiple P-type transistors 12 belonging to the same multiplexing circuit 10 are arranged at intervals along the second direction Y, and along the first direction X, the two ends of the multiple N-type transistors 11 and multiple P-type transistors 12 are respectively aligned, that is, the orthographic projections of the multiple N-type transistors 11 and multiple P-type transistors 12 of the same multiplexing circuit 10 along the second direction Y coincide. For example, the multiple N-type transistors 11 of the same multiplexing circuit 10 are further away from the display area AA than the multiple P-type transistors 12. This is beneficial to reduce the size of a single multiplexing circuit 10 in the first direction X, and to arrange as many multiplexing circuits 10 as possible in the fan-out area BB1, increasing the number of input signal lines 20 and output signal lines 31, and increasing the number of data lines DL, so as to reduce the spacing between data lines DL, improve the pixel circuit density of the array substrate 100, improve the pixel density of the display panel, and enable the display panel to achieve a high pixel density.

[0132] In some embodiments, such as Figure 5 As shown, any two adjacent multiplexed circuits 10 belonging to the same column are spaced apart in the first direction X and in the second direction Y. In other words, the transistors (N-type transistors and P-type transistors) included in the two multiplexed circuits 10 are spaced apart in the first direction X and the second direction Y, respectively. This avoids the risk of interference between adjacent multiplexed circuits 10 and increases the wiring space for multiple multiplexed circuits 10 in a column, increases the spacing between adjacent signal lines (input signal lines and output signal lines, etc.), and reduces the risk of signal interference between adjacent signal lines.

[0133] In other embodiments, see Figure 7Two adjacent multiplexed circuits 10 in the same column are spaced apart along the first direction X, and at least a portion of the two adjacent multiplexed circuits 10 in the same column are arranged opposite each other along the first direction X. In this way, a portion of the two multiplexed circuits 10 share the space in the second direction Y, which is beneficial to reducing the size of the multiple multiplexed circuits 10 in the second direction Y in a column, which is beneficial to reducing the size of the fan-out area BB1 in the second direction Y, and which is beneficial to achieving a narrow bezel in the array substrate 100.

[0134] Continue reading Figure 7 and Figure 8 Multiple N-type transistors 11 and multiple P-type transistors 12 belonging to the same column and closest to each other in the multiplexing circuit 10 are arranged opposite each other along the first direction X. The N-type transistors 11 belonging to the same column of the multiplexing circuit 10 have a third interval D3 in the second direction Y, and the multiple P-type transistors belonging to the same column of the multiplexing circuit 10 have a fourth interval D4 in the second direction Y. In this way, the first sub-line 52 can be arranged within the third interval D3, and the second sub-line 53 can be arranged within the fourth interval D4, which is beneficial to the arrangement of the first sub-line 52 and the second sub-line 53.

[0135] For example, the third interval D3 can be equal to the fourth interval D4.

[0136] For example, such as Figure 7 and Figure 8 As shown, when the multiple N-type transistors 11 included in the multiplexer circuit 10 are farther away from the display area than the multiple P-type transistors, in two adjacent multiplexer circuits 10 in the same column, the P-type transistors 12 included in the multiplexer circuit 10 that are farther away from the display area AA are arranged opposite to the N-type transistors 11 included in the multiplexer circuit 10 that are closer to the display area AA in the first direction X.

[0137] In some embodiments, see Figure 5 and Figure 7The first sub-line 52 includes a plurality of first extension segments 521 and a plurality of second extension segments 522. The plurality of first extension segments 521 extend along a second direction Y, and at least one first extension segment 521 is configured to form the gate of an N-type transistor. The plurality of second extension segments 522 extend along a first direction X, and each end of a second extension segment 522 is connected to a first extension segment 521 along the second direction X. That is, the first sub-line 52 includes a broken line segment, and the first sub-line 52 includes alternately connected first extension segments 521 and second extension segments 522. The first extension segments 521 extend along the second direction Y and are configured to form the gate of an N-type transistor 11, and the second extension segments 522 extend along the first direction X to connect adjacent first extension segments 521. Exemplarily, the orthographic projection of the second extension segment 522 onto the substrate 101 is located within the interval between the orthographic projections of adjacent N-type transistors 11 and P-type transistors 12 onto the substrate, thus reducing the impact of the second extension segment 522 on the N-type transistors 11 and P-type transistors 12.

[0138] Continue reading Figure 5 and Figure 7 Similar to the first sub-line 52, the second sub-line 53 includes a plurality of third extension segments 531 and a plurality of fourth extension segments 532. The plurality of third extension segments 531 extend along a second direction Y, and at least one third extension segment 531 is configured to form the gate of a P-type transistor 12. The plurality of fourth extension segments 532 extend along a first direction X. Along the second direction Y, each end of a fourth extension segment 532 is connected to a third extension segment 531. In other words, the second sub-line 53 is a zigzag line, and includes alternately connected third extension segments 531 and fourth extension segments 532. The third extension segments 531 extend along the second direction Y and are configured to form the gate of a P-type transistor 12, while the fourth extension segments 532 extend along the first direction X to connect adjacent third extension segments 531. Exemplarily, the orthogonal projection of the fourth extension 532 onto the substrate 101 lies within the interval between adjacent N-type transistors 11 and P-type transistors 12, thereby reducing the impact of the fourth extension 532 on the N-type transistors 11 and P-type transistors 12. Alternatively, the orthogonal projection of the fourth extension 532 onto the substrate 101 lies within the interval between the orthogonal projections of adjacent N-type transistors 11 and P-type transistors 12 onto the substrate, thus reducing the impact of the fourth extension 532 on the N-type transistors 11 and P-type transistors 12.

[0139] See Figure 7 and Figure 8In some embodiments, an output signal line group 30 includes two output signal lines 31, and a multiplexing circuit 10 is connected to the two output signal lines 31. In this case, the multiplexing circuit 10 may include two N-type transistors 11 and two P-type transistors 12. The multiplexing circuit 10 includes an N-type semiconductor layer 13, a P-type semiconductor layer 14, a source pattern 15, and three drain patterns 16.

[0140] The N-type semiconductor layer 13 includes a sixth semiconductor pattern 133. The P-type semiconductor layer 14 includes a fifth semiconductor pattern 143. The sixth semiconductor pattern 133 and the fifth semiconductor pattern 143 are arranged along a second square Y. The fifth semiconductor pattern 143 is used to form a channel structure for two P-type transistors 12, and the sixth semiconductor pattern 133 is used to form a channel structure for two N-type transistors 11.

[0141] The source pattern 15 extends along the second direction Y and is connected to the fifth semiconductor pattern 143, the sixth semiconductor pattern 133, and the input signal line 20. Exemplarily, at least one source pattern 15 may include a main body portion 154 and a fourth connection portion 155. The main body portion 154 extends along the second direction Y and is connected to the fifth semiconductor pattern 143 and the sixth semiconductor pattern 133, for forming the first terminals (e.g., sources) of two P-type transistors 12 and two N-type transistors 11. The fourth connection portion 155 may extend along the first direction X, with one end connected to the main body portion 154 and the other end connected to the input signal line 20.

[0142] Two drain patterns 16 are located on both sides of the source pattern 15 along the first direction X, and both drain patterns 16 are connected to the fifth semiconductor pattern 143 and the sixth semiconductor pattern 133. One drain pattern 16 is used to form the drain of a P-type transistor 12 and an N-type transistor 11, and one drain pattern 16 is connected to an output signal line 31.

[0143] In some embodiments, see Figure 9 Multiple N-type transistors 11 and multiple P-type transistors 12 belonging to the same multiplexing circuit 10 are arranged at intervals along the second direction Y. The multiple N-type transistors 11 and multiple P-type transistors 12 of the multiplexing circuit 10 are staggered in the first direction X, that is, the orthogonal projection portions of the multiple N-type transistors 11 and multiple P-type transistors 12 of the same multiplexing circuit 10 overlap along the second direction Y, or in other words, along the second direction Y, portions of the multiple N-type transistors 11 and portions of the multiple P-type transistors 12 of the same multiplexing circuit 10 are arranged opposite each other. For example, as... Figure 9 and Figure 10 As shown, along the first direction X, the left side of a plurality of N-type transistors 11 extends out of the left side of a plurality of P-type transistors 12, and the right side of a plurality of P-type transistors 12 extends out of the right side of a plurality of N-type transistors 11.

[0144] Continue reading Figure 9 Along the second direction Y, portions of the multiple N-type transistors 11 and portions of the multiple P-type transistors 12 of the same multiplexing circuit 10 are arranged opposite each other. This helps to reduce the size of a single multiplexing circuit 10 in the first direction X, and allows for the arrangement of as many multiplexing circuits 10 as possible within the fan-out region BB1, thereby increasing the pixel density of the array substrate 100, increasing the pixel density of the display panel, and enabling the display panel to achieve a high pixel density.

[0145] like Figure 9 As shown, portions of two adjacent multiplexed circuits 10 in the same column are arranged opposite each other along the second direction Y. That is, the orthographic projection portions of two adjacent multiplexed circuits 10 along the second direction Y overlap. This helps to reduce the overall size of the multiple multiplexed circuits 10 in a column along the first direction X, and allows for the arrangement of as many multiplexed circuits 10 as possible within the fan-out area BB1, thereby increasing the pixel circuit density of the array substrate 100, increasing the pixel density of the display panel, and enabling the display panel to achieve a high pixel density.

[0146] Continue reading Figure 9 Two adjacent multiplexed circuits 10 belonging to the same column, with their nearest N-type transistors 11 and P-type transistors 12 spaced apart along a first direction X, exemplarily, the P-type transistors 12 included in a multiplexed circuit 10 on the side away from the display area AA are spaced apart from the N-type transistors 11 included in the multiplexed circuit 10 on the side closer to the display area AA along the first direction X. Portions of the N-type transistors 11 of the two adjacent multiplexed circuits 10 belonging to the same column are arranged opposite each other along a second direction Y, and portions of the P-type transistors 12 of the two adjacent multiplexed circuits 10 belonging to the same column overlap along the second direction Y. This design allows the first sub-line 52 to avoid multiple P-type transistors 12 and the second sub-line 53 to avoid multiple N-type transistors 11. In other words, the above design facilitates the wiring of multiple second gate lines 50 and reduces the size of multiple multiplexed circuits 10 in the first direction X. It also allows for the placement of as many multiplexed circuits 10 as possible within the fan-out area BB1, thereby increasing the pixel density of the array substrate 100, increasing the pixel density of the display panel, and enabling the display panel to achieve a high pixel density.

[0147] In some embodiments, such as Figure 9As shown, the first sub-line 52 includes a plurality of fifth extension segments 523 and a plurality of sixth extension segments 524. The plurality of fifth extension segments 523 all extend along the second direction Y, and one fifth extension segment 523 forms the gate of an N-type transistor. The plurality of sixth extension segments 524 form an angle with the first direction X, and the two ends of one sixth extension segment 524 are respectively connected to two fifth extension segments 523. In other words, the first sub-line 52 includes a broken line segment, and the first sub-line 52 includes a plurality of alternately connected fifth extension segments 523 and a plurality of sixth extension segments 524. The fifth extension segments 523 extend along the second direction Y and form the gate of the N-type transistor 11, and the sixth extension segments 524 form a certain angle with the first direction X to connect adjacent fifth extension segments 523. Exemplarily, the orthographic projection of the sixth extension segment 524 on the substrate 101 is located within the interval between adjacent N-type transistors 11 and P-type transistors 12, which can reduce the influence of the sixth extension segment 524 on the N-type transistor 11 and P-type transistor 12.

[0148] Continue reading Figure 9 Similar to the first sub-line 52, the second sub-line 53 includes a plurality of seventh extension segments 533 and a plurality of eighth extension segments 534. The plurality of seventh extension segments 534 all extend along the second direction Y, and one seventh extension segment 534 forms the gate of a P-type transistor 12. The plurality of eighth extension segments 534 form an angle with the first direction X, and each end of one eighth extension segment 534 is connected to a seventh extension segment 533. That is, the second sub-line 53 includes a broken line segment, and the second broken line 53 includes a plurality of alternately connected seventh extension segments 533 and a plurality of eighth extension segments 534. The seventh extension segments 533 extend along the second direction Y and form the gate of the P-type transistor 12, while the eighth extension segments 534 form an angle with the first direction X and are used to connect adjacent seventh extension segments 533. Exemplarily, the orthographic projection of the eighth extension segment 534 onto the substrate 101 is located within the interval between adjacent N-type transistors 11 and P-type transistors 12, which can reduce the influence of the sixth extension segment 524 on the N-type transistors 11 and P-type transistors 12.

[0149] like Figure 9 and Figure 10 As shown, an output signal line group 30 includes four output signal lines 31, and a multiplexing circuit 10 is connected to the four output signal lines 31. In this case, the multiplexing circuit 10 may include four N-type transistors 11 and four P-type transistors 12. The multiplexing circuit 10 includes a P-type semiconductor layer 14, an N-type semiconductor layer 13, a source pattern 15, and four drain patterns 16.

[0150] The P-type semiconductor layer 14 includes a seventh semiconductor pattern 144 and an eighth semiconductor pattern 145 spaced apart along a first direction X. The seventh semiconductor pattern 144 and the eighth semiconductor pattern 145 are respectively configured to form channel structures for two P-type transistors 12. The N-type semiconductor layer 13 includes a ninth semiconductor pattern 134 and a tenth semiconductor pattern 135 spaced apart along the first direction X. The ninth semiconductor pattern 134 and the tenth semiconductor pattern 135 are respectively configured to form channel structures for two N-type transistors 11. Exemplarily, the seventh semiconductor pattern 144 and the eighth semiconductor pattern 145 are identical in size and shape, and the ninth semiconductor pattern 134 and the tenth semiconductor pattern 135 are identical in size and shape.

[0151] The source pattern 15 includes a third source 156, a fourth source 157, and a second connection portion 158. The third source 156 and the fourth source 157 are spaced apart along a first direction X. The third source 156 is connected to the seventh semiconductor pattern 144 and the ninth semiconductor pattern 135, and the fourth source 157 is connected to the eighth semiconductor pattern 144 and the tenth semiconductor pattern 135. The third source 156 and the fourth source 157 are used to form the first electrode (e.g., the source) of the P-type transistor 12 and the N-type transistor. The second connection portion 158 is located at the adjacent ends of the third source 156 and the fourth source 157. Figure 7 The upper end of the first source is connected to the second source (156) and is connected to the input signal line 20. The third source 156 and the fourth source 157 are connected as a whole through the second connecting part 158 ​​and are both connected to the input signal line 20. The source pattern 15 is used to form the common source of four P-type transistors 12 and four N-type transistors 11.

[0152] Four drain patterns 16 are spaced apart along a first direction X; two drain patterns 16 are located on both sides of the third source 156 along the first direction X, and are both connected to the seventh semiconductor pattern 144 and the ninth semiconductor pattern 134; the other two drain patterns 16 are located on both sides of the fourth source 157 along the first direction X, and are connected to the eighth semiconductor pattern 145 and the tenth semiconductor pattern 135. One drain pattern 16 is used to form the drain of a P-type transistor 12 and an N-type transistor 11, and is connected to an output signal line 31.

[0153] In some embodiments, the channel length (dimension along the second direction Y) of the N-type transistor 11 and the P-type transistor 12 is L. The source-drain width (dimension along the first direction X) of the N-type transistor 11 and the P-type transistor 12 is W. SD A multiplexing circuit 10 is connected to M output signal lines 31, and a column of multiplexing circuits 10 includes N multiplexing circuits 10. The spacing between two adjacent pixel circuits 102 along the first direction X is P. PixelThe spacing between two adjacent pixel circuits 102 in the display area AA along the first direction X can also be understood as the spacing between adjacent sub-pixels P, and the spacing between two adjacent data lines DL. In the fan-out area BB1, where the multiplexing circuit 10 is located (hereinafter referred to as the MUX area), the width of the output signal line 31 in the first direction X is W. data The interval between two adjacent output signal lines 31 is S. data Among them, L and W SD M, N, P Pixel W data and S data satisfy:

[0154] 2MNP pixel =2[ML+(M+1)W SD ]+2MN(W data +S data )+R design (Equation 1)

[0155] In Equation 1 above, R design For design redundancy, R design The value range is ±5μm. R design It reflects the width of the multiplexing circuit 10 along the first direction X and the distance between the transistor (P-type transistor or N-type transistor) and the output signal line 31 in the first direction X, as well as the pitch between the data lines DL in the display area AA, and the difference between the pitch between the output signal lines 31 in the area where the multiplexing circuit 10 is set.

[0156] It should be noted that the spacing between adjacent data lines DL within the display area AA is generally equal to the spacing of pixel circuits 102 along the first direction X, and is generally greater than the spacing between output signal lines 31 within the area set by the multiplexer circuit 10 (hereinafter referred to as the MUX area). Furthermore, the spacing of the pixel circuits 102 depends on the pixel density (Pixels Per Inch, PPI) of the display panel. Currently, in liquid crystal display devices, the sub-pixel spacing is generally greater than or equal to 3μm, and within the fan-out area BB1, the width and spacing of the output signal lines 31 can reach the current technological limit of 2μm to 3μm. Based on this, the aforementioned design redundancy R... design It is the difference between the spacing of the pixel circuits 102 in the display area AA and the spacing of the output signal lines 31 in the MUX area, minus the redundant part after deducting the transistors of the multiplexing circuit 10 and the spacing between the transistors, i.e., the following Equation 2.

[0157] R design =2MNP pixel -2MN(W data +S data)-2[ML+(M+1)W SD (Equation 2)

[0158] By transforming Equations 1 and 2 above, we can obtain:

[0159]

[0160] Equation 3 above can be approximated to obtain:

[0161]

[0162] Equation 4 above can be transformed to obtain:

[0163]

[0164] Due to the spacing P of sub-pixels P within the display area pixel (The spacing of the pixel circuits in the first direction X) will not be less than the spacing of the output signal lines 31 within the fan-out area BB1 (W data +S data (L+(1+1 / M)W) SD () is the average length of a transistor in the multiplexing circuit 10. The resolution of the display panel. As can be seen from the above, in high PPI display devices, the spacing P of sub-pixels P is... pixel Smaller, therefore, the line width and spacing of the output signal lines 31 within the fan-out area BB1 need to be smaller (even approaching the limits of the manufacturing process) in order to meet the requirements of high pixel density.

[0165] From Equation 5 above, we can also obtain:

[0166]

[0167] In Equation 6 above, A represents the number of sources included in a multiplexing circuit 10. For example, when M is 2, A is 1; when M is 3 or 4, A is 2 (at least two transistors share a common source). Based on this, Furthermore, under normal circumstances, the channel length L of the transistor in the multiplexing circuit 10 is equal to the source-drain width W of the transistor. SD 1.5 to 1.6 times, that is, L = (1.5 to 1.6)W SD Based on this, we can approximate the following:

[0168]

[0169] as well as:

[0170]

[0171] And from the above equation 8 and We can approximate the result as follows:

[0172]

[0173] From Equation 9 above, we can obtain the approximate relationship between the number of multiplexing circuits 10 included in a column of multiplexing circuits 10 and the resolution of the display panel, and design the number of rows of multiplexing circuits 10 according to Equation 9 above.

[0174] In some embodiments of this disclosure, the width-to-length ratio of the N-type transistor 11 and the P-type transistor 12 is W / L, wherein W / L ≥ 38 / 7, to improve the charging capability of the N-type transistor 11 and the P-type transistor 12 and reduce the signal transmission delay of the multiplexing circuit 10. Exemplarily, the width-to-length ratio W / L of the N-type transistor 11 and the P-type transistor 12 is 38 μm / 7 μm.

[0175] The source-drain widths W of N-type transistor 11 and P-type transistor 12 SD ≤5μm, for example, the source-drain width W of N-type transistor 11 and P-type transistor 12 SD The pixel size can be 5μm, 4.5μm, 4μm, or 3μm, etc., and will not be listed here. This helps to reduce the size of the multiplexing circuit 10 along the first direction X, and helps to increase the pixel density of the display panel.

[0176] The spacing between two adjacent pixel circuits 102 along the first direction X is P. Pixel ≤7.2μm, meaning the spacing between subpixels of the display panel is ≤7.2μm, and within the display area, the spacing between adjacent data lines DL is ≤7.2μm. For example, the spacing P between two adjacent pixel circuits 102 along the first direction X... Pixel The size can be 7.2μm, 7μm, 5μm or 3μm, etc., and the embodiments disclosed herein do not specifically limit it.

[0177] Within the fan-out region BB1, the line width W of the output signal line 31 is... data ≤2μm, for example, the linewidth W of the output signal line 31 data The spacing can be 2μm, 1.9μm, or 1.8μm, etc., and the embodiments disclosed herein do not specifically limit this. The spacing S between adjacent output signal lines 31 data ≤3.25μm, for example, the spacing S between adjacent output signal lines 31 data It can be 3.25μm, 3μm or 2.5μm, etc., and will not be listed here.

[0178] In some embodiments, the width of the input signal line 20 along the first direction X is W1, wherein W1 ≤ 2.5 μm; and / or, the interval between two adjacent input signal lines 20 along the first direction X is W2, wherein W2 ≤ 7.2 μm. Exemplarily, the width W1 of the input signal line 20 along the first direction X can be 2.5 μm, 2.3 μm, 2 μm, or 1.5 μm, etc., and the interval W2 between two adjacent input signal lines 20 along the first direction X can be 7.2 μm, 7 μm, 6.5 μm, or 5 μm, etc.

[0179] In other embodiments, see Figure 11 In this arrangement, two adjacent multiplexed circuits 10 in the same column are aligned at both ends along the first direction X. That is, two adjacent multiplexed circuits 10 are arranged along the second direction Y, and their projections along the second direction Y coincide. This helps to further reduce the size of multiple multiplexed circuits 10 in a column along the first direction X, allowing for the placement of as many multiplexed circuits 10 as possible within the fan-out area BB1. This improves the pixel density of the display panel, enabling it to achieve a high pixel density. For example, the display panel can achieve a pixel density greater than 1000 PPI.

[0180] In some embodiments, such as Figure 11 As shown, a column includes two multiplexing circuits 10, and each multiplexing circuit 10 includes multiple transistors T10. The multiple transistors T10 can be P-type or N-type transistors, and they can be of the same type to simplify the fabrication process of the array substrate. The multiple transistors T10 included in the multiplexing circuit 10 are arranged in multiple rows along the second direction Y, with each row including at least one transistor T10. This further reduces the size of the multiplexing circuit 10 in the first direction X, allowing for the placement of as many multiplexing circuits 10 as possible within the fan-out region BB1, which is beneficial for increasing the pixel density of the display panel and enabling it to achieve a high pixel density. For example, the display panel can achieve a pixel density greater than 1200 PPI.

[0181] For example, the number of transistors T10 included in the multiplexing circuit 10 is the same as the number of output signal lines 31 connected to the multiplexing circuit 10. For instance, as... Figure 11 As shown, a multiplexing circuit 10 includes three transistors, and the multiplexing circuit 10 is connected to three output signal lines 31. All three transistors can be either P-type transistors or N-type transistors.

[0182] In some embodiments, see Figure 11An output signal line group 30 includes three output signal lines 31. A multiplexing circuit 10 is connected to the three output signal lines 31, and the multiplexing circuit 10 includes three transistors T10, along the second direction Y and close to the display area AA. Figure 11 In the first row (from top to bottom), three transistors T10 are arranged in two rows, with the first row containing two transistors T10 and the second row containing one transistor T10. This allows signal lines (such as input signal line 20, second gate line 51, and output signal line 31) to be arranged on one side of the transistor T10 in the second row. This reduces the space occupied by the signal lines in the first direction X, improves the space utilization of the fan-out area BB1, and consequently reduces the size of the multiplexing circuit 10 in the first direction X. This allows for the placement of as many multiplexing circuits 10 as possible within the fan-out area BB1, which helps increase the pixel density of the display panel, enabling it to achieve a high pixel density. For example, the display panel can achieve a pixel density greater than 1200 PPI.

[0183] For example, such as Figure 11 As shown, the three transistors T10 included in the first row of the multiplexing circuit 10 are transistor T11, transistor T12, and transistor T13, respectively. The three transistors T10 included in the second row of the multiplexing circuit 10 are transistor T14, transistor T15, and transistor T16, respectively. The gates of transistor T11 and transistor T14 are connected to the same second gate line 51, the gates of transistor T12 and transistor T15 are connected to the same second gate line 51, and the gates of transistor T13 and transistor T16 are connected to the same second gate line 51. The first electrode (e.g., the source) of transistor T11, transistor T12, and transistor T13 is shared, and the second electrode (e.g., the drain) of transistor T11, transistor T12, and transistor T13 is each connected to an output signal line 31. The first terminals of the fourth transistor T14, the fifth transistor T15, and the sixth transistor T16 are shared, and the second terminals of the fourth transistor T14, the fifth transistor T15, and the sixth transistor T16 are each connected to an output signal line 31.

[0184] Continue reading Figure 11 The six data lines DL connected to the two multiplexer circuits 10 in the same column are sequentially classified from left to right as: first data line DL1, second data line DL2, ..., fifth data line DL5 and sixth data line DL6. In one example, as... Figure 11As shown, the first transistor T11 can be connected to the first data line DL1 via the output signal line 31; the second transistor T12 can be connected to the fifth data line DL5 via the output signal line 31; and the third transistor T13 can be connected to the third data line DL3 via the output signal line 31. The fourth transistor T14 can be connected to the fourth data line DL4 via the output signal line 31; the fifth transistor T15 can be connected to the second data line DL2 via the output signal line 31; and the sixth transistor T16 can be connected to the sixth data line DL6 via the output signal line 31. Of course, the multiplexing circuit 10 can also be connected to the above six data lines DL in other ways. The embodiments disclosed herein are not specifically limited, as long as the same technical concept is adopted.

[0185] It should be noted that, as Figure 11 As shown, the input signal line 20, output signal line 31, and second gate line 51 can be configured on different conductive layers. This means that any single signal line can cross different conductive layers, which facilitates spatial arrangement of the signal lines and avoids signal interference between them. For example, in... Figure 11 In this context, different filling patterns can represent different conductive layers. Of course, the embodiments disclosed herein are not limited to these specific examples. Figure 11 The wiring method shown can be replaced by any other suitable wiring method, as long as the same technical approach is used.

[0186] In some embodiments, the number of first gate lines 40 included in the array substrate 100 is the same as the number of transistors T10 included in a multiplexing circuit 10. For example, as... Figure 11 As shown, when the multiplexing circuit 10 includes three transistors T10, the array substrate 100 may include three first gate lines 40, the gate of each transistor T10 (each second gate line 51) is connected to one first gate line 40, and the multiplexing circuits 10 in different columns are all connected to the above three first gate lines 40.

[0187] In other embodiments, see Figure 12 A multiplexing circuit 10 is connected to M output signal lines 31. That is, the multiplexing circuit 10 includes M transistors T10 for transmitting data signals to the M data lines DL. M ≥ 2. Exemplarily, the value of M can be 2, 3, or 4. Of course, M can also have other values, which will not be listed in the embodiments of this disclosure. The array substrate 100 includes (Q × M) first gate lines 40. The (Q × M) first gate lines 40 are divided into Q groups, and each group includes M first gate lines 40, where Q ≥ 2. Exemplarily, the value of Q can be 2 or 3. Of course, M can also have other values, which will not be listed in the embodiments of this disclosure.

[0188] A second gate line group 50 is connected to a group of first gate lines 40, and along the first direction X, multiple second gate line groups 50 are alternately connected to Q groups of first gate lines 40. As the pixel density of the display panel increases, the number of multiplexing circuits 10 required to drive the first gate lines 40 also increases. The alternating connection of multiple second gate line groups 50 to Q groups of first gate lines 40 helps to reduce the number of multiplexing circuits 10 driven by each first gate line 40, that is, to reduce the load on the first gate line 40 and reduce the voltage drop of the first gate line 40.

[0189] For example, see Figure 12 The value of M is 3, meaning the multiplexing circuit 10 is connected to 3 output signal lines 31, and the multiplexing circuit 10 includes 3 transistors T10. The value of Q is 2, so the array substrate 100 includes (Q×M) first gate lines 40, that is, the array substrate 100 includes 2×3=6 first gate lines 40; wherein, every 3 first gate lines 40 form a group, the three first gate lines 40 closest to the multiplexing circuit 10 form a group, and the three first gate lines 40 farther away from the multiplexing circuit 10 form a group. The two second gate line groups 50 connected to the multiplexing circuits 10 in adjacent columns are respectively connected to the two groups of first gate lines 40. For example, the three first gate lines 40 closest to the multiplexing circuit 10 are labeled as the first group 401, and the three first gate lines 40 furthest from the multiplexing circuit 10 are labeled as the second group 402. The second gate lines 51 included in the second gate line group 50 connected to the odd-numbered multiplexing circuit 10 are all connected to the three first gate lines 40 of the first group 401, and the second gate lines 51 included in the second gate line group 50 connected to the even-numbered multiplexing circuit 10 are all connected to the three first gate lines 40 of the second group 402. Of course, the embodiments of this disclosure are not limited to this; for example, the values ​​of M and Q can be other values, and multiple second gate line groups 50 and multiple first gate lines 40 can be connected in other ways, as long as the same technical concept is adopted.

[0190] In other embodiments, see Figure 13 A multiplexing circuit 10 is connected to two output signal lines 31. The multiplexing circuit 10 includes two transistors T10. The two transistors are arranged in two rows along the second direction Y, with one transistor T10 in each row. In this way, the transistors T10 and the signal lines (signal lines used to drive the two multiplexing circuits 10 in one row) can be arranged side by side in the first direction X, which can further improve the space utilization of the fan-out area BB, reduce the size of the two multiplexing circuits 10 in one row in the first direction X, and facilitate the placement of as many multiplexing circuits 10 as possible in the fan-out area BB1, thereby improving the pixel density of the display panel and enabling the display panel to achieve a high pixel density. For example, the display panel can achieve a pixel density greater than 1500 PPI.

[0191] In some embodiments, see Figure 13 A multiplexing circuit 10 is connected to M output signal lines 31, meaning the multiplexing circuit 10 includes M transistors T10 for transmitting data signals to the M data lines DL. M ≥ 2; exemplarily, the value of M can be 2, 3, or 4. Of course, M can also have other values, which will not be listed in the embodiments of this disclosure. The array substrate 100 includes (Q × 2M) first gate lines 40, where Q ≥ 2. Exemplarily, the value of Q can be 2 or 3; of course, M can also have other values, which will not be listed in the embodiments of this disclosure.

[0192] The (Q×2M) first gate lines 40 are divided into Q groups, each group consisting of 2M first gate lines 40. Each group of 2M first gate lines 40 is further divided into M subgroups. Each subgroup consists of two first gate lines 40 connected in parallel. A second gate line 51 is connected to the two first gate lines 40 of a subgroup. A second gate line group 50 is connected to a group of first gate lines 40, and multiple second gate line groups 50 are alternately connected to the first gate lines 40 of the Q groups along the first direction X. As the pixel density of the display panel increases, the number of multiplexing circuits 10 required to drive the first gate lines 40 also increases. Connecting a second gate line 51 to the two first gate lines 40 of a subgroup, and having multiple second gate line groups 50 alternately connected to the first gate lines 40 of the Q groups, not only helps reduce the number of multiplexing circuits 10 driven by each first gate line 40 (i.e., reducing the load on the first gate line 40 and the voltage drop of the first gate line 40), but also reduces the resistance of the first gate line 40.

[0193] For example, see Figure 13 M is 2, and Q is 2. That is, the multiplexing circuit 10 includes two transistors T10, and the multiplexing circuit 10 is connected to two output signal lines 31. The array substrate 100 includes eight first gate lines 40, which are divided into two groups. Each group of four first gate lines 40 includes two subgroups, each subgroup including two first gate lines 40 connected in parallel. A second gate line 51 is connected to the two first gate lines 40 of one subgroup, and a second gate line group 50 is connected to the four first gate lines 40 of one group. Along the second direction Y, two adjacent first gate lines 40 are connected in parallel to form a subgroup, and two adjacent subgroups form a group of first gate lines 40. The two second gate line groups 50 connected to the multiplexing circuit 10 of adjacent columns are respectively connected to the two groups of first gate lines 40.

[0194] For example, such as Figure 13As shown, the two first gate lines 40 of a subgroup are labeled 403, and the group of first gate lines 40 closer to the multiplexing circuit 10 is labeled as the first group 401, and the group farther from the multiplexing circuit 10 is labeled as the second group 402. Along the first direction X and from left to right, of the two second gate lines 51 included in the second gate line group 50 connected to the multiplexing circuit 10 of the odd-numbered column (e.g., the first column and the third column), one second gate line 51 is connected to the two first gate lines 40 of a subgroup 403 of the first group 401 that is closer to the multiplexing circuit 10, and the other is connected to the two first gate lines 40 of a subgroup 403 of the first group 401 that is farther from the multiplexing circuit 10. Of the two second gate lines 51 included in the second gate line group 50 connected to the even-numbered column (e.g., the second and fourth columns) multiplexing circuit 10, one second gate line 51 is connected to two first gate lines 40 included in a subgroup 403 of the second group 402 that is close to the multiplexing circuit 10, and the other is connected to two first gate lines 40 included in a subgroup 403 of the second group 402 that is far away from the multiplexing circuit 10.

[0195] like Figure 13 As shown, in some embodiments, the array substrate may include a semiconductor layer (not shown), a gate conductive layer (not shown), a first source-drain conductive layer (not shown), and a second source-drain conductive layer (not shown) stacked along a direction away from the substrate. The active layers of the plurality of transistors T10 may be located in the semiconductor layer, and the gates of the transistors T10 may be located in the gate conductive layer. The first gate line 40, the first electrode (e.g., source) and second electrode (e.g., drain) of the transistors T10, and the data line DL may be located in the first source-drain conductive layer, while the input signal line 20 and the second gate line 51 may be located in the second source-drain conductive layer. Furthermore, as... Figure 13 As shown, the adapter line with the same fill as the input signal line 20 and the second gate line 51 can be located in the second source-drain conductive layer. Of course, the embodiments of this disclosure are not limited to this, and the array substrate may also include other conductive layers, and the above-mentioned signal lines or transistors may be disposed in other suitable conductive layers, as long as the same technical concept is adopted.

[0196] Continue reading Figure 13 When two adjacent first gate lines 40 are arranged in parallel to form a subgroup 403, the array substrate 100 further includes a plurality of third connection portions 41. The plurality of third connection portions 41 are located between the two first gate lines 40 of a subgroup and are connected to the two first gate lines 40 of a subgroup. For example, each subgroup includes a third connection portion 41 spaced apart along the first direction X between the two first gate lines 40.

[0197] The second gate line 51 includes a first end 511, which is connected to a third connecting part 41. Two first gate lines 40 of a subgroup are connected at the third connecting part 41. The two first gate lines 40 and the third connecting part 41 together form a pattern with a large area. The connection between the first end 511 and the two first gate lines 40 at the third connecting part 41 is beneficial to increasing the process window of the second gate line 51, that is, it is beneficial to increase the contact area between the first end 511 and the connecting part and the two first gate lines 40, and reduce the fabrication difficulty of the first end 511.

[0198] In some embodiments, such as Figure 13 As shown, the number of third connecting portions 41 between the two first gate lines 40 of a subgroup can be equal to the number of second gate lines 51 connected to the two first gate lines 40 of a subgroup. In this way, one second gate line 51 corresponds to one third connecting portion 41, and one second gate line 51 is connected to one third connecting portion 41.

[0199] In other embodiments, see Figure 14 The number of third connection portions 41 between two first gate lines 40 of a subgroup 403 can be greater than the number of second gate lines 51 connected to the two first gate lines 40 of a subgroup 403. Thus, at least two second gate lines 51 connected to at least two first gate lines 40 of a subgroup include a third connection portion 41. This improves the connection reliability between the two first gate lines 40 of a subgroup and further reduces the resistance of the two first gate lines 40 of a subgroup. Of course, the embodiments of this disclosure are not limited to this; any embodiment employing the same technical concept is acceptable.

[0200] In some of the embodiments of this disclosure described above, for example in Figures 11-14 In several corresponding embodiments, the multiplexing circuit 10 includes a plurality of transistors T10. The width-to-length ratio of the channel of transistor T10 is W / L, where W / L ≥ 180 μm / 35 μm. This is beneficial for further improving the width-to-length ratio of transistor T10, thereby enhancing the charging capability of transistor T10 and reducing the signal transmission delay of the multiplexing circuit 10.

[0201] In some embodiments, see Figure 15 and Figure 16The array substrate 100 also includes multiple test transistors T20, which are arranged in multiple rows along the second direction Y. Each row of test transistors T20 includes multiple test transistors T20 spaced apart along the first direction X. This increases the number of test transistors T20 within the fan-out region BB1, thus adapting to high PPI array substrates and enabling high resolution. Two adjacent test transistors T20 belonging to adjacent rows are staggered along the first direction X. This facilitates wiring within the gaps between the test transistors T20.

[0202] For example, the two test transistors T20 are completely offset in the first direction X, that is, the orthogonal projections of the two test transistors T20 along the second direction Y do not overlap; or, the two test transistors T20 are partially offset in the first direction X, that is, portions of the two adjacent test transistors T20 are arranged opposite each other along the second direction Y.

[0203] In some embodiments, see Figure 15 The array substrate 100 also includes multiple test signal lines 61, at least one third gate line 62, at least one fourth gate line 63, and multiple signal transmission lines 64. The multiple test transistors T20 include multiple first test transistors T21 and multiple second test transistors T22.

[0204] The plurality of test signal lines 61 include at least one first test signal line 61 and at least one second test signal line 612, wherein the first test signal line 611 is farther away from the display area AA than the second test signal line 612. A third gate line 62 is disposed on the side of the plurality of test signal lines 61 farther away from the display area AA, and a fourth gate line 63 is disposed on the side of the plurality of test signal lines 61 closer to the display area AA. A plurality of signal transmission lines 64 are arranged at intervals along a first direction X, wherein one end of each signal transmission line 64 is configured to be connected to a data line DL, and the other end is configured to be connected to a driver chip (such as a source driver chip).

[0205] Multiple first test transistors T21 are disposed between multiple test signal lines 61 and a third gate line 62 along the second direction Y. The multiple first test transistors T21 are arranged in two rows, and adjacent first test transistors T21 belonging to the two rows are staggered in the first direction X, for example, completely staggered. The gate of the first test transistor T21 is connected to the third gate line 62, the first electrode is connected to a first test signal line 611, and the second electrode is connected to a signal transmission line 64.

[0206] For example, see Figure 15Along the first direction X, two first test transistors T21 are alternately arranged in two rows. In other words, two adjacent first test transistors T21 in the same row are set as a first transistor group 601, and the first transistor groups 601 belonging to the two rows are alternately arranged in the first direction X. Alternatively, one first test transistor T21 (not shown in the figure) can be alternately arranged in two rows along the first direction X. That is, the first test transistors T21 belonging to the two rows are alternately arranged in the first direction X.

[0207] Multiple second test transistors T22 are disposed between multiple test signal lines 61 and a fourth gate line 63 along the second direction Y. The multiple second test transistors T22 are arranged in two rows, and adjacent second test transistors T22 belonging to the two rows are staggered in the first direction X, for example, completely staggered. The gate of the second test transistor T22 is connected to the fourth gate line 63, the first terminal is connected to a second test signal line 612, and the second terminal is connected to a signal transmission line 64.

[0208] For example, see Figure 15 Along the first direction X, two second test transistors T22 are alternately arranged in two rows. In other words, two adjacent second test transistors T22 in the same row are set as a second transistor group 602, and the second transistor groups 602 belonging to the two rows are alternately arranged in the first direction X. Alternatively, along the first direction X, one second test transistor T22 (not shown in the figure) can be alternately arranged in two rows. That is, the second transistors T21 belonging to the two rows are alternately arranged in the first direction X.

[0209] The configuration of the test unit provided in this embodiment of the present disclosure is advantageous in setting a larger number of first test transistors T21 and second test transistors T22 in the fan-out region BB1, thereby improving the pixel density of the display panel. Furthermore, signal traces can be arranged between adjacent test transistors T20, which helps optimize the wiring space of the test signal line 61, the third gate line 62, the fourth gate line 63, and multiple signal transmission lines 64, thereby reducing the size of the fan-out region BB1 in the second direction Y, which in turn helps to reduce the bezel width of the array substrate.

[0210] In one embodiment, such as Figure 15 As shown, the array substrate 100 includes four test signal lines 61. Among them, the two test signal lines 61 farther away from the display area AA are the first test signal lines 611, and the two test signal lines 61 closer to the display area AA are the second test signal lines 612.

[0211] The first terminals of multiple first test transistors T21 are respectively connected to two first test signal lines 611, and along the first direction X, the first terminals of the multiple first test transistors T21 are alternately connected to the two first test signal lines 611. The first terminals of multiple second test transistors T22 are respectively connected to two second test signal lines 612, and along the first direction X, the first terminals of the multiple second test transistors T22 are alternately connected to the two second test signal lines. This helps to reduce the load on the first test signal lines 611 and the second test signal lines 612.

[0212] For example, such as Figure 15 As shown, the spacing between the two second test transistors T22 of the second transistor group 602 in the first direction X is greater than the spacing between the two first test transistors T21 of the first transistor group 601 in the first direction X. This facilitates the routing of signal lines.

[0213] In other embodiments, see Figure 16 The array substrate 100 includes multiple test signal lines 61, multiple test transistors T20, two fifth gate lines 65, and multiple signal transmission lines 64.

[0214] Multiple test signal lines 61 are disposed in the fan-out area BB1, and multiple test transistors T20 are disposed on the side of the test signal lines 61 near the display area AA. The multiple test transistors T20 are arranged in two rows along the second direction Y. Each row includes multiple test transistors T20 spaced apart along the first direction X. Two adjacent test transistors T20 belonging to the two rows are staggered along the first direction X. That is, two adjacent test transistors T20 are offset from each other in the first direction X. This helps to reduce the spacing between two adjacent test transistors T20 and reduce the space occupied by the test transistors T20 in the first direction X, thereby allowing more test transistors T20 to be arranged in the fan-out area BB1, which in turn helps to increase the pixel density of the display panel and enable the display panel to achieve a high pixel density.

[0215] Two fifth gate lines 65 are spaced apart along the second direction Y. The orthogonal projection of one fifth gate line 65 onto the substrate overlaps with the orthogonal projection of a row of test transistors T20 onto the substrate, and is configured to form the gate of the row of test transistors T20. Multiple signal transmission lines 64 are arranged spaced apart along the first direction X. One end of each signal transmission line 64 is configured to be connected to a data line DL, and the other end is configured to be connected to a driver chip. One signal transmission line 64 is also configured to be connected to the first terminal of the test transistor T20. The second terminal of the test transistor T20 is connected to a test signal line 61.

[0216] Continue reading Figure 16Multiple test signal lines 61 are divided into multiple groups 603, with each group 603 including two test signal lines 61. Multiple test transistors T20 are arranged in multiple columns 201 along the first direction X, with each column 201 including two test transistors T20 arranged along the second direction Y. The two test transistors T20 in one column are partially positioned opposite each other along the second direction Y. This helps to reduce the size of the two test transistors T20 in one column along the first direction X, thereby allowing for a larger number of test transistors T20 within the fan-out area BB1. This increases the number of data lines on the array substrate, thereby increasing the pixel density of the display panel and enabling a high PPI. Adjacent columns of test transistors T20 are spaced apart along the first direction X, and this allows for the placement of signal lines (such as signal transmission lines 64) between adjacent columns of test transistors T20. This helps to reduce the width of the fan-out area BB1 of the array substrate along the second direction Y, thereby enabling a narrow bezel in the display panel.

[0217] like Figure 16 As shown, the multiple test signal lines 61 can be divided into multiple groups, with each group consisting of two test signal lines 61. Two test transistors T20 in one column are respectively connected to the two test signal lines 61 in one group, and along the first direction X, multiple columns of test transistors T20 are alternately connected to multiple groups of test signal lines 61, which helps to reduce the load on the test signal lines 61.

[0218] For example, such as Figure 16 As shown, the array substrate 100 includes six test signal lines 61, which are divided into three groups. Along the first direction X from left to right, the test transistors T20 in columns 1, 4, ..., (3K+1) are connected to the group of test signal lines 61 closest to the test transistors T20 along the second direction Y; the test transistors T20 in columns 2, 5, ..., (3K+2) are connected to the group of test signal lines 61 located in the middle along the second direction Y; and the test transistors T20 in columns 3, 6, ..., (3K) are connected to the group of test signal lines 61 furthest from the test transistors T20 along the second direction Y. Here, the value of K can be 0 or any positive integer.

[0219] In some embodiments, such as Figure 17As shown, the signal transmission line 64 includes a first region 641, and the first gate line 40 includes a second region 42. The orthographic projections of the first region 641 and the second region 42 on the substrate coincide, meaning that the first region 641 and the second region 42 are the parts of the signal transmission line 64 and the first gate line 40 that overlap in projection, respectively. The first region 641 is provided with a perforated pattern, and / or the second region 42 is provided with a perforated pattern. This reduces the facing area between the first region 641 and the second region 42, reduces the facing area between the signal transmission line 64 and the first gate line 40, and thus reduces the parasitic capacitance between the transmission line 64 and the first gate line 40, and the signal delay on the transmission line 64 and the first gate line 40. The specific pattern type of the perforated pattern can be designed as needed, and the embodiments of this disclosure are not limited in this regard. For example, the first region 641 and the second region 42 can be a mesh structure, or the first region 641 and the second region 42 can include an array of through holes. Of course, the embodiments of this disclosure are not limited to these, as long as the same technical concept is adopted. The number of first gate lines 40 and signal transmission lines 64 included in the array substrate 100 can be adjusted as needed. Figure 17 This is merely an example, and the embodiments disclosed herein are not limited thereto; any embodiment using the same technical approach may be adopted.

[0220] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, The array substrate includes a substrate, the substrate including a display area and a fan-out area adjacent to the display area; wherein, the array substrate further includes: A multi-column pixel circuit is disposed in the display area. The multi-column pixel circuit is arranged along a first direction, and each multi-column pixel circuit includes multiple pixel circuits arranged along a second direction. The first direction intersects the second direction. Multiple data lines are at least partially disposed in the display area and are spaced apart along the first direction. All multiple data lines extend along the second direction, and one data line is connected to a column of pixel circuits. Multiple multiplexed circuits are disposed in the fan-out area, and the multiple multiplexed circuits are arranged in multiple columns along the first direction, with each column including multiple multiplexed circuits arranged along the second direction. Multiple input signal lines are provided in the fan-out area and located on the side of the multiple multiplexing circuits away from the display area, with each input signal line connected to one multiplexing circuit. Multiple output signal line groups are disposed in the fan-out area and located on the side of the multiple multiplexing circuits closer to the display area. Each output signal line group includes multiple output signal lines. The multiple output signal lines included in one output signal line group are connected to the same multiplexing circuit, and each output signal line is connected to a data line. Multiple first gate lines are disposed in the fan-out area and located on the side of the multiple multiplexed circuits away from the display area; Multiple second gate line groups, each second gate line group comprising multiple second gate lines, each second gate line being connected to a first gate line; the multiple second gate lines comprising a second gate line group being connected to a column of multiple multiplexing circuits.

2. The array substrate according to claim 1, characterized in that, Any two adjacent multiplexed circuits in the same column are staggered in the first direction, and the multiplexed circuit closer to the display area is offset to the same side compared to the multiplexed circuit farther from the display area.

3. The array substrate according to claim 2, characterized in that, The two adjacent multiplexed circuits are arranged symmetrically along the first direction.

4. The array substrate according to claim 2, characterized in that, The angle between the line connecting the geometric centers of the outlines of the orthographic projections of any two adjacent multiplexed circuits in the same column onto the substrate and the second direction is α; 4°≤α≤30°.

5. The array substrate according to claim 4, characterized in that, Any two adjacent multiplexed circuits in the same column have a spacing of D1 in the first direction and a spacing of D2 in the second direction; wherein D1, D2, and α satisfy: .

6. The array substrate according to claim 4, characterized in that, The shape of the outline of the orthographic projection of the multiplexing circuit on the substrate is rectangular.

7. The array substrate according to claim 1, characterized in that, The plurality of second gate lines belonging to a second gate line group include a plurality of first sub-lines and a plurality of second sub-lines; The multiplexing circuit includes: Multiple N-type transistors, wherein multiple control electrodes of the multiple N-type transistors are respectively connected to multiple first sub-lines, multiple first electrodes of the multiple N-type transistors are all connected to the input signal lines, and multiple second electrodes of the multiple N-type transistors are respectively connected to multiple output signal lines of the output signal line group; Multiple P-type transistors, wherein multiple control electrodes of the multiple P-type transistors are respectively connected to multiple second sub-lines, multiple first electrodes of the multiple P-type transistors are all connected to the input signal line, and multiple second electrodes of the multiple P-type transistors are respectively connected to multiple output signal lines of the output signal line group; One of the output signal lines is connected to the second terminal of an N-type transistor and the second terminal of a P-type transistor.

8. The array substrate according to claim 7, characterized in that, The N-type transistor and the P-type transistor connected to the same output signal line have the same conduction state.

9. The array substrate according to claim 7, characterized in that, The N-type transistor has the same dimensions as the P-type transistor.

10. The array substrate according to claim 7, characterized in that, The plurality of N-type transistors and the plurality of P-type transistors belonging to the same multiplexing circuit are arranged at intervals along the second direction, and the two ends of the plurality of N-type transistors and the plurality of P-type transistors are respectively flush along the first direction.

11. The array substrate according to claim 10, characterized in that, Any two adjacent multiplexed circuits in the same column are spaced apart in the first direction and also spaced apart in the second direction.

12. The array substrate according to claim 10, characterized in that, Two adjacent multiplexed circuits in the same column are spaced apart along the first direction, and at least a portion of the two multiplexed circuits are arranged opposite each other along the first direction.

13. The array substrate according to claim 12, characterized in that, Multiple N-type transistors and multiple P-type transistors belonging to the same column of two adjacent multiplexing circuits and being closest to each other are arranged opposite each other along the first direction. The multiple N-type transistors belonging to the same column of two adjacent multiplexing circuits have a third spacing in the second direction, and the multiple P-type transistors belonging to the same column of two adjacent multiplexing circuits have a fourth spacing in the second direction.

14. The array substrate according to any one of claims 7 to 13, characterized in that, The first sub-line includes: A plurality of first extension segments, all extending along the second direction, at least one of the first extension segments being configured to form the gate of an N-type transistor; Multiple second extension segments, each extending along the first direction, with each end of a second extension segment connected to a first extension segment. The second sub-line includes: A plurality of third extension segments, each extending along the second direction, and at least one third extension segment being configured to form the gate of a P-type transistor; A plurality of fourth extension segments, each extending along the first direction, and each of the four extension segments having its two ends connected to a third extension segment.

15. The array substrate according to any one of claims 7 to 13, characterized in that, An output signal line group includes three output signal lines, and the multiplexing circuit is connected to the three output signal lines; The multiplexing circuit includes: The P-type semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern disposed at intervals along the first direction; An N-type semiconductor layer includes a third semiconductor pattern and a fourth semiconductor pattern spaced apart along the first direction; The source pattern includes a first source, a second source, and a first connection portion. The first source and the second source are spaced apart along the first direction and both extend along the second direction. The first connection portion is connected to the adjacent ends of the first source and the second source and is connected to the input signal line. The first source is connected to the first semiconductor pattern and the third semiconductor pattern respectively, and the second source is connected to the second semiconductor pattern and the fourth semiconductor pattern respectively. Three drain patterns are spaced apart along the first direction and extend along the second direction; two drain patterns are located on both sides of the first source along the first direction and are connected to the first semiconductor pattern and the third semiconductor pattern; the other drain pattern is arranged side by side with the second source along the first direction and is connected to the second semiconductor pattern and the fourth semiconductor pattern; one drain pattern is connected to an output signal line.

16. The array substrate according to any one of claims 7 to 13, characterized in that, An output signal line group includes two output signal lines, and the multiplexing circuit is connected to the two output signal lines; The multiplexing circuit includes: P-type semiconductor layer, including a fifth semiconductor pattern; An N-type semiconductor layer, including a sixth semiconductor pattern; The source pattern extends along the second direction and is connected to the fifth semiconductor pattern, the sixth semiconductor pattern, and the input signal line; Two drain patterns are located on opposite sides of the source pattern along the first direction, and both drain patterns are connected to the fifth semiconductor pattern and the sixth semiconductor pattern. One drain pattern is connected to an output signal line.

17. The array substrate according to any one of claims 7 to 13, characterized in that, The plurality of N-type transistors and the plurality of P-type transistors belonging to the same multiplexing circuit are arranged at intervals along the second direction, and the plurality of N-type transistors and the plurality of P-type transistors are staggered in the first direction.

18. The array substrate according to claim 17, characterized in that, Along the second direction, portions of the plurality of N-type transistors of the same multiplexing circuit are arranged opposite to portions of the plurality of P-type transistors.

19. The array substrate according to claim 17, characterized in that, The portions of two adjacent multiplexed circuits in the same column are arranged opposite each other along the second direction.

20. The array substrate according to claim 19, characterized in that, Two adjacent multiplexed circuits belonging to the same column, with their nearest N-type transistors and P-type transistors spaced apart along the first direction, and portions of the N-type transistors in the two adjacent multiplexed circuits belonging to the same column arranged opposite each other along the second direction, and portions of the P-type transistors in the two adjacent multiplexed circuits belonging to the same column arranged opposite each other along the second direction.

21. The array substrate according to claim 17, characterized in that, The first sub-line includes: A plurality of fifth extension segments, all extending along the second direction, and one fifth extension segment being configured to form the gate of an N-type transistor; Multiple sixth extension segments, wherein the multiple sixth extension segments form an angle with the first direction, and the two ends of one sixth extension segment are respectively connected to two fifth extension segments; The second sub-line includes: A plurality of seventh extension segments, each of which extends along the second direction, and one seventh extension segment forms the gate of a P-type transistor; A plurality of eighth extension segments, wherein the plurality of eighth extension segments form an angle with the first direction, and the two ends of one of the eighth extension segments are respectively connected to a seventh extension segment.

22. The array substrate according to claim 21, characterized in that, An output signal line group includes four output signal lines, and the multiplexing circuit is connected to the four output signal lines; The multiplexing circuit also includes: The P-type semiconductor layer includes a seventh semiconductor pattern and an eighth semiconductor pattern spaced apart along the first direction; The N-type semiconductor layer includes a ninth semiconductor pattern and a tenth semiconductor pattern spaced apart along the first direction; The source pattern includes a third source, a fourth source, and a second connection portion. The third source and the fourth source are spaced apart along the first direction. The second connection portion is connected to the adjacent ends of the third source and the fourth source and is connected to the input signal line. The third source is connected to the seventh semiconductor pattern and the ninth semiconductor pattern, and the fourth source is connected to the eighth semiconductor pattern and the tenth semiconductor pattern. Four drain patterns are spaced apart along the first direction; two drain patterns are located on both sides of the third source along the first direction and are connected to the seventh semiconductor pattern and the ninth semiconductor pattern; the other two drain patterns are located on both sides of the fourth source along the first direction and are connected to the eighth semiconductor pattern and the tenth semiconductor pattern; one drain pattern is connected to an output signal line.

23. The array substrate according to any one of claims 7 to 13, characterized in that, The channel length of the N-type transistor and the P-type transistor is L, and the source-drain width of the N-type transistor and the P-type transistor is W. SD One of the multiplexing circuits is connected to M output signal lines; a column of multiplexing circuits includes N multiplexing circuits; the spacing between two adjacent pixel circuits along the first direction is P. Pixel In the region where the multiplexing circuit is located, the width of the output signal line along the first direction is W. data The interval between two adjacent output signal lines is S. data Among them, L and W SD M, N, P Pixel W data and S data satisfy: R design For design redundancy, R design The value range is ±5μm.

24. The array substrate according to claim 23, characterized in that, The L and W SD M, N, P Pixel W data and S data It also approximately satisfies:

25. The array substrate according to claim 23, characterized in that, The width-to-length ratio (W / L) of the N-type transistor and the P-type transistor is ≥38μm / 7μm; and / or, The source-drain widths W of the N-type transistor and the P-type transistor SD ≤5μm; and / or, The spacing P between two adjacent pixel circuits along the first direction Pixel ≤7.2μm; and / or, The width W of the output signal line along the first direction data ≤2μm; and / or, The spacing S between two adjacent output signal lines data ≤3.25μm.

26. The array substrate according to claim 1, characterized in that, The width of the input signal line along the first direction is W1, where W1 ≤ 2.5 μm; and / or, The interval between two adjacent input signal lines along the first direction is W2, where W2 ≤ 7.2 μm.

27. The array substrate according to claim 1, characterized in that, Two adjacent multiplexed circuits in the same column are aligned at both ends along the first direction.

28. The array substrate according to claim 27, characterized in that, A column includes two multiplexing circuits, and a multiplexing circuit includes multiple transistors; the multiple transistors are arranged in multiple rows along the second direction, and each row includes at least one transistor.

29. The array substrate according to claim 28, characterized in that, One of the multiplexing circuits includes three transistors; wherein, along the direction close to the display area, the three transistors are arranged in a first row and a second row, the first row including two transistors and the second row including one transistor.

30. The array substrate according to claim 28, characterized in that, One of the multiplexing circuits includes two transistors; the two transistors are arranged in two rows along the second direction, with one transistor in each row.

31. The array substrate according to any one of claims 27 to 30, characterized in that, One of the multiplexing circuits is connected to M output signal lines, where M ≥ 2; The array substrate includes (Q×M) first gate lines, which are divided into Q groups, each group including M first gate lines, where Q≥2; A second group of gate lines is connected to a group of first gate lines, and along the first direction, the plurality of second groups of gate lines are alternately connected to the first group of Q gate lines.

32. The array substrate according to any one of claims 27 to 30, characterized in that, One of the multiplexing circuits is connected to M output signal lines, where M ≥ 2; The array substrate includes (Q×2M) first gate lines, which are divided into Q groups. Each group includes 2M first gate lines, and the 2M first gate lines in each group are divided into M subgroups. Each subgroup includes two first gate lines arranged in parallel, and a second gate line is connected to the two first gate lines of a subgroup; wherein, Q≥2. A second group of gate lines is connected to a group of first gate lines, and along the first direction, the plurality of second groups of gate lines are alternately connected to the first group of Q gate lines.

33. The array substrate according to claim 32, characterized in that, The array substrate further includes a plurality of third connection portions, which are located between two first gate lines of a subgroup and connected to the two first gate lines of the subgroup; the second gate line is connected to the third connection portion.

34. The array substrate according to claim 33, characterized in that, The number of third connections is greater than the number of second gate lines connected to the two first gate lines of a subgroup.

35. The array substrate according to any one of claims 27 to 30, characterized in that, The multiplexing circuit includes multiple transistors; the width-to-length ratio of the channel of the transistor is W / L, where W / L ≥ 180 / 35.

36. The array substrate according to claim 1, characterized in that, The array substrate further includes: Multiple test signal lines, including at least one first test signal line and at least one second test signal line, wherein the first test signal line is farther away from the display area than the second test signal line; At least one third gate line is disposed on the side of the plurality of test signal lines away from the display area; At least one fourth gate line is disposed on the side of the plurality of test signal lines near the display area; Multiple signal transmission lines are arranged at intervals along the first direction. One end of each signal transmission line is configured to be connected to a data line, and the other end is configured to be connected to a driver chip. Multiple first test transistors are disposed between the multiple test signal lines and the third gate line. Along the second direction, the multiple first test transistors are arranged in two rows, and adjacent first test transistors belonging to the two rows are staggered in the first direction. The gate of the first test transistor is connected to the third gate line, the first electrode is connected to a first test signal line, and the second electrode is connected to a signal transmission line. Multiple second test transistors are disposed between the multiple test signal lines and the fourth gate line. Along the second direction, the multiple second test transistors are arranged in two rows, and adjacent second test transistors belonging to the two rows are staggered in the first direction. The gate of the second test transistor is connected to the fourth gate line, the first electrode is connected to a second test signal line, and the second electrode is connected to a signal transmission line.

37. The array substrate according to claim 36, characterized in that, The array substrate has four test signal lines; the two test signal lines farther away from the display area are the first test signal lines, and the two test signal lines closer to the display area are the second test signal lines. The first electrode of the plurality of first test transistors is connected to the two first test signal lines respectively, and along the first direction, the first electrode of the plurality of first test transistors is alternately connected to the two first test signal lines. The first electrode of the plurality of second test transistors is connected to two second test signal lines respectively, and along the first direction, the first electrode of the plurality of second test transistors is alternately connected to two second test signal lines.

38. The array substrate according to claim 1, characterized in that, The array substrate further includes: Multiple test signal lines are provided in the fan-out area; Multiple test transistors are disposed on the side of the multiple test signal lines near the display area and arranged in two rows along the second direction. Each row includes multiple test transistors distributed at intervals along the first direction. Two adjacent test transistors belonging to the two rows are staggered along the first direction. Two fifth gate lines are spaced apart along the second direction. The orthogonal projection of one fifth gate line on the substrate overlaps with the orthogonal projection of a row of test transistors on the substrate and is configured to form the gate of a row of test transistors. Multiple signal transmission lines are arranged at intervals along the first direction. One end of each signal transmission line is configured to be connected to a data line, and the other end is configured to be connected to a driver chip. The first electrode of the test transistor is connected to a test signal line, and the second electrode is connected to a signal transmission line.

39. The array substrate according to claim 38, characterized in that, The plurality of test transistors are arranged in multiple columns along the first direction, each column including two test transistors arranged along the second direction; at least a portion of the two test transistors in a column are arranged opposite each other along the second direction, and adjacent columns of test transistors are spaced apart in the first direction.

40. The array substrate according to claim 38, characterized in that, The multiple test signal lines are divided into multiple groups, with each group including two test signal lines; wherein, two test transistors in one column are respectively connected to the two test signal lines in one group, and along the first direction, multiple columns of test transistors are alternately connected to multiple groups of test signal lines.

41. The array substrate according to any one of claims 36 to 40, characterized in that, The signal transmission line includes a first region, the first gate line includes a second region, and the orthographic projections of the first region and the second region on the substrate coincide. The first area has a hollowed-out pattern, and / or the second area has a hollowed-out pattern.

42. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 41; A cover plate is provided on a first side of the array substrate, wherein the first side is the side of the array substrate from which the pixel circuits are away from the substrate.

43. A display device, characterized in that, include: The display panel as described in claim 42; A driver circuit board, connected to the array substrate of the display panel, is configured to transmit control signals to the array substrate.

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