A compressor-based FPGA approximate multiplier

Abstract

The application provides a compressor-based FPGA approximate multiplier, and belongs to the field of integrated circuits.The compressor-based FPGA approximate multiplier comprises a partial product generation module, which is used for performing AND operation on each bit of a multiplier and each bit of a multiplicand to generate a partial product matrix; a first accurate compression module, which is used for performing first accurate compression on the partial product matrix based on a plurality of grouping carry compressors to obtain a first compressed element matrix; wherein each grouping carry compressor comprises two LUTs; a second approximate compression module, which is used for performing second approximate compression on the first compressed element matrix by using a plurality of LUTs to obtain a second compressed element matrix; and a carry adder module, which is used for determining a product result by using a carry chain of an FPGA according to the second compressed element matrix.The application improves the utilization rate of an FPGA look-up table and reduces the power consumption of the multiplier.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a compressor-based FPGA approximate multiplier. Background Technology

[0002] Approximate computation is a method that optimizes power consumption at the expense of computational accuracy, and it is widely used in fault-tolerant applications such as multimedia processing and machine learning. These applications typically require a large number of multiplication operations, so using approximate multipliers can effectively reduce power consumption.

[0003] In recent years, many scholars have conducted extensive research on approximate multipliers based on Application Specific Integrated Circuits (ASICs), and these designs have achieved significant performance improvements. With the increasing application scope of Field Programmable Gate Arrays (FPGAs), FPGA-based approximate multiplier designs are becoming increasingly attractive. However, due to the structural differences between FPGAs and ASICs, simply transferring previous ASIC-based designs to FPGAs does not yield matching gains. Therefore, designing approximate multipliers that conform to the characteristics of FPGAs is essential. Summary of the Invention

[0004] The purpose of this invention is to provide an FPGA approximate multiplier based on a compressor, which can improve the utilization of the FPGA lookup table and reduce the power consumption of the multiplier.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A compressor-based FPGA approximate multiplier includes:

[0007] The partial product generation module is used to perform a bitwise AND operation between each bit of the multiplier and each bit of the multiplicand to generate a partial product matrix.

[0008] A single-precision compression module, connected to the partial product generation module, is used to perform a single-precision compression on the partial product matrix based on multiple group carry compressors to obtain a single-compressed element matrix; wherein each group carry compressor includes 2 LUTs;

[0009] A secondary approximation compression module, connected to the primary accurate compression module, is used to perform secondary approximation compression on the primary compression element matrix using multiple LUTs to obtain a secondary compression element matrix.

[0010] The carry adder module, connected to the second approximation compression module, is used to determine the product result using the carry chain of the FPGA based on the second compression element matrix.

[0011] Optionally, both the multiplier and the multiplicand are 8-bit binary numbers; the product result is a 16-bit binary number.

[0012] Optionally, the partial product matrix is ​​an 8-row, 15-column matrix, and the elements in the partial product matrix are the partial products obtained by performing a bitwise AND operation between each bit of the multiplier and each bit of the multiplicand.

[0013] Optionally, the first-order compressed element matrix is ​​a 6-row, 15-column matrix;

[0014] The elements of each column of the first-compression element matrix are the exact summation result or carry result determined by the partial product of the corresponding columns of the partial product matrix;

[0015] The two LUTs of the group carry compressor are used to determine the summation result and the carry result based on the partial product of the input, respectively.

[0016] Optionally, the secondary compression element matrix is ​​a 2-row, 15-column matrix; the element in each column of the secondary compression element matrix is ​​an approximate summation result or carry result determined based on the elements of the corresponding column of the primary compression element matrix.

[0017] Optionally, both the LUT in the first-order precise compression module and the LUT in the second-order approximate compression module are 6-input LUTs.

[0018] Optionally, the single-precision compression module includes 14 complete group carry compressors, totaling 32 LUTs.

[0019] Optionally, the quadratic approximation compression module includes 13 LUTs.

[0020] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects: the first-order precise compression module performs first-order precise compression on the partial product matrix based on multiple group carry compressors to obtain a first-order compressed element matrix, which improves the utilization rate of the FPGA lookup table; the second-order approximation compression module uses multiple LUTs to perform second-order approximation compression on the first-order compressed element matrix to obtain a second-order compressed element matrix; the carry adder module determines the product result based on the second-order compressed element matrix using the FPGA carry chain, and adopts a through-type design structure to reduce the power consumption of the multiplier. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of a lookup table (LUT6) with 6 inputs and 1 output;

[0023] Figure 2 A schematic diagram of a 6-input, 2-output lookup table (LUT6_2);

[0024] Figure 3 Structure diagram of LUT6, a 6-input, 1-output lookup table;

[0025] Figure 4 The structure diagram of a 6-input, 2-output lookup table LUT6_2;

[0026] Figure 5 A schematic diagram of a compressor-based FPGA approximate multiplier module provided for this invention;

[0027] Figure 6 The overall structure diagram of the FPGA approximate multiplier based on the compressor provided by the present invention;

[0028] Figure 7 This is a structural diagram of a group carry compressor;

[0029] Figure 8 This is a structural diagram of two adjacent group carry compressors;

[0030] Figure 9 This is a schematic diagram of the LUT distribution in a precise compression module;

[0031] Figure 10 This is a schematic diagram of the LUT distribution in the quadratic approximation compression module;

[0032] Figure 11 This is a structural diagram of a 4-bit carry chain. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Currently, the programmable and reconfigurable structure of FPGAs has garnered increasing attention. A look-up table (LUT) in an FPGA can be understood as a small memory, similar to a dictionary lookup table. It can find the corresponding output value based on the input number or logic signal (INIT value). A 6-input lookup table means that six signals can be input, and the lookup table determines the output signal value based on the combination of these input signals. This allows the logic function of the FPGA to be flexibly programmed and reconfigured as needed. There are two types of 6-input LUTs: LUT6 and LUT6_2, such as... Figure 1 and Figure 2 As shown, its structure is as follows Figure 3 and Figure 4 As shown, Figure 3 and Figure 4 In the diagram, I0 to I5 are the six inputs of LUT6 and LUT6_2, O is the output of LUT6, and O5 and O6 are the outputs of LUT6_2.

[0035] The purpose of this invention is to provide an FPGA-based approximate multiplier using two FPGA-based compressors to design an 8-bit approximate multiplier. The design adopts a pass-through structure to improve resource utilization and reduce power consumption.

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] like Figure 5 As shown, the FPGA approximate multiplier based on a compressor provided by the present invention includes: a partial product generation module 11, a first-order accurate compression module 12, a second-order approximate compression module 13, and a carry adder module 14.

[0038] The partial product generation module 11 performs a bitwise AND operation between each bit of the multiplier and each bit of the multiplicand to generate a partial product matrix. The partial product generation module 11 performs the bitwise AND operation between each bit of the multiplier and each bit of the multiplicand in both the first-order exact compression module 12 and the second-order approximate compression module 13. Specifically, both the multiplier and the multiplicand are 8-bit binary numbers.

[0039] The partial product matrix is ​​an 8x15 matrix. Each element in the partial product matrix is ​​the partial product obtained by performing a bitwise AND operation between each element of the multiplier and each element of the multiplicand.

[0040] The first-precision compression module 12 is connected to the partial product generation module 11. The first-precision compression module 12 is used to perform a first-precision compression on the partial product matrix based on multiple group carry compressors to obtain a first-compressed element matrix.

[0041] The primary compression element matrix is ​​a 6-row, 15-column matrix. Each column of the primary compression element matrix contains an element that is the exact summation result or carry result determined by the partial product of the corresponding column in the partial product matrix. The two LUTs of the grouped carry compressor are used to determine the summation result and the carry result based on the input partial product, respectively.

[0042] In practical circuit operation, designing a multiplier first requires pairwise AND gates to multiply each bit of the input multiplier (A0-A7) with each bit of the multiplicand (B0-B7), generating an 8x15 partial product matrix, such as... Figure 6 As shown, the partial product matrix is ​​then accumulated (compressed). In an FPGA, a LUT is used to compress the partial product matrix, allowing for free combination of input elements and execution of different operations based on the INIT value (written in the hardware code). For example: Figure 2 The input to LUT6_2 consists of four elements: A1, B0, A0, and B1. These input elements can generate two partial products: A1·B0 and A1·B0. 0· B1; A can also be output from a single port. 0· B0 (i.e., the result P0 of the partial product of the first column), the other port outputs A1·B0⊕A 0· B1 (i.e., the result P1 of the partial product summation in the second column). Both operations only use one LUT6_2 and have the same input elements. The former only produces a partial product, while the latter not only produces a partial product but also performs an accumulation calculation on the partial products. This operation can improve the utilization of the input port, thereby reducing the number of LUTs used.

[0043] In order to improve the utilization rate of LUT, the present invention uses a precise group carry compressor in the single precise compression module 12. Figure 2 In P1, only the sum of the partial products in the second column, A1·B0⊕A0·B1, is calculated. However, these two partial products will also produce a carry result, A1·B0·A0. 0· B1, normally this carry result requires an additional LUT to generate and carry over to the 3rd column for calculation. However, the group carry compressor allows this carry to be generated and calculated directly in the next column, such as... Figure 7 As shown.

[0044] Specifically, the group carry compressor divides the carry result of the input element into two half-carry results. One half-carry result is generated in the compressor of the current weight bit, and the other half-carry result is generated in the next adjacent group carry compressor. For example... Figure 8 As shown, in the i-th group carry compressor, X 1(i) X 2(i) and X 3(i) Represents a product of three parts, where X 1(i) and X2(i) It is the grouped part, their carry (C) gr_i The calculation is performed in the (i+1)th block carry compressor. Therefore, a block carry compressor calculates the three partial products (X) of the current weight bit. 1(i) X 2(i) X 3(i) ) and the previous weighted half carry (C) gr_i-1 The exact summation result S i and half-carry result C i Although the carry result calculated by a single group carry compressor is inaccurate, the final carry result is accurate by cascading the compressors.

[0045] The grouping principle of the grouped carry compressor is: the two partial products that can be formed by the input elements of the next column are the grouped parts. For example, if the input elements of the third column are A2, B0, A1, B1, A0, B2, then A2, B0, A0, and B1 can form the partial products A1·B0 and A0·B1 of this column. Therefore, A1·B0 and A0·B1 are the grouped parts. This is equivalent to grouping A1·B0 and A0·B1... 0· Pack B1 together, and only calculate the sum of them in this column (A1·B0⊕A0·B1), and calculate the carry-over result in the next column (A1·B0·A0·B1).

[0046] Figure 9 This demonstrates the inputs and outputs of each LUT in a precise compression module 12, as well as the operations performed. Figure 9 The diagram only shows the processing of the partial product in the first four rows. Since the use of the group carry compressor in the top and bottom four rows is exactly the same, and the omitted middle part performs the same operation as the previous LUT, the group carry compressor generates P0, P1, P2, and S in a single precise compression module 12. i and C i , i = 0~17. Specifically, the single-precision compression module 12 includes 14 complete group carry compressors, each of which includes two 6-input LUTs. The partial product of every 4 rows of the partial product matrix occupies 16 LUTs, for a total of 32 LUTs in the single-precision compression module 12. Table 1 shows the calculation formulas for each LUT in the single-precision compression module 12.

[0047] Table 1. Calculation formulas for each LUT in a single precise compression module.

[0048]

[0049] Figure 6 The gray portion, which was not utilized in the first precise compression module 12, will be generated and compressed in the second approximate compression module 13.

[0050] The second-order approximation compression module 13 is connected to the first-order accurate compression module 12. The second-order approximation compression module 13 is used to perform second-order approximation compression on the first-order compressed element matrix using multiple LUTs to obtain a second-order compressed element matrix.

[0051] The secondary compression element matrix is ​​a 2-row, 15-column matrix. The element in each column of the secondary compression element matrix is ​​an approximate summation result or carry result determined based on the elements of the corresponding column of the primary compression element matrix.

[0052] To simplify the circuit, the quadratic approximation compression module 13 of the present invention uses an approximate equal-weight bit n-2 compressor.

[0053] Let n be the number of elements in the same column of a compressed element matrix. Taking the elements in the 3rd column as an example, S1, C0, and A0B3 are 3 elements, i.e., n = 3. For the elements in the middle part (columns 3 to 11), the arithmetic sum of the n elements is AR. n For: AR n =∑(t1,t2,…,t n ), where ∑ represents the summation operation, t1, t2, ..., t n This represents n elements in the same column.

[0054] By analyzing each column of AR in the middle section n Probability analysis shows that the most likely result is 0-2. Therefore, using two numbers Y1 and Y2 with the same weight, we can approximately calculate the sum S of the n elements in each column. n Sum of carry result C n The design concept is as follows: if one element with a logical value of 1 appears in each column of n elements, then Y1 is 1; if two elements with a logical value of 1 appear, then Y2 is 1, thus ensuring the accuracy of the calculation.

[0055] Y1 = t1 + t2 + ... + t n .

[0056] Y2=t1•(t2+…+t n )+t2•(t3+…+t n )+…+t n-1 •t n .

[0057] S n =Y1⊕Y2.

[0058] C n =Y1·Y2.

[0059] In this context, the symbol “·” represents performing an AND gate operation, “+” represents performing an OR operation, and “⊕” represents performing an XOR operation.

[0060] Figure 10 The diagram illustrates the inputs and outputs of each LUT in the quadratic approximation compression module 13, along with the computational operations performed. Since a 6-input LUT can only have a maximum of 6 inputs, and the LUTs in columns 7 to 10 have 6 or more inputs, to ensure that the number of LUT ports occupied by each n-2 compressor is within 6, three additional 6-input LUTs are used to generate partial products pp0 to pp5 of A0B7, A4B3, A1B7, A2B7, A7B3, and A3B7, thus reducing the number of ports used. For example, A0B7 originally occupied two ports, but after being converted to pp0, it only occupies one port. Therefore, the quadratic approximation compression module 13 requires a total of 13 LUTs. Table 2 shows the computational formulas for each LUT in the quadratic approximation compression module 13.

[0061] Table 2. Calculation formulas for each LUT in the quadratic approximation compression module.

[0062]

[0063] It should be noted that, Figure 9 and Figure 10 There are no requirements for the placement of LUT6 and LUT6_2. Figure 9 and Figure 10 It's just to help me understand better.

[0064] Due to the structural characteristics of LUTs in FPGAs, each input can achieve different logic combinations and operation results based on different INIT values. Therefore, in FPGAs, the partial product generation stage and the partial product compression stage can be performed simultaneously. That is, the partial product generation stage is performed simultaneously in the partial product generation module 11 and the compression module (first-order accurate compression module 12 and second-order approximate compression module 13).

[0065] The carry adder module 14 is connected to the quadratic approximation compression module 13. The carry adder module 14 is used to determine the product result based on the quadratic compression element matrix and the carry chain of the FPGA. Specifically, the product result is a 16-bit binary number.

[0066] After two compressions, the partial product matrix is ​​compressed into two rows. Therefore, the final result can be directly obtained through the carry chain of the FPGA. When performing addition or multiplication operations in the FPGA, the structure of the 4-bit carry chain is as follows: Figure 11 As shown, it effectively transmits and processes carry signals through a cascaded circuit structure. The carry propagation chain's function is to pass the carry signal generated by each bit to the next bit, performing continuous carry operations at each bit, equivalent to a carry predictor adder. Figure 11 As shown in the carry chain structure, a 4-bit carry chain has four sets of inputs, O5 and O6. O5 is the carry generation signal, and O6 is the carry propagation signal. Typically, O5 performs an AND operation on the two inputs, and O6 performs an XOR operation on the two inputs. Figure 11 In the diagram, AX, BX, CX, and DX represent bypass signals, and each FA represents the execution of a full adder operation.

[0067] In the carry adder module 14, three carry chains are used to determine the product result. Since O5 and O6 in the middle part (columns 3 to 11) can be directly generated by the n-2 compressor, only three LUTs in columns 12 to 14 need to be added in the carry adder module 14.

[0068] The middle part, O5 and O6, is: O5 = S n =Y 1,i ·Y 2,i O6 = C n =Y 1,i ⊕Y 2,i (i = 3, 4, ..., 11).

[0069] In column 12, O5 and O6 are: O5 = S 16 ·C 15 O6 = S 16 ⊕C 15 .

[0070] In column 13, O5 and O6 are: O5 = S 17 ·C 16 O6 = S 17 ⊕C 16 .

[0071] In column 14, O5 and O6 are: O5 = A7B7·C 17 O6 = A7B7⊕C 17 .

[0072] Figure 6 In the middle, P 15 =C out ,pass Figure 11 C on the carry chain out This is directly obtained, equivalent to the carry output port of a full adder. On the FPGA, the carry result is directly output by recursively calculating the previous carry.

[0073] The FPGA approximate multiplier based on a compressor provided by this invention performs a first precise compression using a group carry compressor, and generates results P0, P1, P2, and S using 32 LUTs. i and C iFor i = 0 to 17, the partial product matrix to be processed is reduced from 8 rows to 6 rows. Then, a second approximate compression is performed using an n-2 compressor, and the result Y is generated using 13 LUTs. 1,i ·Y 2,i and Y 1,i ⊕Y 2,i For i = 3 to 11, the partial product matrix to be processed is reduced from 6 rows to 2 rows. Finally, 3 carry chains are used to add 3 LUTs to produce a 16-bit output result, occupying a total of 48 LUTs.

[0074] Compared to FPGA-based exact multipliers, the approximate multiplier provided by this invention reduces power consumption by 46.15%, area by 32.39%, and critical path delay by 16.87%. Within the same accuracy range, the hardware performance of this invention is significantly superior to other existing designs. First, the compressor provided by this invention enables independent parallel operations between multiple lookup tables, reducing the correlation between individual circuit units and significantly improving the utilization of LUT ports. Therefore, the circuit area and power consumption can be optimized. Second, the multiplier provided by this invention employs a pass-through design structure, requiring fewer carry chains than other iterative design structures, thus effectively reducing latency and power consumption.

[0075] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A compressor-based FPGA approximate multiplier, characterized in that, The compressor-based FPGA approximate multiplier includes: The partial product generation module is used to perform a bitwise AND operation between each bit of the multiplier and each bit of the multiplicand to generate a partial product matrix. A single-precision compression module, connected to the partial product generation module, is used to perform single-precision compression on the partial product matrix based on multiple group carry compressors to obtain a single-precision compressed element matrix. Each group carry compressor includes two LUTs. The single-precision compressed element matrix is ​​a 6x15 matrix. Each column of the single-precision compressed element matrix contains elements that are either the exact summation result or the carry result determined by the partial product of the corresponding column in the partial product matrix. The two LUTs of each group carry compressor are used to determine the summation result and the carry result based on the input partial products, respectively. The grouping principle of the group carry compressor is: which two partial products in the next column can form the current column's partial product? These two partial products are the grouped parts. The single-precision compression module includes 14 complete group carry compressors, each including two 6-input LUTs. Every four rows of partial product in the partial product matrix occupy 16 LUTs, for a total of 32 LUTs in the single-precision compression module. A secondary approximation compression module, connected to the primary accurate compression module, is used to perform secondary approximation compression on the primary compression element matrix using multiple LUTs to obtain a secondary compressed element matrix; the secondary compressed element matrix is ​​a 2-row, 15-column matrix; the element of each column of the secondary compressed element matrix is ​​an approximate summation result or carry result determined based on the elements of the corresponding column of the primary compressed element matrix; The carry adder module, connected to the second approximation compression module, is used to determine the product result using the carry chain of the FPGA based on the second compression element matrix.

2. The FPGA approximate multiplier based on a compressor according to claim 1, characterized in that, Both the multiplier and the multiplicand are 8-bit binary numbers; the product is a 16-bit binary number.

3. The FPGA approximate multiplier based on a compressor according to claim 2, characterized in that, The partial product matrix is ​​an 8-row, 15-column matrix, and the elements in the partial product matrix are the partial products obtained by performing a bitwise AND operation between each bit of the multiplier and each bit of the multiplicand.

4. The FPGA approximate multiplier based on a compressor according to claim 1, characterized in that, The second approximate compression module includes 13 LUTs.

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