A method for designing an FIR digital filter for intermediate frequency sampling

Abstract

The present application relates to a kind of FIR digital filter design method for intermediate frequency sampling, according to the theoretical range of bandpass sampling theorem to give sampling frequency;According to the frequency spectrum position relationship of signal after sampling, mirror frequency and its periodic continuation component, determine the initial value of optimal sampling frequency;FIR digital filter design is carried out, and the filter order, single-side roll-off bandwidth, out-of-band rejection ratio are obtained;Whether the number of FPGA multiplier required by filtering operation can be satisfied is evaluated;Expand signal bandwidth, re-evaluate whether the signal after expanding bandwidth meets the requirement of bandpass sampling theorem, if necessary, adjust the out-of-band rejection ratio parameter, cutoff frequency parameter, redesign FIR digital filter, to reduce single-side roll-off bandwidth, until the requirement is met, iteration optimal sampling frequency;Carry out digital filtering trial.The present application can give the optimal FIR digital filter design within the limit of theoretical requirement and engineering non-ideal dual constraints.

Description

Technical Field

[0001] This invention belongs to the field of signal processing technology and relates to a design method for an FIR digital filter oriented towards intermediate frequency sampling. Background Technology

[0002] Receivers in microwave systems typically require analog-to-digital (A / D) sampling of intermediate frequency (IF) signals or low-carrier frequency (RF) signals for digitization. After sampling, the digitized IF signal undergoes digital quadrature demodulation to obtain I and Q baseband signals. The digital quadrature demodulation process includes a digital low-pass filter, which is commonly implemented in engineering by performing a time-domain convolution operation between the signal to be processed and an FIR digital filter.

[0003] The design process of an FIR digital filter mainly involves six types of parameters: sampling frequency, pass frequency, cutoff frequency, in-band flatness, out-of-band rejection ratio, and order. FIR digital filter design can be carried out using tools such as fdatool or filterDesigner in MATLAB software. The key to the design is the proper setting of these parameters.

[0004] Among these factors, the sampling frequency parameter not only affects the filter design results but is also crucial for ensuring distortion-free AD sampling of intermediate frequency (IF) signals. IF signals or low-carrier RF signals are generally bandpass signals, and theoretically, the sampling frequency must meet the requirements of the bandpass sampling theorem. In addition to the theoretical factors mentioned above, the sampling frequency also needs to consider the influence of many non-ideal factors, such as FPGA multiplier resources and FIR filter roll-off bandwidth. If only the bandpass sampling theorem theory is considered while ignoring the impact of non-ideal factors in engineering, two problems may arise: first, the range of sampling frequencies that meet theoretical requirements may be very wide, but may not achieve optimal engineering performance in terms of signal-to-noise isolation and FPGA resource usage; second, the sampling frequency may theoretically meet the requirements, but due to the deterioration caused by non-ideal factors in engineering, the actual performance may not meet the requirements or the required FPGA resources may exceed expectations.

[0005] Furthermore, the pass frequency and cutoff frequency together determine the single-sided roll-off bandwidth of the filter. The single-sided roll-off bandwidth refers to the roll-off process that occurs between the pass frequency and the cutoff frequency, unlike the abrupt rectangular window change of an ideal filter. In-band flatness refers to the amplitude flatness within the filter's passband, which can generally be set according to requirements, for example, 1dB or 0.5dB. Out-of-band rejection ratio (OCR) refers to the ratio of the amplitude reduction outside the passband to the amplitude reduction within the passband, mainly characterizing the filtering capability for suppressing signals outside the passband. It can generally be set according to requirements, for example, 60dB or 80dB. The order refers to the length of the filter's digital sequence. Filtering operations are mainly convolution operations, usually performed on an FPGA processing board. Considering the symmetry of FIR filters about zeros, the number of FPGA multipliers required for the operation is no less than half the filter's order. Therefore, the order characterizes the FPGA multiplier resource requirements for filtering operations. The higher the filter order, the smaller the roll-off bandwidth, the larger the out-of-band rejection ratio, the better the filter performance, and the closer it is to an ideal filter. However, the more FPGA multiplier resources are required for the operation.

[0006] In summary, the design of FIR digital filters requires consideration of parameters such as sampling frequency, pass frequency, cutoff frequency, in-band flatness, out-of-band rejection ratio, and order. These parameters must satisfy theoretical requirements such as the bandpass sampling theorem, while also balancing the influence of non-ideal factors and practical resource constraints. Furthermore, there are trade-offs among these parameters; for example, given a fixed order, a smaller roll-off bandwidth (closer to an ideal filter) results in a worse out-of-band rejection ratio. Therefore, in FIR digital filter design, it is necessary to further optimize relevant parameters beyond meeting theoretical requirements to maximize the suppression of non-ideal factors and achieve a balance between multiple parameters and performance needs within practical resource constraints. Summary of the Invention

[0007] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose an FIR digital filter design method for intermediate frequency sampling. It takes into account the influence of theoretical and engineering factors such as bandpass sampling theorem, filter roll-off bandwidth, FPGA multiplier resource limitations, and actual out-of-band suppression effect after filtering. It can provide the optimal FIR digital filter design within the constraints of both theoretical requirements and engineering non-idealities.

[0008] The solution to the technical problem of this invention is: a design method for an FIR digital filter oriented towards intermediate frequency sampling, comprising the following steps: (1) According to the bandpass sampling theorem, give the theoretical range of sampling frequency; (2) Determine the initial value of the optimal sampling frequency based on the spectral position relationship between the sampled signal, the image frequency and its periodic extension components; (3) Use the fdatool or filterDesigner tool in MATLAB software to design FIR digital filters and obtain the filter order, single-sided roll-off bandwidth, and out-of-band rejection ratio parameters. (4) Based on the design results of the FIR digital filter, evaluate whether the number of FPGA multipliers required for the filtering operation can be met; (5) Based on the single-sided roll-off bandwidth in the FIR digital filter design results, expand the signal bandwidth and re-evaluate whether the sampling frequency range meets the requirements of the bandpass sampling theorem relative to the signal after the bandwidth expansion. If it meets the requirements, obtain the optimal sampling frequency after iteration and proceed to step (7). If it does not meet the requirements, proceed to step (6). (6) Adjust the out-of-band rejection ratio and cutoff frequency parameters, and redesign the FIR digital filter to reduce the single-sided roll-off bandwidth until the sampling frequency range satisfies the bandpass sampling theorem requirement relative to the signal after the bandwidth expansion, and obtain the optimal sampling frequency after iteration. (7) Generate a random signal with the same number of sampling points as the signal to be filtered, filter it using the designed FIR digital filter, and check whether the out-of-band rejection ratio after filtering meets the requirements. If it does, the design of the FIR digital filter is complete. If it does not, adjust the out-of-band rejection ratio parameter and redesign the FIR digital filter until the filter order reaches the upper limit of the FPGA multiplier resource allowance or the actual out-of-band rejection effect after filtering meets the requirements.

[0009] Furthermore, the theoretical range of the sampling frequency is: For a frequency band limited to Time-continuous real signal within When the sampling frequency satisfy , This theoretically ensures the signal Its periodic extension component and its mirror frequency periodic extension component do not overlap in the frequency domain; among which Not greater than The largest positive integer.

[0010] Furthermore, the initial value of the optimal sampling frequency is obtained by solving the following equation:

[0011] The equation obtained by this constraint is The value is the initial value of the optimal sampling frequency.

[0012] Furthermore, the method for evaluating whether the number of FPGA multipliers required for the filtering operation can be met is as follows: the digital filtering operation is performed on the FPGA processing board, and the number of FPGA multipliers required for the filtering operation is not less than half of the filter order. If the requirement is met, proceed to the next step; if the requirement is not met, the cutoff frequency parameter needs to be gradually increased, and the FIR digital filter needs to be redesigned according to step (3) to obtain the filter order until half of the filter order does not exceed the number of multipliers that the FPGA processing board can provide.

[0013] Furthermore, the evaluation method for step (5) is as follows: Let the pass frequency of the filter design result be... Cutoff frequency is Then the one-sided roll-off bandwidth of the filter is Based on this, the signal bandwidth is extended to the left and right by one filter single-sided roll-off bandwidth, that is, the signal frequency band is extended from... Expand to Then, re-evaluate whether the sampling frequency range satisfies the bandpass sampling theorem relative to the signal after the bandwidth extension, following the method in step (1).

[0014] Furthermore, in step (6), when redesigning the FIR digital filter, it is necessary to reduce the out-of-band rejection ratio (OUTR) parameter to lower the cutoff frequency, provided that half of the filter order does not exceed the number of FPGA multipliers used for filtering operations. The purpose of the parameters; when the cutoff frequency... After the parameters are reduced, the one-sided roll-off bandwidth of the filter is reduced. Reduce; thus, by continuously lowering the out-of-band rejection ratio parameter, the one-sided roll-off bandwidth of the filter is continuously reduced. Continue until the requirements of the evaluation method in step (5) are met.

[0015] Furthermore, in step (7) when redesigning the FIR digital filter: evaluate whether half of the current filter order is less than the number of FPGA multipliers for filtering operations. If it is not less, the filter maintains the original design and the design ends; if it is less, increase the filter out-of-band rejection ratio parameter and redesign the FIR digital filter according to step (3) until half of the filter order is equal to the number of FPGA multipliers for filtering operations, or the out-of-band rejection effect after actual filtering meets the requirements and the design ends.

[0016] An FIR digital filter for intermediate frequency sampling is provided, wherein the filter is designed according to the aforementioned design method for an FIR digital filter for intermediate frequency sampling.

[0017] The advantages of this invention compared to the prior art are: (1) The FIR digital filter design method proposed in this invention for intermediate frequency sampling fully considers the influence of various factors such as bandpass sampling theorem, filter roll-off bandwidth, FPGA multiplier resource limitation, and actual out-of-band suppression effect after filtering. It can provide the optimal FIR digital filter design under multiple constraints.

[0018] (2) The FIR digital filter design method for intermediate frequency sampling proposed in this invention not only satisfies the requirements of the bandpass sampling theorem when setting the sampling frequency parameters, but also focuses on the influence of the filter roll-off bandwidth. That is, considering that the non-ideal characteristics of the filter (the roll-off process exists from in-band to out-of-band, rather than the abrupt change of the rectangular window of the non-ideal filter) will cause signal energy to leak within the roll-off bandwidth, the setting of the sampling frequency must not only ensure that the "signal" and the "periodic extension component of the signal and the periodic extension component of the signal image frequency" do not overlap in the frequency domain, but also ensure that the "signal + roll-off bandwidth" and the "periodic extension component of the signal + roll-off bandwidth and the periodic extension component of the signal image frequency + roll-off bandwidth" do not overlap in the frequency domain.

[0019] (3) The FIR digital filter design method for intermediate frequency sampling proposed in this invention can perform design iterations according to the priority of "first ensuring feasibility, then ensuring main performance, and finally ensuring secondary performance" under multiple constraints. First ensuring feasibility means ensuring that the design order of the FIR digital filter matches the number of multipliers that the FPGA processing board can provide, without exceeding the hardware computing resource constraints; second ensuring main performance means ensuring that the sampling frequency parameters can still guarantee non-aliasing sampling even under the non-ideal condition of the filter having roll-off bandwidth; and finally ensuring secondary performance means pursuing better out-of-band rejection ratio performance within the allowable range of FPGA multiplier resources, provided that feasibility and non-aliasing sampling are achieved.

[0020] (4) The FIR digital filter design method for intermediate frequency sampling proposed in this invention is not limited to the filter's own parameters and performance, but also considers the actual filtering effect. That is, by constructing a random signal with the same number of sampling points as the signal to be filtered, the designed FIR digital filter is tested, the out-of-band rejection ratio performance after actual filtering is statistically analyzed, and the FIR digital filter is improved based on this until the out-of-band rejection ratio performance of the actual filtering meets the requirements or the multiplier resources required by the filter reach the upper limit of the constraint. Attached Figure Description

[0021] Figure 1 This represents the spectral positional relationship between the sampled signal, the image frequency, and its periodic extension components. Figure 2 A comparison of the amplitude-frequency curves of a "real filter" and an "ideal filter"; Figure 3The amplitude-frequency curve of signal A (4096 snapshot sampling points); Figure 4 The amplitude-frequency curve of signal A (4096 snapshot sampling points) after filtering; Figure 5 The amplitude-frequency curve of signal B (128 snapshot sampling points); Figure 6 The amplitude-frequency curve of signal B (128 snapshot sampling points) after filtering; Figure 7 This is a flowchart of a design method for an FIR digital filter oriented towards intermediate frequency sampling. Detailed Implementation

[0022] This invention aims to quantify the impact of non-ideal factors in engineering practice within the framework of meeting theoretical requirements, and provides a design method for FIR digital filters oriented towards intermediate frequency sampling under the dual constraints of theoretical requirements and engineering non-ideals. The specific implementation steps are as follows: (1) According to the bandpass sampling theorem, give the theoretical range of sampling frequency; (2) Determine the initial value of the optimal sampling frequency based on the spectral position relationship between the sampled signal, the image frequency and its periodic extension components; (3) Use the fdatool or filterDesigner tool in MATLAB software to design FIR digital filters and obtain the filter order, single-sided roll-off bandwidth, and out-of-band rejection ratio parameters. (4) Based on the design results of the FIR digital filter, evaluate whether the number of FPGA multipliers required for the filtering operation can be met; (5) Based on the single-sided roll-off bandwidth in the FIR digital filter design results, expand the signal bandwidth and re-evaluate whether the sampling frequency range meets the requirements of the bandpass sampling theorem relative to the signal after the bandwidth expansion. If it meets the requirements, obtain the optimal sampling frequency after iteration and proceed to step (7). If it does not meet the requirements, proceed to step (6). (6) Adjust the out-of-band rejection ratio and cutoff frequency parameters, and redesign the FIR digital filter to reduce the single-sided roll-off bandwidth until the sampling frequency range satisfies the bandpass sampling theorem requirement relative to the signal after the bandwidth expansion, and obtain the optimal sampling frequency after iteration. (7) Generate a random signal with the same number of sampling points as the signal to be filtered, filter it using the designed FIR digital filter, and check whether the out-of-band rejection ratio after filtering meets the requirements. If it does, the design of the FIR digital filter is complete. If it does not, adjust the out-of-band rejection ratio parameter and redesign the FIR digital filter until the filter order reaches the upper limit of the FPGA multiplier resource allowance or the actual out-of-band rejection effect after filtering meets the requirements.

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Example 1 like Figure 7 As shown in the figure, the FIR digital filter design method for intermediate frequency sampling proposed in this embodiment includes the following steps: Step 1: According to the bandpass sampling theorem, give the theoretical range of the sampling frequency.

[0025] In theory, for a frequency band limited to Time-continuous real signal within If the sampling frequency Meet the conditions ( In theory, the original signal can be reconstructed without distortion from the sampled sequence. ,in Not greater than The largest positive integer. In other words, satisfying ( Sampling frequency under certain conditions The signal can be theoretically guaranteed. Its periodic extension component and its mirror frequency periodic extension component do not overlap in the frequency domain, such as Figure 1 As shown.

[0026] Step 2: Determine the initial value of the optimal sampling frequency based on the spectral position relationship of the sampled signal, the image frequency, and its periodic extension components.

[0027] The bandpass sampling theorem provides a range of sampling frequencies, not a specific optimal value. Under purely ideal conditions, all values ​​satisfying bandpass sampling guarantee that the sampled signal will not be aliased. However, in reality, the signal is not ideally truncated in frequency during filtering (FIR digital filters have non-ideal characteristics such as roll-off bandwidth; that is, actual filters have a roll-off process from the "pass frequency" to the "cutoff frequency," unlike the abrupt rectangular window transition of ideal filters, such as...). Figure 2 As shown in the figure, even when sampling according to the bandpass sampling theorem, there will still be a small amount of aliasing, and the degree of aliasing will vary with the sampling frequency. Therefore, among all sampling frequency values ​​that satisfy the bandpass sampling theorem, an optimal sampling frequency that minimizes the degree of aliasing should be selected.

[0028] Since the frequency domain function of a real signal is an even function, its spectrum is symmetrical about zero frequency, meaning it has a mirror frequency. After discretization and sampling, the spectrum of a continuous signal will exhibit a periodic extension component; the extension period is the sampling frequency. The optimal sampling frequency aims to maximize the frequency domain distance between the main signal, the image frequency signal, and the periodic extension components, ensuring maximum non-aliasing even under non-ideal conditions where the filter has roll-off bandwidth. If the periodic extension components, the image frequency, and their extension components are considered interference, then interference exists on both sides of the frequency axis, and the frequency domain distances between the signal and the interference on either side are inversely related. To maximize the distance between the signal and the interference, the distances on both sides can be made equal, i.e., (as shown in the example). Figure 2 (The situation shown is an example) The equation obtained by applying this constraint is The value is the initial value of the optimal sampling frequency.

[0029] Step 3: Design an FIR digital filter using the fdatool or filterDesigner tool in MATLAB software.

[0030] Several sets of parameters are interrelated in filter design: sampling frequency, single-sided roll-off bandwidth (represented by the pass frequency and cutoff frequency), in-band flatness, and out-of-band rejection ratio. Using the fdatool or filterDesigner tools in MATLAB to design FIR digital filters mainly involves setting these parameters. Specifically, the sampling frequency is set to the value determined in step 2. The value is set by the frequency to half the signal bandwidth, and the cutoff frequency can be set according to actual needs (for example, it can generally be set to no more than...). Figure 2 middle The in-band flatness is set according to actual needs (e.g., it can generally be set to 1dB or 0.5), and the out-of-band suppression ratio is set according to actual needs (e.g., it can generally be initially set to 60dB or 80dB). After the above parameters are initially set, the design is carried out using the fdatool or filterDesigner tools in MATLAB software. The design will output the FIR digital filter coefficients (i.e., the digital sequence used in the actual filtering operation) and the order.

[0031] Step 4: Based on the FIR digital filter design results, evaluate whether the number of FPGA multipliers required for the filtering operation can be met.

[0032] Digital filtering operations are typically performed on an FPGA processing board, and the number of FPGA multipliers required for filtering operations is usually no less than half the filter order. Therefore, it is necessary to evaluate whether the number of available FPGA multipliers is sufficient to meet the filtering operation requirements.

[0033] If the requirements are met, proceed to the next step.

[0034] If the requirements are not met, the cutoff frequency parameter needs to be gradually increased, and the FIR digital filter needs to be redesigned according to step 3 to obtain the filter order (the filter order will decrease as the cutoff frequency increases) until half of the filter order does not exceed the number of multipliers that the FPGA processing board can provide.

[0035] Step 5: Based on the single-sided roll-off bandwidth in the FIR digital filter design results, expand the signal bandwidth and re-evaluate whether the sampling frequency range meets the requirements of the bandpass sampling theorem relative to the signal after the bandwidth expansion.

[0036] Let the pass frequency of the filter design result be... Cutoff frequency is Then the one-sided roll-off bandwidth of the filter is Based on this, the signal bandwidth is extended to the left and right by one filter single-sided roll-off bandwidth, that is, the signal frequency band is extended from... Expand to Then, re-evaluate whether the sampling frequency range satisfies the bandpass sampling theorem relative to the signal after the bandwidth extension, following the method in step 1.

[0037] If the conditions are met, the optimal sampling frequency after iteration is obtained, and the process proceeds to step 7; otherwise, the process proceeds to step 6.

[0038] Step 6: Adjust the out-of-band rejection ratio and cutoff frequency parameters, and redesign the FIR digital filter to reduce the single-sided roll-off bandwidth until the sampling frequency range satisfies the bandpass sampling theorem requirements relative to the signal after the bandwidth extension, and obtain the optimal sampling frequency after iteration.

[0039] When the bandpass sampling theorem requirement is not met, the filter is redesigned according to the method in step 3. During the design, while ensuring that half the filter order does not exceed the number of FPGA multipliers used for filtering operations, the out-of-band rejection ratio (OUTR) parameter is reduced to lower the cutoff frequency. The purpose of the parameters (a lower out-of-band rejection ratio (OCR) parameter results in a lower filter order; a lower cutoff frequency parameter results in a higher filter order. Therefore, while ensuring the filter order is within a certain limit, the cutoff frequency parameter can be changed by balancing the OCR parameter). When the cutoff frequency... After the parameters are reduced, the one-sided roll-off bandwidth of the filter is reduced. Reduce. Thus, by continuously reducing the out-of-band rejection ratio parameter, the one-sided roll-off bandwidth of the filter is continuously reduced. Continue until the evaluation requirements of the method in step 5 are met.

[0040] Step 7: Conduct trial use of the digital filter, adjust the out-of-band rejection ratio parameter if necessary, and redesign the FIR digital filter.

[0041] A random signal with the same number of sampling points as the signal to be filtered is generated, and then filtered using the designed FIR digital filter. The out-of-band rejection ratio (OCR) performance after actual filtering is statistically analyzed. The essence of digital filtering is the convolution operation between the signal to be filtered (a digital sequence of length X) and the filter (a digital sequence of length Y). If X is much larger than Y, the actual OCR effect after filtering is comparable to the filter's OCR parameter, such as... Figure 3 , 4 As shown. If X is less than Y or roughly equal to Y, the actual out-of-band rejection after filtering is far less than the filter's out-of-band rejection ratio parameter, such as... Figure 5 , 6 As shown, if this situation occurs, it is necessary to increase the out-of-band rejection ratio (OSR) parameter of the filter and redesign the FIR digital filter. The specific method is as follows: Evaluate whether half of the current filter order is less than the number of FPGA multipliers available for filtering operations. If it is not less, the filter maintains its original design (due to FPGA multiplier resource limitations, the filter performance cannot be further improved, and the design ends); if it is less, increase the filter's out-of-band rejection ratio parameter and redesign the FIR digital filter according to step 3 until half of the filter order is equal to the number of FPGA multipliers available for filtering operations (due to FPGA multiplier resource limitations, the filter performance cannot be further improved, and the design ends) or the actual out-of-band rejection effect after filtering meets the requirements (achieving filtering performance, and the design ends).

[0042] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

[0043] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A design method for an FIR digital filter oriented towards intermediate frequency sampling, characterized in that, Includes the following steps: (1) According to the bandpass sampling theorem, give the theoretical range of sampling frequency; (2) Determine the initial value of the optimal sampling frequency based on the spectral position relationship between the sampled signal, the image frequency and its periodic extension components; (3) Use the fdatool or filterDesigner tool in MATLAB software to design FIR digital filters and obtain the filter order, single-sided roll-off bandwidth, and out-of-band rejection ratio parameters. (4) Based on the design results of the FIR digital filter, evaluate whether the number of FPGA multipliers required for the filtering operation can be met; (5) Based on the single-sided roll-off bandwidth in the FIR digital filter design results, expand the signal bandwidth and re-evaluate whether the sampling frequency range meets the requirements of the bandpass sampling theorem relative to the signal after the bandwidth expansion. If it meets the requirements, obtain the optimal sampling frequency after iteration and proceed to step (7). If it does not meet the requirements, proceed to step (6). (6) Adjust the out-of-band rejection ratio and cutoff frequency parameters, and redesign the FIR digital filter to reduce the single-sided roll-off bandwidth until the sampling frequency range satisfies the bandpass sampling theorem requirement relative to the signal after the bandwidth expansion, and obtain the optimal sampling frequency after iteration. (7) Generate a random signal with the same number of sampling points as the signal to be filtered, filter it using the designed FIR digital filter, and check whether the out-of-band rejection ratio after filtering meets the requirements. If it does, the design of the FIR digital filter is complete. If it does not, adjust the out-of-band rejection ratio parameter and redesign the FIR digital filter until the filter order reaches the upper limit of the FPGA multiplier resource allowance or the actual out-of-band rejection effect after filtering meets the requirements.

2. The FIR digital filter design method for intermediate frequency sampling according to claim 1, characterized in that, The theoretical range of the sampling frequency is: For a frequency band limited to Time-continuous real signal within When the sampling frequency satisfy , This theoretically ensures the signal Its periodic extension component and its mirror frequency periodic extension component do not overlap in the frequency domain; among which Not greater than The largest positive integer.

3. The FIR digital filter design method for intermediate frequency sampling according to claim 2, characterized in that, The initial value of the optimal sampling frequency is obtained by solving the following formula: The equation obtained by this constraint is The value is the initial value of the optimal sampling frequency.

4. The FIR digital filter design method for intermediate frequency sampling according to claim 1, characterized in that, The method for evaluating whether the number of FPGA multipliers required for the filtering operation can be met is as follows: the digital filtering operation is performed on the FPGA processing board, and the number of FPGA multipliers required for the filtering operation is not less than half of the filter order. If the requirement is met, proceed to the next step; if the requirement is not met, the cutoff frequency parameter needs to be gradually increased, and the FIR digital filter needs to be redesigned according to step (3) to obtain the filter order until half of the filter order does not exceed the number of multipliers that the FPGA processing board can provide.

5. The FIR digital filter design method for intermediate frequency sampling according to claim 2, characterized in that, The specific evaluation method for step (5) is as follows: Let the pass frequency of the filter design result be... Cutoff frequency is Then the one-sided roll-off bandwidth of the filter is Based on this, the signal bandwidth is extended to the left and right by one filter single-sided roll-off bandwidth, that is, the signal frequency band is extended from... Expand to Then, re-evaluate whether the sampling frequency range satisfies the bandpass sampling theorem relative to the signal after the bandwidth extension, following the method in step (1).

6. The FIR digital filter design method for intermediate frequency sampling according to claim 5, characterized in that, When redesigning the FIR digital filter in step (6), it is necessary to reduce the out-of-band rejection ratio (OUTR) parameter to lower the cutoff frequency, provided that half of the filter order does not exceed the number of FPGA multipliers used for filtering operations. The purpose of the parameters; when the cutoff frequency... After the parameters are reduced, the one-sided roll-off bandwidth of the filter is reduced. Reduce; thus, by continuously lowering the out-of-band rejection ratio parameter, the one-sided roll-off bandwidth of the filter is continuously reduced. Continue until the requirements of the evaluation method in step (5) are met.

7. The FIR digital filter design method for intermediate frequency sampling according to claim 5, characterized in that, When redesigning the FIR digital filter in step (7): evaluate whether half of the current filter order is less than the number of FPGA multipliers for filtering operations. If it is not less, the filter maintains the original design and the design ends. If it is less, increase the filter out-of-band rejection ratio parameter and redesign the FIR digital filter according to step (3) until half of the filter order is equal to the number of FPGA multipliers for filtering operations, or the out-of-band rejection effect after actual filtering meets the requirements and the design ends.

8. A FIR digital filter for intermediate frequency sampling, characterized in that, The filter is designed using an FIR digital filter design method for intermediate frequency sampling according to any one of claims 1 to 7.

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