Voltage buffer and display device

Abstract

The application provides a voltage buffer and a display device, relates to the technical field of display, and the voltage buffer comprises a first input end, a second input end, a first output end, an amplifier, a driving tube, a first compensation module and a second compensation module; the second input end is connected with a positive electrode end of the amplifier and is used for receiving a first driving voltage; the first compensation module is used for making a primary point between the amplifier and the driving tube and a secondary point at the first output end; two ends of the first compensation module are respectively connected with an input end of the driving tube and an output end of the driving tube; the second compensation module is used for inputting an output signal of the driving tube to a negative electrode end of the amplifier; two ends of the second compensation module are respectively connected with an input end of the amplifier and an output end of the driving tube; and the first output end is connected with the output end of the driving tube and is used for outputting a second driving voltage after voltage stabilization. The circuit of the application is simple in structure, improves the overall stability without increasing the system cost, and has good compensation effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a voltage buffer and a display device. Background Technology

[0002] Voltage buffers can maintain the circuit voltage within a relatively stable range. For example, an intermediate reference level (VCOM) buffer is used to control the switching of an LCD.

[0003] A VCOM buffer is a device that converts the analog level input from the VCOM terminal of a panel power management integrated circuit (PMIC) chip, which has limited driving capability, into an analog level output with strong driving capability. This allows the voltage of the VCOM buffer to remain stable when the display panel connected to the VCOM terminal draws current from and draws current into the VCOM buffer.

[0004] When using a VCOM buffer to regulate the voltage of a display panel, the VCOM buffer is connected as a negative feedback loop. At this time, the stability of the loop needs to be considered. The loop stability design of the VCOM needs to be carried out, and a certain phase margin and gain margin are left for the loop through stability compensation.

[0005] For example, the dominant pole compensation used in most designs is achieved by adding a large capacitor of 1-10uF off-chip, sacrificing bandwidth for stability. However, the presence of the large off-chip capacitor increases the load, resulting in poor circuit compensation. Summary of the Invention

[0006] This application provides a voltage buffer and a display device to solve the problem that the circuit compensation effect in the prior art is poor, which causes the voltage buffer to fail to meet the design requirements.

[0007] At least one embodiment of this application provides a voltage buffer, including: a first input terminal, a second input terminal, a first output terminal, an amplifier, a driver transistor, a first compensation module, and a second compensation module; the first input terminal is connected to the negative terminal of the amplifier; the second input terminal is connected to the positive terminal of the amplifier and is used to receive a first driving voltage; the output terminal of the amplifier is connected to the input terminal of the driver transistor; the first compensation module is used to make the dominant pole located between the amplifier and the driver transistor, and the secondary pole located at the first output terminal; the two ends of the first compensation module are respectively connected to the input terminal and the output terminal of the driver transistor; the second compensation module is used to input the output signal of the driver transistor to the negative terminal of the amplifier; the two ends of the second compensation module are respectively connected to the input terminal of the amplifier and the output terminal of the driver transistor; the first output terminal is connected to the output terminal of the driver transistor and is used to output a regulated second driving voltage.

[0008] According to at least one embodiment of the present application, a voltage buffer is provided, wherein a first compensation module includes a first capacitor and a first resistor; a first end of the first capacitor is connected between the input terminal of the driving transistor and the output terminal of the amplifier as the first end of the first compensation module; a second end of the first capacitor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the output terminal of the driving transistor as the second end of the first compensation module.

[0009] According to at least one embodiment of this application, a voltage buffer is provided, wherein the second compensation module includes a second capacitor; the first end of the second capacitor is connected to the negative terminal of the amplifier, and the second end of the second capacitor is connected to the output terminal of the driving transistor.

[0010] A voltage buffer provided according to at least one embodiment of this application further includes a first parasitic capacitor and a second parasitic capacitor; the first end of the first parasitic capacitor is connected to the node between the first end of the second compensation module and the negative terminal of the amplifier, and the second end of the first parasitic capacitor is grounded; the first end of the second parasitic capacitor is connected between the input terminal of the driving transistor and the first end of the first compensation module, and the second end of the second parasitic capacitor is grounded.

[0011] A voltage buffer provided according to at least one embodiment of this application further includes a first protective resistor and a second protective resistor; a first end of the first protective resistor is connected to a first input terminal, and a second end of the first protective resistor is connected to the negative terminal of the amplifier; a first end of the second protective resistor is connected to a second input terminal, and a second end of the second protective resistor is connected to the positive terminal of the amplifier.

[0012] At least one embodiment of this application also provides a display device, including the voltage buffer described above and a display panel connected to the voltage buffer; the display panel is used to control the orientation and deflection angle of liquid crystal molecules according to a second driving voltage.

[0013] A display device according to at least one embodiment of this application further includes a second resistor, a third resistor, and a third capacitor; a first end of the second resistor is connected to a first input terminal of a voltage buffer, and a second end of the second resistor is connected to a first output terminal of the voltage buffer; a first end of the third capacitor is connected to a first end of a display panel, and a second end of the third capacitor is connected to a first end of the third resistor; the second end of the third resistor is connected to the node between the first end of the second resistor and the first input terminal of the voltage buffer; and the second end of the display panel is connected to the node between the second end of the second resistor and the first output terminal of the voltage buffer.

[0014] A display device according to at least one embodiment of the present application further includes a load capacitor; a first end of the load capacitor is connected between a node between a second end of a second resistor and a first output terminal of a voltage buffer and a second end of a display panel, and the second end of the load capacitor is grounded.

[0015] A display device according to at least one embodiment of the present application further includes a third parasitic capacitor; the first end of the third parasitic capacitor is connected between the first end of the second resistor and the first input end of the voltage buffer, and the second end of the third parasitic capacitor is grounded.

[0016] According to at least one embodiment of the present application, a display device is provided, wherein the display panel includes a panel resistor and a panel capacitor; a first end of the panel resistor is connected to a first output terminal of a voltage buffer as a second end of the display panel, the second end of the panel resistor is connected to a first end of the panel capacitor, and the second end of the panel capacitor is grounded; a node between the second end of the panel resistor and the first end of the panel capacitor is connected to a first end of a third capacitor as a first end of the display panel.

[0017] At least one embodiment of this application provides a voltage buffer and a display device, wherein the first input terminal of the voltage buffer is connected to the negative terminal of an amplifier; the second input terminal is connected to the positive terminal of the amplifier for receiving a first driving voltage; the output terminal of the amplifier is connected to the input terminal of a driving transistor; a first compensation module is used to position the dominant pole between the amplifier and the driving transistor, and the secondary pole at the first output terminal; the two ends of the first compensation module are respectively connected to the input terminal and the output terminal of the driving transistor; a second compensation module is used to input the output signal of the driving transistor to the negative terminal of the amplifier; the two ends of the second compensation module are respectively connected to the input terminal of the amplifier and the output terminal of the driving transistor; the first output terminal is connected to the output terminal of the driving transistor for outputting a regulated second driving voltage. Through the above method, by setting the first compensation module and the second compensation module, the bandwidth can be compressed, making the secondary pole farther from the bandwidth; a new feedback path is formed at high frequencies, introducing a high-frequency zero into the system, which can raise the phase and increase the phase margin. Moreover, the circuit structure of the embodiments of this application is simple, improving overall stability without increasing system cost, and the circuit compensation effect is excellent. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of an embodiment of a VCOM buffer with a dominant pole compensation scheme in related technologies;

[0020] Figure 2 This is a schematic diagram of the structure of a voltage buffer provided in at least one embodiment of this application;

[0021] Figure 3This is a schematic diagram of the structure of a voltage buffer provided in at least one embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the structure of a display device provided in at least one embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Figure 1 This is a schematic diagram of an embodiment of a VCOM buffer with a dominant pole compensation scheme in related technologies.

[0025] Please see Figure 1 In this scheme, the VCOM buffer 100 includes a first input terminal a1, a second input terminal a2, a first output terminal b1, an amplifier Q1, and a driver transistor Q2. The first input terminal a1 and the second input terminal a2 are respectively connected to the input terminals of the amplifier Q1, the output terminal of the amplifier Q1 is connected to the input terminal of the driver transistor Q2, and the output terminal of the driver transistor Q2 is connected to the first output terminal b1. The first output terminal b1 is connected to the display panel.

[0026] The first output terminal b1 of the VCOM buffer 100 is connected to the first terminal of a large load capacitor CL (on the order of 10uF), and the second terminal of the large load capacitor CL is grounded, so that the dominant pole p1 is located at the output terminal. The pole formed by the output impedance of the first stage amplifier Q1 in the VCOM buffer 100 and the input equivalent capacitance of the second stage driver transistor Q2 is the secondary pole p2. If this compensation method is to meet the 60-degree phase margin requirement, the loop bandwidth needs to be compressed to half the frequency of the secondary pole p2. Therefore, this scheme sacrifices bandwidth and greatly reduces the loop response speed.

[0027] In other solutions, a resistor can be connected in series with the output capacitor for compensation. This compensation method, by setting a large external resistor Rz, adds a zero near the secondary node p2, which reduces the phase lag at the secondary node p2 and increases the phase margin. Simultaneously, in conjunction with other circuit components, the open-loop amplitude-frequency curve will be raised by the newly introduced zero, which will increase the system bandwidth.

[0028] However, this method of compensating with a series resistor on the output capacitor requires adding an extra large external resistor (100-200Ω) outside the VCOM buffer, which increases the overall system cost, and the voltage regulation effect of the load capacitor CL will be reduced by the resistor.

[0029] Addressing the issues with VCOM buffers in the aforementioned related technologies, this application proposes a voltage buffer that achieves good circuit compensation and improves overall stability without increasing system cost. This voltage buffer can be used as a VCOM buffer, improving loop stability when applied to display panels. It can also be applied to other circuits requiring voltage buffer compensation.

[0030] Figure 2 This is a schematic diagram of the structure of a voltage buffer provided in at least one embodiment of this application. In this embodiment, please refer to... Figure 2 The voltage buffer 200 includes: a first input terminal VIN-, a second input terminal VIN+, a first output terminal VOUT, an amplifier Q1, a driver transistor Q2, a first compensation module 210, and a second compensation module 220.

[0031] The first compensation module 210 is connected to the input and output terminals of the driver transistor Q2, respectively. The first compensation module 210 can position the dominant pole p1 between amplifier Q1 and driver transistor Q2, and the secondary pole p2 at the first output terminal VOUT. By changing the positions of the dominant and secondary poles, the first compensation module 210 enables the system to have higher bandwidth while maintaining the same phase margin.

[0032] The two ends of the second compensation module 220 are connected to the input terminal of amplifier Q1 and the output terminal of driver transistor Q2, respectively. The second compensation module 220 can input the output signal of driver transistor Q2 to the negative terminal of amplifier Q1. The second compensation module 220 forms a new path, so that the output signal of driver transistor Q2 can directly reach the negative terminal of amplifier Q1.

[0033] Specifically, the first input terminal VIN- is connected to the negative terminal of amplifier Q1, the second input terminal VIN+ is connected to the positive terminal of amplifier Q1, and the output terminal of amplifier Q1 is connected to the input terminal of driver transistor Q2.

[0034] The first compensation module 210 is connected in parallel with the driving transistor Q2, that is, the first end of the first compensation module 210 is connected to the input end of the driving transistor Q2, and the second end of the first compensation module 210 is connected to the output end of the driving transistor Q2.

[0035] The first end of the second compensation module 220 is connected to the negative terminal of the amplifier Q1, and the second end of the second compensation module 220 is connected to the output terminal of the driver transistor Q2; the node between the output terminal of the driver transistor Q2, the second end of the first compensation module 210, and the second end of the second compensation module 220 is connected to the first output terminal VOUT.

[0036] The second input terminal VIN+ is used to receive the first driving voltage; the first output terminal VOUT is used to output the regulated second driving voltage.

[0037] Optionally, the first driving voltage can be an external voltage used to drive the liquid crystal display; the second driving voltage is a voltage that can be directly input to the liquid crystal display after being regulated.

[0038] For example, when a voltage buffer is applied to a liquid crystal display, the voltage buffer is a VCOM buffer, and the second driving voltage is the VCOM voltage.

[0039] For example, the VCOM voltage is used to control the orientation and deflection angle of liquid crystal molecules in a liquid crystal display. The VCOM voltage can be generated in the backlight module of the liquid crystal display.

[0040] Furthermore, the first output terminal VOUT of the voltage buffer 200 is connected to the display panel. Between the first output terminal VOUT of the voltage buffer 200 and the node of the display panel, the first terminal of the load resistor CL is also connected, and the second terminal of the load resistor CL is grounded.

[0041] In the voltage buffer 200 of this embodiment, due to the addition of a first compensation module 210 and a second compensation module 220, the first compensation module 210 ensures that the system's dominant pole p1 is located between amplifier Q1 and driver transistor Q2 inside the voltage buffer, and the secondary pole p2 is located at the first output terminal VOUT of the voltage buffer 200. The function of the first compensation module 210 is to change the positions of the dominant and secondary poles, so that the system has a higher bandwidth while maintaining the same phase margin.

[0042] The two ends of the second compensation module 220 are connected to the negative terminal of amplifier Q1 and the output terminal of driver transistor Q2, respectively. The second compensation module 220 can increase system stability through several principles:

[0043] 1) Since the second compensation module 220 forms an integrator with the first stage amplifier Q1 and the second stage driver Q2, it can compress the bandwidth and make the secondary pole p2 farther away from the bandwidth.

[0044] 2) A new feedback path is formed at high frequency, and a high-frequency zero is introduced into the system, which can raise the phase and increase the phase margin.

[0045] In summary, this embodiment provides a voltage buffer, including: a first input terminal, a second input terminal, a first output terminal, an amplifier, a driver transistor, a first compensation module, and a second compensation module. The second input terminal receives a first driving voltage. The first compensation module is used to position the dominant pole between the amplifier and the driver transistor, and the secondary pole at the first output terminal. The second compensation module is used to input the output signal of the driver transistor to the negative terminal of the amplifier. The first output terminal is used to output a regulated second driving voltage. Through the above method, the voltage buffer in this embodiment can compress bandwidth, making the secondary pole farther from the bandwidth; it forms a new feedback path at high frequencies, introducing a high-frequency zero into the system, which can raise the phase and increase the phase margin; and the circuit structure is simple and easy to implement, improving overall stability without increasing system cost. The improved structure in the voltage buffer can be integrated into a chip, improving stability without increasing system cost. The additional compensation capacitor area added to the original circuit is small, therefore the overall circuit compensation effect is good and meets design requirements.

[0046] Optionally, the first compensation module can be a Miller compensation circuit, and the second compensation module can be an integral compensation circuit.

[0047] In some embodiments, the first compensation module may include a first capacitor and a first resistor. The first terminal of the first capacitor is connected between the input terminal of the driving transistor and the output terminal of the amplifier, serving as the first terminal of the first compensation module; the second terminal of the first capacitor is connected to the first terminal of the first resistor, and the second terminal of the first resistor is connected to the output terminal of the driving transistor, serving as the second terminal of the first compensation module.

[0048] By utilizing the Miller effect of the first compensation module, the first capacitor C1 is equivalent to a capacitor with a capacitance value of C1 * the second stage output, connected between the first stage output and ground. Since the first capacitor C1 can be considered an AC short circuit at high frequencies, the impedance to ground seen near the pole frequency at the first output terminal is the reciprocal of the admittance of the output driver stage. This significantly reduces the impedance of the output node, thereby pushing the secondary pole of the output to higher frequencies, resulting in higher bandwidth while maintaining the same phase margin.

[0049] In some embodiments, the second compensation module may include a second capacitor. A first terminal of the second capacitor is connected to the negative terminal of the amplifier, and a second terminal of the second capacitor is connected to the output terminal of the driving transistor.

[0050] In some embodiments, the voltage buffer may further include a first parasitic capacitance and a second parasitic capacitance; the first end of the first parasitic capacitance is connected to the node between the first end of the second compensation module and the negative terminal of the amplifier, and the second end of the first parasitic capacitance is grounded; the first end of the second parasitic capacitance is connected between the input terminal of the driving transistor and the first end of the first compensation module, and the second end of the second parasitic capacitance is grounded.

[0051] In some embodiments, the voltage buffer further includes a first protection resistor and a second protection resistor; a first end of the first protection resistor is connected to a first input terminal, and a second end of the first protection resistor is connected to the negative terminal of the amplifier; a first end of the second protection resistor is connected to a second input terminal, and a second end of the second protection resistor is connected to the positive terminal of the amplifier.

[0052] Figure 3 This is a schematic diagram of the structure of a voltage buffer provided in at least one embodiment of this application. In this embodiment, please refer to... Figure 3 The voltage buffer 300 includes a first input terminal VIN-, a second input terminal VIN+, a first output terminal VOUT, an amplifier Q1, a driver transistor Q2, a first compensation module 310, a second compensation module 320, a first parasitic capacitor C4, a second parasitic capacitor C5, a first protection resistor R4, and a second protection resistor R5.

[0053] The first compensation module 310 includes a first capacitor C1 and a first resistor R1. The second compensation module 320 includes a second capacitor C2.

[0054] The first input terminal VIN- is connected to the first end of the first protection resistor R4, and the second end of the first protection resistor R4 is connected to the negative terminal of the amplifier Q1; the second input terminal VIN+ is connected to the first end of the second protection resistor R5, and the second end of the second protection resistor R5 is connected to the positive terminal of the amplifier Q1.

[0055] The output of amplifier Q1 is connected to the input of driver transistor Q2, and the output of driver transistor Q2 is connected to the first output terminal VOUT.

[0056] The first terminal of the first capacitor C1 is connected between the input terminal of the driver transistor Q2 and the output terminal of the amplifier Q1; the second terminal of the first capacitor C1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the output terminal of the driver transistor Q2.

[0057] The first terminal of the second capacitor C2 is connected to the negative terminal of amplifier Q1, and the second terminal of the second capacitor C2 is connected to the output terminal of driver transistor Q2.

[0058] The first terminal of the first parasitic capacitor C4 is connected between the node between the first terminal of the second capacitor C2 and the negative terminal of the amplifier Q1 and the second terminal of the first protective resistor R4, and the second terminal of the first parasitic capacitor C4 is grounded.

[0059] The first end of the second parasitic capacitor C5 is connected between the input terminal of the driving transistor Q2 and the first end of the first capacitor C1, and the second end of the second parasitic capacitor C5 is grounded.

[0060] This application also proposes a display device, including the voltage buffer described above and a display panel connected to the voltage buffer. The above explanation of the voltage buffer also applies to the display device of this embodiment, and therefore will not be repeated here.

[0061] Figure 4 This is a schematic diagram of the structure of a display device provided in at least one embodiment of this application. In this embodiment, the display device may include the voltage buffer 410 described above and a display panel 420 connected to the voltage buffer 410.

[0062] Please refer to Figure 4 The voltage buffer 410 includes a first compensation module 411 and a second compensation module 412. The first compensation module 411 may include a first capacitor C1 and a first resistor R1. The second compensation module 412 may include a second capacitor C2.

[0063] The display panel 420 can control the orientation and deflection angle of the liquid crystal molecules according to the second driving voltage.

[0064] In some embodiments, the display device 410 may further include a second resistor R2, a third resistor R3, and a third capacitor C3.

[0065] In some embodiments, the display device 410 may further include a load capacitor CL.

[0066] The second resistor R2, the third resistor R3, the third capacitor C3, the load capacitor CL, and the voltage buffer 410 can form a negative feedback system to adjust the stability of the voltage.

[0067] The input port of the negative feedback system is VCOM IN, and the output port of the negative feedback system is VCOM OUT.

[0068] Specifically, the first end of the second resistor R2 is connected to the first input terminal VIN- of the voltage buffer 410, and the second end of the second resistor R2 is connected to the first output terminal VOUT of the voltage buffer 410.

[0069] The first end of the third capacitor C3 is connected to the first end of the display panel 420, the second end of the third capacitor C3 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the node between the first end of the second resistor R2 and the first input terminal VIN- of the voltage buffer 410.

[0070] The second terminal of the display panel 420 is connected to the node between the second terminal of the second resistor R2 and the first output terminal VOUT of the voltage buffer 410.

[0071] The first end of the load capacitor CL is connected between the node between the second end of the second resistor R2 and the first output terminal VOUT of the voltage buffer 410 and the second end of the display panel 420, and the second end of the load capacitor CL is grounded.

[0072] Furthermore, the display panel 420 may include a panel resistor R_panel and a panel capacitor C_panel.

[0073] The first end of the panel resistor R_panel is connected to the first output terminal VOUT of the voltage buffer 410 as the second end of the display panel 410. The second end of the panel resistor R_panel is connected to the first end of the panel capacitor C_panel, and the second end of the panel capacitor C_panel is grounded.

[0074] The node between the second end of the panel resistor R_panel and the first end of the panel capacitor C_panel can be used as the connection between the first end of the display panel 420 and the first end of the third capacitor C3.

[0075] In some embodiments, the display device may further include a third parasitic capacitor C6; the first end of the third parasitic capacitor C6 is connected between the first end of the second resistor R2 and the first input terminal VIN- of the voltage buffer 410, and the second end of the third parasitic capacitor C6 is grounded.

[0076] The third parasitic capacitor C6 can be considered as a parasitic capacitor on the PCB.

[0077] The input port VCOM IN of the negative feedback system is connected to the second input terminal VIN+ of the voltage buffer 410, and the output port VCOM OUT of the negative feedback system is the node between the first terminal of the load capacitor CL, the second terminal of the second resistor R2, and the first output terminal VOUT of the voltage buffer 410. The output port VCOM OUT of the negative feedback system is connected to the display panel 420.

[0078] The first output terminal VOUT of the voltage buffer 410 is connected to the first input terminal VIN- of the voltage buffer 410 through the second resistor R2, so that the DC voltage output by the output port VCOM OUT of the negative feedback system is equal to the voltage entering the input port VCOMIN. After passing through the equivalent resistance and capacitance inside the panel (i.e., the panel resistor R_panel and the panel capacitor C_panel), the output port VCOM OUT is fed back to the first input terminal VIN- of the voltage buffer 410 through the third capacitor C3 and the third resistor R3.

[0079] This connection method allows the voltage buffer and external resistors and capacitors to form a buffer with a closed-loop gain of 1 in the low-frequency range and an inverting amplifier with a closed-loop gain of -10 in the mid-frequency range. In the high-frequency range, due to the bandwidth limitation of the voltage buffer, the gain of the inverting amplifier will decrease as the frequency increases.

[0080] Among them, the frequency range corresponding to the pole formed by the third capacitor C3 and the third resistor R3 is the low frequency band, the frequency range from the pole formed by the third capacitor C3 and the third resistor R3 to the closed-loop bandwidth is the mid frequency band, and the frequency range greater than the bandwidth is the high frequency band.

[0081] The negative feedback system, consisting of a voltage buffer and external resistors and capacitors, enables the second terminal of the panel capacitor C_panel to stabilize the output port VCOM OUT voltage to the DC set value of the input port VCOM IN through the adjustment of the negative feedback system in the presence of noise from inside the panel.

[0082] The output stage current drive capability and operating bandwidth of the voltage buffer determine the speed at which the closed-loop system regulates the output port VCOM OUT when subjected to panel noise, while the open-loop gain and input random offset voltage of the voltage buffer determine the accuracy of the output port VCOM OUT voltage. The stability of the closed-loop system is determined by the relative positions of the loop poles and bandwidth. When evaluating system stability, the second terminal of the panel capacitor C_panel should be considered as AC ground.

[0083] Because the input pin of the voltage buffer requires ESD protection, an ESD protection device and resistor need to be added between the input pin and the actual op-amp input. This will introduce high-frequency poles p3 and p4 into the negative feedback system. If these two high-frequency poles are within 10 times the bandwidth, it will further reduce the stability of the loop. In addition, parasitic capacitances on the printed circuit board will also increase the capacitance at the high-frequency pole p4, further deteriorating the stability.

[0084] In a design without the second capacitor C2, the output signal of the voltage buffer needs to pass through the second resistor R2, the third parasitic capacitor C6, the first protection resistor R4, and the second parasitic capacitor C5. The phase lag caused by these two RCRC stages can be received by the negative terminal of the amplifier Q1, which leads to a further decrease in loop stability due to the non-negligible high-frequency pole.

[0085] In this embodiment, the introduction of the second capacitor C2 creates a new path between the two ends of the two RC stages. As the frequency increases, the second capacitor C2 approaches a short circuit, allowing the output signal of the voltage buffer to reach the negative terminal of amplifier Q1 directly through the second capacitor C2 without needing to experience the phase lag of the two RC stages. In this way, the introduction of the second capacitor C2 also reduces the negative impact of high-frequency poles p3 and p4 on system stability.

[0086] It should be noted that the primary pole p1 mentioned in this embodiment refers to the pole with the lowest frequency, that is, the pole generated by the first capacitor C1 and the output impedance of amplifier Q1; the secondary pole p2 is the pole with the second lowest frequency, that is, the pole generated by the driver transistor Q2 and the load capacitor CL.

[0087] High-frequency poles are parasitic poles generated by components. Among them, high-frequency pole p3 refers to the pole generated by the first protective resistor R4 and the second parasitic capacitance C5, and high-frequency pole p4 refers to the pole generated by the third resistor R3 and the third parasitic capacitance C6.

[0088] In summary, the voltage buffer and display device provided in this application include a voltage buffer comprising a first input terminal, a second input terminal, a first output terminal, an amplifier, a driver transistor, a first compensation module, and a second compensation module. The first input terminal is connected to the negative terminal of the amplifier. The second input terminal is connected to the positive terminal of the amplifier and is used to receive a first driving voltage. The output terminal of the amplifier is connected to the input terminal of the driver transistor. The first compensation module is used to ensure that the dominant pole is located between the amplifier and the driver transistor, and the secondary pole is located at the first output terminal. The two ends of the first compensation module are respectively connected to the input terminal and the output terminal of the driver transistor. The second compensation module is used to input the output signal of the driver transistor to the negative terminal of the amplifier. The two ends of the second compensation module are respectively connected to the input terminal of the amplifier and the output terminal of the driver transistor. The first output terminal is connected to the output terminal of the driver transistor and is used to output a regulated second driving voltage. By using the above methods, this application sets up a first compensation module and a second compensation module, which can compress the bandwidth and make the secondary pole farther away from the bandwidth; it forms a new feedback path at high frequencies, introduces a high-frequency zero into the system, and can raise the phase and increase the phase margin; the circuit structure of this application is simple, improves the overall stability without increasing the system cost, and has a good circuit compensation effect.

[0089] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A voltage buffer, characterized in that, include: First input terminal, second input terminal, first output terminal, amplifier, driver transistor, first compensation module, and second compensation module; The first input terminal is connected to the negative terminal of the amplifier; The second input terminal is connected to the positive terminal of the amplifier and is used to receive the first driving voltage; The output terminal of the amplifier is connected to the input terminal of the driving transistor; The first compensation module is used to position the dominant pole between the amplifier and the driving transistor, and the secondary pole at the first output terminal; The two ends of the first compensation module are respectively connected to the input end of the driving transistor and the output end of the driving transistor; The second compensation module is used to input the output signal of the driving transistor to the negative terminal of the amplifier; The two ends of the second compensation module are respectively connected to the input terminal of the amplifier and the output terminal of the driving transistor; The first output terminal is connected to the output terminal of the driving transistor and is used to output the regulated second driving voltage; The first compensation module includes a first capacitor and a first resistor; The first end of the first capacitor is connected between the input terminal of the driving transistor and the output terminal of the amplifier, serving as the first end of the first compensation module; the second end of the first capacitor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the output terminal of the driving transistor, serving as the second end of the first compensation module.

2. The voltage buffer according to claim 1, characterized in that, The second compensation module includes a second capacitor; The first terminal of the second capacitor is connected to the negative terminal of the amplifier, and the second terminal of the second capacitor is connected to the output terminal of the driving transistor.

3. The voltage buffer according to any one of claims 1 to 2, characterized in that, It also includes the first parasitic capacitance and the second parasitic capacitance; The first end of the first parasitic capacitor is connected to the node between the first end of the second compensation module and the negative terminal of the amplifier, and the second end of the first parasitic capacitor is grounded. The first end of the second parasitic capacitor is connected between the input terminal of the driving transistor and the first terminal of the first compensation module, and the second end of the second parasitic capacitor is grounded.

4. The voltage buffer according to any one of claims 1 to 2, characterized in that, It also includes a first protection resistor and a second protection resistor; The first end of the first protection resistor is connected to the first input terminal, and the second end of the first protection resistor is connected to the negative terminal of the amplifier. The first end of the second protection resistor is connected to the second input terminal, and the second end of the second protection resistor is connected to the positive terminal of the amplifier.

5. A display device, characterized in that, Includes a voltage buffer as described in any one of claims 1 to 4 and a display panel connected to the voltage buffer; The display panel is used to control the orientation and deflection angle of the liquid crystal molecules according to the second driving voltage.

6. The display device according to claim 5, characterized in that, It also includes a second resistor, a third resistor, and a third capacitor; The first end of the second resistor is connected to the first input terminal of the voltage buffer, and the second end of the second resistor is connected to the first output terminal of the voltage buffer. The first end of the third capacitor is connected to the first end of the display panel, the second end of the third capacitor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the node between the first end of the second resistor and the first input end of the voltage buffer. The second end of the display panel is connected to the node between the second end of the second resistor and the first output end of the voltage buffer.

7. The display device according to claim 6, characterized in that, It also includes the load capacitor; The first end of the load capacitor is connected between the node between the second end of the second resistor and the first output terminal of the voltage buffer and the second end of the display panel, and the second end of the load capacitor is grounded.

8. The display device according to claim 7, characterized in that, It also includes the third parasitic capacitance; The first end of the third parasitic capacitor is connected between the first end of the second resistor and the first input end of the voltage buffer, and the second end of the third parasitic capacitor is grounded.

9. The display device according to any one of claims 7 to 8, characterized in that, The display panel includes a panel resistor and a panel capacitor; The first end of the panel resistor is connected to the first output terminal of the voltage buffer as the second end of the display panel. The second end of the panel resistor is connected to the first end of the panel capacitor, and the second end of the panel capacitor is grounded. The node between the second end of the panel resistor and the first end of the panel capacitor is connected to the first end of the third capacitor as the first end of the display panel.

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